andi r1, r1, ~2
mts rmsr, r1
+/*
+ * Here is checking mechanism which check if Microblaze has msr instructions
+ * We load msr and compare it with previous r1 value - if is the same,
+ * msr instructions works if not - cpu don't have them.
+ */
+ or r8, r0, r0 /* 0 - I have msr instr, 1 - I don't have */
+ or r12, r0, r0
+ msrset r12, 0 /* set nothing - just read msr for test */
+ cmpu r12, r12, r1
+ beqi r12, 1f
+ ori r8, r0, 1 /* I don't have msr */
+1:
+
/* r7 may point to an FDT, or there may be one linked in.
if it's in r7, we've got to save it away ASAP.
We ensure r7 points to a valid FDT, just in case the bootloader
* Please see $(ARCH)/mach-$(SUBARCH)/setup.c for
* the function.
*/
- la r8, r0, machine_early_init
- brald r15, r8
+ la r9, r0, machine_early_init
+ brald r15, r9
nop
#ifndef CONFIG_MMU