Blackfin: decouple unrelated cache settings to get exact behavior
[safe/jmp/linux-2.6] / arch / blackfin / mach-common / pm.c
index d3d70fd..9e7e27b 100644 (file)
@@ -82,10 +82,9 @@ void bfin_pm_suspend_standby_enter(void)
 
        bfin_pm_standby_restore();
 
-#if defined(CONFIG_BF54x) || defined(CONFIG_BF52x)  || defined(CONFIG_BF561) || \
-       defined(CONFIG_BF538) || defined(CONFIG_BF539) || defined(CONFIG_BF51x)
+#ifdef SIC_IWR0
        bfin_write_SIC_IWR0(IWR_DISABLE_ALL);
-#if defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
+# ifdef SIC_IWR1
        /* BF52x system reset does not properly reset SIC_IWR1 which
         * will screw up the bootrom as it relies on MDMA0/1 waking it
         * up from IDLE instructions.  See this report for more info:
@@ -95,10 +94,8 @@ void bfin_pm_suspend_standby_enter(void)
                bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11));
        else
                bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#else
-       bfin_write_SIC_IWR1(IWR_DISABLE_ALL);
-#endif
-# ifdef CONFIG_BF54x
+# endif
+# ifdef SIC_IWR2
        bfin_write_SIC_IWR2(IWR_DISABLE_ALL);
 # endif
 #else
@@ -135,7 +132,7 @@ int bf53x_resume_l1_mem(unsigned char *memptr)
        return 0;
 }
 
-#ifdef CONFIG_BFIN_WB
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
 static void flushinv_all_dcache(void)
 {
        u32 way, bank, subbank, set;
@@ -178,7 +175,7 @@ static inline void dcache_disable(void)
 #ifdef CONFIG_BFIN_DCACHE
        unsigned long ctrl;
 
-#ifdef CONFIG_BFIN_WB
+#if defined(CONFIG_BFIN_EXTMEM_WRITEBACK) || defined(CONFIG_BFIN_L2_WRITEBACK)
        flushinv_all_dcache();
 #endif
        SSYNC();
@@ -290,7 +287,7 @@ int bfin_pm_suspend_mem_enter(void)
 static int bfin_pm_valid(suspend_state_t state)
 {
        return (state == PM_SUSPEND_STANDBY
-#ifndef BF533_FAMILY
+#if !(defined(BF533_FAMILY) || defined(CONFIG_BF561))
        /*
         * On BF533/2/1:
         * If we enter Hibernate the SCKE Pin is driven Low,