Blackfin: mass clean up of copyright/licensing info
[safe/jmp/linux-2.6] / arch / blackfin / mach-bf548 / include / mach / bfin_serial_5xx.h
index 5e29446..dd44aa7 100644 (file)
@@ -1,32 +1,7 @@
 /*
- * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
- * based on:
- * author:
+ * Copyright 2007-2009 Analog Devices Inc.
  *
- * created:
- * description:
- *     blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ * Licensed under the GPL-2 or later.
  */
 
 #include <linux/serial.h>
 #define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
 #define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
 #define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
-#define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
+#define UART_CLEAR_IER(uart,v)  bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
 #define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
 #define UART_PUT_LSR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
 #define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
 #define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
 #define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
 #define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
+#define UART_CLEAR_SCTS(uart)   bfin_write16(((uart)->port.membase + OFFSET_MSR),SCTS)
 
 #define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
 #define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
 
 #define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
-#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
+#define UART_DISABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) & ~(ARTS|MRTS))
+#define UART_ENABLE_RTS(x) UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS | ARTS)
 #define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
 #define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
 
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS) || \
+       defined(CONFIG_BFIN_UART2_CTSRTS) || defined(CONFIG_BFIN_UART3_CTSRTS)
+# define CONFIG_SERIAL_BFIN_HARD_CTSRTS
+#endif
 
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
+#define BFIN_UART_TX_FIFO_SIZE 2
 
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
 /*
  * The pin configuration is different from schematic
  */
 struct bfin_serial_port {
         struct uart_port        port;
         unsigned int            old_status;
+       int                     status_irq;
 #ifdef CONFIG_SERIAL_BFIN_DMA
        int                     tx_done;
        int                     tx_count;
@@ -98,24 +63,24 @@ struct bfin_serial_port {
        unsigned int            rx_dma_channel;
        struct work_struct      tx_dma_workqueue;
 #endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-       struct timer_list       cts_timer;
-       int             cts_pin;
-       int             rts_pin;
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       int                     scts;
+       int                     cts_pin;
+       int                     rts_pin;
 #endif
 };
 
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
 struct bfin_serial_res {
        unsigned long   uart_base_addr;
        int             uart_irq;
+       int             uart_status_irq;
 #ifdef CONFIG_SERIAL_BFIN_DMA
        unsigned int    uart_tx_dma_channel;
        unsigned int    uart_rx_dma_channel;
 #endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-       int     uart_cts_pin;
-       int     uart_rts_pin;
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       int             uart_cts_pin;
+       int             uart_rts_pin;
 #endif
 };
 
@@ -124,13 +89,14 @@ struct bfin_serial_res bfin_serial_resource[] = {
        {
        0xFFC00400,
        IRQ_UART0_RX,
+       IRQ_UART0_ERROR,
 #ifdef CONFIG_SERIAL_BFIN_DMA
        CH_UART0_TX,
        CH_UART0_RX,
 #endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-       CONFIG_UART0_CTS_PIN,
-       CONFIG_UART0_RTS_PIN,
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       0,
+       0,
 #endif
        },
 #endif
@@ -138,23 +104,29 @@ struct bfin_serial_res bfin_serial_resource[] = {
        {
        0xFFC02000,
        IRQ_UART1_RX,
+       IRQ_UART1_ERROR,
 #ifdef CONFIG_SERIAL_BFIN_DMA
        CH_UART1_TX,
        CH_UART1_RX,
 #endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       GPIO_PE10,
+       GPIO_PE9,
+#endif
        },
 #endif
 #ifdef CONFIG_SERIAL_BFIN_UART2
        {
        0xFFC02100,
        IRQ_UART2_RX,
+       IRQ_UART2_ERROR,
 #ifdef CONFIG_SERIAL_BFIN_DMA
        CH_UART2_TX,
        CH_UART2_RX,
 #endif
-#ifdef CONFIG_BFIN_UART2_CTSRTS
-       CONFIG_UART2_CTS_PIN,
-       CONFIG_UART2_RTS_PIN,
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       0,
+       0,
 #endif
        },
 #endif
@@ -162,59 +134,17 @@ struct bfin_serial_res bfin_serial_resource[] = {
        {
        0xFFC03100,
        IRQ_UART3_RX,
+       IRQ_UART3_ERROR,
 #ifdef CONFIG_SERIAL_BFIN_DMA
        CH_UART3_TX,
        CH_UART3_RX,
 #endif
+#ifdef CONFIG_SERIAL_BFIN_HARD_CTSRTS
+       GPIO_PB3,
+       GPIO_PB2,
+#endif
        },
 #endif
 };
 
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
 #define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-#ifdef CONFIG_SERIAL_BFIN_UART0
-       peripheral_request(P_UART0_TX, DRIVER_NAME);
-       peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-       peripheral_request(P_UART1_TX, DRIVER_NAME);
-       peripheral_request(P_UART1_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-       peripheral_request(P_UART1_RTS, DRIVER_NAME);
-       peripheral_request(P_UART1_CTS, DRIVER_NAME);
-#endif
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART2
-       peripheral_request(P_UART2_TX, DRIVER_NAME);
-       peripheral_request(P_UART2_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART3
-       peripheral_request(P_UART3_TX, DRIVER_NAME);
-       peripheral_request(P_UART3_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART3_CTSRTS
-       peripheral_request(P_UART3_RTS, DRIVER_NAME);
-       peripheral_request(P_UART3_CTS, DRIVER_NAME);
-#endif
-#endif
-       SSYNC();
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-       if (uart->cts_pin >= 0) {
-               gpio_request(uart->cts_pin, DRIVER_NAME);
-               gpio_direction_input(uart->cts_pin);
-       }
-
-       if (uart->rts_pin >= 0) {
-               gpio_request(uart->rts_pin, DRIVER_NAME);
-               gpio_direction_output(uart->rts_pin, 0);
-       }
-#endif
-}