Blackfin: scrub unused RTC masks
[safe/jmp/linux-2.6] / arch / blackfin / mach-bf518 / include / mach / defBF51x_base.h
index 1bec8d1..48c702d 100644 (file)
@@ -1,31 +1,7 @@
 /*
- * File:         include/asm-blackfin/mach-bf518/defBF51x_base.h
- * Based on:
- * Author:
+ * Copyright 2008 Analog Devices Inc.
  *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ * Licensed under the ADI BSD license or the GPL-2 (or later)
  */
 
 #ifndef _DEF_BF51X_H
 #define HMDMA0_CONTROL         0xFFC03300      /* Handshake MDMA0 Control Register                                     */
 #define HMDMA0_ECINIT          0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
 #define HMDMA0_BCINIT          0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT                0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
+#define HMDMA0_ECURGENT                0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshold Register          */
 #define HMDMA0_ECOVERFLOW      0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
 #define HMDMA0_ECOUNT          0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
 #define HMDMA0_BCOUNT          0xFFC03318      /* HMDMA0 Current Block Count Register                          */
 #define HMDMA1_CONTROL         0xFFC03340      /* Handshake MDMA1 Control Register                                     */
 #define HMDMA1_ECINIT          0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
 #define HMDMA1_BCINIT          0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT                0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
+#define HMDMA1_ECURGENT                0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshold Register          */
 #define HMDMA1_ECOVERFLOW      0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
 #define HMDMA1_ECOUNT          0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
 #define HMDMA1_BCOUNT          0xFFC03358      /* HMDMA1 Current Block Count Register                          */
 #define TRO_P 0x0F
 
 
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks                                                                                */
-#define        RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
-#define        RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
-#define        RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
-#define        RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
-
-/* RTC_ALARM Macro                     z=day           y=hr    x=min   w=sec           */
-#define SET_ALARM(z,y,x,w)     ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-
-/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                                */
-#define        STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
-#define        ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
-#define        SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
-#define        MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
-#define        HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
-#define        DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
-#define        DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
-#define        WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
-#define        WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
-
-/* RTC_FAST / RTC_PREN Mask                                                                                            */
-#define PREN                           0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
-
-
 /* ************** UART CONTROLLER MASKS *************************/
 /* UARTx_LCR Masks                                                                                             */
 #define WLS(x)         (((x)-5) & 0x03)        /* Word Length Select */