Blackfin arch: SMP supporting patchset: Blackfin CPLB related code

[safe/jmp/linux-2.6] / arch / blackfin / kernel / cplb-mpu / cplbinit.c

diff --git a/arch/blackfin/kernel/cplb-mpu/cplbinit.c b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
index 55af729..269d2a3 100644 (file)
--- a/arch/blackfin/kernel/cplb-mpu/cplbinit.c
+++ b/arch/blackfin/kernel/cplb-mpu/cplbinit.c
@@ -30,13 +30,13 @@
 # error the MPU will not function safely while Anomaly 05000263 applies
 #endif
 
-struct cplb_entry icplb_tbl[MAX_CPLBS];
-struct cplb_entry dcplb_tbl[MAX_CPLBS];
+struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
+struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
 
 int first_switched_icplb, first_switched_dcplb;
 int first_mask_dcplb;
 
-void __init generate_cplb_tables(void)
+void __init generate_cplb_tables_cpu(unsigned int cpu)
 {
        int i_d, i_i;
        unsigned long addr;
@@ -55,15 +55,16 @@ void __init generate_cplb_tables(void)
        d_cache |= CPLB_L1_AOW | CPLB_WT;
 #endif
 #endif
+
        i_d = i_i = 0;
 
        /* Set up the zero page.  */
-       dcplb_tbl[i_d].addr = 0;
-       dcplb_tbl[i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
+       dcplb_tbl[cpu][i_d].addr = 0;
+       dcplb_tbl[cpu][i_d++].data = SDRAM_OOPS | PAGE_SIZE_1KB;
 
 #if 0
-       icplb_tbl[i_i].addr = 0;
-       icplb_tbl[i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
+       icplb_tbl[cpu][i_i].addr = 0;
+       icplb_tbl[cpu][i_i++].data = i_cache | CPLB_USER_RD | PAGE_SIZE_4KB;
 #endif
 
        /* Cover kernel memory with 4M pages.  */
@@ -72,28 +73,28 @@ void __init generate_cplb_tables(void)
        i_data = i_cache | CPLB_VALID | CPLB_PORTPRIO | PAGE_SIZE_4MB;
 
        for (; addr < memory_start; addr += 4 * 1024 * 1024) {
-               dcplb_tbl[i_d].addr = addr;
-               dcplb_tbl[i_d++].data = d_data;
-               icplb_tbl[i_i].addr = addr;
-               icplb_tbl[i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
+               dcplb_tbl[cpu][i_d].addr = addr;
+               dcplb_tbl[cpu][i_d++].data = d_data;
+               icplb_tbl[cpu][i_i].addr = addr;
+               icplb_tbl[cpu][i_i++].data = i_data | (addr == 0 ? CPLB_USER_RD : 0);
        }
 
        /* Cover L1 memory.  One 4M area for code and data each is enough.  */
 #if L1_DATA_A_LENGTH > 0 || L1_DATA_B_LENGTH > 0
-       dcplb_tbl[i_d].addr = L1_DATA_A_START;
-       dcplb_tbl[i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
+       dcplb_tbl[cpu][i_d].addr = get_l1_data_a_start_cpu(cpu);
+       dcplb_tbl[cpu][i_d++].data = L1_DMEMORY | PAGE_SIZE_4MB;
 #endif
 #if L1_CODE_LENGTH > 0
-       icplb_tbl[i_i].addr = L1_CODE_START;
-       icplb_tbl[i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
+       icplb_tbl[cpu][i_i].addr = get_l1_code_start_cpu(cpu);
+       icplb_tbl[cpu][i_i++].data = L1_IMEMORY | PAGE_SIZE_4MB;
 #endif
 
        /* Cover L2 memory */
 #if L2_LENGTH > 0
-       dcplb_tbl[i_d].addr = L2_START;
-       dcplb_tbl[i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
-       icplb_tbl[i_i].addr = L2_START;
-       icplb_tbl[i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
+       dcplb_tbl[cpu][i_d].addr = L2_START;
+       dcplb_tbl[cpu][i_d++].data = L2_DMEMORY | PAGE_SIZE_1MB;
+       icplb_tbl[cpu][i_i].addr = L2_START;
+       icplb_tbl[cpu][i_i++].data = L2_IMEMORY | PAGE_SIZE_1MB;
 #endif
 
        first_mask_dcplb = i_d;
@@ -101,7 +102,7 @@ void __init generate_cplb_tables(void)
        first_switched_icplb = i_i;
 
        while (i_d < MAX_CPLBS)
-               dcplb_tbl[i_d++].data = 0;
+               dcplb_tbl[cpu][i_d++].data = 0;
        while (i_i < MAX_CPLBS)
-               icplb_tbl[i_i++].data = 0;
+               icplb_tbl[cpu][i_i++].data = 0;
 }