Blackfin arch: SMP supporting patchset: Blackfin CPLB related code

[safe/jmp/linux-2.6] / arch / blackfin / include / asm / cplb-mpu.h

diff --git a/arch/blackfin/include/asm/cplb-mpu.h b/arch/blackfin/include/asm/cplb-mpu.h
index 75c67b9..80680ad 100644 (file)
--- a/arch/blackfin/include/asm/cplb-mpu.h
+++ b/arch/blackfin/include/asm/cplb-mpu.h
@@ -28,6 +28,7 @@
  */
 #ifndef __ASM_BFIN_CPLB_MPU_H
 #define __ASM_BFIN_CPLB_MPU_H
+#include <linux/threads.h>
 
 struct cplb_entry {
        unsigned long data, addr;
@@ -39,22 +40,22 @@ struct mem_region {
        unsigned long icplb_data;
 };
 
-extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[MAX_CPLBS];
+extern struct cplb_entry dcplb_tbl[NR_CPUS][MAX_CPLBS];
+extern struct cplb_entry icplb_tbl[NR_CPUS][MAX_CPLBS];
 extern int first_switched_icplb;
 extern int first_mask_dcplb;
 extern int first_switched_dcplb;
 
-extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
-extern int nr_cplb_flush;
+extern int nr_dcplb_miss[], nr_icplb_miss[], nr_icplb_supv_miss[];
+extern int nr_dcplb_prot[], nr_cplb_flush[];
 
 extern int page_mask_order;
 extern int page_mask_nelts;
 
-extern unsigned long *current_rwx_mask;
+extern unsigned long *current_rwx_mask[NR_CPUS];
 
-extern void flush_switched_cplbs(void);
-extern void set_mask_dcplbs(unsigned long *);
+extern void flush_switched_cplbs(unsigned int);
+extern void set_mask_dcplbs(unsigned long *, unsigned int);
 
 extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);