#include <linux/interrupt.h>
#include <linux/irq.h>
#include <linux/io.h>
+#include <linux/slab.h>
#include <asm/system.h>
#include <mach/hardware.h>
-#include <mach/dma.h>
+#include <plat/dma.h>
-#include <mach/tc.h>
+#include <plat/tc.h>
#undef DEBUG
#endif
#define OMAP_DMA_ACTIVE 0x01
-#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
static int enable_1510_mode;
+static struct omap_dma_global_context_registers {
+ u32 dma_irqenable_l0;
+ u32 dma_ocp_sysconfig;
+ u32 dma_gcr;
+} omap_dma_global_context;
+
struct omap_dma_lch {
int next_lch;
int dev_id;
static inline void omap2_enable_irq_lch(int lch)
{
u32 val;
+ unsigned long flags;
if (!cpu_class_is_omap2())
return;
+ spin_lock_irqsave(&dma_chan_lock, flags);
val = dma_read(IRQENABLE_L0);
val |= 1 << lch;
dma_write(val, IRQENABLE_L0);
+ spin_unlock_irqrestore(&dma_chan_lock, flags);
}
int omap_request_dma(int dev_id, const char *dev_name,
if (cpu_class_is_omap2()) {
u32 val;
+
+ spin_lock_irqsave(&dma_chan_lock, flags);
/* Disable interrupts */
val = dma_read(IRQENABLE_L0);
val &= ~(1 << lch);
dma_write(val, IRQENABLE_L0);
+ spin_unlock_irqrestore(&dma_chan_lock, flags);
/* Clear the CSR register and IRQ status register */
dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(lch));
{
int lch;
- /* Check if LCD DMA is running */
- if (cpu_is_omap16xx())
- if (omap_readw(OMAP1610_DMA_LCD_CCR) & OMAP_DMA_CCR_EN)
+ if (cpu_class_is_omap1())
+ if (omap_lcd_dma_running())
return 1;
for (lch = 0; lch < dma_chan_count; lch++)
}
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
- (dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
+ (dma_chan[lch_queue].flags & OMAP_DMA_ACTIVE)) {
printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
"before unlinking\n");
dump_stack();
* OMAP_DMA_DYNAMIC_CHAIN
* @params - Channel parameters
*
- * @return - Succes : 0
+ * @return - Success : 0
* Failure: -EINVAL/-ENOMEM
*/
int omap_request_dma_chain(int dev_id, const char *dev_name,
#define omap1_dma_irq_handler NULL
#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
- defined(CONFIG_ARCH_OMAP4)
+#ifdef CONFIG_ARCH_OMAP2PLUS
static int omap2_dma_handle_ch(int ch)
{
/*----------------------------------------------------------------------------*/
-static struct lcd_dma_info {
- spinlock_t lock;
- int reserved;
- void (*callback)(u16 status, void *data);
- void *cb_data;
-
- int active;
- unsigned long addr, size;
- int rotate, data_type, xres, yres;
- int vxres;
- int mirror;
- int xscale, yscale;
- int ext_ctrl;
- int src_port;
- int single_transfer;
-} lcd_dma;
-
-void omap_set_lcd_dma_b1(unsigned long addr, u16 fb_xres, u16 fb_yres,
- int data_type)
+void omap_dma_global_context_save(void)
{
- lcd_dma.addr = addr;
- lcd_dma.data_type = data_type;
- lcd_dma.xres = fb_xres;
- lcd_dma.yres = fb_yres;
+ omap_dma_global_context.dma_irqenable_l0 =
+ dma_read(IRQENABLE_L0);
+ omap_dma_global_context.dma_ocp_sysconfig =
+ dma_read(OCP_SYSCONFIG);
+ omap_dma_global_context.dma_gcr = dma_read(GCR);
}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-void omap_set_lcd_dma_src_port(int port)
+void omap_dma_global_context_restore(void)
{
- lcd_dma.src_port = port;
-}
+ int ch;
-void omap_set_lcd_dma_ext_controller(int external)
-{
- lcd_dma.ext_ctrl = external;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-
-void omap_set_lcd_dma_single_transfer(int single)
-{
- lcd_dma.single_transfer = single;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-
-void omap_set_lcd_dma_b1_rotation(int rotate)
-{
- if (omap_dma_in_1510_mode()) {
- printk(KERN_ERR "DMA rotation is not supported in 1510 mode\n");
- BUG();
- return;
- }
- lcd_dma.rotate = rotate;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-
-void omap_set_lcd_dma_b1_mirror(int mirror)
-{
- if (omap_dma_in_1510_mode()) {
- printk(KERN_ERR "DMA mirror is not supported in 1510 mode\n");
- BUG();
- }
- lcd_dma.mirror = mirror;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
-
-void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
-{
- if (omap_dma_in_1510_mode()) {
- printk(KERN_ERR "DMA virtual resulotion is not supported "
- "in 1510 mode\n");
- BUG();
- }
- lcd_dma.vxres = vxres;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-
-void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
-{
- if (omap_dma_in_1510_mode()) {
- printk(KERN_ERR "DMA scale is not supported in 1510 mode\n");
- BUG();
- }
- lcd_dma.xscale = xscale;
- lcd_dma.yscale = yscale;
-}
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-
-static void set_b1_regs(void)
-{
- unsigned long top, bottom;
- int es;
- u16 w;
- unsigned long en, fn;
- long ei, fi;
- unsigned long vxres;
- unsigned int xscale, yscale;
-
- switch (lcd_dma.data_type) {
- case OMAP_DMA_DATA_TYPE_S8:
- es = 1;
- break;
- case OMAP_DMA_DATA_TYPE_S16:
- es = 2;
- break;
- case OMAP_DMA_DATA_TYPE_S32:
- es = 4;
- break;
- default:
- BUG();
- return;
- }
-
- vxres = lcd_dma.vxres ? lcd_dma.vxres : lcd_dma.xres;
- xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
- yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
- BUG_ON(vxres < lcd_dma.xres);
-
-#define PIXADDR(x, y) (lcd_dma.addr + \
- ((y) * vxres * yscale + (x) * xscale) * es)
-#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
-
- switch (lcd_dma.rotate) {
- case 0:
- if (!lcd_dma.mirror) {
- top = PIXADDR(0, 0);
- bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
- /* 1510 DMA requires the bottom address to be 2 more
- * than the actual last memory access location. */
- if (omap_dma_in_1510_mode() &&
- lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
- bottom += 2;
- ei = PIXSTEP(0, 0, 1, 0);
- fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
- } else {
- top = PIXADDR(lcd_dma.xres - 1, 0);
- bottom = PIXADDR(0, lcd_dma.yres - 1);
- ei = PIXSTEP(1, 0, 0, 0);
- fi = PIXSTEP(0, 0, lcd_dma.xres - 1, 1);
- }
- en = lcd_dma.xres;
- fn = lcd_dma.yres;
- break;
- case 90:
- if (!lcd_dma.mirror) {
- top = PIXADDR(0, lcd_dma.yres - 1);
- bottom = PIXADDR(lcd_dma.xres - 1, 0);
- ei = PIXSTEP(0, 1, 0, 0);
- fi = PIXSTEP(0, 0, 1, lcd_dma.yres - 1);
- } else {
- top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
- bottom = PIXADDR(0, 0);
- ei = PIXSTEP(0, 1, 0, 0);
- fi = PIXSTEP(1, 0, 0, lcd_dma.yres - 1);
- }
- en = lcd_dma.yres;
- fn = lcd_dma.xres;
- break;
- case 180:
- if (!lcd_dma.mirror) {
- top = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
- bottom = PIXADDR(0, 0);
- ei = PIXSTEP(1, 0, 0, 0);
- fi = PIXSTEP(0, 1, lcd_dma.xres - 1, 0);
- } else {
- top = PIXADDR(0, lcd_dma.yres - 1);
- bottom = PIXADDR(lcd_dma.xres - 1, 0);
- ei = PIXSTEP(0, 0, 1, 0);
- fi = PIXSTEP(lcd_dma.xres - 1, 1, 0, 0);
- }
- en = lcd_dma.xres;
- fn = lcd_dma.yres;
- break;
- case 270:
- if (!lcd_dma.mirror) {
- top = PIXADDR(lcd_dma.xres - 1, 0);
- bottom = PIXADDR(0, lcd_dma.yres - 1);
- ei = PIXSTEP(0, 0, 0, 1);
- fi = PIXSTEP(1, lcd_dma.yres - 1, 0, 0);
- } else {
- top = PIXADDR(0, 0);
- bottom = PIXADDR(lcd_dma.xres - 1, lcd_dma.yres - 1);
- ei = PIXSTEP(0, 0, 0, 1);
- fi = PIXSTEP(0, lcd_dma.yres - 1, 1, 0);
- }
- en = lcd_dma.yres;
- fn = lcd_dma.xres;
- break;
- default:
- BUG();
- return; /* Suppress warning about uninitialized vars */
- }
-
- if (omap_dma_in_1510_mode()) {
- omap_writew(top >> 16, OMAP1510_DMA_LCD_TOP_F1_U);
- omap_writew(top, OMAP1510_DMA_LCD_TOP_F1_L);
- omap_writew(bottom >> 16, OMAP1510_DMA_LCD_BOT_F1_U);
- omap_writew(bottom, OMAP1510_DMA_LCD_BOT_F1_L);
-
- return;
- }
-
- /* 1610 regs */
- omap_writew(top >> 16, OMAP1610_DMA_LCD_TOP_B1_U);
- omap_writew(top, OMAP1610_DMA_LCD_TOP_B1_L);
- omap_writew(bottom >> 16, OMAP1610_DMA_LCD_BOT_B1_U);
- omap_writew(bottom, OMAP1610_DMA_LCD_BOT_B1_L);
-
- omap_writew(en, OMAP1610_DMA_LCD_SRC_EN_B1);
- omap_writew(fn, OMAP1610_DMA_LCD_SRC_FN_B1);
-
- w = omap_readw(OMAP1610_DMA_LCD_CSDP);
- w &= ~0x03;
- w |= lcd_dma.data_type;
- omap_writew(w, OMAP1610_DMA_LCD_CSDP);
-
- w = omap_readw(OMAP1610_DMA_LCD_CTRL);
- /* Always set the source port as SDRAM for now*/
- w &= ~(0x03 << 6);
- if (lcd_dma.callback != NULL)
- w |= 1 << 1; /* Block interrupt enable */
- else
- w &= ~(1 << 1);
- omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
- if (!(lcd_dma.rotate || lcd_dma.mirror ||
- lcd_dma.vxres || lcd_dma.xscale || lcd_dma.yscale))
- return;
-
- w = omap_readw(OMAP1610_DMA_LCD_CCR);
- /* Set the double-indexed addressing mode */
- w |= (0x03 << 12);
- omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
- omap_writew(ei, OMAP1610_DMA_LCD_SRC_EI_B1);
- omap_writew(fi >> 16, OMAP1610_DMA_LCD_SRC_FI_B1_U);
- omap_writew(fi, OMAP1610_DMA_LCD_SRC_FI_B1_L);
-}
-
-static irqreturn_t lcd_dma_irq_handler(int irq, void *dev_id)
-{
- u16 w;
-
- w = omap_readw(OMAP1610_DMA_LCD_CTRL);
- if (unlikely(!(w & (1 << 3)))) {
- printk(KERN_WARNING "Spurious LCD DMA IRQ\n");
- return IRQ_NONE;
- }
- /* Ack the IRQ */
- w |= (1 << 3);
- omap_writew(w, OMAP1610_DMA_LCD_CTRL);
- lcd_dma.active = 0;
- if (lcd_dma.callback != NULL)
- lcd_dma.callback(w, lcd_dma.cb_data);
-
- return IRQ_HANDLED;
-}
-
-int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
- void *data)
-{
- spin_lock_irq(&lcd_dma.lock);
- if (lcd_dma.reserved) {
- spin_unlock_irq(&lcd_dma.lock);
- printk(KERN_ERR "LCD DMA channel already reserved\n");
- BUG();
- return -EBUSY;
- }
- lcd_dma.reserved = 1;
- spin_unlock_irq(&lcd_dma.lock);
- lcd_dma.callback = callback;
- lcd_dma.cb_data = data;
- lcd_dma.active = 0;
- lcd_dma.single_transfer = 0;
- lcd_dma.rotate = 0;
- lcd_dma.vxres = 0;
- lcd_dma.mirror = 0;
- lcd_dma.xscale = 0;
- lcd_dma.yscale = 0;
- lcd_dma.ext_ctrl = 0;
- lcd_dma.src_port = 0;
-
- return 0;
-}
-EXPORT_SYMBOL(omap_request_lcd_dma);
-
-void omap_free_lcd_dma(void)
-{
- spin_lock(&lcd_dma.lock);
- if (!lcd_dma.reserved) {
- spin_unlock(&lcd_dma.lock);
- printk(KERN_ERR "LCD DMA is not reserved\n");
- BUG();
- return;
- }
- if (!enable_1510_mode)
- omap_writew(omap_readw(OMAP1610_DMA_LCD_CCR) & ~1,
- OMAP1610_DMA_LCD_CCR);
- lcd_dma.reserved = 0;
- spin_unlock(&lcd_dma.lock);
-}
-EXPORT_SYMBOL(omap_free_lcd_dma);
-
-void omap_enable_lcd_dma(void)
-{
- u16 w;
+ dma_write(omap_dma_global_context.dma_gcr, GCR);
+ dma_write(omap_dma_global_context.dma_ocp_sysconfig,
+ OCP_SYSCONFIG);
+ dma_write(omap_dma_global_context.dma_irqenable_l0,
+ IRQENABLE_L0);
/*
- * Set the Enable bit only if an external controller is
- * connected. Otherwise the OMAP internal controller will
- * start the transfer when it gets enabled.
+ * A bug in ROM code leaves IRQ status for channels 0 and 1 uncleared
+ * after secure sram context save and restore. Hence we need to
+ * manually clear those IRQs to avoid spurious interrupts. This
+ * affects only secure devices.
*/
- if (enable_1510_mode || !lcd_dma.ext_ctrl)
- return;
-
- w = omap_readw(OMAP1610_DMA_LCD_CTRL);
- w |= 1 << 8;
- omap_writew(w, OMAP1610_DMA_LCD_CTRL);
-
- lcd_dma.active = 1;
-
- w = omap_readw(OMAP1610_DMA_LCD_CCR);
- w |= 1 << 7;
- omap_writew(w, OMAP1610_DMA_LCD_CCR);
-}
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-
-void omap_setup_lcd_dma(void)
-{
- BUG_ON(lcd_dma.active);
- if (!enable_1510_mode) {
- /* Set some reasonable defaults */
- omap_writew(0x5440, OMAP1610_DMA_LCD_CCR);
- omap_writew(0x9102, OMAP1610_DMA_LCD_CSDP);
- omap_writew(0x0004, OMAP1610_DMA_LCD_LCH_CTRL);
- }
- set_b1_regs();
- if (!enable_1510_mode) {
- u16 w;
-
- w = omap_readw(OMAP1610_DMA_LCD_CCR);
- /*
- * If DMA was already active set the end_prog bit to have
- * the programmed register set loaded into the active
- * register set.
- */
- w |= 1 << 11; /* End_prog */
- if (!lcd_dma.single_transfer)
- w |= (3 << 8); /* Auto_init, repeat */
- omap_writew(w, OMAP1610_DMA_LCD_CCR);
- }
-}
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-
-void omap_stop_lcd_dma(void)
-{
- u16 w;
+ if (cpu_is_omap34xx() && (omap_type() != OMAP2_DEVICE_TYPE_GP))
+ dma_write(0x3 , IRQSTATUS_L0);
- lcd_dma.active = 0;
- if (enable_1510_mode || !lcd_dma.ext_ctrl)
- return;
-
- w = omap_readw(OMAP1610_DMA_LCD_CCR);
- w &= ~(1 << 7);
- omap_writew(w, OMAP1610_DMA_LCD_CCR);
-
- w = omap_readw(OMAP1610_DMA_LCD_CTRL);
- w &= ~(1 << 8);
- omap_writew(w, OMAP1610_DMA_LCD_CTRL);
+ for (ch = 0; ch < dma_chan_count; ch++)
+ if (dma_chan[ch].dev_id != -1)
+ omap_clear_dma(ch);
}
-EXPORT_SYMBOL(omap_stop_lcd_dma);
/*----------------------------------------------------------------------------*/
static int __init omap_init_dma(void)
{
+ unsigned long base;
int ch, r;
if (cpu_class_is_omap1()) {
- omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
+ base = OMAP1_DMA_BASE;
dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap24xx()) {
- omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
+ base = OMAP24XX_DMA4_BASE;
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap34xx()) {
- omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
+ base = OMAP34XX_DMA4_BASE;
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap44xx()) {
- omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
+ base = OMAP44XX_DMA4_BASE;
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else {
pr_err("DMA init failed for unsupported omap\n");
return -ENODEV;
}
+ omap_dma_base = ioremap(base, SZ_4K);
+ BUG_ON(!omap_dma_base);
+
if (cpu_class_is_omap2() && omap_dma_reserve_channels
&& (omap_dma_reserve_channels <= dma_lch_count))
dma_lch_count = omap_dma_reserve_channels;
dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
GFP_KERNEL);
- if (!dma_chan)
- return -ENOMEM;
+ if (!dma_chan) {
+ r = -ENOMEM;
+ goto out_unmap;
+ }
if (cpu_class_is_omap2()) {
dma_linked_lch = kzalloc(sizeof(struct dma_link_info) *
dma_lch_count, GFP_KERNEL);
if (!dma_linked_lch) {
- kfree(dma_chan);
- return -ENOMEM;
+ r = -ENOMEM;
+ goto out_free;
}
}
dma_chan_count = 16;
} else
dma_chan_count = 9;
- if (cpu_is_omap16xx()) {
- u16 w;
-
- /* this would prevent OMAP sleep */
- w = omap_readw(OMAP1610_DMA_LCD_CTRL);
- w &= ~(1 << 8);
- omap_writew(w, OMAP1610_DMA_LCD_CTRL);
- }
} else if (cpu_class_is_omap2()) {
u8 revision = dma_read(REVISION) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
return 0;
}
- spin_lock_init(&lcd_dma.lock);
spin_lock_init(&dma_chan_lock);
for (ch = 0; ch < dma_chan_count; ch++) {
for (i = 0; i < ch; i++)
free_irq(omap1_dma_irq[i],
(void *) (i + 1));
- return r;
+ goto out_free;
}
}
}
if (cpu_class_is_omap2()) {
int irq;
if (cpu_is_omap44xx())
- irq = INT_44XX_SDMA_IRQ0;
+ irq = OMAP44XX_IRQ_SDMA_0;
else
irq = INT_24XX_SDMA_IRQ0;
setup_irq(irq, &omap24xx_dma_irq);
}
- /* Enable smartidle idlemodes and autoidle */
- if (cpu_is_omap34xx()) {
+ if (cpu_is_omap34xx() || cpu_is_omap44xx()) {
+ /* Enable smartidle idlemodes and autoidle */
u32 v = dma_read(OCP_SYSCONFIG);
v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
DMA_SYSCONFIG_SIDLEMODE_MASK |
DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
DMA_SYSCONFIG_AUTOIDLE);
dma_write(v , OCP_SYSCONFIG);
- }
-
-
- /* FIXME: Update LCD DMA to work on 24xx */
- if (cpu_class_is_omap1()) {
- r = request_irq(INT_DMA_LCD, lcd_dma_irq_handler, 0,
- "LCD DMA", NULL);
- if (r != 0) {
- int i;
-
- printk(KERN_ERR "unable to request IRQ for LCD DMA "
- "(error %d)\n", r);
- for (i = 0; i < dma_chan_count; i++)
- free_irq(omap1_dma_irq[i], (void *) (i + 1));
- return r;
+ /* reserve dma channels 0 and 1 in high security devices */
+ if (cpu_is_omap34xx() &&
+ (omap_type() != OMAP2_DEVICE_TYPE_GP)) {
+ printk(KERN_INFO "Reserving DMA channels 0 and 1 for "
+ "HS ROM code\n");
+ dma_chan[0].dev_id = 0;
+ dma_chan[1].dev_id = 1;
}
}
return 0;
+
+out_free:
+ kfree(dma_chan);
+
+out_unmap:
+ iounmap(omap_dma_base);
+
+ return r;
}
arch_initcall(omap_init_dma);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff