/*
* linux/arch/arm/plat-omap/dma.c
*
- * Copyright (C) 2003 Nokia Corporation
+ * Copyright (C) 2003 - 2008 Nokia Corporation
* Author: Juha Yrjölä <juha.yrjola@nokia.com>
* DMA channel linking for 1610 by Samuel Ortiz <samuel.ortiz@nokia.com>
* Graphics DMA and LCD DMA graphics tranformations
* Merged to support both OMAP1 and OMAP2 by Tony Lindgren <tony@atomide.com>
* Some functions based on earlier dma-omap.c Copyright (C) 2001 RidgeRun, Inc.
*
+ * Copyright (C) 2009 Texas Instruments
+ * Added OMAP4 support - Santosh Shilimkar <santosh.shilimkar@ti.com>
+ *
* Support functions for the OMAP internal DMA channels.
*
* This program is free software; you can redistribute it and/or modify
#include <linux/errno.h>
#include <linux/interrupt.h>
#include <linux/irq.h>
+#include <linux/io.h>
#include <asm/system.h>
-#include <asm/hardware.h>
-#include <asm/dma.h>
-#include <asm/io.h>
+#include <mach/hardware.h>
+#include <mach/dma.h>
-#include <asm/arch/tc.h>
+#include <mach/tc.h>
#undef DEBUG
enum { DMA_CHAIN_STARTED, DMA_CHAIN_NOTSTARTED };
#endif
-#define OMAP_DMA_ACTIVE 0x01
-#define OMAP_DMA_CCR_EN (1 << 7)
+#define OMAP_DMA_ACTIVE 0x01
+#define OMAP_DMA_CCR_EN (1 << 7)
#define OMAP2_DMA_CSR_CLEAR_MASK 0xffe
-#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
+#define OMAP_FUNC_MUX_ARM_BASE (0xfffe1000 + 0xec)
-static int enable_1510_mode = 0;
+static int enable_1510_mode;
struct omap_dma_lch {
int next_lch;
u16 saved_csr;
u16 enabled_irqs;
const char *dev_name;
- void (* callback)(int lch, u16 ch_status, void *data);
+ void (*callback)(int lch, u16 ch_status, void *data);
void *data;
#ifndef CONFIG_ARCH_OMAP1
static int dma_lch_count;
static int dma_chan_count;
+static int omap_dma_reserve_channels;
static spinlock_t dma_chan_lock;
static struct omap_dma_lch *dma_chan;
dma_write(ccr, CCR(lch));
}
}
+EXPORT_SYMBOL(omap_set_dma_priority);
void omap_set_dma_transfer_params(int lch, int data_type, int elem_count,
int frame_count, int sync_mode,
u32 val;
val = dma_read(CCR(lch));
- val &= ~(3 << 19);
- if (dma_trigger > 63)
- val |= 1 << 20;
- if (dma_trigger > 31)
- val |= 1 << 19;
- val &= ~(0x1f);
- val |= (dma_trigger & 0x1f);
+ /* DMA_SYNCHRO_CONTROL_UPPER depends on the channel number */
+ val &= ~((3 << 19) | 0x1f);
+ val |= (dma_trigger & ~0x1f) << 14;
+ val |= dma_trigger & 0x1f;
if (sync_mode & OMAP_DMA_SYNC_FRAME)
val |= 1 << 5;
dma_write(elem_count, CEN(lch));
dma_write(frame_count, CFN(lch));
}
+EXPORT_SYMBOL(omap_set_dma_transfer_params);
void omap_set_dma_color_mode(int lch, enum omap_dma_color_mode mode, u32 color)
{
- u16 w;
-
BUG_ON(omap_dma_in_1510_mode());
- if (cpu_class_is_omap2()) {
- REVISIT_24XX();
- return;
- }
+ if (cpu_class_is_omap1()) {
+ u16 w;
- w = dma_read(CCR2(lch));
- w &= ~0x03;
+ w = dma_read(CCR2(lch));
+ w &= ~0x03;
- switch (mode) {
- case OMAP_DMA_CONSTANT_FILL:
- w |= 0x01;
- break;
- case OMAP_DMA_TRANSPARENT_COPY:
- w |= 0x02;
- break;
- case OMAP_DMA_COLOR_DIS:
- break;
- default:
- BUG();
+ switch (mode) {
+ case OMAP_DMA_CONSTANT_FILL:
+ w |= 0x01;
+ break;
+ case OMAP_DMA_TRANSPARENT_COPY:
+ w |= 0x02;
+ break;
+ case OMAP_DMA_COLOR_DIS:
+ break;
+ default:
+ BUG();
+ }
+ dma_write(w, CCR2(lch));
+
+ w = dma_read(LCH_CTRL(lch));
+ w &= ~0x0f;
+ /* Default is channel type 2D */
+ if (mode) {
+ dma_write((u16)color, COLOR_L(lch));
+ dma_write((u16)(color >> 16), COLOR_U(lch));
+ w |= 1; /* Channel type G */
+ }
+ dma_write(w, LCH_CTRL(lch));
}
- dma_write(w, CCR2(lch));
- w = dma_read(LCH_CTRL(lch));
- w &= ~0x0f;
- /* Default is channel type 2D */
- if (mode) {
- dma_write((u16)color, COLOR_L(lch));
- dma_write((u16)(color >> 16), COLOR_U(lch));
- w |= 1; /* Channel type G */
+ if (cpu_class_is_omap2()) {
+ u32 val;
+
+ val = dma_read(CCR(lch));
+ val &= ~((1 << 17) | (1 << 16));
+
+ switch (mode) {
+ case OMAP_DMA_CONSTANT_FILL:
+ val |= 1 << 16;
+ break;
+ case OMAP_DMA_TRANSPARENT_COPY:
+ val |= 1 << 17;
+ break;
+ case OMAP_DMA_COLOR_DIS:
+ break;
+ default:
+ BUG();
+ }
+ dma_write(val, CCR(lch));
+
+ color &= 0xffffff;
+ dma_write(color, COLOR(lch));
}
- dma_write(w, LCH_CTRL(lch));
}
+EXPORT_SYMBOL(omap_set_dma_color_mode);
void omap_set_dma_write_mode(int lch, enum omap_dma_write_mode mode)
{
dma_write(csdp, CSDP(lch));
}
}
+EXPORT_SYMBOL(omap_set_dma_write_mode);
void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode)
{
unsigned long src_start,
int src_ei, int src_fi)
{
+ u32 l;
+
if (cpu_class_is_omap1()) {
u16 w;
w &= ~(0x1f << 2);
w |= src_port << 2;
dma_write(w, CSDP(lch));
+ }
- w = dma_read(CCR(lch));
- w &= ~(0x03 << 12);
- w |= src_amode << 12;
- dma_write(w, CCR(lch));
+ l = dma_read(CCR(lch));
+ l &= ~(0x03 << 12);
+ l |= src_amode << 12;
+ dma_write(l, CCR(lch));
+ if (cpu_class_is_omap1()) {
dma_write(src_start >> 16, CSSA_U(lch));
dma_write((u16)src_start, CSSA_L(lch));
-
- dma_write(src_ei, CSEI(lch));
- dma_write(src_fi, CSFI(lch));
}
- if (cpu_class_is_omap2()) {
- u32 l;
-
- l = dma_read(CCR(lch));
- l &= ~(0x03 << 12);
- l |= src_amode << 12;
- dma_write(l, CCR(lch));
-
+ if (cpu_class_is_omap2())
dma_write(src_start, CSSA(lch));
- dma_write(src_ei, CSEI(lch));
- dma_write(src_fi, CSFI(lch));
- }
+
+ dma_write(src_ei, CSEI(lch));
+ dma_write(src_fi, CSFI(lch));
}
+EXPORT_SYMBOL(omap_set_dma_src_params);
-void omap_set_dma_params(int lch, struct omap_dma_channel_params * params)
+void omap_set_dma_params(int lch, struct omap_dma_channel_params *params)
{
omap_set_dma_transfer_params(lch, params->data_type,
params->elem_count, params->frame_count,
omap_dma_set_prio_lch(lch, params->read_prio,
params->write_prio);
}
+EXPORT_SYMBOL(omap_set_dma_params);
void omap_set_dma_src_index(int lch, int eidx, int fidx)
{
- if (cpu_class_is_omap2()) {
- REVISIT_24XX();
+ if (cpu_class_is_omap2())
return;
- }
+
dma_write(eidx, CSEI(lch));
dma_write(fidx, CSFI(lch));
}
+EXPORT_SYMBOL(omap_set_dma_src_index);
void omap_set_dma_src_data_pack(int lch, int enable)
{
l |= (1 << 6);
dma_write(l, CSDP(lch));
}
+EXPORT_SYMBOL(omap_set_dma_src_data_pack);
void omap_set_dma_src_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
l |= (burst << 7);
dma_write(l, CSDP(lch));
}
+EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
/* Note that dest_port is only for OMAP1 */
void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
dma_write(dst_ei, CDEI(lch));
dma_write(dst_fi, CDFI(lch));
}
+EXPORT_SYMBOL(omap_set_dma_dest_params);
void omap_set_dma_dest_index(int lch, int eidx, int fidx)
{
- if (cpu_class_is_omap2()) {
- REVISIT_24XX();
+ if (cpu_class_is_omap2())
return;
- }
+
dma_write(eidx, CDEI(lch));
dma_write(fidx, CDFI(lch));
}
+EXPORT_SYMBOL(omap_set_dma_dest_index);
void omap_set_dma_dest_data_pack(int lch, int enable)
{
l |= 1 << 13;
dma_write(l, CSDP(lch));
}
+EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
void omap_set_dma_dest_burst_mode(int lch, enum omap_dma_burst_mode burst_mode)
{
l |= (burst << 14);
dma_write(l, CSDP(lch));
}
+EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
static inline void omap_enable_channel_irq(int lch)
{
{
dma_chan[lch].enabled_irqs |= bits;
}
+EXPORT_SYMBOL(omap_enable_dma_irq);
void omap_disable_dma_irq(int lch, u16 bits)
{
dma_chan[lch].enabled_irqs &= ~bits;
}
+EXPORT_SYMBOL(omap_disable_dma_irq);
static inline void enable_lnk(int lch)
{
l = dma_chan[lch].next_lch | (1 << 15);
#ifndef CONFIG_ARCH_OMAP1
- if (dma_chan[lch].next_linked_ch != -1)
- l = dma_chan[lch].next_linked_ch | (1 << 15);
+ if (cpu_class_is_omap2())
+ if (dma_chan[lch].next_linked_ch != -1)
+ l = dma_chan[lch].next_linked_ch | (1 << 15);
#endif
dma_write(l, CLNK_CTRL(lch));
}
int omap_request_dma(int dev_id, const char *dev_name,
- void (* callback)(int lch, u16 ch_status, void *data),
+ void (*callback)(int lch, u16 ch_status, void *data),
void *data, int *dma_ch_out)
{
int ch, free_ch = -1;
chan->dev_name = dev_name;
chan->callback = callback;
chan->data = data;
+ chan->flags = 0;
+
#ifndef CONFIG_ARCH_OMAP1
- chan->chain_id = -1;
- chan->next_linked_ch = -1;
+ if (cpu_class_is_omap2()) {
+ chan->chain_id = -1;
+ chan->next_linked_ch = -1;
+ }
#endif
+
chan->enabled_irqs = OMAP_DMA_DROP_IRQ | OMAP_DMA_BLOCK_IRQ;
if (cpu_class_is_omap1())
set_gdma_dev(free_ch + 1, dev_id);
dev_id = free_ch + 1;
}
- /* Disable the 1510 compatibility mode and set the sync device
- * id. */
+ /*
+ * Disable the 1510 compatibility mode and set the sync device
+ * id.
+ */
dma_write(dev_id | (1 << 10), CCR(free_ch));
- } else if (cpu_is_omap730() || cpu_is_omap15xx()) {
+ } else if (cpu_is_omap7xx() || cpu_is_omap15xx()) {
dma_write(dev_id, CCR(free_ch));
}
if (cpu_class_is_omap2()) {
omap2_enable_irq_lch(free_ch);
-
omap_enable_channel_irq(free_ch);
/* Clear the CSR register and IRQ status register */
dma_write(OMAP2_DMA_CSR_CLEAR_MASK, CSR(free_ch));
return 0;
}
+EXPORT_SYMBOL(omap_request_dma);
void omap_free_dma(int lch)
{
unsigned long flags;
- spin_lock_irqsave(&dma_chan_lock, flags);
if (dma_chan[lch].dev_id == -1) {
- printk("omap_dma: trying to free nonallocated DMA channel %d\n",
+ pr_err("omap_dma: trying to free unallocated DMA channel %d\n",
lch);
- spin_unlock_irqrestore(&dma_chan_lock, flags);
return;
}
- dma_chan[lch].dev_id = -1;
- dma_chan[lch].next_lch = -1;
- dma_chan[lch].callback = NULL;
- spin_unlock_irqrestore(&dma_chan_lock, flags);
if (cpu_class_is_omap1()) {
/* Disable all DMA interrupts for the channel. */
dma_write(0, CCR(lch));
omap_clear_dma(lch);
}
+
+ spin_lock_irqsave(&dma_chan_lock, flags);
+ dma_chan[lch].dev_id = -1;
+ dma_chan[lch].next_lch = -1;
+ dma_chan[lch].callback = NULL;
+ spin_unlock_irqrestore(&dma_chan_lock, flags);
}
+EXPORT_SYMBOL(omap_free_dma);
/**
* @brief omap_dma_set_global_params : Set global priority settings for dma
*
* @param arb_rate
* @param max_fifo_depth
- * @param tparams - Number of thereads to reserve : DMA_THREAD_RESERVE_NORM
- * DMA_THREAD_RESERVE_ONET
- * DMA_THREAD_RESERVE_TWOT
- * DMA_THREAD_RESERVE_THREET
+ * @param tparams - Number of threads to reserve : DMA_THREAD_RESERVE_NORM
+ * DMA_THREAD_RESERVE_ONET
+ * DMA_THREAD_RESERVE_TWOT
+ * DMA_THREAD_RESERVE_THREET
*/
void
omap_dma_set_global_params(int arb_rate, int max_fifo_depth, int tparams)
return;
}
+ if (max_fifo_depth == 0)
+ max_fifo_depth = 1;
if (arb_rate == 0)
arb_rate = 1;
- reg = (arb_rate & 0xff) << 16;
- reg |= (0xff & max_fifo_depth);
+ reg = 0xff & max_fifo_depth;
+ reg |= (0x3 & tparams) << 12;
+ reg |= (arb_rate & 0xff) << 16;
dma_write(reg, GCR);
}
}
l = dma_read(CCR(lch));
l &= ~((1 << 6) | (1 << 26));
- if (cpu_is_omap2430() || cpu_is_omap34xx())
+ if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
l |= ((read_prio & 0x1) << 6) | ((write_prio & 0x1) << 26);
else
l |= ((read_prio & 0x1) << 6);
local_irq_restore(flags);
}
+EXPORT_SYMBOL(omap_clear_dma);
void omap_start_dma(int lch)
{
cur_lch = next_lch;
} while (next_lch != -1);
- } else if (cpu_class_is_omap2()) {
+ } else if (cpu_is_omap242x() ||
+ (cpu_is_omap243x() && omap_type() <= OMAP2430_REV_ES1_0)) {
+
/* Errata: Need to write lch even if not using chaining */
dma_write(lch, CLNK_CTRL(lch));
}
l = dma_read(CCR(lch));
- /* Errata: On ES2.0 BUFFERING disable must be set.
- * This will always fail on ES1.0 */
+ /*
+ * Errata: On ES2.0 BUFFERING disable must be set.
+ * This will always fail on ES1.0
+ */
if (cpu_is_omap24xx())
l |= OMAP_DMA_CCR_EN;
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
+EXPORT_SYMBOL(omap_start_dma);
void omap_stop_dma(int lch)
{
u32 l;
+ /* Disable all interrupts on the channel */
+ if (cpu_class_is_omap1())
+ dma_write(0, CICR(lch));
+
+ l = dma_read(CCR(lch));
+ l &= ~OMAP_DMA_CCR_EN;
+ dma_write(l, CCR(lch));
+
if (!omap_dma_in_1510_mode() && dma_chan[lch].next_lch != -1) {
int next_lch, cur_lch = lch;
char dma_chan_link_map[OMAP_DMA4_LOGICAL_DMA_CH_COUNT];
next_lch = dma_chan[cur_lch].next_lch;
cur_lch = next_lch;
} while (next_lch != -1);
-
- return;
}
- /* Disable all interrupts on the channel */
- if (cpu_class_is_omap1())
- dma_write(0, CICR(lch));
-
- l = dma_read(CCR(lch));
- l &= ~OMAP_DMA_CCR_EN;
- dma_write(l, CCR(lch));
-
dma_chan[lch].flags &= ~OMAP_DMA_ACTIVE;
}
+EXPORT_SYMBOL(omap_stop_dma);
/*
* Allows changing the DMA callback function or data. This may be needed if
* the driver shares a single DMA channel for multiple dma triggers.
*/
int omap_set_dma_callback(int lch,
- void (* callback)(int lch, u16 ch_status, void *data),
+ void (*callback)(int lch, u16 ch_status, void *data),
void *data)
{
unsigned long flags;
return 0;
}
+EXPORT_SYMBOL(omap_set_dma_callback);
/*
* Returns current physical source address for the given DMA channel.
return offset;
}
+EXPORT_SYMBOL(omap_get_dma_src_pos);
/*
* Returns current physical destination address for the given DMA channel.
return offset;
}
-
-/*
- * Returns current source transfer counting for the given DMA channel.
- * Can be used to monitor the progress of a transfer inside a block.
- * It must be called with disabled interrupts.
- */
-int omap_get_dma_src_addr_counter(int lch)
-{
- return (dma_addr_t)dma_read(CSAC(lch));
-}
+EXPORT_SYMBOL(omap_get_dma_dst_pos);
int omap_get_dma_active_status(int lch)
{
* For this DMA link to start, you still need to start (see omap_start_dma)
* the first one. That will fire up the entire queue.
*/
-void omap_dma_link_lch (int lch_head, int lch_queue)
+void omap_dma_link_lch(int lch_head, int lch_queue)
{
if (omap_dma_in_1510_mode()) {
+ if (lch_head == lch_queue) {
+ dma_write(dma_read(CCR(lch_head)) | (3 << 8),
+ CCR(lch_head));
+ return;
+ }
printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
BUG();
return;
dma_chan[lch_head].next_lch = lch_queue;
}
+EXPORT_SYMBOL(omap_dma_link_lch);
/*
* Once the DMA queue is stopped, we can destroy it.
*/
-void omap_dma_unlink_lch (int lch_head, int lch_queue)
+void omap_dma_unlink_lch(int lch_head, int lch_queue)
{
if (omap_dma_in_1510_mode()) {
+ if (lch_head == lch_queue) {
+ dma_write(dma_read(CCR(lch_head)) & ~(3 << 8),
+ CCR(lch_head));
+ return;
+ }
printk(KERN_ERR "DMA linking is not supported in 1510 mode\n");
BUG();
return;
dump_stack();
}
-
if ((dma_chan[lch_head].flags & OMAP_DMA_ACTIVE) ||
(dma_chan[lch_head].flags & OMAP_DMA_ACTIVE)) {
printk(KERN_ERR "omap_dma: You need to stop the DMA channels "
dma_chan[lch_head].next_lch = -1;
}
+EXPORT_SYMBOL(omap_dma_unlink_lch);
+
+/*----------------------------------------------------------------------------*/
#ifndef CONFIG_ARCH_OMAP1
/* Create chain of DMA channesls */
* OMAP_DMA_DYNAMIC_CHAIN
* @params - Channel parameters
*
- * @return - Succes : 0
+ * @return - Success : 0
* Failure: -EINVAL/-ENOMEM
*/
int omap_request_dma_chain(int dev_id, const char *dev_name,
- void (*callback) (int chain_id, u16 ch_status,
+ void (*callback) (int lch, u16 ch_status,
void *data),
int *chain_id, int no_of_chans, int chain_mode,
struct omap_dma_channel_params params)
/* request and reserve DMA channels for the chain */
for (i = 0; i < no_of_chans; i++) {
err = omap_request_dma(dev_id, dev_name,
- callback, 0, &channels[i]);
+ callback, NULL, &channels[i]);
if (err < 0) {
int j;
for (j = 0; j < i; j++)
for (i = 0; i < (no_of_chans - 1); i++)
create_dma_lch_chain(channels[i], channels[i + 1]);
}
+
return 0;
}
EXPORT_SYMBOL(omap_request_dma_chain);
*/
omap_set_dma_params(channels[i], ¶ms);
}
+
return 0;
}
EXPORT_SYMBOL(omap_modify_dma_chain_params);
dma_linked_lch[chain_id].linked_dmach_q = NULL;
dma_linked_lch[chain_id].chain_mode = -1;
dma_linked_lch[chain_id].chain_state = -1;
+
return (0);
}
EXPORT_SYMBOL(omap_free_dma_chain);
if (OMAP_DMA_CHAIN_QEMPTY(chain_id))
return OMAP_DMA_CHAIN_INACTIVE;
+
return OMAP_DMA_CHAIN_ACTIVE;
}
EXPORT_SYMBOL(omap_dma_chain_status);
u32 l, lch;
int start_dma = 0;
- /* if buffer size is less than 1 then there is
- * no use of starting the chain */
+ /*
+ * if buffer size is less than 1 then there is
+ * no use of starting the chain
+ */
if (elem_count < 1) {
printk(KERN_ERR "Invalid buffer size\n");
return -EINVAL;
dma_write(elem_count, CEN(lch));
dma_write(frame_count, CFN(lch));
- /* If the chain is dynamically linked,
- * then we may have to start the chain if its not active */
+ /*
+ * If the chain is dynamically linked,
+ * then we may have to start the chain if its not active
+ */
if (dma_linked_lch[chain_id].chain_mode == OMAP_DMA_DYNAMIC_CHAIN) {
- /* In Dynamic chain, if the chain is not started,
- * queue the channel */
+ /*
+ * In Dynamic chain, if the chain is not started,
+ * queue the channel
+ */
if (dma_linked_lch[chain_id].chain_state ==
DMA_CHAIN_NOTSTARTED) {
/* Enable the link in previous channel */
dma_chan[lch].state = DMA_CH_QUEUED;
}
- /* Chain is already started, make sure its active,
- * if not then start the chain */
+ /*
+ * Chain is already started, make sure its active,
+ * if not then start the chain
+ */
else {
start_dma = 1;
dma_chan[lch].flags |= OMAP_DMA_ACTIVE;
}
}
+
return 0;
}
EXPORT_SYMBOL(omap_dma_chain_a_transfer);
dma_write(l, CCR(channels[0]));
dma_chan[channels[0]].flags |= OMAP_DMA_ACTIVE;
+
return 0;
}
EXPORT_SYMBOL(omap_start_dma_chain_transfers);
}
channels = dma_linked_lch[chain_id].linked_dmach_q;
- /* DMA Errata:
+ /*
+ * DMA Errata:
* Special programming model needed to disable DMA before end of block
*/
sys_cf = dma_read(OCP_SYSCONFIG);
/* Errata - put in the old value */
dma_write(sys_cf, OCP_SYSCONFIG);
+
return 0;
}
EXPORT_SYMBOL(omap_stop_dma_chain_transfers);
return dma_read(CSAC(lch));
}
EXPORT_SYMBOL(omap_get_dma_chain_src_pos);
-#endif
+#endif /* ifndef CONFIG_ARCH_OMAP1 */
/*----------------------------------------------------------------------------*/
dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, csr, dma_chan[ch].data);
+
return 1;
}
#define omap1_dma_irq_handler NULL
#endif
-#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3)
+#if defined(CONFIG_ARCH_OMAP2) || defined(CONFIG_ARCH_OMAP3) || \
+ defined(CONFIG_ARCH_OMAP4)
static int omap2_dma_handle_ch(int ch)
{
if (!status) {
if (printk_ratelimit())
- printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n", ch);
+ printk(KERN_WARNING "Spurious DMA IRQ for lch %d\n",
+ ch);
dma_write(1 << ch, IRQSTATUS_L0);
return 0;
}
printk(KERN_INFO
"DMA synchronization event drop occurred with device "
"%d\n", dma_chan[ch].dev_id);
- if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ))
+ if (unlikely(status & OMAP2_DMA_TRANS_ERR_IRQ)) {
printk(KERN_INFO "DMA transaction error with device %d\n",
dma_chan[ch].dev_id);
+ if (cpu_class_is_omap2()) {
+ /* Errata: sDMA Channel is not disabled
+ * after a transaction error. So we explicitely
+ * disable the channel
+ */
+ u32 ccr;
+
+ ccr = dma_read(CCR(ch));
+ ccr &= ~OMAP_DMA_CCR_EN;
+ dma_write(ccr, CCR(ch));
+ dma_chan[ch].flags &= ~OMAP_DMA_ACTIVE;
+ }
+ }
if (unlikely(status & OMAP2_DMA_SECURE_ERR_IRQ))
printk(KERN_INFO "DMA secure error with device %d\n",
dma_chan[ch].dev_id);
status = dma_read(CSR(ch));
}
+ dma_write(status, CSR(ch));
+
if (likely(dma_chan[ch].callback != NULL))
dma_chan[ch].callback(ch, status, dma_chan[ch].data);
- dma_write(status, CSR(ch));
-
return 0;
}
/* STATUS register count is from 1-32 while our is 0-31 */
static irqreturn_t omap2_dma_irq_handler(int irq, void *dev_id)
{
- u32 val;
+ u32 val, enable_reg;
int i;
val = dma_read(IRQSTATUS_L0);
printk(KERN_WARNING "Spurious DMA IRQ\n");
return IRQ_HANDLED;
}
+ enable_reg = dma_read(IRQENABLE_L0);
+ val &= enable_reg; /* Dispatch only relevant interrupts */
for (i = 0; i < dma_lch_count && val != 0; i++) {
if (val & 1)
omap2_dma_handle_ch(i);
static struct lcd_dma_info {
spinlock_t lock;
int reserved;
- void (* callback)(u16 status, void *data);
+ void (*callback)(u16 status, void *data);
void *cb_data;
int active;
lcd_dma.xres = fb_xres;
lcd_dma.yres = fb_yres;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1);
void omap_set_lcd_dma_src_port(int port)
{
{
lcd_dma.ext_ctrl = external;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
void omap_set_lcd_dma_single_transfer(int single)
{
lcd_dma.single_transfer = single;
}
-
+EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
void omap_set_lcd_dma_b1_rotation(int rotate)
{
}
lcd_dma.rotate = rotate;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
void omap_set_lcd_dma_b1_mirror(int mirror)
{
}
lcd_dma.mirror = mirror;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
void omap_set_lcd_dma_b1_vxres(unsigned long vxres)
{
}
lcd_dma.vxres = vxres;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
void omap_set_lcd_dma_b1_scale(unsigned int xscale, unsigned int yscale)
{
lcd_dma.xscale = xscale;
lcd_dma.yscale = yscale;
}
+EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
static void set_b1_regs(void)
{
xscale = lcd_dma.xscale ? lcd_dma.xscale : 1;
yscale = lcd_dma.yscale ? lcd_dma.yscale : 1;
BUG_ON(vxres < lcd_dma.xres);
-#define PIXADDR(x,y) (lcd_dma.addr + ((y) * vxres * yscale + (x) * xscale) * es)
+
+#define PIXADDR(x, y) (lcd_dma.addr + \
+ ((y) * vxres * yscale + (x) * xscale) * es)
#define PIXSTEP(sx, sy, dx, dy) (PIXADDR(dx, dy) - PIXADDR(sx, sy) - es + 1)
+
switch (lcd_dma.rotate) {
case 0:
if (!lcd_dma.mirror) {
/* 1510 DMA requires the bottom address to be 2 more
* than the actual last memory access location. */
if (omap_dma_in_1510_mode() &&
- lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
- bottom += 2;
+ lcd_dma.data_type == OMAP_DMA_DATA_TYPE_S32)
+ bottom += 2;
ei = PIXSTEP(0, 0, 1, 0);
fi = PIXSTEP(lcd_dma.xres - 1, 0, 0, 1);
} else {
return IRQ_HANDLED;
}
-int omap_request_lcd_dma(void (* callback)(u16 status, void *data),
+int omap_request_lcd_dma(void (*callback)(u16 status, void *data),
void *data)
{
spin_lock_irq(&lcd_dma.lock);
return 0;
}
+EXPORT_SYMBOL(omap_request_lcd_dma);
void omap_free_lcd_dma(void)
{
lcd_dma.reserved = 0;
spin_unlock(&lcd_dma.lock);
}
+EXPORT_SYMBOL(omap_free_lcd_dma);
void omap_enable_lcd_dma(void)
{
u16 w;
- /* Set the Enable bit only if an external controller is
+ /*
+ * Set the Enable bit only if an external controller is
* connected. Otherwise the OMAP internal controller will
* start the transfer when it gets enabled.
*/
w |= 1 << 7;
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
+EXPORT_SYMBOL(omap_enable_lcd_dma);
void omap_setup_lcd_dma(void)
{
u16 w;
w = omap_readw(OMAP1610_DMA_LCD_CCR);
- /* If DMA was already active set the end_prog bit to have
+ /*
+ * If DMA was already active set the end_prog bit to have
* the programmed register set loaded into the active
* register set.
*/
w |= 1 << 11; /* End_prog */
if (!lcd_dma.single_transfer)
- w |= (3 << 8); /* Auto_init, repeat */
+ w |= (3 << 8); /* Auto_init, repeat */
omap_writew(w, OMAP1610_DMA_LCD_CCR);
}
}
+EXPORT_SYMBOL(omap_setup_lcd_dma);
void omap_stop_lcd_dma(void)
{
w &= ~(1 << 8);
omap_writew(w, OMAP1610_DMA_LCD_CTRL);
}
+EXPORT_SYMBOL(omap_stop_lcd_dma);
/*----------------------------------------------------------------------------*/
int ch, r;
if (cpu_class_is_omap1()) {
- omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP1_DMA_BASE);
+ omap_dma_base = OMAP1_IO_ADDRESS(OMAP1_DMA_BASE);
dma_lch_count = OMAP1_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap24xx()) {
- omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP24XX_DMA4_BASE);
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP24XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else if (cpu_is_omap34xx()) {
- omap_dma_base = (void __iomem *)IO_ADDRESS(OMAP34XX_DMA4_BASE);
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP34XX_DMA4_BASE);
+ dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+ } else if (cpu_is_omap44xx()) {
+ omap_dma_base = OMAP2_IO_ADDRESS(OMAP44XX_DMA4_BASE);
dma_lch_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
} else {
pr_err("DMA init failed for unsupported omap\n");
return -ENODEV;
}
+ if (cpu_class_is_omap2() && omap_dma_reserve_channels
+ && (omap_dma_reserve_channels <= dma_lch_count))
+ dma_lch_count = omap_dma_reserve_channels;
+
dma_chan = kzalloc(sizeof(struct omap_dma_lch) * dma_lch_count,
GFP_KERNEL);
if (!dma_chan)
printk(KERN_INFO "DMA support for OMAP15xx initialized\n");
dma_chan_count = 9;
enable_1510_mode = 1;
- } else if (cpu_is_omap16xx() || cpu_is_omap730()) {
+ } else if (cpu_is_omap16xx() || cpu_is_omap7xx()) {
printk(KERN_INFO "OMAP DMA hardware version %d\n",
dma_read(HW_ID));
printk(KERN_INFO "DMA capabilities: %08x:%08x:%04x:%04x:%04x\n",
u8 revision = dma_read(REVISION) & 0xff;
printk(KERN_INFO "OMAP DMA hardware revision %d.%d\n",
revision >> 4, revision & 0xf);
- dma_chan_count = OMAP_DMA4_LOGICAL_DMA_CH_COUNT;
+ dma_chan_count = dma_lch_count;
} else {
dma_chan_count = 0;
return 0;
continue;
if (cpu_class_is_omap1()) {
- /* request_irq() doesn't like dev_id (ie. ch) being
- * zero, so we have to kludge around this. */
+ /*
+ * request_irq() doesn't like dev_id (ie. ch) being
+ * zero, so we have to kludge around this.
+ */
r = request_irq(omap1_dma_irq[ch],
omap1_dma_irq_handler, 0, "DMA",
(void *) (ch + 1));
}
}
- if (cpu_is_omap2430() || cpu_is_omap34xx())
+ if (cpu_is_omap2430() || cpu_is_omap34xx() || cpu_is_omap44xx())
omap_dma_set_global_params(DMA_DEFAULT_ARB_RATE,
DMA_DEFAULT_FIFO_DEPTH, 0);
- if (cpu_class_is_omap2())
- setup_irq(INT_24XX_SDMA_IRQ0, &omap24xx_dma_irq);
+ if (cpu_class_is_omap2()) {
+ int irq;
+ if (cpu_is_omap44xx())
+ irq = INT_44XX_SDMA_IRQ0;
+ else
+ irq = INT_24XX_SDMA_IRQ0;
+ setup_irq(irq, &omap24xx_dma_irq);
+ }
+
+ /* Enable smartidle idlemodes and autoidle */
+ if (cpu_is_omap34xx()) {
+ u32 v = dma_read(OCP_SYSCONFIG);
+ v &= ~(DMA_SYSCONFIG_MIDLEMODE_MASK |
+ DMA_SYSCONFIG_SIDLEMODE_MASK |
+ DMA_SYSCONFIG_AUTOIDLE);
+ v |= (DMA_SYSCONFIG_MIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+ DMA_SYSCONFIG_SIDLEMODE(DMA_IDLEMODE_SMARTIDLE) |
+ DMA_SYSCONFIG_AUTOIDLE);
+ dma_write(v , OCP_SYSCONFIG);
+ }
+
/* FIXME: Update LCD DMA to work on 24xx */
if (cpu_class_is_omap1()) {
arch_initcall(omap_init_dma);
-EXPORT_SYMBOL(omap_get_dma_src_pos);
-EXPORT_SYMBOL(omap_get_dma_dst_pos);
-EXPORT_SYMBOL(omap_get_dma_src_addr_counter);
-EXPORT_SYMBOL(omap_clear_dma);
-EXPORT_SYMBOL(omap_set_dma_priority);
-EXPORT_SYMBOL(omap_request_dma);
-EXPORT_SYMBOL(omap_free_dma);
-EXPORT_SYMBOL(omap_start_dma);
-EXPORT_SYMBOL(omap_stop_dma);
-EXPORT_SYMBOL(omap_set_dma_callback);
-EXPORT_SYMBOL(omap_enable_dma_irq);
-EXPORT_SYMBOL(omap_disable_dma_irq);
-
-EXPORT_SYMBOL(omap_set_dma_transfer_params);
-EXPORT_SYMBOL(omap_set_dma_color_mode);
-EXPORT_SYMBOL(omap_set_dma_write_mode);
-
-EXPORT_SYMBOL(omap_set_dma_src_params);
-EXPORT_SYMBOL(omap_set_dma_src_index);
-EXPORT_SYMBOL(omap_set_dma_src_data_pack);
-EXPORT_SYMBOL(omap_set_dma_src_burst_mode);
-
-EXPORT_SYMBOL(omap_set_dma_dest_params);
-EXPORT_SYMBOL(omap_set_dma_dest_index);
-EXPORT_SYMBOL(omap_set_dma_dest_data_pack);
-EXPORT_SYMBOL(omap_set_dma_dest_burst_mode);
+/*
+ * Reserve the omap SDMA channels using cmdline bootarg
+ * "omap_dma_reserve_ch=". The valid range is 1 to 32
+ */
+static int __init omap_dma_cmdline_reserve_ch(char *str)
+{
+ if (get_option(&str, &omap_dma_reserve_channels) != 1)
+ omap_dma_reserve_channels = 0;
+ return 1;
+}
-EXPORT_SYMBOL(omap_set_dma_params);
+__setup("omap_dma_reserve_ch=", omap_dma_cmdline_reserve_ch);
-EXPORT_SYMBOL(omap_dma_link_lch);
-EXPORT_SYMBOL(omap_dma_unlink_lch);
-
-EXPORT_SYMBOL(omap_request_lcd_dma);
-EXPORT_SYMBOL(omap_free_lcd_dma);
-EXPORT_SYMBOL(omap_enable_lcd_dma);
-EXPORT_SYMBOL(omap_setup_lcd_dma);
-EXPORT_SYMBOL(omap_stop_lcd_dma);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1);
-EXPORT_SYMBOL(omap_set_lcd_dma_single_transfer);
-EXPORT_SYMBOL(omap_set_lcd_dma_ext_controller);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_rotation);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_vxres);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_scale);
-EXPORT_SYMBOL(omap_set_lcd_dma_b1_mirror);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blobdiff