#include <linux/list.h>
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
-#include <linux/slab.h>
#include <linux/string.h>
#include <linux/sysdev.h>
#include <linux/amba/bus.h>
#include <linux/amba/kmi.h>
#include <linux/amba/clcd.h>
+#include <linux/amba/mmci.h>
+#include <linux/io.h>
+#include <linux/gfp.h>
-#include <asm/hardware.h>
-#include <asm/io.h>
+#include <asm/clkdev.h>
+#include <mach/clkdev.h>
+#include <mach/hardware.h>
#include <asm/irq.h>
#include <asm/setup.h>
#include <asm/mach-types.h>
#include <asm/hardware/icst525.h>
-#include <asm/arch/cm.h>
-#include <asm/arch/lm.h>
+#include <mach/cm.h>
+#include <mach/lm.h>
#include <asm/mach/arch.h>
#include <asm/mach/flash.h>
#include <asm/mach/irq.h>
-#include <asm/mach/mmc.h>
#include <asm/mach/map.h>
#include <asm/mach/time.h>
#include "common.h"
-#include "clock.h"
#define INTCP_PA_MMC_BASE 0x1c000000
#define INTCP_PA_AACI_BASE 0x1d000000
#define INTCP_PA_CLCD_BASE 0xc0000000
-#define INTCP_VA_CIC_BASE 0xf1000040
-#define INTCP_VA_PIC_BASE 0xf1400000
-#define INTCP_VA_SIC_BASE 0xfca00000
+#define INTCP_VA_CIC_BASE IO_ADDRESS(INTEGRATOR_HDR_BASE) + 0x40
+#define INTCP_VA_PIC_BASE IO_ADDRESS(INTEGRATOR_IC_BASE)
+#define INTCP_VA_SIC_BASE IO_ADDRESS(0xca000000)
#define INTCP_PA_ETH_BASE 0xc8000000
#define INTCP_ETH_SIZE 0x10
-#define INTCP_VA_CTRL_BASE 0xfcb00000
+#define INTCP_VA_CTRL_BASE IO_ADDRESS(0xcb000000)
#define INTCP_FLASHPROG 0x04
#define CINTEGRATOR_FLASHPROG_FLVPPEN (1 << 0)
#define CINTEGRATOR_FLASHPROG_FLWREN (1 << 1)
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = 0xfca00000,
+ .virtual = IO_ADDRESS(0xca000000),
.pfn = __phys_to_pfn(0xca000000),
.length = SZ_4K,
.type = MT_DEVICE
}, {
- .virtual = 0xfcb00000,
+ .virtual = IO_ADDRESS(0xcb000000),
.pfn = __phys_to_pfn(0xcb000000),
.length = SZ_4K,
.type = MT_DEVICE
cic_writel(1 << irq, INTCP_VA_CIC_BASE + IRQ_ENABLE_SET);
}
-static struct irqchip cic_chip = {
+static struct irq_chip cic_chip = {
+ .name = "CIC",
.ack = cic_mask_irq,
.mask = cic_mask_irq,
.unmask = cic_unmask_irq,
pic_writel(1 << irq, INTCP_VA_PIC_BASE + IRQ_ENABLE_SET);
}
-static struct irqchip pic_chip = {
+static struct irq_chip pic_chip = {
+ .name = "PIC",
.ack = pic_mask_irq,
.mask = pic_mask_irq,
.unmask = pic_unmask_irq,
sic_writel(1 << irq, INTCP_VA_SIC_BASE + IRQ_ENABLE_SET);
}
-static struct irqchip sic_chip = {
+static struct irq_chip sic_chip = {
+ .name = "SIC",
.ack = sic_mask_irq,
.mask = sic_mask_irq,
.unmask = sic_unmask_irq,
};
static void
-sic_handle_irq(unsigned int irq, struct irqdesc *desc, struct pt_regs *regs)
+sic_handle_irq(unsigned int irq, struct irq_desc *desc)
{
unsigned long status = sic_readl(INTCP_VA_SIC_BASE + IRQ_STATUS);
if (status == 0) {
- do_bad_IRQ(irq, desc, regs);
+ do_bad_IRQ(irq, desc);
return;
}
irq += IRQ_SIC_START;
- desc = irq_desc + irq;
- desc_handle_irq(irq, desc, regs);
+ generic_handle_irq(irq);
} while (status);
}
for (i = IRQ_PIC_START; i <= IRQ_PIC_END; i++) {
if (i == 11)
i = 22;
- if (i == IRQ_CP_CPPLDINT)
- i++;
if (i == 29)
break;
set_irq_chip(i, &pic_chip);
- set_irq_handler(i, do_level_IRQ);
+ set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
for (i = IRQ_CIC_START; i <= IRQ_CIC_END; i++) {
set_irq_chip(i, &cic_chip);
- set_irq_handler(i, do_level_IRQ);
+ set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID);
}
for (i = IRQ_SIC_START; i <= IRQ_SIC_END; i++) {
set_irq_chip(i, &sic_chip);
- set_irq_handler(i, do_level_IRQ);
+ set_irq_handler(i, handle_level_irq);
set_irq_flags(i, IRQF_VALID | IRQF_PROBE);
}
- set_irq_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
- pic_unmask_irq(IRQ_CP_CPPLDINT);
+ set_irq_chained_handler(IRQ_CP_CPPLDINT, sic_handle_irq);
}
/*
writel(0, CM_LOCK);
}
-static struct clk cp_clcd_clk = {
- .name = "CLCDCLK",
+static struct clk cp_auxclk = {
.params = &cp_auxvco_params,
.setvco = cp_auxvco_set,
};
-static struct clk cp_mmci_clk = {
- .name = "MCLK",
- .rate = 14745600,
+static struct clk_lookup cp_lookups[] = {
+ { /* CLCD */
+ .dev_id = "mb:c0",
+ .clk = &cp_auxclk,
+ },
};
/*
*/
static unsigned int mmc_status(struct device *dev)
{
- unsigned int status = readl(0xfca00004);
- writel(8, 0xfcb00008);
+ unsigned int status = readl(IO_ADDRESS(0xca000000) + 4);
+ writel(8, IO_ADDRESS(0xcb000000) + 8);
return status & 8;
}
-static struct mmc_platform_data mmc_data = {
+static struct mmci_platform_data mmc_data = {
.ocr_mask = MMC_VDD_32_33|MMC_VDD_33_34,
.status = mmc_status,
+ .gpio_wp = -1,
+ .gpio_cd = -1,
};
static struct amba_device mmc_device = {
.dev = {
- .bus_id = "mb:1c",
+ .init_name = "mb:1c",
.platform_data = &mmc_data,
},
.res = {
static struct amba_device aaci_device = {
.dev = {
- .bus_id = "mb:1d",
+ .init_name = "mb:1d",
},
.res = {
.start = INTCP_PA_AACI_BASE,
if (fb->fb.var.bits_per_pixel <= 8)
val = CM_CTRL_LCDMUXSEL_VGA_8421BPP;
else if (fb->fb.var.bits_per_pixel <= 16)
- val = CM_CTRL_LCDMUXSEL_VGA_16BPP;
+ val = CM_CTRL_LCDMUXSEL_VGA_16BPP
+ | CM_CTRL_LCDEN0 | CM_CTRL_LCDEN1
+ | CM_CTRL_STATIC1 | CM_CTRL_STATIC2;
else
val = 0; /* no idea for this, don't trust the docs */
static struct amba_device clcd_device = {
.dev = {
- .bus_id = "mb:c0",
+ .init_name = "mb:c0",
.coherent_dma_mask = ~0,
.platform_data = &clcd_data,
},
{
int i;
- clk_register(&cp_clcd_clk);
- clk_register(&cp_mmci_clk);
-
+ clkdev_add_table(cp_lookups, ARRAY_SIZE(cp_lookups));
platform_add_devices(intcp_devs, ARRAY_SIZE(intcp_devs));
for (i = 0; i < ARRAY_SIZE(amba_devs); i++) {
MACHINE_START(CINTEGRATOR, "ARM-IntegratorCP")
/* Maintainer: ARM Ltd/Deep Blue Solutions Ltd */
- .phys_ram = 0x00000000,
.phys_io = 0x16000000,
.io_pg_offst = ((0xf1600000) >> 18) & 0xfffc,
.boot_params = 0x00000100,