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   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  82                  "(0 = auto, 1 = none, 2 = POSBUF).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, bool, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, SCH},"
 129                          "{ATI, SB450},"
 130                          "{ATI, SB600},"
 131                          "{ATI, RS600},"
 132                          "{ATI, RS690},"
 133                          "{ATI, RS780},"
 134                          "{ATI, R600},"
 135                          "{ATI, RV630},"
 136                          "{ATI, RV610},"
 137                          "{ATI, RV670},"
 138                          "{ATI, RV635},"
 139                          "{ATI, RV620},"
 140                          "{ATI, RV770},"
 141                          "{VIA, VT8251},"
 142                          "{VIA, VT8237A},"
 143                          "{SiS, SIS966},"
 144                          "{ULI, M5461}}");
 145 MODULE_DESCRIPTION("Intel HDA driver");
 146
 147 #ifdef CONFIG_SND_VERBOSE_PRINTK
 148 #define SFX     /* nop */
 149 #else
 150 #define SFX     "hda-intel: "
 151 #endif
 152
 153 /*
 154  * registers
 155  */
 156 #define ICH6_REG_GCAP                   0x00
 157 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 158 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 159 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 160 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 161 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 162 #define ICH6_REG_VMIN                   0x02
 163 #define ICH6_REG_VMAJ                   0x03
 164 #define ICH6_REG_OUTPAY                 0x04
 165 #define ICH6_REG_INPAY                  0x06
 166 #define ICH6_REG_GCTL                   0x08
 167 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 168 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 169 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 170 #define ICH6_REG_WAKEEN                 0x0c
 171 #define ICH6_REG_STATESTS               0x0e
 172 #define ICH6_REG_GSTS                   0x10
 173 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 174 #define ICH6_REG_INTCTL                 0x20
 175 #define ICH6_REG_INTSTS                 0x24
 176 #define ICH6_REG_WALCLK                 0x30
 177 #define ICH6_REG_SYNC                   0x34
 178 #define ICH6_REG_CORBLBASE              0x40
 179 #define ICH6_REG_CORBUBASE              0x44
 180 #define ICH6_REG_CORBWP                 0x48
 181 #define ICH6_REG_CORBRP                 0x4a
 182 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 183 #define ICH6_REG_CORBCTL                0x4c
 184 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 185 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 186 #define ICH6_REG_CORBSTS                0x4d
 187 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 188 #define ICH6_REG_CORBSIZE               0x4e
 189
 190 #define ICH6_REG_RIRBLBASE              0x50
 191 #define ICH6_REG_RIRBUBASE              0x54
 192 #define ICH6_REG_RIRBWP                 0x58
 193 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 194 #define ICH6_REG_RINTCNT                0x5a
 195 #define ICH6_REG_RIRBCTL                0x5c
 196 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 197 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 198 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 199 #define ICH6_REG_RIRBSTS                0x5d
 200 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 201 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 202 #define ICH6_REG_RIRBSIZE               0x5e
 203
 204 #define ICH6_REG_IC                     0x60
 205 #define ICH6_REG_IR                     0x64
 206 #define ICH6_REG_IRS                    0x68
 207 #define   ICH6_IRS_VALID        (1<<1)
 208 #define   ICH6_IRS_BUSY         (1<<0)
 209
 210 #define ICH6_REG_DPLBASE                0x70
 211 #define ICH6_REG_DPUBASE                0x74
 212 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 213
 214 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 215 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 216
 217 /* stream register offsets from stream base */
 218 #define ICH6_REG_SD_CTL                 0x00
 219 #define ICH6_REG_SD_STS                 0x03
 220 #define ICH6_REG_SD_LPIB                0x04
 221 #define ICH6_REG_SD_CBL                 0x08
 222 #define ICH6_REG_SD_LVI                 0x0c
 223 #define ICH6_REG_SD_FIFOW               0x0e
 224 #define ICH6_REG_SD_FIFOSIZE            0x10
 225 #define ICH6_REG_SD_FORMAT              0x12
 226 #define ICH6_REG_SD_BDLPL               0x18
 227 #define ICH6_REG_SD_BDLPU               0x1c
 228
 229 /* PCI space */
 230 #define ICH6_PCIREG_TCSEL       0x44
 231
 232 /*
 233  * other constants
 234  */
 235
 236 /* max number of SDs */
 237 /* ICH, ATI and VIA have 4 playback and 4 capture */
 238 #define ICH6_NUM_CAPTURE        4
 239 #define ICH6_NUM_PLAYBACK       4
 240
 241 /* ULI has 6 playback and 5 capture */
 242 #define ULI_NUM_CAPTURE         5
 243 #define ULI_NUM_PLAYBACK        6
 244
 245 /* ATI HDMI has 1 playback and 0 capture */
 246 #define ATIHDMI_NUM_CAPTURE     0
 247 #define ATIHDMI_NUM_PLAYBACK    1
 248
 249 /* TERA has 4 playback and 3 capture */
 250 #define TERA_NUM_CAPTURE        3
 251 #define TERA_NUM_PLAYBACK       4
 252
 253 /* this number is statically defined for simplicity */
 254 #define MAX_AZX_DEV             16
 255
 256 /* max number of fragments - we may use more if allocating more pages for BDL */
 257 #define BDL_SIZE                4096
 258 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 259 #define AZX_MAX_FRAG            32
 260 /* max buffer size - no h/w limit, you can increase as you like */
 261 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 262 /* max number of PCM devics per card */
 263 #define AZX_MAX_PCMS            8
 264
 265 /* RIRB int mask: overrun[2], response[0] */
 266 #define RIRB_INT_RESPONSE       0x01
 267 #define RIRB_INT_OVERRUN        0x04
 268 #define RIRB_INT_MASK           0x05
 269
 270 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 271 #define AZX_MAX_CODECS          4
 272 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 273
 274 /* SD_CTL bits */
 275 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 276 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 277 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 278 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 279 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 280 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 281 #define SD_CTL_STREAM_TAG_SHIFT 20
 282
 283 /* SD_CTL and SD_STS */
 284 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 285 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 286 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 287 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 288                                  SD_INT_COMPLETE)
 289
 290 /* SD_STS */
 291 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 292
 293 /* INTCTL and INTSTS */
 294 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 295 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 296 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 297
 298 /* below are so far hardcoded - should read registers in future */
 299 #define ICH6_MAX_CORB_ENTRIES   256
 300 #define ICH6_MAX_RIRB_ENTRIES   256
 301
 302 /* position fix mode */
 303 enum {
 304         POS_FIX_AUTO,
 305         POS_FIX_LPIB,
 306         POS_FIX_POSBUF,
 307 };
 308
 309 /* Defines for ATI HD Audio support in SB450 south bridge */
 310 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 311 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 312
 313 /* Defines for Nvidia HDA support */
 314 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 315 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 316 #define NVIDIA_HDA_ISTRM_COH          0x4d
 317 #define NVIDIA_HDA_OSTRM_COH          0x4c
 318 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 319
 320 /* Defines for Intel SCH HDA snoop control */
 321 #define INTEL_SCH_HDA_DEVC      0x78
 322 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 323
 324 /* Define IN stream 0 FIFO size offset in VIA controller */
 325 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 326 /* Define VIA HD Audio Device ID*/
 327 #define VIA_HDAC_DEVICE_ID              0x3288
 328
 329 /* HD Audio class code */
 330 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 331
 332 /*
 333  */
 334
 335 struct azx_dev {
 336         struct snd_dma_buffer bdl; /* BDL buffer */
 337         u32 *posbuf;            /* position buffer pointer */
 338
 339         unsigned int bufsize;   /* size of the play buffer in bytes */
 340         unsigned int period_bytes; /* size of the period in bytes */
 341         unsigned int frags;     /* number for period in the play buffer */
 342         unsigned int fifo_size; /* FIFO size */
 343         unsigned long start_jiffies;    /* start + minimum jiffies */
 344         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 345
 346         void __iomem *sd_addr;  /* stream descriptor pointer */
 347
 348         u32 sd_int_sta_mask;    /* stream int status mask */
 349
 350         /* pcm support */
 351         struct snd_pcm_substream *substream;    /* assigned substream,
 352                                                  * set in PCM open
 353                                                  */
 354         unsigned int format_val;        /* format value to be set in the
 355                                          * controller and the codec
 356                                          */
 357         unsigned char stream_tag;       /* assigned stream */
 358         unsigned char index;            /* stream index */
 359         int device;                     /* last device number assigned to */
 360
 361         unsigned int opened :1;
 362         unsigned int running :1;
 363         unsigned int irq_pending :1;
 364         unsigned int start_flag: 1;     /* stream full start flag */
 365         /*
 366          * For VIA:
 367          *  A flag to ensure DMA position is 0
 368          *  when link position is not greater than FIFO size
 369          */
 370         unsigned int insufficient :1;
 371 };
 372
 373 /* CORB/RIRB */
 374 struct azx_rb {
 375         u32 *buf;               /* CORB/RIRB buffer
 376                                  * Each CORB entry is 4byte, RIRB is 8byte
 377                                  */
 378         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 379         /* for RIRB */
 380         unsigned short rp, wp;  /* read/write pointers */
 381         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 382         u32 res[AZX_MAX_CODECS];        /* last read value */
 383 };
 384
 385 struct azx {
 386         struct snd_card *card;
 387         struct pci_dev *pci;
 388         int dev_index;
 389
 390         /* chip type specific */
 391         int driver_type;
 392         int playback_streams;
 393         int playback_index_offset;
 394         int capture_streams;
 395         int capture_index_offset;
 396         int num_streams;
 397
 398         /* pci resources */
 399         unsigned long addr;
 400         void __iomem *remap_addr;
 401         int irq;
 402
 403         /* locks */
 404         spinlock_t reg_lock;
 405         struct mutex open_mutex;
 406
 407         /* streams (x num_streams) */
 408         struct azx_dev *azx_dev;
 409
 410         /* PCM */
 411         struct snd_pcm *pcm[AZX_MAX_PCMS];
 412
 413         /* HD codec */
 414         unsigned short codec_mask;
 415         int  codec_probe_mask; /* copied from probe_mask option */
 416         struct hda_bus *bus;
 417         unsigned int beep_mode;
 418
 419         /* CORB/RIRB */
 420         struct azx_rb corb;
 421         struct azx_rb rirb;
 422
 423         /* CORB/RIRB and position buffers */
 424         struct snd_dma_buffer rb;
 425         struct snd_dma_buffer posbuf;
 426
 427         /* flags */
 428         int position_fix;
 429         int poll_count;
 430         unsigned int running :1;
 431         unsigned int initialized :1;
 432         unsigned int single_cmd :1;
 433         unsigned int polling_mode :1;
 434         unsigned int msi :1;
 435         unsigned int irq_pending_warned :1;
 436         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_SCH,
 453         AZX_DRIVER_ATI,
 454         AZX_DRIVER_ATIHDMI,
 455         AZX_DRIVER_VIA,
 456         AZX_DRIVER_SIS,
 457         AZX_DRIVER_ULI,
 458         AZX_DRIVER_NVIDIA,
 459         AZX_DRIVER_TERA,
 460         AZX_DRIVER_GENERIC,
 461         AZX_NUM_DRIVERS, /* keep this as last entry */
 462 };
 463
 464 static char *driver_short_names[] __devinitdata = {
 465         [AZX_DRIVER_ICH] = "HDA Intel",
 466         [AZX_DRIVER_SCH] = "HDA Intel MID",
 467         [AZX_DRIVER_ATI] = "HDA ATI SB",
 468         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 469         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 470         [AZX_DRIVER_SIS] = "HDA SIS966",
 471         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 472         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 473         [AZX_DRIVER_TERA] = "HDA Teradici",
 474         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 475 };
 476
 477 /*
 478  * macros for easy use
 479  */
 480 #define azx_writel(chip,reg,value) \
 481         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 482 #define azx_readl(chip,reg) \
 483         readl((chip)->remap_addr + ICH6_REG_##reg)
 484 #define azx_writew(chip,reg,value) \
 485         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_readw(chip,reg) \
 487         readw((chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_writeb(chip,reg,value) \
 489         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_readb(chip,reg) \
 491         readb((chip)->remap_addr + ICH6_REG_##reg)
 492
 493 #define azx_sd_writel(dev,reg,value) \
 494         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 495 #define azx_sd_readl(dev,reg) \
 496         readl((dev)->sd_addr + ICH6_REG_##reg)
 497 #define azx_sd_writew(dev,reg,value) \
 498         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_readw(dev,reg) \
 500         readw((dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_writeb(dev,reg,value) \
 502         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_readb(dev,reg) \
 504         readb((dev)->sd_addr + ICH6_REG_##reg)
 505
 506 /* for pcm support */
 507 #define get_azx_dev(substream) (substream->runtime->private_data)
 508
 509 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 510 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 511 /*
 512  * Interface for HD codec
 513  */
 514
 515 /*
 516  * CORB / RIRB interface
 517  */
 518 static int azx_alloc_cmd_io(struct azx *chip)
 519 {
 520         int err;
 521
 522         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 523         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 524                                   snd_dma_pci_data(chip->pci),
 525                                   PAGE_SIZE, &chip->rb);
 526         if (err < 0) {
 527                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 528                 return err;
 529         }
 530         return 0;
 531 }
 532
 533 static void azx_init_cmd_io(struct azx *chip)
 534 {
 535         spin_lock_irq(&chip->reg_lock);
 536         /* CORB set up */
 537         chip->corb.addr = chip->rb.addr;
 538         chip->corb.buf = (u32 *)chip->rb.area;
 539         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 540         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 541
 542         /* set the corb size to 256 entries (ULI requires explicitly) */
 543         azx_writeb(chip, CORBSIZE, 0x02);
 544         /* set the corb write pointer to 0 */
 545         azx_writew(chip, CORBWP, 0);
 546         /* reset the corb hw read pointer */
 547         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 548         /* enable corb dma */
 549         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 550
 551         /* RIRB set up */
 552         chip->rirb.addr = chip->rb.addr + 2048;
 553         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 554         chip->rirb.wp = chip->rirb.rp = 0;
 555         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 556         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 557         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 558
 559         /* set the rirb size to 256 entries (ULI requires explicitly) */
 560         azx_writeb(chip, RIRBSIZE, 0x02);
 561         /* reset the rirb hw write pointer */
 562         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 563         /* set N=1, get RIRB response interrupt for new entry */
 564         azx_writew(chip, RINTCNT, 1);
 565         /* enable rirb dma and response irq */
 566         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 567         spin_unlock_irq(&chip->reg_lock);
 568 }
 569
 570 static void azx_free_cmd_io(struct azx *chip)
 571 {
 572         spin_lock_irq(&chip->reg_lock);
 573         /* disable ringbuffer DMAs */
 574         azx_writeb(chip, RIRBCTL, 0);
 575         azx_writeb(chip, CORBCTL, 0);
 576         spin_unlock_irq(&chip->reg_lock);
 577 }
 578
 579 static unsigned int azx_command_addr(u32 cmd)
 580 {
 581         unsigned int addr = cmd >> 28;
 582
 583         if (addr >= AZX_MAX_CODECS) {
 584                 snd_BUG();
 585                 addr = 0;
 586         }
 587
 588         return addr;
 589 }
 590
 591 static unsigned int azx_response_addr(u32 res)
 592 {
 593         unsigned int addr = res & 0xf;
 594
 595         if (addr >= AZX_MAX_CODECS) {
 596                 snd_BUG();
 597                 addr = 0;
 598         }
 599
 600         return addr;
 601 }
 602
 603 /* send a command */
 604 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 605 {
 606         struct azx *chip = bus->private_data;
 607         unsigned int addr = azx_command_addr(val);
 608         unsigned int wp;
 609
 610         spin_lock_irq(&chip->reg_lock);
 611
 612         /* add command to corb */
 613         wp = azx_readb(chip, CORBWP);
 614         wp++;
 615         wp %= ICH6_MAX_CORB_ENTRIES;
 616
 617         chip->rirb.cmds[addr]++;
 618         chip->corb.buf[wp] = cpu_to_le32(val);
 619         azx_writel(chip, CORBWP, wp);
 620
 621         spin_unlock_irq(&chip->reg_lock);
 622
 623         return 0;
 624 }
 625
 626 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 627
 628 /* retrieve RIRB entry - called from interrupt handler */
 629 static void azx_update_rirb(struct azx *chip)
 630 {
 631         unsigned int rp, wp;
 632         unsigned int addr;
 633         u32 res, res_ex;
 634
 635         wp = azx_readb(chip, RIRBWP);
 636         if (wp == chip->rirb.wp)
 637                 return;
 638         chip->rirb.wp = wp;
 639
 640         while (chip->rirb.rp != wp) {
 641                 chip->rirb.rp++;
 642                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 643
 644                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 645                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 646                 res = le32_to_cpu(chip->rirb.buf[rp]);
 647                 addr = azx_response_addr(res_ex);
 648                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 649                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 650                 else if (chip->rirb.cmds[addr]) {
 651                         chip->rirb.res[addr] = res;
 652                         smp_wmb();
 653                         chip->rirb.cmds[addr]--;
 654                 } else
 655                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 656                                    "last cmd=%#08x\n",
 657                                    res, res_ex,
 658                                    chip->last_cmd[addr]);
 659         }
 660 }
 661
 662 /* receive a response */
 663 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 664                                           unsigned int addr)
 665 {
 666         struct azx *chip = bus->private_data;
 667         unsigned long timeout;
 668         int do_poll = 0;
 669
 670  again:
 671         timeout = jiffies + msecs_to_jiffies(1000);
 672         for (;;) {
 673                 if (chip->polling_mode || do_poll) {
 674                         spin_lock_irq(&chip->reg_lock);
 675                         azx_update_rirb(chip);
 676                         spin_unlock_irq(&chip->reg_lock);
 677                 }
 678                 if (!chip->rirb.cmds[addr]) {
 679                         smp_rmb();
 680                         bus->rirb_error = 0;
 681
 682                         if (!do_poll)
 683                                 chip->poll_count = 0;
 684                         return chip->rirb.res[addr]; /* the last value */
 685                 }
 686                 if (time_after(jiffies, timeout))
 687                         break;
 688                 if (bus->needs_damn_long_delay)
 689                         msleep(2); /* temporary workaround */
 690                 else {
 691                         udelay(10);
 692                         cond_resched();
 693                 }
 694         }
 695
 696         if (!chip->polling_mode && chip->poll_count < 2) {
 697                 snd_printdd(SFX "azx_get_response timeout, "
 698                            "polling the codec once: last cmd=0x%08x\n",
 699                            chip->last_cmd[addr]);
 700                 do_poll = 1;
 701                 chip->poll_count++;
 702                 goto again;
 703         }
 704
 705
 706         if (!chip->polling_mode) {
 707                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 708                            "switching to polling mode: last cmd=0x%08x\n",
 709                            chip->last_cmd[addr]);
 710                 chip->polling_mode = 1;
 711                 goto again;
 712         }
 713
 714         if (chip->msi) {
 715                 snd_printk(KERN_WARNING SFX "No response from codec, "
 716                            "disabling MSI: last cmd=0x%08x\n",
 717                            chip->last_cmd[addr]);
 718                 free_irq(chip->irq, chip);
 719                 chip->irq = -1;
 720                 pci_disable_msi(chip->pci);
 721                 chip->msi = 0;
 722                 if (azx_acquire_irq(chip, 1) < 0) {
 723                         bus->rirb_error = 1;
 724                         return -1;
 725                 }
 726                 goto again;
 727         }
 728
 729         if (chip->probing) {
 730                 /* If this critical timeout happens during the codec probing
 731                  * phase, this is likely an access to a non-existing codec
 732                  * slot.  Better to return an error and reset the system.
 733                  */
 734                 return -1;
 735         }
 736
 737         /* a fatal communication error; need either to reset or to fallback
 738          * to the single_cmd mode
 739          */
 740         bus->rirb_error = 1;
 741         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 742                 bus->response_reset = 1;
 743                 return -1; /* give a chance to retry */
 744         }
 745
 746         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 747                    "switching to single_cmd mode: last cmd=0x%08x\n",
 748                    chip->last_cmd[addr]);
 749         chip->single_cmd = 1;
 750         bus->response_reset = 0;
 751         /* release CORB/RIRB */
 752         azx_free_cmd_io(chip);
 753         /* disable unsolicited responses */
 754         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 755         return -1;
 756 }
 757
 758 /*
 759  * Use the single immediate command instead of CORB/RIRB for simplicity
 760  *
 761  * Note: according to Intel, this is not preferred use.  The command was
 762  *       intended for the BIOS only, and may get confused with unsolicited
 763  *       responses.  So, we shouldn't use it for normal operation from the
 764  *       driver.
 765  *       I left the codes, however, for debugging/testing purposes.
 766  */
 767
 768 /* receive a response */
 769 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 770 {
 771         int timeout = 50;
 772
 773         while (timeout--) {
 774                 /* check IRV busy bit */
 775                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 776                         /* reuse rirb.res as the response return value */
 777                         chip->rirb.res[addr] = azx_readl(chip, IR);
 778                         return 0;
 779                 }
 780                 udelay(1);
 781         }
 782         if (printk_ratelimit())
 783                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 784                            azx_readw(chip, IRS));
 785         chip->rirb.res[addr] = -1;
 786         return -EIO;
 787 }
 788
 789 /* send a command */
 790 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 791 {
 792         struct azx *chip = bus->private_data;
 793         unsigned int addr = azx_command_addr(val);
 794         int timeout = 50;
 795
 796         bus->rirb_error = 0;
 797         while (timeout--) {
 798                 /* check ICB busy bit */
 799                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 800                         /* Clear IRV valid bit */
 801                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 802                                    ICH6_IRS_VALID);
 803                         azx_writel(chip, IC, val);
 804                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 805                                    ICH6_IRS_BUSY);
 806                         return azx_single_wait_for_response(chip, addr);
 807                 }
 808                 udelay(1);
 809         }
 810         if (printk_ratelimit())
 811                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 812                            azx_readw(chip, IRS), val);
 813         return -EIO;
 814 }
 815
 816 /* receive a response */
 817 static unsigned int azx_single_get_response(struct hda_bus *bus,
 818                                             unsigned int addr)
 819 {
 820         struct azx *chip = bus->private_data;
 821         return chip->rirb.res[addr];
 822 }
 823
 824 /*
 825  * The below are the main callbacks from hda_codec.
 826  *
 827  * They are just the skeleton to call sub-callbacks according to the
 828  * current setting of chip->single_cmd.
 829  */
 830
 831 /* send a command */
 832 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 833 {
 834         struct azx *chip = bus->private_data;
 835
 836         chip->last_cmd[azx_command_addr(val)] = val;
 837         if (chip->single_cmd)
 838                 return azx_single_send_cmd(bus, val);
 839         else
 840                 return azx_corb_send_cmd(bus, val);
 841 }
 842
 843 /* get a response */
 844 static unsigned int azx_get_response(struct hda_bus *bus,
 845                                      unsigned int addr)
 846 {
 847         struct azx *chip = bus->private_data;
 848         if (chip->single_cmd)
 849                 return azx_single_get_response(bus, addr);
 850         else
 851                 return azx_rirb_get_response(bus, addr);
 852 }
 853
 854 #ifdef CONFIG_SND_HDA_POWER_SAVE
 855 static void azx_power_notify(struct hda_bus *bus);
 856 #endif
 857
 858 /* reset codec link */
 859 static int azx_reset(struct azx *chip)
 860 {
 861         int count;
 862
 863         /* clear STATESTS */
 864         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 865
 866         /* reset controller */
 867         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 868
 869         count = 50;
 870         while (azx_readb(chip, GCTL) && --count)
 871                 msleep(1);
 872
 873         /* delay for >= 100us for codec PLL to settle per spec
 874          * Rev 0.9 section 5.5.1
 875          */
 876         msleep(1);
 877
 878         /* Bring controller out of reset */
 879         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 880
 881         count = 50;
 882         while (!azx_readb(chip, GCTL) && --count)
 883                 msleep(1);
 884
 885         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 886         msleep(1);
 887
 888         /* check to see if controller is ready */
 889         if (!azx_readb(chip, GCTL)) {
 890                 snd_printd(SFX "azx_reset: controller not ready!\n");
 891                 return -EBUSY;
 892         }
 893
 894         /* Accept unsolicited responses */
 895         if (!chip->single_cmd)
 896                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 897                            ICH6_GCTL_UNSOL);
 898
 899         /* detect codecs */
 900         if (!chip->codec_mask) {
 901                 chip->codec_mask = azx_readw(chip, STATESTS);
 902                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 903         }
 904
 905         return 0;
 906 }
 907
 908
 909 /*
 910  * Lowlevel interface
 911  */
 912
 913 /* enable interrupts */
 914 static void azx_int_enable(struct azx *chip)
 915 {
 916         /* enable controller CIE and GIE */
 917         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 918                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 919 }
 920
 921 /* disable interrupts */
 922 static void azx_int_disable(struct azx *chip)
 923 {
 924         int i;
 925
 926         /* disable interrupts in stream descriptor */
 927         for (i = 0; i < chip->num_streams; i++) {
 928                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 929                 azx_sd_writeb(azx_dev, SD_CTL,
 930                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 931         }
 932
 933         /* disable SIE for all streams */
 934         azx_writeb(chip, INTCTL, 0);
 935
 936         /* disable controller CIE and GIE */
 937         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 938                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 939 }
 940
 941 /* clear interrupts */
 942 static void azx_int_clear(struct azx *chip)
 943 {
 944         int i;
 945
 946         /* clear stream status */
 947         for (i = 0; i < chip->num_streams; i++) {
 948                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 949                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 950         }
 951
 952         /* clear STATESTS */
 953         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 954
 955         /* clear rirb status */
 956         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 957
 958         /* clear int status */
 959         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 960 }
 961
 962 /* start a stream */
 963 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 964 {
 965         /*
 966          * Before stream start, initialize parameter
 967          */
 968         azx_dev->insufficient = 1;
 969
 970         /* enable SIE */
 971         azx_writeb(chip, INTCTL,
 972                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 973         /* set DMA start and interrupt mask */
 974         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 975                       SD_CTL_DMA_START | SD_INT_MASK);
 976 }
 977
 978 /* stop DMA */
 979 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 980 {
 981         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 982                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 983         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 984 }
 985
 986 /* stop a stream */
 987 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 988 {
 989         azx_stream_clear(chip, azx_dev);
 990         /* disable SIE */
 991         azx_writeb(chip, INTCTL,
 992                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 993 }
 994
 995
 996 /*
 997  * reset and start the controller registers
 998  */
 999 static void azx_init_chip(struct azx *chip)
1000 {
1001         if (chip->initialized)
1002                 return;
1003
1004         /* reset controller */
1005         azx_reset(chip);
1006
1007         /* initialize interrupts */
1008         azx_int_clear(chip);
1009         azx_int_enable(chip);
1010
1011         /* initialize the codec command I/O */
1012         if (!chip->single_cmd)
1013                 azx_init_cmd_io(chip);
1014
1015         /* program the position buffer */
1016         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1017         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1018
1019         chip->initialized = 1;
1020 }
1021
1022 /*
1023  * initialize the PCI registers
1024  */
1025 /* update bits in a PCI register byte */
1026 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1027                             unsigned char mask, unsigned char val)
1028 {
1029         unsigned char data;
1030
1031         pci_read_config_byte(pci, reg, &data);
1032         data &= ~mask;
1033         data |= (val & mask);
1034         pci_write_config_byte(pci, reg, data);
1035 }
1036
1037 static void azx_init_pci(struct azx *chip)
1038 {
1039         unsigned short snoop;
1040
1041         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1042          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1043          * Ensuring these bits are 0 clears playback static on some HD Audio
1044          * codecs
1045          */
1046         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1047
1048         switch (chip->driver_type) {
1049         case AZX_DRIVER_ATI:
1050                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1051                 update_pci_byte(chip->pci,
1052                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1053                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1054                 break;
1055         case AZX_DRIVER_NVIDIA:
1056                 /* For NVIDIA HDA, enable snoop */
1057                 update_pci_byte(chip->pci,
1058                                 NVIDIA_HDA_TRANSREG_ADDR,
1059                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1060                 update_pci_byte(chip->pci,
1061                                 NVIDIA_HDA_ISTRM_COH,
1062                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1063                 update_pci_byte(chip->pci,
1064                                 NVIDIA_HDA_OSTRM_COH,
1065                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1066                 break;
1067         case AZX_DRIVER_SCH:
1068                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1069                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1070                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1071                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1072                         pci_read_config_word(chip->pci,
1073                                 INTEL_SCH_HDA_DEVC, &snoop);
1074                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1075                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1076                                 ? "Failed" : "OK");
1077                 }
1078                 break;
1079
1080         }
1081 }
1082
1083
1084 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1085
1086 /*
1087  * interrupt handler
1088  */
1089 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1090 {
1091         struct azx *chip = dev_id;
1092         struct azx_dev *azx_dev;
1093         u32 status;
1094         int i, ok;
1095
1096         spin_lock(&chip->reg_lock);
1097
1098         status = azx_readl(chip, INTSTS);
1099         if (status == 0) {
1100                 spin_unlock(&chip->reg_lock);
1101                 return IRQ_NONE;
1102         }
1103
1104         for (i = 0; i < chip->num_streams; i++) {
1105                 azx_dev = &chip->azx_dev[i];
1106                 if (status & azx_dev->sd_int_sta_mask) {
1107                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1108                         if (!azx_dev->substream || !azx_dev->running)
1109                                 continue;
1110                         /* check whether this IRQ is really acceptable */
1111                         ok = azx_position_ok(chip, azx_dev);
1112                         if (ok == 1) {
1113                                 azx_dev->irq_pending = 0;
1114                                 spin_unlock(&chip->reg_lock);
1115                                 snd_pcm_period_elapsed(azx_dev->substream);
1116                                 spin_lock(&chip->reg_lock);
1117                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1118                                 /* bogus IRQ, process it later */
1119                                 azx_dev->irq_pending = 1;
1120                                 queue_work(chip->bus->workq,
1121                                            &chip->irq_pending_work);
1122                         }
1123                 }
1124         }
1125
1126         /* clear rirb int */
1127         status = azx_readb(chip, RIRBSTS);
1128         if (status & RIRB_INT_MASK) {
1129                 if (status & RIRB_INT_RESPONSE)
1130                         azx_update_rirb(chip);
1131                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1132         }
1133
1134 #if 0
1135         /* clear state status int */
1136         if (azx_readb(chip, STATESTS) & 0x04)
1137                 azx_writeb(chip, STATESTS, 0x04);
1138 #endif
1139         spin_unlock(&chip->reg_lock);
1140
1141         return IRQ_HANDLED;
1142 }
1143
1144
1145 /*
1146  * set up a BDL entry
1147  */
1148 static int setup_bdle(struct snd_pcm_substream *substream,
1149                       struct azx_dev *azx_dev, u32 **bdlp,
1150                       int ofs, int size, int with_ioc)
1151 {
1152         u32 *bdl = *bdlp;
1153
1154         while (size > 0) {
1155                 dma_addr_t addr;
1156                 int chunk;
1157
1158                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1159                         return -EINVAL;
1160
1161                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1162                 /* program the address field of the BDL entry */
1163                 bdl[0] = cpu_to_le32((u32)addr);
1164                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1165                 /* program the size field of the BDL entry */
1166                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1167                 bdl[2] = cpu_to_le32(chunk);
1168                 /* program the IOC to enable interrupt
1169                  * only when the whole fragment is processed
1170                  */
1171                 size -= chunk;
1172                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1173                 bdl += 4;
1174                 azx_dev->frags++;
1175                 ofs += chunk;
1176         }
1177         *bdlp = bdl;
1178         return ofs;
1179 }
1180
1181 /*
1182  * set up BDL entries
1183  */
1184 static int azx_setup_periods(struct azx *chip,
1185                              struct snd_pcm_substream *substream,
1186                              struct azx_dev *azx_dev)
1187 {
1188         u32 *bdl;
1189         int i, ofs, periods, period_bytes;
1190         int pos_adj;
1191
1192         /* reset BDL address */
1193         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1194         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1195
1196         period_bytes = azx_dev->period_bytes;
1197         periods = azx_dev->bufsize / period_bytes;
1198
1199         /* program the initial BDL entries */
1200         bdl = (u32 *)azx_dev->bdl.area;
1201         ofs = 0;
1202         azx_dev->frags = 0;
1203         pos_adj = bdl_pos_adj[chip->dev_index];
1204         if (pos_adj > 0) {
1205                 struct snd_pcm_runtime *runtime = substream->runtime;
1206                 int pos_align = pos_adj;
1207                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1208                 if (!pos_adj)
1209                         pos_adj = pos_align;
1210                 else
1211                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1212                                 pos_align;
1213                 pos_adj = frames_to_bytes(runtime, pos_adj);
1214                 if (pos_adj >= period_bytes) {
1215                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1216                                    bdl_pos_adj[chip->dev_index]);
1217                         pos_adj = 0;
1218                 } else {
1219                         ofs = setup_bdle(substream, azx_dev,
1220                                          &bdl, ofs, pos_adj, 1);
1221                         if (ofs < 0)
1222                                 goto error;
1223                 }
1224         } else
1225                 pos_adj = 0;
1226         for (i = 0; i < periods; i++) {
1227                 if (i == periods - 1 && pos_adj)
1228                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1229                                          period_bytes - pos_adj, 0);
1230                 else
1231                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1232                                          period_bytes, 1);
1233                 if (ofs < 0)
1234                         goto error;
1235         }
1236         return 0;
1237
1238  error:
1239         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1240                    azx_dev->bufsize, period_bytes);
1241         return -EINVAL;
1242 }
1243
1244 /* reset stream */
1245 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1246 {
1247         unsigned char val;
1248         int timeout;
1249
1250         azx_stream_clear(chip, azx_dev);
1251
1252         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1253                       SD_CTL_STREAM_RESET);
1254         udelay(3);
1255         timeout = 300;
1256         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1257                --timeout)
1258                 ;
1259         val &= ~SD_CTL_STREAM_RESET;
1260         azx_sd_writeb(azx_dev, SD_CTL, val);
1261         udelay(3);
1262
1263         timeout = 300;
1264         /* waiting for hardware to report that the stream is out of reset */
1265         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1266                --timeout)
1267                 ;
1268
1269         /* reset first position - may not be synced with hw at this time */
1270         *azx_dev->posbuf = 0;
1271 }
1272
1273 /*
1274  * set up the SD for streaming
1275  */
1276 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1277 {
1278         /* make sure the run bit is zero for SD */
1279         azx_stream_clear(chip, azx_dev);
1280         /* program the stream_tag */
1281         azx_sd_writel(azx_dev, SD_CTL,
1282                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1283                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1284
1285         /* program the length of samples in cyclic buffer */
1286         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1287
1288         /* program the stream format */
1289         /* this value needs to be the same as the one programmed */
1290         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1291
1292         /* program the stream LVI (last valid index) of the BDL */
1293         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1294
1295         /* program the BDL address */
1296         /* lower BDL address */
1297         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1298         /* upper BDL address */
1299         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1300
1301         /* enable the position buffer */
1302         if (chip->position_fix == POS_FIX_POSBUF ||
1303             chip->position_fix == POS_FIX_AUTO ||
1304             chip->via_dmapos_patch) {
1305                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1306                         azx_writel(chip, DPLBASE,
1307                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1308         }
1309
1310         /* set the interrupt enable bits in the descriptor control register */
1311         azx_sd_writel(azx_dev, SD_CTL,
1312                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1313
1314         return 0;
1315 }
1316
1317 /*
1318  * Probe the given codec address
1319  */
1320 static int probe_codec(struct azx *chip, int addr)
1321 {
1322         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1323                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1324         unsigned int res;
1325
1326         mutex_lock(&chip->bus->cmd_mutex);
1327         chip->probing = 1;
1328         azx_send_cmd(chip->bus, cmd);
1329         res = azx_get_response(chip->bus, addr);
1330         chip->probing = 0;
1331         mutex_unlock(&chip->bus->cmd_mutex);
1332         if (res == -1)
1333                 return -EIO;
1334         snd_printdd(SFX "codec #%d probed OK\n", addr);
1335         return 0;
1336 }
1337
1338 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1339                                  struct hda_pcm *cpcm);
1340 static void azx_stop_chip(struct azx *chip);
1341
1342 static void azx_bus_reset(struct hda_bus *bus)
1343 {
1344         struct azx *chip = bus->private_data;
1345
1346         bus->in_reset = 1;
1347         azx_stop_chip(chip);
1348         azx_init_chip(chip);
1349 #ifdef CONFIG_PM
1350         if (chip->initialized) {
1351                 int i;
1352
1353                 for (i = 0; i < AZX_MAX_PCMS; i++)
1354                         snd_pcm_suspend_all(chip->pcm[i]);
1355                 snd_hda_suspend(chip->bus);
1356                 snd_hda_resume(chip->bus);
1357         }
1358 #endif
1359         bus->in_reset = 0;
1360 }
1361
1362 /*
1363  * Codec initialization
1364  */
1365
1366 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1367 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1368         [AZX_DRIVER_TERA] = 1,
1369 };
1370
1371 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1372 {
1373         struct hda_bus_template bus_temp;
1374         int c, codecs, err;
1375         int max_slots;
1376
1377         memset(&bus_temp, 0, sizeof(bus_temp));
1378         bus_temp.private_data = chip;
1379         bus_temp.modelname = model;
1380         bus_temp.pci = chip->pci;
1381         bus_temp.ops.command = azx_send_cmd;
1382         bus_temp.ops.get_response = azx_get_response;
1383         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1384         bus_temp.ops.bus_reset = azx_bus_reset;
1385 #ifdef CONFIG_SND_HDA_POWER_SAVE
1386         bus_temp.power_save = &power_save;
1387         bus_temp.ops.pm_notify = azx_power_notify;
1388 #endif
1389
1390         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1391         if (err < 0)
1392                 return err;
1393
1394         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1395                 chip->bus->needs_damn_long_delay = 1;
1396
1397         codecs = 0;
1398         max_slots = azx_max_codecs[chip->driver_type];
1399         if (!max_slots)
1400                 max_slots = AZX_MAX_CODECS;
1401
1402         /* First try to probe all given codec slots */
1403         for (c = 0; c < max_slots; c++) {
1404                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1405                         if (probe_codec(chip, c) < 0) {
1406                                 /* Some BIOSen give you wrong codec addresses
1407                                  * that don't exist
1408                                  */
1409                                 snd_printk(KERN_WARNING SFX
1410                                            "Codec #%d probe error; "
1411                                            "disabling it...\n", c);
1412                                 chip->codec_mask &= ~(1 << c);
1413                                 /* More badly, accessing to a non-existing
1414                                  * codec often screws up the controller chip,
1415                                  * and distrubs the further communications.
1416                                  * Thus if an error occurs during probing,
1417                                  * better to reset the controller chip to
1418                                  * get back to the sanity state.
1419                                  */
1420                                 azx_stop_chip(chip);
1421                                 azx_init_chip(chip);
1422                         }
1423                 }
1424         }
1425
1426         /* Then create codec instances */
1427         for (c = 0; c < max_slots; c++) {
1428                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1429                         struct hda_codec *codec;
1430                         err = snd_hda_codec_new(chip->bus, c, &codec);
1431                         if (err < 0)
1432                                 continue;
1433                         codec->beep_mode = chip->beep_mode;
1434                         codecs++;
1435                 }
1436         }
1437         if (!codecs) {
1438                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1439                 return -ENXIO;
1440         }
1441         return 0;
1442 }
1443
1444 /* configure each codec instance */
1445 static int __devinit azx_codec_configure(struct azx *chip)
1446 {
1447         struct hda_codec *codec;
1448         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1449                 snd_hda_codec_configure(codec);
1450         }
1451         return 0;
1452 }
1453
1454
1455 /*
1456  * PCM support
1457  */
1458
1459 /* assign a stream for the PCM */
1460 static inline struct azx_dev *
1461 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1462 {
1463         int dev, i, nums;
1464         struct azx_dev *res = NULL;
1465
1466         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1467                 dev = chip->playback_index_offset;
1468                 nums = chip->playback_streams;
1469         } else {
1470                 dev = chip->capture_index_offset;
1471                 nums = chip->capture_streams;
1472         }
1473         for (i = 0; i < nums; i++, dev++)
1474                 if (!chip->azx_dev[dev].opened) {
1475                         res = &chip->azx_dev[dev];
1476                         if (res->device == substream->pcm->device)
1477                                 break;
1478                 }
1479         if (res) {
1480                 res->opened = 1;
1481                 res->device = substream->pcm->device;
1482         }
1483         return res;
1484 }
1485
1486 /* release the assigned stream */
1487 static inline void azx_release_device(struct azx_dev *azx_dev)
1488 {
1489         azx_dev->opened = 0;
1490 }
1491
1492 static struct snd_pcm_hardware azx_pcm_hw = {
1493         .info =                 (SNDRV_PCM_INFO_MMAP |
1494                                  SNDRV_PCM_INFO_INTERLEAVED |
1495                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1496                                  SNDRV_PCM_INFO_MMAP_VALID |
1497                                  /* No full-resume yet implemented */
1498                                  /* SNDRV_PCM_INFO_RESUME |*/
1499                                  SNDRV_PCM_INFO_PAUSE |
1500                                  SNDRV_PCM_INFO_SYNC_START),
1501         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1502         .rates =                SNDRV_PCM_RATE_48000,
1503         .rate_min =             48000,
1504         .rate_max =             48000,
1505         .channels_min =         2,
1506         .channels_max =         2,
1507         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1508         .period_bytes_min =     128,
1509         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1510         .periods_min =          2,
1511         .periods_max =          AZX_MAX_FRAG,
1512         .fifo_size =            0,
1513 };
1514
1515 struct azx_pcm {
1516         struct azx *chip;
1517         struct hda_codec *codec;
1518         struct hda_pcm_stream *hinfo[2];
1519 };
1520
1521 static int azx_pcm_open(struct snd_pcm_substream *substream)
1522 {
1523         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1524         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1525         struct azx *chip = apcm->chip;
1526         struct azx_dev *azx_dev;
1527         struct snd_pcm_runtime *runtime = substream->runtime;
1528         unsigned long flags;
1529         int err;
1530
1531         mutex_lock(&chip->open_mutex);
1532         azx_dev = azx_assign_device(chip, substream);
1533         if (azx_dev == NULL) {
1534                 mutex_unlock(&chip->open_mutex);
1535                 return -EBUSY;
1536         }
1537         runtime->hw = azx_pcm_hw;
1538         runtime->hw.channels_min = hinfo->channels_min;
1539         runtime->hw.channels_max = hinfo->channels_max;
1540         runtime->hw.formats = hinfo->formats;
1541         runtime->hw.rates = hinfo->rates;
1542         snd_pcm_limit_hw_rates(runtime);
1543         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1544         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1545                                    128);
1546         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1547                                    128);
1548         snd_hda_power_up(apcm->codec);
1549         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1550         if (err < 0) {
1551                 azx_release_device(azx_dev);
1552                 snd_hda_power_down(apcm->codec);
1553                 mutex_unlock(&chip->open_mutex);
1554                 return err;
1555         }
1556         snd_pcm_limit_hw_rates(runtime);
1557         /* sanity check */
1558         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1559             snd_BUG_ON(!runtime->hw.channels_max) ||
1560             snd_BUG_ON(!runtime->hw.formats) ||
1561             snd_BUG_ON(!runtime->hw.rates)) {
1562                 azx_release_device(azx_dev);
1563                 hinfo->ops.close(hinfo, apcm->codec, substream);
1564                 snd_hda_power_down(apcm->codec);
1565                 mutex_unlock(&chip->open_mutex);
1566                 return -EINVAL;
1567         }
1568         spin_lock_irqsave(&chip->reg_lock, flags);
1569         azx_dev->substream = substream;
1570         azx_dev->running = 0;
1571         spin_unlock_irqrestore(&chip->reg_lock, flags);
1572
1573         runtime->private_data = azx_dev;
1574         snd_pcm_set_sync(substream);
1575         mutex_unlock(&chip->open_mutex);
1576         return 0;
1577 }
1578
1579 static int azx_pcm_close(struct snd_pcm_substream *substream)
1580 {
1581         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1582         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1583         struct azx *chip = apcm->chip;
1584         struct azx_dev *azx_dev = get_azx_dev(substream);
1585         unsigned long flags;
1586
1587         mutex_lock(&chip->open_mutex);
1588         spin_lock_irqsave(&chip->reg_lock, flags);
1589         azx_dev->substream = NULL;
1590         azx_dev->running = 0;
1591         spin_unlock_irqrestore(&chip->reg_lock, flags);
1592         azx_release_device(azx_dev);
1593         hinfo->ops.close(hinfo, apcm->codec, substream);
1594         snd_hda_power_down(apcm->codec);
1595         mutex_unlock(&chip->open_mutex);
1596         return 0;
1597 }
1598
1599 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1600                              struct snd_pcm_hw_params *hw_params)
1601 {
1602         struct azx_dev *azx_dev = get_azx_dev(substream);
1603
1604         azx_dev->bufsize = 0;
1605         azx_dev->period_bytes = 0;
1606         azx_dev->format_val = 0;
1607         return snd_pcm_lib_malloc_pages(substream,
1608                                         params_buffer_bytes(hw_params));
1609 }
1610
1611 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1612 {
1613         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1614         struct azx_dev *azx_dev = get_azx_dev(substream);
1615         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1616
1617         /* reset BDL address */
1618         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1619         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1620         azx_sd_writel(azx_dev, SD_CTL, 0);
1621         azx_dev->bufsize = 0;
1622         azx_dev->period_bytes = 0;
1623         azx_dev->format_val = 0;
1624
1625         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1626
1627         return snd_pcm_lib_free_pages(substream);
1628 }
1629
1630 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1631 {
1632         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1633         struct azx *chip = apcm->chip;
1634         struct azx_dev *azx_dev = get_azx_dev(substream);
1635         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1636         struct snd_pcm_runtime *runtime = substream->runtime;
1637         unsigned int bufsize, period_bytes, format_val;
1638         int err;
1639
1640         azx_stream_reset(chip, azx_dev);
1641         format_val = snd_hda_calc_stream_format(runtime->rate,
1642                                                 runtime->channels,
1643                                                 runtime->format,
1644                                                 hinfo->maxbps);
1645         if (!format_val) {
1646                 snd_printk(KERN_ERR SFX
1647                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1648                            runtime->rate, runtime->channels, runtime->format);
1649                 return -EINVAL;
1650         }
1651
1652         bufsize = snd_pcm_lib_buffer_bytes(substream);
1653         period_bytes = snd_pcm_lib_period_bytes(substream);
1654
1655         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1656                     bufsize, format_val);
1657
1658         if (bufsize != azx_dev->bufsize ||
1659             period_bytes != azx_dev->period_bytes ||
1660             format_val != azx_dev->format_val) {
1661                 azx_dev->bufsize = bufsize;
1662                 azx_dev->period_bytes = period_bytes;
1663                 azx_dev->format_val = format_val;
1664                 err = azx_setup_periods(chip, substream, azx_dev);
1665                 if (err < 0)
1666                         return err;
1667         }
1668
1669         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1670                                                 (runtime->rate * 2);
1671         azx_setup_controller(chip, azx_dev);
1672         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1673                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1674         else
1675                 azx_dev->fifo_size = 0;
1676
1677         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1678                                   azx_dev->format_val, substream);
1679 }
1680
1681 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1682 {
1683         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1684         struct azx *chip = apcm->chip;
1685         struct azx_dev *azx_dev;
1686         struct snd_pcm_substream *s;
1687         int rstart = 0, start, nsync = 0, sbits = 0;
1688         int nwait, timeout;
1689
1690         switch (cmd) {
1691         case SNDRV_PCM_TRIGGER_START:
1692                 rstart = 1;
1693         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1694         case SNDRV_PCM_TRIGGER_RESUME:
1695                 start = 1;
1696                 break;
1697         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1698         case SNDRV_PCM_TRIGGER_SUSPEND:
1699         case SNDRV_PCM_TRIGGER_STOP:
1700                 start = 0;
1701                 break;
1702         default:
1703                 return -EINVAL;
1704         }
1705
1706         snd_pcm_group_for_each_entry(s, substream) {
1707                 if (s->pcm->card != substream->pcm->card)
1708                         continue;
1709                 azx_dev = get_azx_dev(s);
1710                 sbits |= 1 << azx_dev->index;
1711                 nsync++;
1712                 snd_pcm_trigger_done(s, substream);
1713         }
1714
1715         spin_lock(&chip->reg_lock);
1716         if (nsync > 1) {
1717                 /* first, set SYNC bits of corresponding streams */
1718                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1719         }
1720         snd_pcm_group_for_each_entry(s, substream) {
1721                 if (s->pcm->card != substream->pcm->card)
1722                         continue;
1723                 azx_dev = get_azx_dev(s);
1724                 if (rstart) {
1725                         azx_dev->start_flag = 1;
1726                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1727                 }
1728                 if (start)
1729                         azx_stream_start(chip, azx_dev);
1730                 else
1731                         azx_stream_stop(chip, azx_dev);
1732                 azx_dev->running = start;
1733         }
1734         spin_unlock(&chip->reg_lock);
1735         if (start) {
1736                 if (nsync == 1)
1737                         return 0;
1738                 /* wait until all FIFOs get ready */
1739                 for (timeout = 5000; timeout; timeout--) {
1740                         nwait = 0;
1741                         snd_pcm_group_for_each_entry(s, substream) {
1742                                 if (s->pcm->card != substream->pcm->card)
1743                                         continue;
1744                                 azx_dev = get_azx_dev(s);
1745                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1746                                       SD_STS_FIFO_READY))
1747                                         nwait++;
1748                         }
1749                         if (!nwait)
1750                                 break;
1751                         cpu_relax();
1752                 }
1753         } else {
1754                 /* wait until all RUN bits are cleared */
1755                 for (timeout = 5000; timeout; timeout--) {
1756                         nwait = 0;
1757                         snd_pcm_group_for_each_entry(s, substream) {
1758                                 if (s->pcm->card != substream->pcm->card)
1759                                         continue;
1760                                 azx_dev = get_azx_dev(s);
1761                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1762                                     SD_CTL_DMA_START)
1763                                         nwait++;
1764                         }
1765                         if (!nwait)
1766                                 break;
1767                         cpu_relax();
1768                 }
1769         }
1770         if (nsync > 1) {
1771                 spin_lock(&chip->reg_lock);
1772                 /* reset SYNC bits */
1773                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1774                 spin_unlock(&chip->reg_lock);
1775         }
1776         return 0;
1777 }
1778
1779 /* get the current DMA position with correction on VIA chips */
1780 static unsigned int azx_via_get_position(struct azx *chip,
1781                                          struct azx_dev *azx_dev)
1782 {
1783         unsigned int link_pos, mini_pos, bound_pos;
1784         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1785         unsigned int fifo_size;
1786
1787         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1788         if (azx_dev->index >= 4) {
1789                 /* Playback, no problem using link position */
1790                 return link_pos;
1791         }
1792
1793         /* Capture */
1794         /* For new chipset,
1795          * use mod to get the DMA position just like old chipset
1796          */
1797         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1798         mod_dma_pos %= azx_dev->period_bytes;
1799
1800         /* azx_dev->fifo_size can't get FIFO size of in stream.
1801          * Get from base address + offset.
1802          */
1803         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1804
1805         if (azx_dev->insufficient) {
1806                 /* Link position never gather than FIFO size */
1807                 if (link_pos <= fifo_size)
1808                         return 0;
1809
1810                 azx_dev->insufficient = 0;
1811         }
1812
1813         if (link_pos <= fifo_size)
1814                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1815         else
1816                 mini_pos = link_pos - fifo_size;
1817
1818         /* Find nearest previous boudary */
1819         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1820         mod_link_pos = link_pos % azx_dev->period_bytes;
1821         if (mod_link_pos >= fifo_size)
1822                 bound_pos = link_pos - mod_link_pos;
1823         else if (mod_dma_pos >= mod_mini_pos)
1824                 bound_pos = mini_pos - mod_mini_pos;
1825         else {
1826                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1827                 if (bound_pos >= azx_dev->bufsize)
1828                         bound_pos = 0;
1829         }
1830
1831         /* Calculate real DMA position we want */
1832         return bound_pos + mod_dma_pos;
1833 }
1834
1835 static unsigned int azx_get_position(struct azx *chip,
1836                                      struct azx_dev *azx_dev)
1837 {
1838         unsigned int pos;
1839
1840         if (chip->via_dmapos_patch)
1841                 pos = azx_via_get_position(chip, azx_dev);
1842         else if (chip->position_fix == POS_FIX_POSBUF ||
1843                  chip->position_fix == POS_FIX_AUTO) {
1844                 /* use the position buffer */
1845                 pos = le32_to_cpu(*azx_dev->posbuf);
1846         } else {
1847                 /* read LPIB */
1848                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1849         }
1850         if (pos >= azx_dev->bufsize)
1851                 pos = 0;
1852         return pos;
1853 }
1854
1855 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1856 {
1857         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1858         struct azx *chip = apcm->chip;
1859         struct azx_dev *azx_dev = get_azx_dev(substream);
1860         return bytes_to_frames(substream->runtime,
1861                                azx_get_position(chip, azx_dev));
1862 }
1863
1864 /*
1865  * Check whether the current DMA position is acceptable for updating
1866  * periods.  Returns non-zero if it's OK.
1867  *
1868  * Many HD-audio controllers appear pretty inaccurate about
1869  * the update-IRQ timing.  The IRQ is issued before actually the
1870  * data is processed.  So, we need to process it afterwords in a
1871  * workqueue.
1872  */
1873 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1874 {
1875         unsigned int pos;
1876
1877         if (azx_dev->start_flag &&
1878             time_before_eq(jiffies, azx_dev->start_jiffies))
1879                 return -1;      /* bogus (too early) interrupt */
1880         azx_dev->start_flag = 0;
1881
1882         pos = azx_get_position(chip, azx_dev);
1883         if (chip->position_fix == POS_FIX_AUTO) {
1884                 if (!pos) {
1885                         printk(KERN_WARNING
1886                                "hda-intel: Invalid position buffer, "
1887                                "using LPIB read method instead.\n");
1888                         chip->position_fix = POS_FIX_LPIB;
1889                         pos = azx_get_position(chip, azx_dev);
1890                 } else
1891                         chip->position_fix = POS_FIX_POSBUF;
1892         }
1893
1894         if (!bdl_pos_adj[chip->dev_index])
1895                 return 1; /* no delayed ack */
1896         if (azx_dev->period_bytes == 0) {
1897                 printk(KERN_WARNING
1898                        "hda-intel: Divide by zero was avoided "
1899                        "in azx_dev->period_bytes.\n");
1900                 return 0;
1901         }
1902         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1903                 return 0; /* NG - it's below the period boundary */
1904         return 1; /* OK, it's fine */
1905 }
1906
1907 /*
1908  * The work for pending PCM period updates.
1909  */
1910 static void azx_irq_pending_work(struct work_struct *work)
1911 {
1912         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1913         int i, pending;
1914
1915         if (!chip->irq_pending_warned) {
1916                 printk(KERN_WARNING
1917                        "hda-intel: IRQ timing workaround is activated "
1918                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1919                        chip->card->number);
1920                 chip->irq_pending_warned = 1;
1921         }
1922
1923         for (;;) {
1924                 pending = 0;
1925                 spin_lock_irq(&chip->reg_lock);
1926                 for (i = 0; i < chip->num_streams; i++) {
1927                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1928                         if (!azx_dev->irq_pending ||
1929                             !azx_dev->substream ||
1930                             !azx_dev->running)
1931                                 continue;
1932                         if (azx_position_ok(chip, azx_dev)) {
1933                                 azx_dev->irq_pending = 0;
1934                                 spin_unlock(&chip->reg_lock);
1935                                 snd_pcm_period_elapsed(azx_dev->substream);
1936                                 spin_lock(&chip->reg_lock);
1937                         } else
1938                                 pending++;
1939                 }
1940                 spin_unlock_irq(&chip->reg_lock);
1941                 if (!pending)
1942                         return;
1943                 cond_resched();
1944         }
1945 }
1946
1947 /* clear irq_pending flags and assure no on-going workq */
1948 static void azx_clear_irq_pending(struct azx *chip)
1949 {
1950         int i;
1951
1952         spin_lock_irq(&chip->reg_lock);
1953         for (i = 0; i < chip->num_streams; i++)
1954                 chip->azx_dev[i].irq_pending = 0;
1955         spin_unlock_irq(&chip->reg_lock);
1956 }
1957
1958 static struct snd_pcm_ops azx_pcm_ops = {
1959         .open = azx_pcm_open,
1960         .close = azx_pcm_close,
1961         .ioctl = snd_pcm_lib_ioctl,
1962         .hw_params = azx_pcm_hw_params,
1963         .hw_free = azx_pcm_hw_free,
1964         .prepare = azx_pcm_prepare,
1965         .trigger = azx_pcm_trigger,
1966         .pointer = azx_pcm_pointer,
1967         .page = snd_pcm_sgbuf_ops_page,
1968 };
1969
1970 static void azx_pcm_free(struct snd_pcm *pcm)
1971 {
1972         struct azx_pcm *apcm = pcm->private_data;
1973         if (apcm) {
1974                 apcm->chip->pcm[pcm->device] = NULL;
1975                 kfree(apcm);
1976         }
1977 }
1978
1979 static int
1980 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1981                       struct hda_pcm *cpcm)
1982 {
1983         struct azx *chip = bus->private_data;
1984         struct snd_pcm *pcm;
1985         struct azx_pcm *apcm;
1986         int pcm_dev = cpcm->device;
1987         int s, err;
1988
1989         if (pcm_dev >= AZX_MAX_PCMS) {
1990                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1991                            pcm_dev);
1992                 return -EINVAL;
1993         }
1994         if (chip->pcm[pcm_dev]) {
1995                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1996                 return -EBUSY;
1997         }
1998         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1999                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2000                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2001                           &pcm);
2002         if (err < 0)
2003                 return err;
2004         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2005         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2006         if (apcm == NULL)
2007                 return -ENOMEM;
2008         apcm->chip = chip;
2009         apcm->codec = codec;
2010         pcm->private_data = apcm;
2011         pcm->private_free = azx_pcm_free;
2012         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2013                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2014         chip->pcm[pcm_dev] = pcm;
2015         cpcm->pcm = pcm;
2016         for (s = 0; s < 2; s++) {
2017                 apcm->hinfo[s] = &cpcm->stream[s];
2018                 if (cpcm->stream[s].substreams)
2019                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2020         }
2021         /* buffer pre-allocation */
2022         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2023                                               snd_dma_pci_data(chip->pci),
2024                                               1024 * 64, 32 * 1024 * 1024);
2025         return 0;
2026 }
2027
2028 /*
2029  * mixer creation - all stuff is implemented in hda module
2030  */
2031 static int __devinit azx_mixer_create(struct azx *chip)
2032 {
2033         return snd_hda_build_controls(chip->bus);
2034 }
2035
2036
2037 /*
2038  * initialize SD streams
2039  */
2040 static int __devinit azx_init_stream(struct azx *chip)
2041 {
2042         int i;
2043
2044         /* initialize each stream (aka device)
2045          * assign the starting bdl address to each stream (device)
2046          * and initialize
2047          */
2048         for (i = 0; i < chip->num_streams; i++) {
2049                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2050                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2051                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2052                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2053                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2054                 azx_dev->sd_int_sta_mask = 1 << i;
2055                 /* stream tag: must be non-zero and unique */
2056                 azx_dev->index = i;
2057                 azx_dev->stream_tag = i + 1;
2058         }
2059
2060         return 0;
2061 }
2062
2063 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2064 {
2065         if (request_irq(chip->pci->irq, azx_interrupt,
2066                         chip->msi ? 0 : IRQF_SHARED,
2067                         "hda_intel", chip)) {
2068                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2069                        "disabling device\n", chip->pci->irq);
2070                 if (do_disconnect)
2071                         snd_card_disconnect(chip->card);
2072                 return -1;
2073         }
2074         chip->irq = chip->pci->irq;
2075         pci_intx(chip->pci, !chip->msi);
2076         return 0;
2077 }
2078
2079
2080 static void azx_stop_chip(struct azx *chip)
2081 {
2082         if (!chip->initialized)
2083                 return;
2084
2085         /* disable interrupts */
2086         azx_int_disable(chip);
2087         azx_int_clear(chip);
2088
2089         /* disable CORB/RIRB */
2090         azx_free_cmd_io(chip);
2091
2092         /* disable position buffer */
2093         azx_writel(chip, DPLBASE, 0);
2094         azx_writel(chip, DPUBASE, 0);
2095
2096         chip->initialized = 0;
2097 }
2098
2099 #ifdef CONFIG_SND_HDA_POWER_SAVE
2100 /* power-up/down the controller */
2101 static void azx_power_notify(struct hda_bus *bus)
2102 {
2103         struct azx *chip = bus->private_data;
2104         struct hda_codec *c;
2105         int power_on = 0;
2106
2107         list_for_each_entry(c, &bus->codec_list, list) {
2108                 if (c->power_on) {
2109                         power_on = 1;
2110                         break;
2111                 }
2112         }
2113         if (power_on)
2114                 azx_init_chip(chip);
2115         else if (chip->running && power_save_controller &&
2116                  !bus->power_keep_link_on)
2117                 azx_stop_chip(chip);
2118 }
2119 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2120
2121 #ifdef CONFIG_PM
2122 /*
2123  * power management
2124  */
2125
2126 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2127 {
2128         struct hda_codec *codec;
2129
2130         list_for_each_entry(codec, &bus->codec_list, list) {
2131                 if (snd_hda_codec_needs_resume(codec))
2132                         return 1;
2133         }
2134         return 0;
2135 }
2136
2137 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2138 {
2139         struct snd_card *card = pci_get_drvdata(pci);
2140         struct azx *chip = card->private_data;
2141         int i;
2142
2143         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2144         azx_clear_irq_pending(chip);
2145         for (i = 0; i < AZX_MAX_PCMS; i++)
2146                 snd_pcm_suspend_all(chip->pcm[i]);
2147         if (chip->initialized)
2148                 snd_hda_suspend(chip->bus);
2149         azx_stop_chip(chip);
2150         if (chip->irq >= 0) {
2151                 free_irq(chip->irq, chip);
2152                 chip->irq = -1;
2153         }
2154         if (chip->msi)
2155                 pci_disable_msi(chip->pci);
2156         pci_disable_device(pci);
2157         pci_save_state(pci);
2158         pci_set_power_state(pci, pci_choose_state(pci, state));
2159         return 0;
2160 }
2161
2162 static int azx_resume(struct pci_dev *pci)
2163 {
2164         struct snd_card *card = pci_get_drvdata(pci);
2165         struct azx *chip = card->private_data;
2166
2167         pci_set_power_state(pci, PCI_D0);
2168         pci_restore_state(pci);
2169         if (pci_enable_device(pci) < 0) {
2170                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2171                        "disabling device\n");
2172                 snd_card_disconnect(card);
2173                 return -EIO;
2174         }
2175         pci_set_master(pci);
2176         if (chip->msi)
2177                 if (pci_enable_msi(pci) < 0)
2178                         chip->msi = 0;
2179         if (azx_acquire_irq(chip, 1) < 0)
2180                 return -EIO;
2181         azx_init_pci(chip);
2182
2183         if (snd_hda_codecs_inuse(chip->bus))
2184                 azx_init_chip(chip);
2185
2186         snd_hda_resume(chip->bus);
2187         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2188         return 0;
2189 }
2190 #endif /* CONFIG_PM */
2191
2192
2193 /*
2194  * reboot notifier for hang-up problem at power-down
2195  */
2196 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2197 {
2198         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2199         snd_hda_bus_reboot_notify(chip->bus);
2200         azx_stop_chip(chip);
2201         return NOTIFY_OK;
2202 }
2203
2204 static void azx_notifier_register(struct azx *chip)
2205 {
2206         chip->reboot_notifier.notifier_call = azx_halt;
2207         register_reboot_notifier(&chip->reboot_notifier);
2208 }
2209
2210 static void azx_notifier_unregister(struct azx *chip)
2211 {
2212         if (chip->reboot_notifier.notifier_call)
2213                 unregister_reboot_notifier(&chip->reboot_notifier);
2214 }
2215
2216 /*
2217  * destructor
2218  */
2219 static int azx_free(struct azx *chip)
2220 {
2221         int i;
2222
2223         azx_notifier_unregister(chip);
2224
2225         if (chip->initialized) {
2226                 azx_clear_irq_pending(chip);
2227                 for (i = 0; i < chip->num_streams; i++)
2228                         azx_stream_stop(chip, &chip->azx_dev[i]);
2229                 azx_stop_chip(chip);
2230         }
2231
2232         if (chip->irq >= 0)
2233                 free_irq(chip->irq, (void*)chip);
2234         if (chip->msi)
2235                 pci_disable_msi(chip->pci);
2236         if (chip->remap_addr)
2237                 iounmap(chip->remap_addr);
2238
2239         if (chip->azx_dev) {
2240                 for (i = 0; i < chip->num_streams; i++)
2241                         if (chip->azx_dev[i].bdl.area)
2242                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2243         }
2244         if (chip->rb.area)
2245                 snd_dma_free_pages(&chip->rb);
2246         if (chip->posbuf.area)
2247                 snd_dma_free_pages(&chip->posbuf);
2248         pci_release_regions(chip->pci);
2249         pci_disable_device(chip->pci);
2250         kfree(chip->azx_dev);
2251         kfree(chip);
2252
2253         return 0;
2254 }
2255
2256 static int azx_dev_free(struct snd_device *device)
2257 {
2258         return azx_free(device->device_data);
2259 }
2260
2261 /*
2262  * white/black-listing for position_fix
2263  */
2264 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2265         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2266         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2267         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2268         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2269         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2270         {}
2271 };
2272
2273 static int __devinit check_position_fix(struct azx *chip, int fix)
2274 {
2275         const struct snd_pci_quirk *q;
2276
2277         switch (fix) {
2278         case POS_FIX_LPIB:
2279         case POS_FIX_POSBUF:
2280                 return fix;
2281         }
2282
2283         /* Check VIA/ATI HD Audio Controller exist */
2284         switch (chip->driver_type) {
2285         case AZX_DRIVER_VIA:
2286         case AZX_DRIVER_ATI:
2287                 chip->via_dmapos_patch = 1;
2288                 /* Use link position directly, avoid any transfer problem. */
2289                 return POS_FIX_LPIB;
2290         }
2291         chip->via_dmapos_patch = 0;
2292
2293         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2294         if (q) {
2295                 printk(KERN_INFO
2296                        "hda_intel: position_fix set to %d "
2297                        "for device %04x:%04x\n",
2298                        q->value, q->subvendor, q->subdevice);
2299                 return q->value;
2300         }
2301         return POS_FIX_AUTO;
2302 }
2303
2304 /*
2305  * black-lists for probe_mask
2306  */
2307 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2308         /* Thinkpad often breaks the controller communication when accessing
2309          * to the non-working (or non-existing) modem codec slot.
2310          */
2311         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2312         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2313         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2314         /* broken BIOS */
2315         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2316         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2317         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2318         /* forced codec slots */
2319         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2320         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2321         {}
2322 };
2323
2324 #define AZX_FORCE_CODEC_MASK    0x100
2325
2326 static void __devinit check_probe_mask(struct azx *chip, int dev)
2327 {
2328         const struct snd_pci_quirk *q;
2329
2330         chip->codec_probe_mask = probe_mask[dev];
2331         if (chip->codec_probe_mask == -1) {
2332                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2333                 if (q) {
2334                         printk(KERN_INFO
2335                                "hda_intel: probe_mask set to 0x%x "
2336                                "for device %04x:%04x\n",
2337                                q->value, q->subvendor, q->subdevice);
2338                         chip->codec_probe_mask = q->value;
2339                 }
2340         }
2341
2342         /* check forced option */
2343         if (chip->codec_probe_mask != -1 &&
2344             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2345                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2346                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2347                        chip->codec_mask);
2348         }
2349 }
2350
2351 /*
2352  * white/black-list for enable_msi
2353  */
2354 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2355         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2356         SND_PCI_QUIRK(0x1043, 0x829c, "ASUS", 0), /* nvidia */
2357         {}
2358 };
2359
2360 static void __devinit check_msi(struct azx *chip)
2361 {
2362         const struct snd_pci_quirk *q;
2363
2364         if (enable_msi >= 0) {
2365                 chip->msi = !!enable_msi;
2366                 return;
2367         }
2368         chip->msi = 1;  /* enable MSI as default */
2369         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2370         if (q) {
2371                 printk(KERN_INFO
2372                        "hda_intel: msi for device %04x:%04x set to %d\n",
2373                        q->subvendor, q->subdevice, q->value);
2374                 chip->msi = q->value;
2375         }
2376 }
2377
2378
2379 /*
2380  * constructor
2381  */
2382 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2383                                 int dev, int driver_type,
2384                                 struct azx **rchip)
2385 {
2386         struct azx *chip;
2387         int i, err;
2388         unsigned short gcap;
2389         static struct snd_device_ops ops = {
2390                 .dev_free = azx_dev_free,
2391         };
2392
2393         *rchip = NULL;
2394
2395         err = pci_enable_device(pci);
2396         if (err < 0)
2397                 return err;
2398
2399         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2400         if (!chip) {
2401                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2402                 pci_disable_device(pci);
2403                 return -ENOMEM;
2404         }
2405
2406         spin_lock_init(&chip->reg_lock);
2407         mutex_init(&chip->open_mutex);
2408         chip->card = card;
2409         chip->pci = pci;
2410         chip->irq = -1;
2411         chip->driver_type = driver_type;
2412         check_msi(chip);
2413         chip->dev_index = dev;
2414         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2415
2416         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2417         check_probe_mask(chip, dev);
2418
2419         chip->single_cmd = single_cmd;
2420
2421         if (bdl_pos_adj[dev] < 0) {
2422                 switch (chip->driver_type) {
2423                 case AZX_DRIVER_ICH:
2424                         bdl_pos_adj[dev] = 1;
2425                         break;
2426                 default:
2427                         bdl_pos_adj[dev] = 32;
2428                         break;
2429                 }
2430         }
2431
2432 #if BITS_PER_LONG != 64
2433         /* Fix up base address on ULI M5461 */
2434         if (chip->driver_type == AZX_DRIVER_ULI) {
2435                 u16 tmp3;
2436                 pci_read_config_word(pci, 0x40, &tmp3);
2437                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2438                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2439         }
2440 #endif
2441
2442         err = pci_request_regions(pci, "ICH HD audio");
2443         if (err < 0) {
2444                 kfree(chip);
2445                 pci_disable_device(pci);
2446                 return err;
2447         }
2448
2449         chip->addr = pci_resource_start(pci, 0);
2450         chip->remap_addr = pci_ioremap_bar(pci, 0);
2451         if (chip->remap_addr == NULL) {
2452                 snd_printk(KERN_ERR SFX "ioremap error\n");
2453                 err = -ENXIO;
2454                 goto errout;
2455         }
2456
2457         if (chip->msi)
2458                 if (pci_enable_msi(pci) < 0)
2459                         chip->msi = 0;
2460
2461         if (azx_acquire_irq(chip, 0) < 0) {
2462                 err = -EBUSY;
2463                 goto errout;
2464         }
2465
2466         pci_set_master(pci);
2467         synchronize_irq(chip->irq);
2468
2469         gcap = azx_readw(chip, GCAP);
2470         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2471
2472         /* disable SB600 64bit support for safety */
2473         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2474             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2475                 struct pci_dev *p_smbus;
2476                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2477                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2478                                          NULL);
2479                 if (p_smbus) {
2480                         if (p_smbus->revision < 0x30)
2481                                 gcap &= ~ICH6_GCAP_64OK;
2482                         pci_dev_put(p_smbus);
2483                 }
2484         }
2485
2486         /* disable 64bit DMA address for Teradici */
2487         /* it does not work with device 6549:1200 subsys e4a2:040b */
2488         if (chip->driver_type == AZX_DRIVER_TERA)
2489                 gcap &= ~ICH6_GCAP_64OK;
2490
2491         /* allow 64bit DMA address if supported by H/W */
2492         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2493                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2494         else {
2495                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2496                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2497         }
2498
2499         /* read number of streams from GCAP register instead of using
2500          * hardcoded value
2501          */
2502         chip->capture_streams = (gcap >> 8) & 0x0f;
2503         chip->playback_streams = (gcap >> 12) & 0x0f;
2504         if (!chip->playback_streams && !chip->capture_streams) {
2505                 /* gcap didn't give any info, switching to old method */
2506
2507                 switch (chip->driver_type) {
2508                 case AZX_DRIVER_ULI:
2509                         chip->playback_streams = ULI_NUM_PLAYBACK;
2510                         chip->capture_streams = ULI_NUM_CAPTURE;
2511                         break;
2512                 case AZX_DRIVER_ATIHDMI:
2513                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2514                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2515                         break;
2516                 case AZX_DRIVER_GENERIC:
2517                 default:
2518                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2519                         chip->capture_streams = ICH6_NUM_CAPTURE;
2520                         break;
2521                 }
2522         }
2523         chip->capture_index_offset = 0;
2524         chip->playback_index_offset = chip->capture_streams;
2525         chip->num_streams = chip->playback_streams + chip->capture_streams;
2526         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2527                                 GFP_KERNEL);
2528         if (!chip->azx_dev) {
2529                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2530                 goto errout;
2531         }
2532
2533         for (i = 0; i < chip->num_streams; i++) {
2534                 /* allocate memory for the BDL for each stream */
2535                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2536                                           snd_dma_pci_data(chip->pci),
2537                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2538                 if (err < 0) {
2539                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2540                         goto errout;
2541                 }
2542         }
2543         /* allocate memory for the position buffer */
2544         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2545                                   snd_dma_pci_data(chip->pci),
2546                                   chip->num_streams * 8, &chip->posbuf);
2547         if (err < 0) {
2548                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2549                 goto errout;
2550         }
2551         /* allocate CORB/RIRB */
2552         err = azx_alloc_cmd_io(chip);
2553         if (err < 0)
2554                 goto errout;
2555
2556         /* initialize streams */
2557         azx_init_stream(chip);
2558
2559         /* initialize chip */
2560         azx_init_pci(chip);
2561         azx_init_chip(chip);
2562
2563         /* codec detection */
2564         if (!chip->codec_mask) {
2565                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2566                 err = -ENODEV;
2567                 goto errout;
2568         }
2569
2570         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2571         if (err <0) {
2572                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2573                 goto errout;
2574         }
2575
2576         strcpy(card->driver, "HDA-Intel");
2577         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2578                 sizeof(card->shortname));
2579         snprintf(card->longname, sizeof(card->longname),
2580                  "%s at 0x%lx irq %i",
2581                  card->shortname, chip->addr, chip->irq);
2582
2583         *rchip = chip;
2584         return 0;
2585
2586  errout:
2587         azx_free(chip);
2588         return err;
2589 }
2590
2591 static void power_down_all_codecs(struct azx *chip)
2592 {
2593 #ifdef CONFIG_SND_HDA_POWER_SAVE
2594         /* The codecs were powered up in snd_hda_codec_new().
2595          * Now all initialization done, so turn them down if possible
2596          */
2597         struct hda_codec *codec;
2598         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2599                 snd_hda_power_down(codec);
2600         }
2601 #endif
2602 }
2603
2604 static int __devinit azx_probe(struct pci_dev *pci,
2605                                const struct pci_device_id *pci_id)
2606 {
2607         static int dev;
2608         struct snd_card *card;
2609         struct azx *chip;
2610         int err;
2611
2612         if (dev >= SNDRV_CARDS)
2613                 return -ENODEV;
2614         if (!enable[dev]) {
2615                 dev++;
2616                 return -ENOENT;
2617         }
2618
2619         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2620         if (err < 0) {
2621                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2622                 return err;
2623         }
2624
2625         /* set this here since it's referred in snd_hda_load_patch() */
2626         snd_card_set_dev(card, &pci->dev);
2627
2628         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2629         if (err < 0)
2630                 goto out_free;
2631         card->private_data = chip;
2632
2633 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2634         chip->beep_mode = beep_mode[dev];
2635 #endif
2636
2637         /* create codec instances */
2638         err = azx_codec_create(chip, model[dev]);
2639         if (err < 0)
2640                 goto out_free;
2641 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2642         if (patch[dev]) {
2643                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2644                            patch[dev]);
2645                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2646                 if (err < 0)
2647                         goto out_free;
2648         }
2649 #endif
2650         if (!probe_only[dev]) {
2651                 err = azx_codec_configure(chip);
2652                 if (err < 0)
2653                         goto out_free;
2654         }
2655
2656         /* create PCM streams */
2657         err = snd_hda_build_pcms(chip->bus);
2658         if (err < 0)
2659                 goto out_free;
2660
2661         /* create mixer controls */
2662         err = azx_mixer_create(chip);
2663         if (err < 0)
2664                 goto out_free;
2665
2666         err = snd_card_register(card);
2667         if (err < 0)
2668                 goto out_free;
2669
2670         pci_set_drvdata(pci, card);
2671         chip->running = 1;
2672         power_down_all_codecs(chip);
2673         azx_notifier_register(chip);
2674
2675         dev++;
2676         return err;
2677 out_free:
2678         snd_card_free(card);
2679         return err;
2680 }
2681
2682 static void __devexit azx_remove(struct pci_dev *pci)
2683 {
2684         snd_card_free(pci_get_drvdata(pci));
2685         pci_set_drvdata(pci, NULL);
2686 }
2687
2688 /* PCI IDs */
2689 static struct pci_device_id azx_ids[] = {
2690         /* ICH 6..10 */
2691         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2692         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2693         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2694         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2695         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2696         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2697         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2698         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2699         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2700         /* PCH */
2701         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2702         /* SCH */
2703         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2704         /* ATI SB 450/600 */
2705         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2706         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2707         /* ATI HDMI */
2708         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2709         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2710         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2711         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2712         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2713         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2714         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2715         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2716         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2717         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2718         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2719         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2720         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2721         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2722         /* VIA VT8251/VT8237A */
2723         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2724         /* SIS966 */
2725         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2726         /* ULI M5461 */
2727         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2728         /* NVIDIA MCP */
2729         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2730         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2731         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2732         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2733         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2734         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2735         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2736         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2737         { PCI_DEVICE(0x10de, 0x0590), .driver_data = AZX_DRIVER_NVIDIA },
2738         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2739         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2740         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2741         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2742         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2743         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2744         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2745         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2746         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2747         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2748         { PCI_DEVICE(0x10de, 0x0be2), .driver_data = AZX_DRIVER_NVIDIA },
2749         { PCI_DEVICE(0x10de, 0x0be3), .driver_data = AZX_DRIVER_NVIDIA },
2750         { PCI_DEVICE(0x10de, 0x0be4), .driver_data = AZX_DRIVER_NVIDIA },
2751         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2752         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2753         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2754         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2755         /* Teradici */
2756         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2757         /* Creative X-Fi (CA0110-IBG) */
2758 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2759         /* the following entry conflicts with snd-ctxfi driver,
2760          * as ctxfi driver mutates from HD-audio to native mode with
2761          * a special command sequence.
2762          */
2763         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2764           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2765           .class_mask = 0xffffff,
2766           .driver_data = AZX_DRIVER_GENERIC },
2767 #else
2768         /* this entry seems still valid -- i.e. without emu20kx chip */
2769         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2770 #endif
2771         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2772         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2773           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2774           .class_mask = 0xffffff,
2775           .driver_data = AZX_DRIVER_GENERIC },
2776         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2777           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2778           .class_mask = 0xffffff,
2779           .driver_data = AZX_DRIVER_GENERIC },
2780         { 0, }
2781 };
2782 MODULE_DEVICE_TABLE(pci, azx_ids);
2783
2784 /* pci_driver definition */
2785 static struct pci_driver driver = {
2786         .name = "HDA Intel",
2787         .id_table = azx_ids,
2788         .probe = azx_probe,
2789         .remove = __devexit_p(azx_remove),
2790 #ifdef CONFIG_PM
2791         .suspend = azx_suspend,
2792         .resume = azx_resume,
2793 #endif
2794 };
2795
2796 static int __init alsa_card_azx_init(void)
2797 {
2798         return pci_register_driver(&driver);
2799 }
2800
2801 static void __exit alsa_card_azx_exit(void)
2802 {
2803         pci_unregister_driver(&driver);
2804 }
2805
2806 module_init(alsa_card_azx_init)
2807 module_exit(alsa_card_azx_exit)