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   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  82                  "(0 = auto, 1 = none, 2 = POSBUF).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, bool, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, SCH},"
 130                          "{ATI, SB450},"
 131                          "{ATI, SB600},"
 132                          "{ATI, RS600},"
 133                          "{ATI, RS690},"
 134                          "{ATI, RS780},"
 135                          "{ATI, R600},"
 136                          "{ATI, RV630},"
 137                          "{ATI, RV610},"
 138                          "{ATI, RV670},"
 139                          "{ATI, RV635},"
 140                          "{ATI, RV620},"
 141                          "{ATI, RV770},"
 142                          "{VIA, VT8251},"
 143                          "{VIA, VT8237A},"
 144                          "{SiS, SIS966},"
 145                          "{ULI, M5461}}");
 146 MODULE_DESCRIPTION("Intel HDA driver");
 147
 148 #ifdef CONFIG_SND_VERBOSE_PRINTK
 149 #define SFX     /* nop */
 150 #else
 151 #define SFX     "hda-intel: "
 152 #endif
 153
 154 /*
 155  * registers
 156  */
 157 #define ICH6_REG_GCAP                   0x00
 158 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 159 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 160 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 161 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 162 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 163 #define ICH6_REG_VMIN                   0x02
 164 #define ICH6_REG_VMAJ                   0x03
 165 #define ICH6_REG_OUTPAY                 0x04
 166 #define ICH6_REG_INPAY                  0x06
 167 #define ICH6_REG_GCTL                   0x08
 168 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 169 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 170 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 171 #define ICH6_REG_WAKEEN                 0x0c
 172 #define ICH6_REG_STATESTS               0x0e
 173 #define ICH6_REG_GSTS                   0x10
 174 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 175 #define ICH6_REG_INTCTL                 0x20
 176 #define ICH6_REG_INTSTS                 0x24
 177 #define ICH6_REG_WALCLK                 0x30
 178 #define ICH6_REG_SYNC                   0x34
 179 #define ICH6_REG_CORBLBASE              0x40
 180 #define ICH6_REG_CORBUBASE              0x44
 181 #define ICH6_REG_CORBWP                 0x48
 182 #define ICH6_REG_CORBRP                 0x4a
 183 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 184 #define ICH6_REG_CORBCTL                0x4c
 185 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 186 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 187 #define ICH6_REG_CORBSTS                0x4d
 188 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 189 #define ICH6_REG_CORBSIZE               0x4e
 190
 191 #define ICH6_REG_RIRBLBASE              0x50
 192 #define ICH6_REG_RIRBUBASE              0x54
 193 #define ICH6_REG_RIRBWP                 0x58
 194 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 195 #define ICH6_REG_RINTCNT                0x5a
 196 #define ICH6_REG_RIRBCTL                0x5c
 197 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 198 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 199 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 200 #define ICH6_REG_RIRBSTS                0x5d
 201 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 202 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 203 #define ICH6_REG_RIRBSIZE               0x5e
 204
 205 #define ICH6_REG_IC                     0x60
 206 #define ICH6_REG_IR                     0x64
 207 #define ICH6_REG_IRS                    0x68
 208 #define   ICH6_IRS_VALID        (1<<1)
 209 #define   ICH6_IRS_BUSY         (1<<0)
 210
 211 #define ICH6_REG_DPLBASE                0x70
 212 #define ICH6_REG_DPUBASE                0x74
 213 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 214
 215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 217
 218 /* stream register offsets from stream base */
 219 #define ICH6_REG_SD_CTL                 0x00
 220 #define ICH6_REG_SD_STS                 0x03
 221 #define ICH6_REG_SD_LPIB                0x04
 222 #define ICH6_REG_SD_CBL                 0x08
 223 #define ICH6_REG_SD_LVI                 0x0c
 224 #define ICH6_REG_SD_FIFOW               0x0e
 225 #define ICH6_REG_SD_FIFOSIZE            0x10
 226 #define ICH6_REG_SD_FORMAT              0x12
 227 #define ICH6_REG_SD_BDLPL               0x18
 228 #define ICH6_REG_SD_BDLPU               0x1c
 229
 230 /* PCI space */
 231 #define ICH6_PCIREG_TCSEL       0x44
 232
 233 /*
 234  * other constants
 235  */
 236
 237 /* max number of SDs */
 238 /* ICH, ATI and VIA have 4 playback and 4 capture */
 239 #define ICH6_NUM_CAPTURE        4
 240 #define ICH6_NUM_PLAYBACK       4
 241
 242 /* ULI has 6 playback and 5 capture */
 243 #define ULI_NUM_CAPTURE         5
 244 #define ULI_NUM_PLAYBACK        6
 245
 246 /* ATI HDMI has 1 playback and 0 capture */
 247 #define ATIHDMI_NUM_CAPTURE     0
 248 #define ATIHDMI_NUM_PLAYBACK    1
 249
 250 /* TERA has 4 playback and 3 capture */
 251 #define TERA_NUM_CAPTURE        3
 252 #define TERA_NUM_PLAYBACK       4
 253
 254 /* this number is statically defined for simplicity */
 255 #define MAX_AZX_DEV             16
 256
 257 /* max number of fragments - we may use more if allocating more pages for BDL */
 258 #define BDL_SIZE                4096
 259 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 260 #define AZX_MAX_FRAG            32
 261 /* max buffer size - no h/w limit, you can increase as you like */
 262 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 263 /* max number of PCM devics per card */
 264 #define AZX_MAX_PCMS            8
 265
 266 /* RIRB int mask: overrun[2], response[0] */
 267 #define RIRB_INT_RESPONSE       0x01
 268 #define RIRB_INT_OVERRUN        0x04
 269 #define RIRB_INT_MASK           0x05
 270
 271 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 272 #define AZX_MAX_CODECS          4
 273 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 274
 275 /* SD_CTL bits */
 276 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 277 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 278 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 279 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 280 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 281 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 282 #define SD_CTL_STREAM_TAG_SHIFT 20
 283
 284 /* SD_CTL and SD_STS */
 285 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 286 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 287 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 288 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 289                                  SD_INT_COMPLETE)
 290
 291 /* SD_STS */
 292 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 293
 294 /* INTCTL and INTSTS */
 295 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 296 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 297 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 298
 299 /* below are so far hardcoded - should read registers in future */
 300 #define ICH6_MAX_CORB_ENTRIES   256
 301 #define ICH6_MAX_RIRB_ENTRIES   256
 302
 303 /* position fix mode */
 304 enum {
 305         POS_FIX_AUTO,
 306         POS_FIX_LPIB,
 307         POS_FIX_POSBUF,
 308 };
 309
 310 /* Defines for ATI HD Audio support in SB450 south bridge */
 311 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 312 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 313
 314 /* Defines for Nvidia HDA support */
 315 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 316 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 317 #define NVIDIA_HDA_ISTRM_COH          0x4d
 318 #define NVIDIA_HDA_OSTRM_COH          0x4c
 319 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 320
 321 /* Defines for Intel SCH HDA snoop control */
 322 #define INTEL_SCH_HDA_DEVC      0x78
 323 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 324
 325 /* Define IN stream 0 FIFO size offset in VIA controller */
 326 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 327 /* Define VIA HD Audio Device ID*/
 328 #define VIA_HDAC_DEVICE_ID              0x3288
 329
 330 /* HD Audio class code */
 331 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 332
 333 /*
 334  */
 335
 336 struct azx_dev {
 337         struct snd_dma_buffer bdl; /* BDL buffer */
 338         u32 *posbuf;            /* position buffer pointer */
 339
 340         unsigned int bufsize;   /* size of the play buffer in bytes */
 341         unsigned int period_bytes; /* size of the period in bytes */
 342         unsigned int frags;     /* number for period in the play buffer */
 343         unsigned int fifo_size; /* FIFO size */
 344         unsigned long start_jiffies;    /* start + minimum jiffies */
 345         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 346
 347         void __iomem *sd_addr;  /* stream descriptor pointer */
 348
 349         u32 sd_int_sta_mask;    /* stream int status mask */
 350
 351         /* pcm support */
 352         struct snd_pcm_substream *substream;    /* assigned substream,
 353                                                  * set in PCM open
 354                                                  */
 355         unsigned int format_val;        /* format value to be set in the
 356                                          * controller and the codec
 357                                          */
 358         unsigned char stream_tag;       /* assigned stream */
 359         unsigned char index;            /* stream index */
 360         int device;                     /* last device number assigned to */
 361
 362         unsigned int opened :1;
 363         unsigned int running :1;
 364         unsigned int irq_pending :1;
 365         unsigned int start_flag: 1;     /* stream full start flag */
 366         /*
 367          * For VIA:
 368          *  A flag to ensure DMA position is 0
 369          *  when link position is not greater than FIFO size
 370          */
 371         unsigned int insufficient :1;
 372 };
 373
 374 /* CORB/RIRB */
 375 struct azx_rb {
 376         u32 *buf;               /* CORB/RIRB buffer
 377                                  * Each CORB entry is 4byte, RIRB is 8byte
 378                                  */
 379         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 380         /* for RIRB */
 381         unsigned short rp, wp;  /* read/write pointers */
 382         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 383         u32 res[AZX_MAX_CODECS];        /* last read value */
 384 };
 385
 386 struct azx {
 387         struct snd_card *card;
 388         struct pci_dev *pci;
 389         int dev_index;
 390
 391         /* chip type specific */
 392         int driver_type;
 393         int playback_streams;
 394         int playback_index_offset;
 395         int capture_streams;
 396         int capture_index_offset;
 397         int num_streams;
 398
 399         /* pci resources */
 400         unsigned long addr;
 401         void __iomem *remap_addr;
 402         int irq;
 403
 404         /* locks */
 405         spinlock_t reg_lock;
 406         struct mutex open_mutex;
 407
 408         /* streams (x num_streams) */
 409         struct azx_dev *azx_dev;
 410
 411         /* PCM */
 412         struct snd_pcm *pcm[AZX_MAX_PCMS];
 413
 414         /* HD codec */
 415         unsigned short codec_mask;
 416         int  codec_probe_mask; /* copied from probe_mask option */
 417         struct hda_bus *bus;
 418         unsigned int beep_mode;
 419
 420         /* CORB/RIRB */
 421         struct azx_rb corb;
 422         struct azx_rb rirb;
 423
 424         /* CORB/RIRB and position buffers */
 425         struct snd_dma_buffer rb;
 426         struct snd_dma_buffer posbuf;
 427
 428         /* flags */
 429         int position_fix;
 430         unsigned int running :1;
 431         unsigned int initialized :1;
 432         unsigned int single_cmd :1;
 433         unsigned int polling_mode :1;
 434         unsigned int msi :1;
 435         unsigned int irq_pending_warned :1;
 436         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_SCH,
 453         AZX_DRIVER_ATI,
 454         AZX_DRIVER_ATIHDMI,
 455         AZX_DRIVER_VIA,
 456         AZX_DRIVER_SIS,
 457         AZX_DRIVER_ULI,
 458         AZX_DRIVER_NVIDIA,
 459         AZX_DRIVER_TERA,
 460         AZX_DRIVER_GENERIC,
 461         AZX_NUM_DRIVERS, /* keep this as last entry */
 462 };
 463
 464 static char *driver_short_names[] __devinitdata = {
 465         [AZX_DRIVER_ICH] = "HDA Intel",
 466         [AZX_DRIVER_SCH] = "HDA Intel MID",
 467         [AZX_DRIVER_ATI] = "HDA ATI SB",
 468         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 469         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 470         [AZX_DRIVER_SIS] = "HDA SIS966",
 471         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 472         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 473         [AZX_DRIVER_TERA] = "HDA Teradici",
 474         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 475 };
 476
 477 /*
 478  * macros for easy use
 479  */
 480 #define azx_writel(chip,reg,value) \
 481         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 482 #define azx_readl(chip,reg) \
 483         readl((chip)->remap_addr + ICH6_REG_##reg)
 484 #define azx_writew(chip,reg,value) \
 485         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_readw(chip,reg) \
 487         readw((chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_writeb(chip,reg,value) \
 489         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_readb(chip,reg) \
 491         readb((chip)->remap_addr + ICH6_REG_##reg)
 492
 493 #define azx_sd_writel(dev,reg,value) \
 494         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 495 #define azx_sd_readl(dev,reg) \
 496         readl((dev)->sd_addr + ICH6_REG_##reg)
 497 #define azx_sd_writew(dev,reg,value) \
 498         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_readw(dev,reg) \
 500         readw((dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_writeb(dev,reg,value) \
 502         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_readb(dev,reg) \
 504         readb((dev)->sd_addr + ICH6_REG_##reg)
 505
 506 /* for pcm support */
 507 #define get_azx_dev(substream) (substream->runtime->private_data)
 508
 509 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 510
 511 /*
 512  * Interface for HD codec
 513  */
 514
 515 /*
 516  * CORB / RIRB interface
 517  */
 518 static int azx_alloc_cmd_io(struct azx *chip)
 519 {
 520         int err;
 521
 522         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 523         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 524                                   snd_dma_pci_data(chip->pci),
 525                                   PAGE_SIZE, &chip->rb);
 526         if (err < 0) {
 527                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 528                 return err;
 529         }
 530         return 0;
 531 }
 532
 533 static void azx_init_cmd_io(struct azx *chip)
 534 {
 535         spin_lock_irq(&chip->reg_lock);
 536         /* CORB set up */
 537         chip->corb.addr = chip->rb.addr;
 538         chip->corb.buf = (u32 *)chip->rb.area;
 539         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 540         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 541
 542         /* set the corb size to 256 entries (ULI requires explicitly) */
 543         azx_writeb(chip, CORBSIZE, 0x02);
 544         /* set the corb write pointer to 0 */
 545         azx_writew(chip, CORBWP, 0);
 546         /* reset the corb hw read pointer */
 547         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 548         /* enable corb dma */
 549         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 550
 551         /* RIRB set up */
 552         chip->rirb.addr = chip->rb.addr + 2048;
 553         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 554         chip->rirb.wp = chip->rirb.rp = 0;
 555         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 556         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 557         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 558
 559         /* set the rirb size to 256 entries (ULI requires explicitly) */
 560         azx_writeb(chip, RIRBSIZE, 0x02);
 561         /* reset the rirb hw write pointer */
 562         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 563         /* set N=1, get RIRB response interrupt for new entry */
 564         azx_writew(chip, RINTCNT, 1);
 565         /* enable rirb dma and response irq */
 566         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 567         spin_unlock_irq(&chip->reg_lock);
 568 }
 569
 570 static void azx_free_cmd_io(struct azx *chip)
 571 {
 572         spin_lock_irq(&chip->reg_lock);
 573         /* disable ringbuffer DMAs */
 574         azx_writeb(chip, RIRBCTL, 0);
 575         azx_writeb(chip, CORBCTL, 0);
 576         spin_unlock_irq(&chip->reg_lock);
 577 }
 578
 579 static unsigned int azx_command_addr(u32 cmd)
 580 {
 581         unsigned int addr = cmd >> 28;
 582
 583         if (addr >= AZX_MAX_CODECS) {
 584                 snd_BUG();
 585                 addr = 0;
 586         }
 587
 588         return addr;
 589 }
 590
 591 static unsigned int azx_response_addr(u32 res)
 592 {
 593         unsigned int addr = res & 0xf;
 594
 595         if (addr >= AZX_MAX_CODECS) {
 596                 snd_BUG();
 597                 addr = 0;
 598         }
 599
 600         return addr;
 601 }
 602
 603 /* send a command */
 604 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 605 {
 606         struct azx *chip = bus->private_data;
 607         unsigned int addr = azx_command_addr(val);
 608         unsigned int wp;
 609
 610         spin_lock_irq(&chip->reg_lock);
 611
 612         /* add command to corb */
 613         wp = azx_readb(chip, CORBWP);
 614         wp++;
 615         wp %= ICH6_MAX_CORB_ENTRIES;
 616
 617         chip->rirb.cmds[addr]++;
 618         chip->corb.buf[wp] = cpu_to_le32(val);
 619         azx_writel(chip, CORBWP, wp);
 620
 621         spin_unlock_irq(&chip->reg_lock);
 622
 623         return 0;
 624 }
 625
 626 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 627
 628 /* retrieve RIRB entry - called from interrupt handler */
 629 static void azx_update_rirb(struct azx *chip)
 630 {
 631         unsigned int rp, wp;
 632         unsigned int addr;
 633         u32 res, res_ex;
 634
 635         wp = azx_readb(chip, RIRBWP);
 636         if (wp == chip->rirb.wp)
 637                 return;
 638         chip->rirb.wp = wp;
 639
 640         while (chip->rirb.rp != wp) {
 641                 chip->rirb.rp++;
 642                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 643
 644                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 645                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 646                 res = le32_to_cpu(chip->rirb.buf[rp]);
 647                 addr = azx_response_addr(res_ex);
 648                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 649                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 650                 else if (chip->rirb.cmds[addr]) {
 651                         chip->rirb.res[addr] = res;
 652                         smp_wmb();
 653                         chip->rirb.cmds[addr]--;
 654                 } else
 655                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 656                                    "last cmd=%#08x\n",
 657                                    res, res_ex,
 658                                    chip->last_cmd[addr]);
 659         }
 660 }
 661
 662 /* receive a response */
 663 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 664                                           unsigned int addr)
 665 {
 666         struct azx *chip = bus->private_data;
 667         unsigned long timeout;
 668
 669  again:
 670         timeout = jiffies + msecs_to_jiffies(1000);
 671         for (;;) {
 672                 if (chip->polling_mode) {
 673                         spin_lock_irq(&chip->reg_lock);
 674                         azx_update_rirb(chip);
 675                         spin_unlock_irq(&chip->reg_lock);
 676                 }
 677                 if (!chip->rirb.cmds[addr]) {
 678                         smp_rmb();
 679                         bus->rirb_error = 0;
 680                         return chip->rirb.res[addr]; /* the last value */
 681                 }
 682                 if (time_after(jiffies, timeout))
 683                         break;
 684                 if (bus->needs_damn_long_delay)
 685                         msleep(2); /* temporary workaround */
 686                 else {
 687                         udelay(10);
 688                         cond_resched();
 689                 }
 690         }
 691
 692         if (!chip->polling_mode) {
 693                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 694                            "switching to polling mode: last cmd=0x%08x\n",
 695                            chip->last_cmd[addr]);
 696                 chip->polling_mode = 1;
 697                 goto again;
 698         }
 699
 700         if (chip->msi) {
 701                 snd_printk(KERN_WARNING SFX "No response from codec, "
 702                            "disabling MSI: last cmd=0x%08x\n",
 703                            chip->last_cmd[addr]);
 704                 free_irq(chip->irq, chip);
 705                 chip->irq = -1;
 706                 pci_disable_msi(chip->pci);
 707                 chip->msi = 0;
 708                 if (azx_acquire_irq(chip, 1) < 0) {
 709                         bus->rirb_error = 1;
 710                         return -1;
 711                 }
 712                 goto again;
 713         }
 714
 715         if (chip->probing) {
 716                 /* If this critical timeout happens during the codec probing
 717                  * phase, this is likely an access to a non-existing codec
 718                  * slot.  Better to return an error and reset the system.
 719                  */
 720                 return -1;
 721         }
 722
 723         /* a fatal communication error; need either to reset or to fallback
 724          * to the single_cmd mode
 725          */
 726         bus->rirb_error = 1;
 727         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 728                 bus->response_reset = 1;
 729                 return -1; /* give a chance to retry */
 730         }
 731
 732         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 733                    "switching to single_cmd mode: last cmd=0x%08x\n",
 734                    chip->last_cmd[addr]);
 735         chip->single_cmd = 1;
 736         bus->response_reset = 0;
 737         /* release CORB/RIRB */
 738         azx_free_cmd_io(chip);
 739         /* disable unsolicited responses */
 740         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 741         return -1;
 742 }
 743
 744 /*
 745  * Use the single immediate command instead of CORB/RIRB for simplicity
 746  *
 747  * Note: according to Intel, this is not preferred use.  The command was
 748  *       intended for the BIOS only, and may get confused with unsolicited
 749  *       responses.  So, we shouldn't use it for normal operation from the
 750  *       driver.
 751  *       I left the codes, however, for debugging/testing purposes.
 752  */
 753
 754 /* receive a response */
 755 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 756 {
 757         int timeout = 50;
 758
 759         while (timeout--) {
 760                 /* check IRV busy bit */
 761                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 762                         /* reuse rirb.res as the response return value */
 763                         chip->rirb.res[addr] = azx_readl(chip, IR);
 764                         return 0;
 765                 }
 766                 udelay(1);
 767         }
 768         if (printk_ratelimit())
 769                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 770                            azx_readw(chip, IRS));
 771         chip->rirb.res[addr] = -1;
 772         return -EIO;
 773 }
 774
 775 /* send a command */
 776 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 777 {
 778         struct azx *chip = bus->private_data;
 779         unsigned int addr = azx_command_addr(val);
 780         int timeout = 50;
 781
 782         bus->rirb_error = 0;
 783         while (timeout--) {
 784                 /* check ICB busy bit */
 785                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 786                         /* Clear IRV valid bit */
 787                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 788                                    ICH6_IRS_VALID);
 789                         azx_writel(chip, IC, val);
 790                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 791                                    ICH6_IRS_BUSY);
 792                         return azx_single_wait_for_response(chip, addr);
 793                 }
 794                 udelay(1);
 795         }
 796         if (printk_ratelimit())
 797                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 798                            azx_readw(chip, IRS), val);
 799         return -EIO;
 800 }
 801
 802 /* receive a response */
 803 static unsigned int azx_single_get_response(struct hda_bus *bus,
 804                                             unsigned int addr)
 805 {
 806         struct azx *chip = bus->private_data;
 807         return chip->rirb.res[addr];
 808 }
 809
 810 /*
 811  * The below are the main callbacks from hda_codec.
 812  *
 813  * They are just the skeleton to call sub-callbacks according to the
 814  * current setting of chip->single_cmd.
 815  */
 816
 817 /* send a command */
 818 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 819 {
 820         struct azx *chip = bus->private_data;
 821
 822         chip->last_cmd[azx_command_addr(val)] = val;
 823         if (chip->single_cmd)
 824                 return azx_single_send_cmd(bus, val);
 825         else
 826                 return azx_corb_send_cmd(bus, val);
 827 }
 828
 829 /* get a response */
 830 static unsigned int azx_get_response(struct hda_bus *bus,
 831                                      unsigned int addr)
 832 {
 833         struct azx *chip = bus->private_data;
 834         if (chip->single_cmd)
 835                 return azx_single_get_response(bus, addr);
 836         else
 837                 return azx_rirb_get_response(bus, addr);
 838 }
 839
 840 #ifdef CONFIG_SND_HDA_POWER_SAVE
 841 static void azx_power_notify(struct hda_bus *bus);
 842 #endif
 843
 844 /* reset codec link */
 845 static int azx_reset(struct azx *chip)
 846 {
 847         int count;
 848
 849         /* clear STATESTS */
 850         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 851
 852         /* reset controller */
 853         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 854
 855         count = 50;
 856         while (azx_readb(chip, GCTL) && --count)
 857                 msleep(1);
 858
 859         /* delay for >= 100us for codec PLL to settle per spec
 860          * Rev 0.9 section 5.5.1
 861          */
 862         msleep(1);
 863
 864         /* Bring controller out of reset */
 865         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 866
 867         count = 50;
 868         while (!azx_readb(chip, GCTL) && --count)
 869                 msleep(1);
 870
 871         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 872         msleep(1);
 873
 874         /* check to see if controller is ready */
 875         if (!azx_readb(chip, GCTL)) {
 876                 snd_printd(SFX "azx_reset: controller not ready!\n");
 877                 return -EBUSY;
 878         }
 879
 880         /* Accept unsolicited responses */
 881         if (!chip->single_cmd)
 882                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 883                            ICH6_GCTL_UNSOL);
 884
 885         /* detect codecs */
 886         if (!chip->codec_mask) {
 887                 chip->codec_mask = azx_readw(chip, STATESTS);
 888                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 889         }
 890
 891         return 0;
 892 }
 893
 894
 895 /*
 896  * Lowlevel interface
 897  */
 898
 899 /* enable interrupts */
 900 static void azx_int_enable(struct azx *chip)
 901 {
 902         /* enable controller CIE and GIE */
 903         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 904                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 905 }
 906
 907 /* disable interrupts */
 908 static void azx_int_disable(struct azx *chip)
 909 {
 910         int i;
 911
 912         /* disable interrupts in stream descriptor */
 913         for (i = 0; i < chip->num_streams; i++) {
 914                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 915                 azx_sd_writeb(azx_dev, SD_CTL,
 916                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 917         }
 918
 919         /* disable SIE for all streams */
 920         azx_writeb(chip, INTCTL, 0);
 921
 922         /* disable controller CIE and GIE */
 923         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 924                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 925 }
 926
 927 /* clear interrupts */
 928 static void azx_int_clear(struct azx *chip)
 929 {
 930         int i;
 931
 932         /* clear stream status */
 933         for (i = 0; i < chip->num_streams; i++) {
 934                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 935                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 936         }
 937
 938         /* clear STATESTS */
 939         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 940
 941         /* clear rirb status */
 942         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 943
 944         /* clear int status */
 945         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 946 }
 947
 948 /* start a stream */
 949 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 950 {
 951         /*
 952          * Before stream start, initialize parameter
 953          */
 954         azx_dev->insufficient = 1;
 955
 956         /* enable SIE */
 957         azx_writeb(chip, INTCTL,
 958                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 959         /* set DMA start and interrupt mask */
 960         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 961                       SD_CTL_DMA_START | SD_INT_MASK);
 962 }
 963
 964 /* stop DMA */
 965 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 966 {
 967         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 968                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 969         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 970 }
 971
 972 /* stop a stream */
 973 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 974 {
 975         azx_stream_clear(chip, azx_dev);
 976         /* disable SIE */
 977         azx_writeb(chip, INTCTL,
 978                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 979 }
 980
 981
 982 /*
 983  * reset and start the controller registers
 984  */
 985 static void azx_init_chip(struct azx *chip)
 986 {
 987         if (chip->initialized)
 988                 return;
 989
 990         /* reset controller */
 991         azx_reset(chip);
 992
 993         /* initialize interrupts */
 994         azx_int_clear(chip);
 995         azx_int_enable(chip);
 996
 997         /* initialize the codec command I/O */
 998         if (!chip->single_cmd)
 999                 azx_init_cmd_io(chip);
1000
1001         /* program the position buffer */
1002         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1003         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1004
1005         chip->initialized = 1;
1006 }
1007
1008 /*
1009  * initialize the PCI registers
1010  */
1011 /* update bits in a PCI register byte */
1012 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1013                             unsigned char mask, unsigned char val)
1014 {
1015         unsigned char data;
1016
1017         pci_read_config_byte(pci, reg, &data);
1018         data &= ~mask;
1019         data |= (val & mask);
1020         pci_write_config_byte(pci, reg, data);
1021 }
1022
1023 static void azx_init_pci(struct azx *chip)
1024 {
1025         unsigned short snoop;
1026
1027         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1028          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1029          * Ensuring these bits are 0 clears playback static on some HD Audio
1030          * codecs
1031          */
1032         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1033
1034         switch (chip->driver_type) {
1035         case AZX_DRIVER_ATI:
1036                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1037                 update_pci_byte(chip->pci,
1038                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1039                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1040                 break;
1041         case AZX_DRIVER_NVIDIA:
1042                 /* For NVIDIA HDA, enable snoop */
1043                 update_pci_byte(chip->pci,
1044                                 NVIDIA_HDA_TRANSREG_ADDR,
1045                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1046                 update_pci_byte(chip->pci,
1047                                 NVIDIA_HDA_ISTRM_COH,
1048                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1049                 update_pci_byte(chip->pci,
1050                                 NVIDIA_HDA_OSTRM_COH,
1051                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1052                 break;
1053         case AZX_DRIVER_SCH:
1054                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1055                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1056                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1057                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1058                         pci_read_config_word(chip->pci,
1059                                 INTEL_SCH_HDA_DEVC, &snoop);
1060                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1061                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1062                                 ? "Failed" : "OK");
1063                 }
1064                 break;
1065
1066         }
1067 }
1068
1069
1070 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1071
1072 /*
1073  * interrupt handler
1074  */
1075 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1076 {
1077         struct azx *chip = dev_id;
1078         struct azx_dev *azx_dev;
1079         u32 status;
1080         int i, ok;
1081
1082         spin_lock(&chip->reg_lock);
1083
1084         status = azx_readl(chip, INTSTS);
1085         if (status == 0) {
1086                 spin_unlock(&chip->reg_lock);
1087                 return IRQ_NONE;
1088         }
1089
1090         for (i = 0; i < chip->num_streams; i++) {
1091                 azx_dev = &chip->azx_dev[i];
1092                 if (status & azx_dev->sd_int_sta_mask) {
1093                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1094                         if (!azx_dev->substream || !azx_dev->running)
1095                                 continue;
1096                         /* check whether this IRQ is really acceptable */
1097                         ok = azx_position_ok(chip, azx_dev);
1098                         if (ok == 1) {
1099                                 azx_dev->irq_pending = 0;
1100                                 spin_unlock(&chip->reg_lock);
1101                                 snd_pcm_period_elapsed(azx_dev->substream);
1102                                 spin_lock(&chip->reg_lock);
1103                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1104                                 /* bogus IRQ, process it later */
1105                                 azx_dev->irq_pending = 1;
1106                                 queue_work(chip->bus->workq,
1107                                            &chip->irq_pending_work);
1108                         }
1109                 }
1110         }
1111
1112         /* clear rirb int */
1113         status = azx_readb(chip, RIRBSTS);
1114         if (status & RIRB_INT_MASK) {
1115                 if (status & RIRB_INT_RESPONSE)
1116                         azx_update_rirb(chip);
1117                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1118         }
1119
1120 #if 0
1121         /* clear state status int */
1122         if (azx_readb(chip, STATESTS) & 0x04)
1123                 azx_writeb(chip, STATESTS, 0x04);
1124 #endif
1125         spin_unlock(&chip->reg_lock);
1126
1127         return IRQ_HANDLED;
1128 }
1129
1130
1131 /*
1132  * set up a BDL entry
1133  */
1134 static int setup_bdle(struct snd_pcm_substream *substream,
1135                       struct azx_dev *azx_dev, u32 **bdlp,
1136                       int ofs, int size, int with_ioc)
1137 {
1138         u32 *bdl = *bdlp;
1139
1140         while (size > 0) {
1141                 dma_addr_t addr;
1142                 int chunk;
1143
1144                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1145                         return -EINVAL;
1146
1147                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1148                 /* program the address field of the BDL entry */
1149                 bdl[0] = cpu_to_le32((u32)addr);
1150                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1151                 /* program the size field of the BDL entry */
1152                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1153                 bdl[2] = cpu_to_le32(chunk);
1154                 /* program the IOC to enable interrupt
1155                  * only when the whole fragment is processed
1156                  */
1157                 size -= chunk;
1158                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1159                 bdl += 4;
1160                 azx_dev->frags++;
1161                 ofs += chunk;
1162         }
1163         *bdlp = bdl;
1164         return ofs;
1165 }
1166
1167 /*
1168  * set up BDL entries
1169  */
1170 static int azx_setup_periods(struct azx *chip,
1171                              struct snd_pcm_substream *substream,
1172                              struct azx_dev *azx_dev)
1173 {
1174         u32 *bdl;
1175         int i, ofs, periods, period_bytes;
1176         int pos_adj;
1177
1178         /* reset BDL address */
1179         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1180         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1181
1182         period_bytes = azx_dev->period_bytes;
1183         periods = azx_dev->bufsize / period_bytes;
1184
1185         /* program the initial BDL entries */
1186         bdl = (u32 *)azx_dev->bdl.area;
1187         ofs = 0;
1188         azx_dev->frags = 0;
1189         pos_adj = bdl_pos_adj[chip->dev_index];
1190         if (pos_adj > 0) {
1191                 struct snd_pcm_runtime *runtime = substream->runtime;
1192                 int pos_align = pos_adj;
1193                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1194                 if (!pos_adj)
1195                         pos_adj = pos_align;
1196                 else
1197                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1198                                 pos_align;
1199                 pos_adj = frames_to_bytes(runtime, pos_adj);
1200                 if (pos_adj >= period_bytes) {
1201                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1202                                    bdl_pos_adj[chip->dev_index]);
1203                         pos_adj = 0;
1204                 } else {
1205                         ofs = setup_bdle(substream, azx_dev,
1206                                          &bdl, ofs, pos_adj, 1);
1207                         if (ofs < 0)
1208                                 goto error;
1209                 }
1210         } else
1211                 pos_adj = 0;
1212         for (i = 0; i < periods; i++) {
1213                 if (i == periods - 1 && pos_adj)
1214                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1215                                          period_bytes - pos_adj, 0);
1216                 else
1217                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1218                                          period_bytes, 1);
1219                 if (ofs < 0)
1220                         goto error;
1221         }
1222         return 0;
1223
1224  error:
1225         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1226                    azx_dev->bufsize, period_bytes);
1227         return -EINVAL;
1228 }
1229
1230 /* reset stream */
1231 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1232 {
1233         unsigned char val;
1234         int timeout;
1235
1236         azx_stream_clear(chip, azx_dev);
1237
1238         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1239                       SD_CTL_STREAM_RESET);
1240         udelay(3);
1241         timeout = 300;
1242         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1243                --timeout)
1244                 ;
1245         val &= ~SD_CTL_STREAM_RESET;
1246         azx_sd_writeb(azx_dev, SD_CTL, val);
1247         udelay(3);
1248
1249         timeout = 300;
1250         /* waiting for hardware to report that the stream is out of reset */
1251         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1252                --timeout)
1253                 ;
1254
1255         /* reset first position - may not be synced with hw at this time */
1256         *azx_dev->posbuf = 0;
1257 }
1258
1259 /*
1260  * set up the SD for streaming
1261  */
1262 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1263 {
1264         /* make sure the run bit is zero for SD */
1265         azx_stream_clear(chip, azx_dev);
1266         /* program the stream_tag */
1267         azx_sd_writel(azx_dev, SD_CTL,
1268                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1269                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1270
1271         /* program the length of samples in cyclic buffer */
1272         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1273
1274         /* program the stream format */
1275         /* this value needs to be the same as the one programmed */
1276         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1277
1278         /* program the stream LVI (last valid index) of the BDL */
1279         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1280
1281         /* program the BDL address */
1282         /* lower BDL address */
1283         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1284         /* upper BDL address */
1285         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1286
1287         /* enable the position buffer */
1288         if (chip->position_fix == POS_FIX_POSBUF ||
1289             chip->position_fix == POS_FIX_AUTO ||
1290             chip->via_dmapos_patch) {
1291                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1292                         azx_writel(chip, DPLBASE,
1293                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1294         }
1295
1296         /* set the interrupt enable bits in the descriptor control register */
1297         azx_sd_writel(azx_dev, SD_CTL,
1298                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1299
1300         return 0;
1301 }
1302
1303 /*
1304  * Probe the given codec address
1305  */
1306 static int probe_codec(struct azx *chip, int addr)
1307 {
1308         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1309                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1310         unsigned int res;
1311
1312         mutex_lock(&chip->bus->cmd_mutex);
1313         chip->probing = 1;
1314         azx_send_cmd(chip->bus, cmd);
1315         res = azx_get_response(chip->bus, addr);
1316         chip->probing = 0;
1317         mutex_unlock(&chip->bus->cmd_mutex);
1318         if (res == -1)
1319                 return -EIO;
1320         snd_printdd(SFX "codec #%d probed OK\n", addr);
1321         return 0;
1322 }
1323
1324 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1325                                  struct hda_pcm *cpcm);
1326 static void azx_stop_chip(struct azx *chip);
1327
1328 static void azx_bus_reset(struct hda_bus *bus)
1329 {
1330         struct azx *chip = bus->private_data;
1331
1332         bus->in_reset = 1;
1333         azx_stop_chip(chip);
1334         azx_init_chip(chip);
1335 #ifdef CONFIG_PM
1336         if (chip->initialized) {
1337                 int i;
1338
1339                 for (i = 0; i < AZX_MAX_PCMS; i++)
1340                         snd_pcm_suspend_all(chip->pcm[i]);
1341                 snd_hda_suspend(chip->bus);
1342                 snd_hda_resume(chip->bus);
1343         }
1344 #endif
1345         bus->in_reset = 0;
1346 }
1347
1348 /*
1349  * Codec initialization
1350  */
1351
1352 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1353 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1354         [AZX_DRIVER_TERA] = 1,
1355 };
1356
1357 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1358 {
1359         struct hda_bus_template bus_temp;
1360         int c, codecs, err;
1361         int max_slots;
1362
1363         memset(&bus_temp, 0, sizeof(bus_temp));
1364         bus_temp.private_data = chip;
1365         bus_temp.modelname = model;
1366         bus_temp.pci = chip->pci;
1367         bus_temp.ops.command = azx_send_cmd;
1368         bus_temp.ops.get_response = azx_get_response;
1369         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1370         bus_temp.ops.bus_reset = azx_bus_reset;
1371 #ifdef CONFIG_SND_HDA_POWER_SAVE
1372         bus_temp.power_save = &power_save;
1373         bus_temp.ops.pm_notify = azx_power_notify;
1374 #endif
1375
1376         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1377         if (err < 0)
1378                 return err;
1379
1380         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1381                 chip->bus->needs_damn_long_delay = 1;
1382
1383         codecs = 0;
1384         max_slots = azx_max_codecs[chip->driver_type];
1385         if (!max_slots)
1386                 max_slots = AZX_MAX_CODECS;
1387
1388         /* First try to probe all given codec slots */
1389         for (c = 0; c < max_slots; c++) {
1390                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1391                         if (probe_codec(chip, c) < 0) {
1392                                 /* Some BIOSen give you wrong codec addresses
1393                                  * that don't exist
1394                                  */
1395                                 snd_printk(KERN_WARNING SFX
1396                                            "Codec #%d probe error; "
1397                                            "disabling it...\n", c);
1398                                 chip->codec_mask &= ~(1 << c);
1399                                 /* More badly, accessing to a non-existing
1400                                  * codec often screws up the controller chip,
1401                                  * and distrubs the further communications.
1402                                  * Thus if an error occurs during probing,
1403                                  * better to reset the controller chip to
1404                                  * get back to the sanity state.
1405                                  */
1406                                 azx_stop_chip(chip);
1407                                 azx_init_chip(chip);
1408                         }
1409                 }
1410         }
1411
1412         /* Then create codec instances */
1413         for (c = 0; c < max_slots; c++) {
1414                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1415                         struct hda_codec *codec;
1416                         err = snd_hda_codec_new(chip->bus, c, &codec);
1417                         if (err < 0)
1418                                 continue;
1419                         codec->beep_mode = chip->beep_mode;
1420                         codecs++;
1421                 }
1422         }
1423         if (!codecs) {
1424                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1425                 return -ENXIO;
1426         }
1427         return 0;
1428 }
1429
1430 /* configure each codec instance */
1431 static int __devinit azx_codec_configure(struct azx *chip)
1432 {
1433         struct hda_codec *codec;
1434         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1435                 snd_hda_codec_configure(codec);
1436         }
1437         return 0;
1438 }
1439
1440
1441 /*
1442  * PCM support
1443  */
1444
1445 /* assign a stream for the PCM */
1446 static inline struct azx_dev *
1447 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1448 {
1449         int dev, i, nums;
1450         struct azx_dev *res = NULL;
1451
1452         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1453                 dev = chip->playback_index_offset;
1454                 nums = chip->playback_streams;
1455         } else {
1456                 dev = chip->capture_index_offset;
1457                 nums = chip->capture_streams;
1458         }
1459         for (i = 0; i < nums; i++, dev++)
1460                 if (!chip->azx_dev[dev].opened) {
1461                         res = &chip->azx_dev[dev];
1462                         if (res->device == substream->pcm->device)
1463                                 break;
1464                 }
1465         if (res) {
1466                 res->opened = 1;
1467                 res->device = substream->pcm->device;
1468         }
1469         return res;
1470 }
1471
1472 /* release the assigned stream */
1473 static inline void azx_release_device(struct azx_dev *azx_dev)
1474 {
1475         azx_dev->opened = 0;
1476 }
1477
1478 static struct snd_pcm_hardware azx_pcm_hw = {
1479         .info =                 (SNDRV_PCM_INFO_MMAP |
1480                                  SNDRV_PCM_INFO_INTERLEAVED |
1481                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1482                                  SNDRV_PCM_INFO_MMAP_VALID |
1483                                  /* No full-resume yet implemented */
1484                                  /* SNDRV_PCM_INFO_RESUME |*/
1485                                  SNDRV_PCM_INFO_PAUSE |
1486                                  SNDRV_PCM_INFO_SYNC_START),
1487         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1488         .rates =                SNDRV_PCM_RATE_48000,
1489         .rate_min =             48000,
1490         .rate_max =             48000,
1491         .channels_min =         2,
1492         .channels_max =         2,
1493         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1494         .period_bytes_min =     128,
1495         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1496         .periods_min =          2,
1497         .periods_max =          AZX_MAX_FRAG,
1498         .fifo_size =            0,
1499 };
1500
1501 struct azx_pcm {
1502         struct azx *chip;
1503         struct hda_codec *codec;
1504         struct hda_pcm_stream *hinfo[2];
1505 };
1506
1507 static int azx_pcm_open(struct snd_pcm_substream *substream)
1508 {
1509         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1510         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1511         struct azx *chip = apcm->chip;
1512         struct azx_dev *azx_dev;
1513         struct snd_pcm_runtime *runtime = substream->runtime;
1514         unsigned long flags;
1515         int err;
1516
1517         mutex_lock(&chip->open_mutex);
1518         azx_dev = azx_assign_device(chip, substream);
1519         if (azx_dev == NULL) {
1520                 mutex_unlock(&chip->open_mutex);
1521                 return -EBUSY;
1522         }
1523         runtime->hw = azx_pcm_hw;
1524         runtime->hw.channels_min = hinfo->channels_min;
1525         runtime->hw.channels_max = hinfo->channels_max;
1526         runtime->hw.formats = hinfo->formats;
1527         runtime->hw.rates = hinfo->rates;
1528         snd_pcm_limit_hw_rates(runtime);
1529         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1530         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1531                                    128);
1532         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1533                                    128);
1534         snd_hda_power_up(apcm->codec);
1535         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1536         if (err < 0) {
1537                 azx_release_device(azx_dev);
1538                 snd_hda_power_down(apcm->codec);
1539                 mutex_unlock(&chip->open_mutex);
1540                 return err;
1541         }
1542         snd_pcm_limit_hw_rates(runtime);
1543         /* sanity check */
1544         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1545             snd_BUG_ON(!runtime->hw.channels_max) ||
1546             snd_BUG_ON(!runtime->hw.formats) ||
1547             snd_BUG_ON(!runtime->hw.rates)) {
1548                 azx_release_device(azx_dev);
1549                 hinfo->ops.close(hinfo, apcm->codec, substream);
1550                 snd_hda_power_down(apcm->codec);
1551                 mutex_unlock(&chip->open_mutex);
1552                 return -EINVAL;
1553         }
1554         spin_lock_irqsave(&chip->reg_lock, flags);
1555         azx_dev->substream = substream;
1556         azx_dev->running = 0;
1557         spin_unlock_irqrestore(&chip->reg_lock, flags);
1558
1559         runtime->private_data = azx_dev;
1560         snd_pcm_set_sync(substream);
1561         mutex_unlock(&chip->open_mutex);
1562         return 0;
1563 }
1564
1565 static int azx_pcm_close(struct snd_pcm_substream *substream)
1566 {
1567         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1568         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1569         struct azx *chip = apcm->chip;
1570         struct azx_dev *azx_dev = get_azx_dev(substream);
1571         unsigned long flags;
1572
1573         mutex_lock(&chip->open_mutex);
1574         spin_lock_irqsave(&chip->reg_lock, flags);
1575         azx_dev->substream = NULL;
1576         azx_dev->running = 0;
1577         spin_unlock_irqrestore(&chip->reg_lock, flags);
1578         azx_release_device(azx_dev);
1579         hinfo->ops.close(hinfo, apcm->codec, substream);
1580         snd_hda_power_down(apcm->codec);
1581         mutex_unlock(&chip->open_mutex);
1582         return 0;
1583 }
1584
1585 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1586                              struct snd_pcm_hw_params *hw_params)
1587 {
1588         struct azx_dev *azx_dev = get_azx_dev(substream);
1589
1590         azx_dev->bufsize = 0;
1591         azx_dev->period_bytes = 0;
1592         azx_dev->format_val = 0;
1593         return snd_pcm_lib_malloc_pages(substream,
1594                                         params_buffer_bytes(hw_params));
1595 }
1596
1597 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1598 {
1599         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1600         struct azx_dev *azx_dev = get_azx_dev(substream);
1601         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1602
1603         /* reset BDL address */
1604         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1605         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1606         azx_sd_writel(azx_dev, SD_CTL, 0);
1607         azx_dev->bufsize = 0;
1608         azx_dev->period_bytes = 0;
1609         azx_dev->format_val = 0;
1610
1611         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1612
1613         return snd_pcm_lib_free_pages(substream);
1614 }
1615
1616 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1617 {
1618         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1619         struct azx *chip = apcm->chip;
1620         struct azx_dev *azx_dev = get_azx_dev(substream);
1621         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1622         struct snd_pcm_runtime *runtime = substream->runtime;
1623         unsigned int bufsize, period_bytes, format_val;
1624         int err;
1625
1626         azx_stream_reset(chip, azx_dev);
1627         format_val = snd_hda_calc_stream_format(runtime->rate,
1628                                                 runtime->channels,
1629                                                 runtime->format,
1630                                                 hinfo->maxbps);
1631         if (!format_val) {
1632                 snd_printk(KERN_ERR SFX
1633                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1634                            runtime->rate, runtime->channels, runtime->format);
1635                 return -EINVAL;
1636         }
1637
1638         bufsize = snd_pcm_lib_buffer_bytes(substream);
1639         period_bytes = snd_pcm_lib_period_bytes(substream);
1640
1641         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1642                     bufsize, format_val);
1643
1644         if (bufsize != azx_dev->bufsize ||
1645             period_bytes != azx_dev->period_bytes ||
1646             format_val != azx_dev->format_val) {
1647                 azx_dev->bufsize = bufsize;
1648                 azx_dev->period_bytes = period_bytes;
1649                 azx_dev->format_val = format_val;
1650                 err = azx_setup_periods(chip, substream, azx_dev);
1651                 if (err < 0)
1652                         return err;
1653         }
1654
1655         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1656                                                 (runtime->rate * 2);
1657         azx_setup_controller(chip, azx_dev);
1658         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1659                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1660         else
1661                 azx_dev->fifo_size = 0;
1662
1663         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1664                                   azx_dev->format_val, substream);
1665 }
1666
1667 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1668 {
1669         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1670         struct azx *chip = apcm->chip;
1671         struct azx_dev *azx_dev;
1672         struct snd_pcm_substream *s;
1673         int rstart = 0, start, nsync = 0, sbits = 0;
1674         int nwait, timeout;
1675
1676         switch (cmd) {
1677         case SNDRV_PCM_TRIGGER_START:
1678                 rstart = 1;
1679         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1680         case SNDRV_PCM_TRIGGER_RESUME:
1681                 start = 1;
1682                 break;
1683         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1684         case SNDRV_PCM_TRIGGER_SUSPEND:
1685         case SNDRV_PCM_TRIGGER_STOP:
1686                 start = 0;
1687                 break;
1688         default:
1689                 return -EINVAL;
1690         }
1691
1692         snd_pcm_group_for_each_entry(s, substream) {
1693                 if (s->pcm->card != substream->pcm->card)
1694                         continue;
1695                 azx_dev = get_azx_dev(s);
1696                 sbits |= 1 << azx_dev->index;
1697                 nsync++;
1698                 snd_pcm_trigger_done(s, substream);
1699         }
1700
1701         spin_lock(&chip->reg_lock);
1702         if (nsync > 1) {
1703                 /* first, set SYNC bits of corresponding streams */
1704                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1705         }
1706         snd_pcm_group_for_each_entry(s, substream) {
1707                 if (s->pcm->card != substream->pcm->card)
1708                         continue;
1709                 azx_dev = get_azx_dev(s);
1710                 if (rstart) {
1711                         azx_dev->start_flag = 1;
1712                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1713                 }
1714                 if (start)
1715                         azx_stream_start(chip, azx_dev);
1716                 else
1717                         azx_stream_stop(chip, azx_dev);
1718                 azx_dev->running = start;
1719         }
1720         spin_unlock(&chip->reg_lock);
1721         if (start) {
1722                 if (nsync == 1)
1723                         return 0;
1724                 /* wait until all FIFOs get ready */
1725                 for (timeout = 5000; timeout; timeout--) {
1726                         nwait = 0;
1727                         snd_pcm_group_for_each_entry(s, substream) {
1728                                 if (s->pcm->card != substream->pcm->card)
1729                                         continue;
1730                                 azx_dev = get_azx_dev(s);
1731                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1732                                       SD_STS_FIFO_READY))
1733                                         nwait++;
1734                         }
1735                         if (!nwait)
1736                                 break;
1737                         cpu_relax();
1738                 }
1739         } else {
1740                 /* wait until all RUN bits are cleared */
1741                 for (timeout = 5000; timeout; timeout--) {
1742                         nwait = 0;
1743                         snd_pcm_group_for_each_entry(s, substream) {
1744                                 if (s->pcm->card != substream->pcm->card)
1745                                         continue;
1746                                 azx_dev = get_azx_dev(s);
1747                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1748                                     SD_CTL_DMA_START)
1749                                         nwait++;
1750                         }
1751                         if (!nwait)
1752                                 break;
1753                         cpu_relax();
1754                 }
1755         }
1756         if (nsync > 1) {
1757                 spin_lock(&chip->reg_lock);
1758                 /* reset SYNC bits */
1759                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1760                 spin_unlock(&chip->reg_lock);
1761         }
1762         return 0;
1763 }
1764
1765 /* get the current DMA position with correction on VIA chips */
1766 static unsigned int azx_via_get_position(struct azx *chip,
1767                                          struct azx_dev *azx_dev)
1768 {
1769         unsigned int link_pos, mini_pos, bound_pos;
1770         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1771         unsigned int fifo_size;
1772
1773         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1774         if (azx_dev->index >= 4) {
1775                 /* Playback, no problem using link position */
1776                 return link_pos;
1777         }
1778
1779         /* Capture */
1780         /* For new chipset,
1781          * use mod to get the DMA position just like old chipset
1782          */
1783         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1784         mod_dma_pos %= azx_dev->period_bytes;
1785
1786         /* azx_dev->fifo_size can't get FIFO size of in stream.
1787          * Get from base address + offset.
1788          */
1789         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1790
1791         if (azx_dev->insufficient) {
1792                 /* Link position never gather than FIFO size */
1793                 if (link_pos <= fifo_size)
1794                         return 0;
1795
1796                 azx_dev->insufficient = 0;
1797         }
1798
1799         if (link_pos <= fifo_size)
1800                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1801         else
1802                 mini_pos = link_pos - fifo_size;
1803
1804         /* Find nearest previous boudary */
1805         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1806         mod_link_pos = link_pos % azx_dev->period_bytes;
1807         if (mod_link_pos >= fifo_size)
1808                 bound_pos = link_pos - mod_link_pos;
1809         else if (mod_dma_pos >= mod_mini_pos)
1810                 bound_pos = mini_pos - mod_mini_pos;
1811         else {
1812                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1813                 if (bound_pos >= azx_dev->bufsize)
1814                         bound_pos = 0;
1815         }
1816
1817         /* Calculate real DMA position we want */
1818         return bound_pos + mod_dma_pos;
1819 }
1820
1821 static unsigned int azx_get_position(struct azx *chip,
1822                                      struct azx_dev *azx_dev)
1823 {
1824         unsigned int pos;
1825
1826         if (chip->via_dmapos_patch)
1827                 pos = azx_via_get_position(chip, azx_dev);
1828         else if (chip->position_fix == POS_FIX_POSBUF ||
1829                  chip->position_fix == POS_FIX_AUTO) {
1830                 /* use the position buffer */
1831                 pos = le32_to_cpu(*azx_dev->posbuf);
1832         } else {
1833                 /* read LPIB */
1834                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1835         }
1836         if (pos >= azx_dev->bufsize)
1837                 pos = 0;
1838         return pos;
1839 }
1840
1841 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1842 {
1843         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1844         struct azx *chip = apcm->chip;
1845         struct azx_dev *azx_dev = get_azx_dev(substream);
1846         return bytes_to_frames(substream->runtime,
1847                                azx_get_position(chip, azx_dev));
1848 }
1849
1850 /*
1851  * Check whether the current DMA position is acceptable for updating
1852  * periods.  Returns non-zero if it's OK.
1853  *
1854  * Many HD-audio controllers appear pretty inaccurate about
1855  * the update-IRQ timing.  The IRQ is issued before actually the
1856  * data is processed.  So, we need to process it afterwords in a
1857  * workqueue.
1858  */
1859 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1860 {
1861         unsigned int pos;
1862
1863         if (azx_dev->start_flag &&
1864             time_before_eq(jiffies, azx_dev->start_jiffies))
1865                 return -1;      /* bogus (too early) interrupt */
1866         azx_dev->start_flag = 0;
1867
1868         pos = azx_get_position(chip, azx_dev);
1869         if (chip->position_fix == POS_FIX_AUTO) {
1870                 if (!pos) {
1871                         printk(KERN_WARNING
1872                                "hda-intel: Invalid position buffer, "
1873                                "using LPIB read method instead.\n");
1874                         chip->position_fix = POS_FIX_LPIB;
1875                         pos = azx_get_position(chip, azx_dev);
1876                 } else
1877                         chip->position_fix = POS_FIX_POSBUF;
1878         }
1879
1880         if (!bdl_pos_adj[chip->dev_index])
1881                 return 1; /* no delayed ack */
1882         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1883                 return 0; /* NG - it's below the period boundary */
1884         return 1; /* OK, it's fine */
1885 }
1886
1887 /*
1888  * The work for pending PCM period updates.
1889  */
1890 static void azx_irq_pending_work(struct work_struct *work)
1891 {
1892         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1893         int i, pending;
1894
1895         if (!chip->irq_pending_warned) {
1896                 printk(KERN_WARNING
1897                        "hda-intel: IRQ timing workaround is activated "
1898                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1899                        chip->card->number);
1900                 chip->irq_pending_warned = 1;
1901         }
1902
1903         for (;;) {
1904                 pending = 0;
1905                 spin_lock_irq(&chip->reg_lock);
1906                 for (i = 0; i < chip->num_streams; i++) {
1907                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1908                         if (!azx_dev->irq_pending ||
1909                             !azx_dev->substream ||
1910                             !azx_dev->running)
1911                                 continue;
1912                         if (azx_position_ok(chip, azx_dev)) {
1913                                 azx_dev->irq_pending = 0;
1914                                 spin_unlock(&chip->reg_lock);
1915                                 snd_pcm_period_elapsed(azx_dev->substream);
1916                                 spin_lock(&chip->reg_lock);
1917                         } else
1918                                 pending++;
1919                 }
1920                 spin_unlock_irq(&chip->reg_lock);
1921                 if (!pending)
1922                         return;
1923                 cond_resched();
1924         }
1925 }
1926
1927 /* clear irq_pending flags and assure no on-going workq */
1928 static void azx_clear_irq_pending(struct azx *chip)
1929 {
1930         int i;
1931
1932         spin_lock_irq(&chip->reg_lock);
1933         for (i = 0; i < chip->num_streams; i++)
1934                 chip->azx_dev[i].irq_pending = 0;
1935         spin_unlock_irq(&chip->reg_lock);
1936 }
1937
1938 static struct snd_pcm_ops azx_pcm_ops = {
1939         .open = azx_pcm_open,
1940         .close = azx_pcm_close,
1941         .ioctl = snd_pcm_lib_ioctl,
1942         .hw_params = azx_pcm_hw_params,
1943         .hw_free = azx_pcm_hw_free,
1944         .prepare = azx_pcm_prepare,
1945         .trigger = azx_pcm_trigger,
1946         .pointer = azx_pcm_pointer,
1947         .page = snd_pcm_sgbuf_ops_page,
1948 };
1949
1950 static void azx_pcm_free(struct snd_pcm *pcm)
1951 {
1952         struct azx_pcm *apcm = pcm->private_data;
1953         if (apcm) {
1954                 apcm->chip->pcm[pcm->device] = NULL;
1955                 kfree(apcm);
1956         }
1957 }
1958
1959 static int
1960 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1961                       struct hda_pcm *cpcm)
1962 {
1963         struct azx *chip = bus->private_data;
1964         struct snd_pcm *pcm;
1965         struct azx_pcm *apcm;
1966         int pcm_dev = cpcm->device;
1967         int s, err;
1968
1969         if (pcm_dev >= AZX_MAX_PCMS) {
1970                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1971                            pcm_dev);
1972                 return -EINVAL;
1973         }
1974         if (chip->pcm[pcm_dev]) {
1975                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1976                 return -EBUSY;
1977         }
1978         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1979                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1980                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1981                           &pcm);
1982         if (err < 0)
1983                 return err;
1984         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1985         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1986         if (apcm == NULL)
1987                 return -ENOMEM;
1988         apcm->chip = chip;
1989         apcm->codec = codec;
1990         pcm->private_data = apcm;
1991         pcm->private_free = azx_pcm_free;
1992         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1993                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1994         chip->pcm[pcm_dev] = pcm;
1995         cpcm->pcm = pcm;
1996         for (s = 0; s < 2; s++) {
1997                 apcm->hinfo[s] = &cpcm->stream[s];
1998                 if (cpcm->stream[s].substreams)
1999                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2000         }
2001         /* buffer pre-allocation */
2002         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2003                                               snd_dma_pci_data(chip->pci),
2004                                               1024 * 64, 32 * 1024 * 1024);
2005         return 0;
2006 }
2007
2008 /*
2009  * mixer creation - all stuff is implemented in hda module
2010  */
2011 static int __devinit azx_mixer_create(struct azx *chip)
2012 {
2013         return snd_hda_build_controls(chip->bus);
2014 }
2015
2016
2017 /*
2018  * initialize SD streams
2019  */
2020 static int __devinit azx_init_stream(struct azx *chip)
2021 {
2022         int i;
2023
2024         /* initialize each stream (aka device)
2025          * assign the starting bdl address to each stream (device)
2026          * and initialize
2027          */
2028         for (i = 0; i < chip->num_streams; i++) {
2029                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2030                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2031                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2032                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2033                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2034                 azx_dev->sd_int_sta_mask = 1 << i;
2035                 /* stream tag: must be non-zero and unique */
2036                 azx_dev->index = i;
2037                 azx_dev->stream_tag = i + 1;
2038         }
2039
2040         return 0;
2041 }
2042
2043 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2044 {
2045         if (request_irq(chip->pci->irq, azx_interrupt,
2046                         chip->msi ? 0 : IRQF_SHARED,
2047                         "HDA Intel", chip)) {
2048                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2049                        "disabling device\n", chip->pci->irq);
2050                 if (do_disconnect)
2051                         snd_card_disconnect(chip->card);
2052                 return -1;
2053         }
2054         chip->irq = chip->pci->irq;
2055         pci_intx(chip->pci, !chip->msi);
2056         return 0;
2057 }
2058
2059
2060 static void azx_stop_chip(struct azx *chip)
2061 {
2062         if (!chip->initialized)
2063                 return;
2064
2065         /* disable interrupts */
2066         azx_int_disable(chip);
2067         azx_int_clear(chip);
2068
2069         /* disable CORB/RIRB */
2070         azx_free_cmd_io(chip);
2071
2072         /* disable position buffer */
2073         azx_writel(chip, DPLBASE, 0);
2074         azx_writel(chip, DPUBASE, 0);
2075
2076         chip->initialized = 0;
2077 }
2078
2079 #ifdef CONFIG_SND_HDA_POWER_SAVE
2080 /* power-up/down the controller */
2081 static void azx_power_notify(struct hda_bus *bus)
2082 {
2083         struct azx *chip = bus->private_data;
2084         struct hda_codec *c;
2085         int power_on = 0;
2086
2087         list_for_each_entry(c, &bus->codec_list, list) {
2088                 if (c->power_on) {
2089                         power_on = 1;
2090                         break;
2091                 }
2092         }
2093         if (power_on)
2094                 azx_init_chip(chip);
2095         else if (chip->running && power_save_controller &&
2096                  !bus->power_keep_link_on)
2097                 azx_stop_chip(chip);
2098 }
2099 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2100
2101 #ifdef CONFIG_PM
2102 /*
2103  * power management
2104  */
2105
2106 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2107 {
2108         struct hda_codec *codec;
2109
2110         list_for_each_entry(codec, &bus->codec_list, list) {
2111                 if (snd_hda_codec_needs_resume(codec))
2112                         return 1;
2113         }
2114         return 0;
2115 }
2116
2117 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2118 {
2119         struct snd_card *card = pci_get_drvdata(pci);
2120         struct azx *chip = card->private_data;
2121         int i;
2122
2123         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2124         azx_clear_irq_pending(chip);
2125         for (i = 0; i < AZX_MAX_PCMS; i++)
2126                 snd_pcm_suspend_all(chip->pcm[i]);
2127         if (chip->initialized)
2128                 snd_hda_suspend(chip->bus);
2129         azx_stop_chip(chip);
2130         if (chip->irq >= 0) {
2131                 free_irq(chip->irq, chip);
2132                 chip->irq = -1;
2133         }
2134         if (chip->msi)
2135                 pci_disable_msi(chip->pci);
2136         pci_disable_device(pci);
2137         pci_save_state(pci);
2138         pci_set_power_state(pci, pci_choose_state(pci, state));
2139         return 0;
2140 }
2141
2142 static int azx_resume(struct pci_dev *pci)
2143 {
2144         struct snd_card *card = pci_get_drvdata(pci);
2145         struct azx *chip = card->private_data;
2146
2147         pci_set_power_state(pci, PCI_D0);
2148         pci_restore_state(pci);
2149         if (pci_enable_device(pci) < 0) {
2150                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2151                        "disabling device\n");
2152                 snd_card_disconnect(card);
2153                 return -EIO;
2154         }
2155         pci_set_master(pci);
2156         if (chip->msi)
2157                 if (pci_enable_msi(pci) < 0)
2158                         chip->msi = 0;
2159         if (azx_acquire_irq(chip, 1) < 0)
2160                 return -EIO;
2161         azx_init_pci(chip);
2162
2163         if (snd_hda_codecs_inuse(chip->bus))
2164                 azx_init_chip(chip);
2165
2166         snd_hda_resume(chip->bus);
2167         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2168         return 0;
2169 }
2170 #endif /* CONFIG_PM */
2171
2172
2173 /*
2174  * reboot notifier for hang-up problem at power-down
2175  */
2176 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2177 {
2178         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2179         snd_hda_bus_reboot_notify(chip->bus);
2180         azx_stop_chip(chip);
2181         return NOTIFY_OK;
2182 }
2183
2184 static void azx_notifier_register(struct azx *chip)
2185 {
2186         chip->reboot_notifier.notifier_call = azx_halt;
2187         register_reboot_notifier(&chip->reboot_notifier);
2188 }
2189
2190 static void azx_notifier_unregister(struct azx *chip)
2191 {
2192         if (chip->reboot_notifier.notifier_call)
2193                 unregister_reboot_notifier(&chip->reboot_notifier);
2194 }
2195
2196 /*
2197  * destructor
2198  */
2199 static int azx_free(struct azx *chip)
2200 {
2201         int i;
2202
2203         azx_notifier_unregister(chip);
2204
2205         if (chip->initialized) {
2206                 azx_clear_irq_pending(chip);
2207                 for (i = 0; i < chip->num_streams; i++)
2208                         azx_stream_stop(chip, &chip->azx_dev[i]);
2209                 azx_stop_chip(chip);
2210         }
2211
2212         if (chip->irq >= 0)
2213                 free_irq(chip->irq, (void*)chip);
2214         if (chip->msi)
2215                 pci_disable_msi(chip->pci);
2216         if (chip->remap_addr)
2217                 iounmap(chip->remap_addr);
2218
2219         if (chip->azx_dev) {
2220                 for (i = 0; i < chip->num_streams; i++)
2221                         if (chip->azx_dev[i].bdl.area)
2222                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2223         }
2224         if (chip->rb.area)
2225                 snd_dma_free_pages(&chip->rb);
2226         if (chip->posbuf.area)
2227                 snd_dma_free_pages(&chip->posbuf);
2228         pci_release_regions(chip->pci);
2229         pci_disable_device(chip->pci);
2230         kfree(chip->azx_dev);
2231         kfree(chip);
2232
2233         return 0;
2234 }
2235
2236 static int azx_dev_free(struct snd_device *device)
2237 {
2238         return azx_free(device->device_data);
2239 }
2240
2241 /*
2242  * white/black-listing for position_fix
2243  */
2244 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2245         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2246         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2247         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2248         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2249         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2250         {}
2251 };
2252
2253 static int __devinit check_position_fix(struct azx *chip, int fix)
2254 {
2255         const struct snd_pci_quirk *q;
2256
2257         switch (fix) {
2258         case POS_FIX_LPIB:
2259         case POS_FIX_POSBUF:
2260                 return fix;
2261         }
2262
2263         /* Check VIA/ATI HD Audio Controller exist */
2264         switch (chip->driver_type) {
2265         case AZX_DRIVER_VIA:
2266         case AZX_DRIVER_ATI:
2267                 chip->via_dmapos_patch = 1;
2268                 /* Use link position directly, avoid any transfer problem. */
2269                 return POS_FIX_LPIB;
2270         }
2271         chip->via_dmapos_patch = 0;
2272
2273         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2274         if (q) {
2275                 printk(KERN_INFO
2276                        "hda_intel: position_fix set to %d "
2277                        "for device %04x:%04x\n",
2278                        q->value, q->subvendor, q->subdevice);
2279                 return q->value;
2280         }
2281         return POS_FIX_AUTO;
2282 }
2283
2284 /*
2285  * black-lists for probe_mask
2286  */
2287 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2288         /* Thinkpad often breaks the controller communication when accessing
2289          * to the non-working (or non-existing) modem codec slot.
2290          */
2291         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2292         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2293         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2294         /* broken BIOS */
2295         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2296         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2297         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2298         /* forced codec slots */
2299         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2300         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2301         {}
2302 };
2303
2304 #define AZX_FORCE_CODEC_MASK    0x100
2305
2306 static void __devinit check_probe_mask(struct azx *chip, int dev)
2307 {
2308         const struct snd_pci_quirk *q;
2309
2310         chip->codec_probe_mask = probe_mask[dev];
2311         if (chip->codec_probe_mask == -1) {
2312                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2313                 if (q) {
2314                         printk(KERN_INFO
2315                                "hda_intel: probe_mask set to 0x%x "
2316                                "for device %04x:%04x\n",
2317                                q->value, q->subvendor, q->subdevice);
2318                         chip->codec_probe_mask = q->value;
2319                 }
2320         }
2321
2322         /* check forced option */
2323         if (chip->codec_probe_mask != -1 &&
2324             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2325                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2326                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2327                        chip->codec_mask);
2328         }
2329 }
2330
2331 /*
2332  * white/black-list for enable_msi
2333  */
2334 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2335         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2336         {}
2337 };
2338
2339 static void __devinit check_msi(struct azx *chip)
2340 {
2341         const struct snd_pci_quirk *q;
2342
2343         if (enable_msi >= 0) {
2344                 chip->msi = !!enable_msi;
2345                 return;
2346         }
2347         chip->msi = 1;  /* enable MSI as default */
2348         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2349         if (q) {
2350                 printk(KERN_INFO
2351                        "hda_intel: msi for device %04x:%04x set to %d\n",
2352                        q->subvendor, q->subdevice, q->value);
2353                 chip->msi = q->value;
2354         }
2355 }
2356
2357
2358 /*
2359  * constructor
2360  */
2361 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2362                                 int dev, int driver_type,
2363                                 struct azx **rchip)
2364 {
2365         struct azx *chip;
2366         int i, err;
2367         unsigned short gcap;
2368         static struct snd_device_ops ops = {
2369                 .dev_free = azx_dev_free,
2370         };
2371
2372         *rchip = NULL;
2373
2374         err = pci_enable_device(pci);
2375         if (err < 0)
2376                 return err;
2377
2378         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2379         if (!chip) {
2380                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2381                 pci_disable_device(pci);
2382                 return -ENOMEM;
2383         }
2384
2385         spin_lock_init(&chip->reg_lock);
2386         mutex_init(&chip->open_mutex);
2387         chip->card = card;
2388         chip->pci = pci;
2389         chip->irq = -1;
2390         chip->driver_type = driver_type;
2391         check_msi(chip);
2392         chip->dev_index = dev;
2393         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2394
2395         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2396         check_probe_mask(chip, dev);
2397
2398         chip->single_cmd = single_cmd;
2399
2400         if (bdl_pos_adj[dev] < 0) {
2401                 switch (chip->driver_type) {
2402                 case AZX_DRIVER_ICH:
2403                         bdl_pos_adj[dev] = 1;
2404                         break;
2405                 default:
2406                         bdl_pos_adj[dev] = 32;
2407                         break;
2408                 }
2409         }
2410
2411 #if BITS_PER_LONG != 64
2412         /* Fix up base address on ULI M5461 */
2413         if (chip->driver_type == AZX_DRIVER_ULI) {
2414                 u16 tmp3;
2415                 pci_read_config_word(pci, 0x40, &tmp3);
2416                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2417                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2418         }
2419 #endif
2420
2421         err = pci_request_regions(pci, "ICH HD audio");
2422         if (err < 0) {
2423                 kfree(chip);
2424                 pci_disable_device(pci);
2425                 return err;
2426         }
2427
2428         chip->addr = pci_resource_start(pci, 0);
2429         chip->remap_addr = pci_ioremap_bar(pci, 0);
2430         if (chip->remap_addr == NULL) {
2431                 snd_printk(KERN_ERR SFX "ioremap error\n");
2432                 err = -ENXIO;
2433                 goto errout;
2434         }
2435
2436         if (chip->msi)
2437                 if (pci_enable_msi(pci) < 0)
2438                         chip->msi = 0;
2439
2440         if (azx_acquire_irq(chip, 0) < 0) {
2441                 err = -EBUSY;
2442                 goto errout;
2443         }
2444
2445         pci_set_master(pci);
2446         synchronize_irq(chip->irq);
2447
2448         gcap = azx_readw(chip, GCAP);
2449         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2450
2451         /* disable SB600 64bit support for safety */
2452         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2453             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2454                 struct pci_dev *p_smbus;
2455                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2456                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2457                                          NULL);
2458                 if (p_smbus) {
2459                         if (p_smbus->revision < 0x30)
2460                                 gcap &= ~ICH6_GCAP_64OK;
2461                         pci_dev_put(p_smbus);
2462                 }
2463         }
2464
2465         /* disable 64bit DMA address for Teradici */
2466         /* it does not work with device 6549:1200 subsys e4a2:040b */
2467         if (chip->driver_type == AZX_DRIVER_TERA)
2468                 gcap &= ~ICH6_GCAP_64OK;
2469
2470         /* allow 64bit DMA address if supported by H/W */
2471         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2472                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2473         else {
2474                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2475                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2476         }
2477
2478         /* read number of streams from GCAP register instead of using
2479          * hardcoded value
2480          */
2481         chip->capture_streams = (gcap >> 8) & 0x0f;
2482         chip->playback_streams = (gcap >> 12) & 0x0f;
2483         if (!chip->playback_streams && !chip->capture_streams) {
2484                 /* gcap didn't give any info, switching to old method */
2485
2486                 switch (chip->driver_type) {
2487                 case AZX_DRIVER_ULI:
2488                         chip->playback_streams = ULI_NUM_PLAYBACK;
2489                         chip->capture_streams = ULI_NUM_CAPTURE;
2490                         break;
2491                 case AZX_DRIVER_ATIHDMI:
2492                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2493                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2494                         break;
2495                 case AZX_DRIVER_GENERIC:
2496                 default:
2497                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2498                         chip->capture_streams = ICH6_NUM_CAPTURE;
2499                         break;
2500                 }
2501         }
2502         chip->capture_index_offset = 0;
2503         chip->playback_index_offset = chip->capture_streams;
2504         chip->num_streams = chip->playback_streams + chip->capture_streams;
2505         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2506                                 GFP_KERNEL);
2507         if (!chip->azx_dev) {
2508                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2509                 goto errout;
2510         }
2511
2512         for (i = 0; i < chip->num_streams; i++) {
2513                 /* allocate memory for the BDL for each stream */
2514                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2515                                           snd_dma_pci_data(chip->pci),
2516                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2517                 if (err < 0) {
2518                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2519                         goto errout;
2520                 }
2521         }
2522         /* allocate memory for the position buffer */
2523         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2524                                   snd_dma_pci_data(chip->pci),
2525                                   chip->num_streams * 8, &chip->posbuf);
2526         if (err < 0) {
2527                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2528                 goto errout;
2529         }
2530         /* allocate CORB/RIRB */
2531         err = azx_alloc_cmd_io(chip);
2532         if (err < 0)
2533                 goto errout;
2534
2535         /* initialize streams */
2536         azx_init_stream(chip);
2537
2538         /* initialize chip */
2539         azx_init_pci(chip);
2540         azx_init_chip(chip);
2541
2542         /* codec detection */
2543         if (!chip->codec_mask) {
2544                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2545                 err = -ENODEV;
2546                 goto errout;
2547         }
2548
2549         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2550         if (err <0) {
2551                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2552                 goto errout;
2553         }
2554
2555         strcpy(card->driver, "HDA-Intel");
2556         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2557                 sizeof(card->shortname));
2558         snprintf(card->longname, sizeof(card->longname),
2559                  "%s at 0x%lx irq %i",
2560                  card->shortname, chip->addr, chip->irq);
2561
2562         *rchip = chip;
2563         return 0;
2564
2565  errout:
2566         azx_free(chip);
2567         return err;
2568 }
2569
2570 static void power_down_all_codecs(struct azx *chip)
2571 {
2572 #ifdef CONFIG_SND_HDA_POWER_SAVE
2573         /* The codecs were powered up in snd_hda_codec_new().
2574          * Now all initialization done, so turn them down if possible
2575          */
2576         struct hda_codec *codec;
2577         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2578                 snd_hda_power_down(codec);
2579         }
2580 #endif
2581 }
2582
2583 static int __devinit azx_probe(struct pci_dev *pci,
2584                                const struct pci_device_id *pci_id)
2585 {
2586         static int dev;
2587         struct snd_card *card;
2588         struct azx *chip;
2589         int err;
2590
2591         if (dev >= SNDRV_CARDS)
2592                 return -ENODEV;
2593         if (!enable[dev]) {
2594                 dev++;
2595                 return -ENOENT;
2596         }
2597
2598         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2599         if (err < 0) {
2600                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2601                 return err;
2602         }
2603
2604         /* set this here since it's referred in snd_hda_load_patch() */
2605         snd_card_set_dev(card, &pci->dev);
2606
2607         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2608         if (err < 0)
2609                 goto out_free;
2610         card->private_data = chip;
2611
2612 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2613         chip->beep_mode = beep_mode[dev];
2614 #endif
2615
2616         /* create codec instances */
2617         err = azx_codec_create(chip, model[dev]);
2618         if (err < 0)
2619                 goto out_free;
2620 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2621         if (patch[dev]) {
2622                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2623                            patch[dev]);
2624                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2625                 if (err < 0)
2626                         goto out_free;
2627         }
2628 #endif
2629         if (!probe_only[dev]) {
2630                 err = azx_codec_configure(chip);
2631                 if (err < 0)
2632                         goto out_free;
2633         }
2634
2635         /* create PCM streams */
2636         err = snd_hda_build_pcms(chip->bus);
2637         if (err < 0)
2638                 goto out_free;
2639
2640         /* create mixer controls */
2641         err = azx_mixer_create(chip);
2642         if (err < 0)
2643                 goto out_free;
2644
2645         err = snd_card_register(card);
2646         if (err < 0)
2647                 goto out_free;
2648
2649         pci_set_drvdata(pci, card);
2650         chip->running = 1;
2651         power_down_all_codecs(chip);
2652         azx_notifier_register(chip);
2653
2654         dev++;
2655         return err;
2656 out_free:
2657         snd_card_free(card);
2658         return err;
2659 }
2660
2661 static void __devexit azx_remove(struct pci_dev *pci)
2662 {
2663         snd_card_free(pci_get_drvdata(pci));
2664         pci_set_drvdata(pci, NULL);
2665 }
2666
2667 /* PCI IDs */
2668 static struct pci_device_id azx_ids[] = {
2669         /* ICH 6..10 */
2670         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2671         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2672         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2673         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2674         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2675         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2676         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2677         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2678         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2679         /* PCH */
2680         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2681         /* CPT */
2682         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_ICH },
2683         /* SCH */
2684         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2685         /* ATI SB 450/600 */
2686         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2687         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2688         /* ATI HDMI */
2689         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2690         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2691         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2692         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2693         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2694         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2695         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2696         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2697         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2698         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2699         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2700         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2701         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2702         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2703         /* VIA VT8251/VT8237A */
2704         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2705         /* SIS966 */
2706         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2707         /* ULI M5461 */
2708         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2709         /* NVIDIA MCP */
2710         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2711           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2712           .class_mask = 0xffffff,
2713           .driver_data = AZX_DRIVER_NVIDIA },
2714         /* Teradici */
2715         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2716         /* Creative X-Fi (CA0110-IBG) */
2717 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2718         /* the following entry conflicts with snd-ctxfi driver,
2719          * as ctxfi driver mutates from HD-audio to native mode with
2720          * a special command sequence.
2721          */
2722         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2723           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2724           .class_mask = 0xffffff,
2725           .driver_data = AZX_DRIVER_GENERIC },
2726 #else
2727         /* this entry seems still valid -- i.e. without emu20kx chip */
2728         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2729 #endif
2730         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2731         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2732           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2733           .class_mask = 0xffffff,
2734           .driver_data = AZX_DRIVER_GENERIC },
2735         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2736           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2737           .class_mask = 0xffffff,
2738           .driver_data = AZX_DRIVER_GENERIC },
2739         { 0, }
2740 };
2741 MODULE_DEVICE_TABLE(pci, azx_ids);
2742
2743 /* pci_driver definition */
2744 static struct pci_driver driver = {
2745         .name = "HDA Intel",
2746         .id_table = azx_ids,
2747         .probe = azx_probe,
2748         .remove = __devexit_p(azx_remove),
2749 #ifdef CONFIG_PM
2750         .suspend = azx_suspend,
2751         .resume = azx_resume,
2752 #endif
2753 };
2754
2755 static int __init alsa_card_azx_init(void)
2756 {
2757         return pci_register_driver(&driver);
2758 }
2759
2760 static void __exit alsa_card_azx_exit(void)
2761 {
2762         pci_unregister_driver(&driver);
2763 }
2764
2765 module_init(alsa_card_azx_init)
2766 module_exit(alsa_card_azx_exit)