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   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi;
  64
  65 module_param_array(index, int, NULL, 0444);
  66 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  67 module_param_array(id, charp, NULL, 0444);
  68 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  69 module_param_array(enable, bool, NULL, 0444);
  70 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  71 module_param_array(model, charp, NULL, 0444);
  72 MODULE_PARM_DESC(model, "Use the given board model.");
  73 module_param_array(position_fix, int, NULL, 0444);
  74 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  75                  "(0 = auto, 1 = none, 2 = POSBUF).");
  76 module_param_array(bdl_pos_adj, int, NULL, 0644);
  77 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  78 module_param_array(probe_mask, int, NULL, 0444);
  79 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  80 module_param_array(probe_only, bool, NULL, 0444);
  81 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  82 module_param(single_cmd, bool, 0444);
  83 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  84                  "(for debugging only).");
  85 module_param(enable_msi, int, 0444);
  86 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  87
  88 #ifdef CONFIG_SND_HDA_POWER_SAVE
  89 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
  90 module_param(power_save, int, 0644);
  91 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
  92                  "(in second, 0 = disable).");
  93
  94 /* reset the HD-audio controller in power save mode.
  95  * this may give more power-saving, but will take longer time to
  96  * wake up.
  97  */
  98 static int power_save_controller = 1;
  99 module_param(power_save_controller, bool, 0644);
 100 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 101 #endif
 102
 103 MODULE_LICENSE("GPL");
 104 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 105                          "{Intel, ICH6M},"
 106                          "{Intel, ICH7},"
 107                          "{Intel, ESB2},"
 108                          "{Intel, ICH8},"
 109                          "{Intel, ICH9},"
 110                          "{Intel, ICH10},"
 111                          "{Intel, PCH},"
 112                          "{Intel, SCH},"
 113                          "{ATI, SB450},"
 114                          "{ATI, SB600},"
 115                          "{ATI, RS600},"
 116                          "{ATI, RS690},"
 117                          "{ATI, RS780},"
 118                          "{ATI, R600},"
 119                          "{ATI, RV630},"
 120                          "{ATI, RV610},"
 121                          "{ATI, RV670},"
 122                          "{ATI, RV635},"
 123                          "{ATI, RV620},"
 124                          "{ATI, RV770},"
 125                          "{VIA, VT8251},"
 126                          "{VIA, VT8237A},"
 127                          "{SiS, SIS966},"
 128                          "{ULI, M5461}}");
 129 MODULE_DESCRIPTION("Intel HDA driver");
 130
 131 #ifdef CONFIG_SND_VERBOSE_PRINTK
 132 #define SFX     /* nop */
 133 #else
 134 #define SFX     "hda-intel: "
 135 #endif
 136
 137 /*
 138  * registers
 139  */
 140 #define ICH6_REG_GCAP                   0x00
 141 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 142 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 143 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 144 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 145 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 146 #define ICH6_REG_VMIN                   0x02
 147 #define ICH6_REG_VMAJ                   0x03
 148 #define ICH6_REG_OUTPAY                 0x04
 149 #define ICH6_REG_INPAY                  0x06
 150 #define ICH6_REG_GCTL                   0x08
 151 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 152 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 153 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 154 #define ICH6_REG_WAKEEN                 0x0c
 155 #define ICH6_REG_STATESTS               0x0e
 156 #define ICH6_REG_GSTS                   0x10
 157 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 158 #define ICH6_REG_INTCTL                 0x20
 159 #define ICH6_REG_INTSTS                 0x24
 160 #define ICH6_REG_WALCLK                 0x30
 161 #define ICH6_REG_SYNC                   0x34
 162 #define ICH6_REG_CORBLBASE              0x40
 163 #define ICH6_REG_CORBUBASE              0x44
 164 #define ICH6_REG_CORBWP                 0x48
 165 #define ICH6_REG_CORBRP                 0x4a
 166 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 167 #define ICH6_REG_CORBCTL                0x4c
 168 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 169 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 170 #define ICH6_REG_CORBSTS                0x4d
 171 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 172 #define ICH6_REG_CORBSIZE               0x4e
 173
 174 #define ICH6_REG_RIRBLBASE              0x50
 175 #define ICH6_REG_RIRBUBASE              0x54
 176 #define ICH6_REG_RIRBWP                 0x58
 177 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 178 #define ICH6_REG_RINTCNT                0x5a
 179 #define ICH6_REG_RIRBCTL                0x5c
 180 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 181 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 182 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 183 #define ICH6_REG_RIRBSTS                0x5d
 184 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 185 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 186 #define ICH6_REG_RIRBSIZE               0x5e
 187
 188 #define ICH6_REG_IC                     0x60
 189 #define ICH6_REG_IR                     0x64
 190 #define ICH6_REG_IRS                    0x68
 191 #define   ICH6_IRS_VALID        (1<<1)
 192 #define   ICH6_IRS_BUSY         (1<<0)
 193
 194 #define ICH6_REG_DPLBASE                0x70
 195 #define ICH6_REG_DPUBASE                0x74
 196 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 197
 198 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 199 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 200
 201 /* stream register offsets from stream base */
 202 #define ICH6_REG_SD_CTL                 0x00
 203 #define ICH6_REG_SD_STS                 0x03
 204 #define ICH6_REG_SD_LPIB                0x04
 205 #define ICH6_REG_SD_CBL                 0x08
 206 #define ICH6_REG_SD_LVI                 0x0c
 207 #define ICH6_REG_SD_FIFOW               0x0e
 208 #define ICH6_REG_SD_FIFOSIZE            0x10
 209 #define ICH6_REG_SD_FORMAT              0x12
 210 #define ICH6_REG_SD_BDLPL               0x18
 211 #define ICH6_REG_SD_BDLPU               0x1c
 212
 213 /* PCI space */
 214 #define ICH6_PCIREG_TCSEL       0x44
 215
 216 /*
 217  * other constants
 218  */
 219
 220 /* max number of SDs */
 221 /* ICH, ATI and VIA have 4 playback and 4 capture */
 222 #define ICH6_NUM_CAPTURE        4
 223 #define ICH6_NUM_PLAYBACK       4
 224
 225 /* ULI has 6 playback and 5 capture */
 226 #define ULI_NUM_CAPTURE         5
 227 #define ULI_NUM_PLAYBACK        6
 228
 229 /* ATI HDMI has 1 playback and 0 capture */
 230 #define ATIHDMI_NUM_CAPTURE     0
 231 #define ATIHDMI_NUM_PLAYBACK    1
 232
 233 /* TERA has 4 playback and 3 capture */
 234 #define TERA_NUM_CAPTURE        3
 235 #define TERA_NUM_PLAYBACK       4
 236
 237 /* this number is statically defined for simplicity */
 238 #define MAX_AZX_DEV             16
 239
 240 /* max number of fragments - we may use more if allocating more pages for BDL */
 241 #define BDL_SIZE                4096
 242 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 243 #define AZX_MAX_FRAG            32
 244 /* max buffer size - no h/w limit, you can increase as you like */
 245 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 246 /* max number of PCM devics per card */
 247 #define AZX_MAX_PCMS            8
 248
 249 /* RIRB int mask: overrun[2], response[0] */
 250 #define RIRB_INT_RESPONSE       0x01
 251 #define RIRB_INT_OVERRUN        0x04
 252 #define RIRB_INT_MASK           0x05
 253
 254 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 255 #define AZX_MAX_CODECS          4
 256 #define STATESTS_INT_MASK       0x0f
 257
 258 /* SD_CTL bits */
 259 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 260 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 261 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 262 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 263 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 264 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 265 #define SD_CTL_STREAM_TAG_SHIFT 20
 266
 267 /* SD_CTL and SD_STS */
 268 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 269 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 270 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 271 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 272                                  SD_INT_COMPLETE)
 273
 274 /* SD_STS */
 275 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 276
 277 /* INTCTL and INTSTS */
 278 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 279 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 280 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 281
 282 /* below are so far hardcoded - should read registers in future */
 283 #define ICH6_MAX_CORB_ENTRIES   256
 284 #define ICH6_MAX_RIRB_ENTRIES   256
 285
 286 /* position fix mode */
 287 enum {
 288         POS_FIX_AUTO,
 289         POS_FIX_LPIB,
 290         POS_FIX_POSBUF,
 291 };
 292
 293 /* Defines for ATI HD Audio support in SB450 south bridge */
 294 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 295 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 296
 297 /* Defines for Nvidia HDA support */
 298 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 299 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 300 #define NVIDIA_HDA_ISTRM_COH          0x4d
 301 #define NVIDIA_HDA_OSTRM_COH          0x4c
 302 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 303
 304 /* Defines for Intel SCH HDA snoop control */
 305 #define INTEL_SCH_HDA_DEVC      0x78
 306 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 307
 308 /* Define IN stream 0 FIFO size offset in VIA controller */
 309 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 310 /* Define VIA HD Audio Device ID*/
 311 #define VIA_HDAC_DEVICE_ID              0x3288
 312
 313 /* HD Audio class code */
 314 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 315
 316 /*
 317  */
 318
 319 struct azx_dev {
 320         struct snd_dma_buffer bdl; /* BDL buffer */
 321         u32 *posbuf;            /* position buffer pointer */
 322
 323         unsigned int bufsize;   /* size of the play buffer in bytes */
 324         unsigned int period_bytes; /* size of the period in bytes */
 325         unsigned int frags;     /* number for period in the play buffer */
 326         unsigned int fifo_size; /* FIFO size */
 327         unsigned long start_jiffies;    /* start + minimum jiffies */
 328         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 329
 330         void __iomem *sd_addr;  /* stream descriptor pointer */
 331
 332         u32 sd_int_sta_mask;    /* stream int status mask */
 333
 334         /* pcm support */
 335         struct snd_pcm_substream *substream;    /* assigned substream,
 336                                                  * set in PCM open
 337                                                  */
 338         unsigned int format_val;        /* format value to be set in the
 339                                          * controller and the codec
 340                                          */
 341         unsigned char stream_tag;       /* assigned stream */
 342         unsigned char index;            /* stream index */
 343
 344         unsigned int opened :1;
 345         unsigned int running :1;
 346         unsigned int irq_pending :1;
 347         unsigned int start_flag: 1;     /* stream full start flag */
 348         /*
 349          * For VIA:
 350          *  A flag to ensure DMA position is 0
 351          *  when link position is not greater than FIFO size
 352          */
 353         unsigned int insufficient :1;
 354 };
 355
 356 /* CORB/RIRB */
 357 struct azx_rb {
 358         u32 *buf;               /* CORB/RIRB buffer
 359                                  * Each CORB entry is 4byte, RIRB is 8byte
 360                                  */
 361         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 362         /* for RIRB */
 363         unsigned short rp, wp;  /* read/write pointers */
 364         int cmds;               /* number of pending requests */
 365         u32 res;                /* last read value */
 366 };
 367
 368 struct azx {
 369         struct snd_card *card;
 370         struct pci_dev *pci;
 371         int dev_index;
 372
 373         /* chip type specific */
 374         int driver_type;
 375         int playback_streams;
 376         int playback_index_offset;
 377         int capture_streams;
 378         int capture_index_offset;
 379         int num_streams;
 380
 381         /* pci resources */
 382         unsigned long addr;
 383         void __iomem *remap_addr;
 384         int irq;
 385
 386         /* locks */
 387         spinlock_t reg_lock;
 388         struct mutex open_mutex;
 389
 390         /* streams (x num_streams) */
 391         struct azx_dev *azx_dev;
 392
 393         /* PCM */
 394         struct snd_pcm *pcm[AZX_MAX_PCMS];
 395
 396         /* HD codec */
 397         unsigned short codec_mask;
 398         int  codec_probe_mask; /* copied from probe_mask option */
 399         struct hda_bus *bus;
 400
 401         /* CORB/RIRB */
 402         struct azx_rb corb;
 403         struct azx_rb rirb;
 404
 405         /* CORB/RIRB and position buffers */
 406         struct snd_dma_buffer rb;
 407         struct snd_dma_buffer posbuf;
 408
 409         /* flags */
 410         int position_fix;
 411         unsigned int running :1;
 412         unsigned int initialized :1;
 413         unsigned int single_cmd :1;
 414         unsigned int polling_mode :1;
 415         unsigned int msi :1;
 416         unsigned int irq_pending_warned :1;
 417         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 418         unsigned int probing :1; /* codec probing phase */
 419
 420         /* for debugging */
 421         unsigned int last_cmd;  /* last issued command (to sync) */
 422
 423         /* for pending irqs */
 424         struct work_struct irq_pending_work;
 425
 426         /* reboot notifier (for mysterious hangup problem at power-down) */
 427         struct notifier_block reboot_notifier;
 428 };
 429
 430 /* driver types */
 431 enum {
 432         AZX_DRIVER_ICH,
 433         AZX_DRIVER_SCH,
 434         AZX_DRIVER_ATI,
 435         AZX_DRIVER_ATIHDMI,
 436         AZX_DRIVER_VIA,
 437         AZX_DRIVER_SIS,
 438         AZX_DRIVER_ULI,
 439         AZX_DRIVER_NVIDIA,
 440         AZX_DRIVER_TERA,
 441         AZX_DRIVER_GENERIC,
 442         AZX_NUM_DRIVERS, /* keep this as last entry */
 443 };
 444
 445 static char *driver_short_names[] __devinitdata = {
 446         [AZX_DRIVER_ICH] = "HDA Intel",
 447         [AZX_DRIVER_SCH] = "HDA Intel MID",
 448         [AZX_DRIVER_ATI] = "HDA ATI SB",
 449         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 450         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 451         [AZX_DRIVER_SIS] = "HDA SIS966",
 452         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 453         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 454         [AZX_DRIVER_TERA] = "HDA Teradici",
 455         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 456 };
 457
 458 /*
 459  * macros for easy use
 460  */
 461 #define azx_writel(chip,reg,value) \
 462         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 463 #define azx_readl(chip,reg) \
 464         readl((chip)->remap_addr + ICH6_REG_##reg)
 465 #define azx_writew(chip,reg,value) \
 466         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 467 #define azx_readw(chip,reg) \
 468         readw((chip)->remap_addr + ICH6_REG_##reg)
 469 #define azx_writeb(chip,reg,value) \
 470         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 471 #define azx_readb(chip,reg) \
 472         readb((chip)->remap_addr + ICH6_REG_##reg)
 473
 474 #define azx_sd_writel(dev,reg,value) \
 475         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 476 #define azx_sd_readl(dev,reg) \
 477         readl((dev)->sd_addr + ICH6_REG_##reg)
 478 #define azx_sd_writew(dev,reg,value) \
 479         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 480 #define azx_sd_readw(dev,reg) \
 481         readw((dev)->sd_addr + ICH6_REG_##reg)
 482 #define azx_sd_writeb(dev,reg,value) \
 483         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 484 #define azx_sd_readb(dev,reg) \
 485         readb((dev)->sd_addr + ICH6_REG_##reg)
 486
 487 /* for pcm support */
 488 #define get_azx_dev(substream) (substream->runtime->private_data)
 489
 490 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 491
 492 /*
 493  * Interface for HD codec
 494  */
 495
 496 /*
 497  * CORB / RIRB interface
 498  */
 499 static int azx_alloc_cmd_io(struct azx *chip)
 500 {
 501         int err;
 502
 503         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 504         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 505                                   snd_dma_pci_data(chip->pci),
 506                                   PAGE_SIZE, &chip->rb);
 507         if (err < 0) {
 508                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 509                 return err;
 510         }
 511         return 0;
 512 }
 513
 514 static void azx_init_cmd_io(struct azx *chip)
 515 {
 516         /* CORB set up */
 517         chip->corb.addr = chip->rb.addr;
 518         chip->corb.buf = (u32 *)chip->rb.area;
 519         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 520         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 521
 522         /* set the corb size to 256 entries (ULI requires explicitly) */
 523         azx_writeb(chip, CORBSIZE, 0x02);
 524         /* set the corb write pointer to 0 */
 525         azx_writew(chip, CORBWP, 0);
 526         /* reset the corb hw read pointer */
 527         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 528         /* enable corb dma */
 529         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 530
 531         /* RIRB set up */
 532         chip->rirb.addr = chip->rb.addr + 2048;
 533         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 534         chip->rirb.wp = chip->rirb.rp = chip->rirb.cmds = 0;
 535         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 536         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 537
 538         /* set the rirb size to 256 entries (ULI requires explicitly) */
 539         azx_writeb(chip, RIRBSIZE, 0x02);
 540         /* reset the rirb hw write pointer */
 541         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 542         /* set N=1, get RIRB response interrupt for new entry */
 543         azx_writew(chip, RINTCNT, 1);
 544         /* enable rirb dma and response irq */
 545         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 546 }
 547
 548 static void azx_free_cmd_io(struct azx *chip)
 549 {
 550         /* disable ringbuffer DMAs */
 551         azx_writeb(chip, RIRBCTL, 0);
 552         azx_writeb(chip, CORBCTL, 0);
 553 }
 554
 555 /* send a command */
 556 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 557 {
 558         struct azx *chip = bus->private_data;
 559         unsigned int wp;
 560
 561         /* add command to corb */
 562         wp = azx_readb(chip, CORBWP);
 563         wp++;
 564         wp %= ICH6_MAX_CORB_ENTRIES;
 565
 566         spin_lock_irq(&chip->reg_lock);
 567         chip->rirb.cmds++;
 568         chip->corb.buf[wp] = cpu_to_le32(val);
 569         azx_writel(chip, CORBWP, wp);
 570         spin_unlock_irq(&chip->reg_lock);
 571
 572         return 0;
 573 }
 574
 575 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 576
 577 /* retrieve RIRB entry - called from interrupt handler */
 578 static void azx_update_rirb(struct azx *chip)
 579 {
 580         unsigned int rp, wp;
 581         u32 res, res_ex;
 582
 583         wp = azx_readb(chip, RIRBWP);
 584         if (wp == chip->rirb.wp)
 585                 return;
 586         chip->rirb.wp = wp;
 587
 588         while (chip->rirb.rp != wp) {
 589                 chip->rirb.rp++;
 590                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 591
 592                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 593                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 594                 res = le32_to_cpu(chip->rirb.buf[rp]);
 595                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 596                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 597                 else if (chip->rirb.cmds) {
 598                         chip->rirb.res = res;
 599                         smp_wmb();
 600                         chip->rirb.cmds--;
 601                 }
 602         }
 603 }
 604
 605 /* receive a response */
 606 static unsigned int azx_rirb_get_response(struct hda_bus *bus)
 607 {
 608         struct azx *chip = bus->private_data;
 609         unsigned long timeout;
 610
 611  again:
 612         timeout = jiffies + msecs_to_jiffies(1000);
 613         for (;;) {
 614                 if (chip->polling_mode) {
 615                         spin_lock_irq(&chip->reg_lock);
 616                         azx_update_rirb(chip);
 617                         spin_unlock_irq(&chip->reg_lock);
 618                 }
 619                 if (!chip->rirb.cmds) {
 620                         smp_rmb();
 621                         bus->rirb_error = 0;
 622                         return chip->rirb.res; /* the last value */
 623                 }
 624                 if (time_after(jiffies, timeout))
 625                         break;
 626                 if (bus->needs_damn_long_delay)
 627                         msleep(2); /* temporary workaround */
 628                 else {
 629                         udelay(10);
 630                         cond_resched();
 631                 }
 632         }
 633
 634         if (chip->msi) {
 635                 snd_printk(KERN_WARNING SFX "No response from codec, "
 636                            "disabling MSI: last cmd=0x%08x\n", chip->last_cmd);
 637                 free_irq(chip->irq, chip);
 638                 chip->irq = -1;
 639                 pci_disable_msi(chip->pci);
 640                 chip->msi = 0;
 641                 if (azx_acquire_irq(chip, 1) < 0) {
 642                         bus->rirb_error = 1;
 643                         return -1;
 644                 }
 645                 goto again;
 646         }
 647
 648         if (!chip->polling_mode) {
 649                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 650                            "switching to polling mode: last cmd=0x%08x\n",
 651                            chip->last_cmd);
 652                 chip->polling_mode = 1;
 653                 goto again;
 654         }
 655
 656         if (chip->probing) {
 657                 /* If this critical timeout happens during the codec probing
 658                  * phase, this is likely an access to a non-existing codec
 659                  * slot.  Better to return an error and reset the system.
 660                  */
 661                 return -1;
 662         }
 663
 664         snd_printk(KERN_ERR SFX "azx_get_response timeout (ERROR): "
 665                    "last cmd=0x%08x\n", chip->last_cmd);
 666         /* re-initialize CORB/RIRB */
 667         spin_lock_irq(&chip->reg_lock);
 668         bus->rirb_error = 1;
 669         azx_free_cmd_io(chip);
 670         azx_init_cmd_io(chip);
 671         spin_unlock_irq(&chip->reg_lock);
 672         return -1;
 673 }
 674
 675 /*
 676  * Use the single immediate command instead of CORB/RIRB for simplicity
 677  *
 678  * Note: according to Intel, this is not preferred use.  The command was
 679  *       intended for the BIOS only, and may get confused with unsolicited
 680  *       responses.  So, we shouldn't use it for normal operation from the
 681  *       driver.
 682  *       I left the codes, however, for debugging/testing purposes.
 683  */
 684
 685 /* receive a response */
 686 static int azx_single_wait_for_response(struct azx *chip)
 687 {
 688         int timeout = 50;
 689
 690         while (timeout--) {
 691                 /* check IRV busy bit */
 692                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 693                         /* reuse rirb.res as the response return value */
 694                         chip->rirb.res = azx_readl(chip, IR);
 695                         return 0;
 696                 }
 697                 udelay(1);
 698         }
 699         if (printk_ratelimit())
 700                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 701                            azx_readw(chip, IRS));
 702         chip->rirb.res = -1;
 703         return -EIO;
 704 }
 705
 706 /* send a command */
 707 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 708 {
 709         struct azx *chip = bus->private_data;
 710         int timeout = 50;
 711
 712         while (timeout--) {
 713                 /* check ICB busy bit */
 714                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 715                         /* Clear IRV valid bit */
 716                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 717                                    ICH6_IRS_VALID);
 718                         azx_writel(chip, IC, val);
 719                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 720                                    ICH6_IRS_BUSY);
 721                         return azx_single_wait_for_response(chip);
 722                 }
 723                 udelay(1);
 724         }
 725         if (printk_ratelimit())
 726                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 727                            azx_readw(chip, IRS), val);
 728         return -EIO;
 729 }
 730
 731 /* receive a response */
 732 static unsigned int azx_single_get_response(struct hda_bus *bus)
 733 {
 734         struct azx *chip = bus->private_data;
 735         return chip->rirb.res;
 736 }
 737
 738 /*
 739  * The below are the main callbacks from hda_codec.
 740  *
 741  * They are just the skeleton to call sub-callbacks according to the
 742  * current setting of chip->single_cmd.
 743  */
 744
 745 /* send a command */
 746 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 747 {
 748         struct azx *chip = bus->private_data;
 749
 750         chip->last_cmd = val;
 751         if (chip->single_cmd)
 752                 return azx_single_send_cmd(bus, val);
 753         else
 754                 return azx_corb_send_cmd(bus, val);
 755 }
 756
 757 /* get a response */
 758 static unsigned int azx_get_response(struct hda_bus *bus)
 759 {
 760         struct azx *chip = bus->private_data;
 761         if (chip->single_cmd)
 762                 return azx_single_get_response(bus);
 763         else
 764                 return azx_rirb_get_response(bus);
 765 }
 766
 767 #ifdef CONFIG_SND_HDA_POWER_SAVE
 768 static void azx_power_notify(struct hda_bus *bus);
 769 #endif
 770
 771 /* reset codec link */
 772 static int azx_reset(struct azx *chip)
 773 {
 774         int count;
 775
 776         /* clear STATESTS */
 777         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 778
 779         /* reset controller */
 780         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 781
 782         count = 50;
 783         while (azx_readb(chip, GCTL) && --count)
 784                 msleep(1);
 785
 786         /* delay for >= 100us for codec PLL to settle per spec
 787          * Rev 0.9 section 5.5.1
 788          */
 789         msleep(1);
 790
 791         /* Bring controller out of reset */
 792         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 793
 794         count = 50;
 795         while (!azx_readb(chip, GCTL) && --count)
 796                 msleep(1);
 797
 798         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 799         msleep(1);
 800
 801         /* check to see if controller is ready */
 802         if (!azx_readb(chip, GCTL)) {
 803                 snd_printd(SFX "azx_reset: controller not ready!\n");
 804                 return -EBUSY;
 805         }
 806
 807         /* Accept unsolicited responses */
 808         azx_writel(chip, GCTL, azx_readl(chip, GCTL) | ICH6_GCTL_UNSOL);
 809
 810         /* detect codecs */
 811         if (!chip->codec_mask) {
 812                 chip->codec_mask = azx_readw(chip, STATESTS);
 813                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 814         }
 815
 816         return 0;
 817 }
 818
 819
 820 /*
 821  * Lowlevel interface
 822  */
 823
 824 /* enable interrupts */
 825 static void azx_int_enable(struct azx *chip)
 826 {
 827         /* enable controller CIE and GIE */
 828         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 829                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 830 }
 831
 832 /* disable interrupts */
 833 static void azx_int_disable(struct azx *chip)
 834 {
 835         int i;
 836
 837         /* disable interrupts in stream descriptor */
 838         for (i = 0; i < chip->num_streams; i++) {
 839                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 840                 azx_sd_writeb(azx_dev, SD_CTL,
 841                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 842         }
 843
 844         /* disable SIE for all streams */
 845         azx_writeb(chip, INTCTL, 0);
 846
 847         /* disable controller CIE and GIE */
 848         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 849                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 850 }
 851
 852 /* clear interrupts */
 853 static void azx_int_clear(struct azx *chip)
 854 {
 855         int i;
 856
 857         /* clear stream status */
 858         for (i = 0; i < chip->num_streams; i++) {
 859                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 860                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 861         }
 862
 863         /* clear STATESTS */
 864         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 865
 866         /* clear rirb status */
 867         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 868
 869         /* clear int status */
 870         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 871 }
 872
 873 /* start a stream */
 874 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 875 {
 876         /*
 877          * Before stream start, initialize parameter
 878          */
 879         azx_dev->insufficient = 1;
 880
 881         /* enable SIE */
 882         azx_writeb(chip, INTCTL,
 883                    azx_readb(chip, INTCTL) | (1 << azx_dev->index));
 884         /* set DMA start and interrupt mask */
 885         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 886                       SD_CTL_DMA_START | SD_INT_MASK);
 887 }
 888
 889 /* stop DMA */
 890 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 891 {
 892         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 893                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 894         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 895 }
 896
 897 /* stop a stream */
 898 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 899 {
 900         azx_stream_clear(chip, azx_dev);
 901         /* disable SIE */
 902         azx_writeb(chip, INTCTL,
 903                    azx_readb(chip, INTCTL) & ~(1 << azx_dev->index));
 904 }
 905
 906
 907 /*
 908  * reset and start the controller registers
 909  */
 910 static void azx_init_chip(struct azx *chip)
 911 {
 912         if (chip->initialized)
 913                 return;
 914
 915         /* reset controller */
 916         azx_reset(chip);
 917
 918         /* initialize interrupts */
 919         azx_int_clear(chip);
 920         azx_int_enable(chip);
 921
 922         /* initialize the codec command I/O */
 923         azx_init_cmd_io(chip);
 924
 925         /* program the position buffer */
 926         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
 927         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
 928
 929         chip->initialized = 1;
 930 }
 931
 932 /*
 933  * initialize the PCI registers
 934  */
 935 /* update bits in a PCI register byte */
 936 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
 937                             unsigned char mask, unsigned char val)
 938 {
 939         unsigned char data;
 940
 941         pci_read_config_byte(pci, reg, &data);
 942         data &= ~mask;
 943         data |= (val & mask);
 944         pci_write_config_byte(pci, reg, data);
 945 }
 946
 947 static void azx_init_pci(struct azx *chip)
 948 {
 949         unsigned short snoop;
 950
 951         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
 952          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
 953          * Ensuring these bits are 0 clears playback static on some HD Audio
 954          * codecs
 955          */
 956         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
 957
 958         switch (chip->driver_type) {
 959         case AZX_DRIVER_ATI:
 960                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
 961                 update_pci_byte(chip->pci,
 962                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
 963                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
 964                 break;
 965         case AZX_DRIVER_NVIDIA:
 966                 /* For NVIDIA HDA, enable snoop */
 967                 update_pci_byte(chip->pci,
 968                                 NVIDIA_HDA_TRANSREG_ADDR,
 969                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
 970                 update_pci_byte(chip->pci,
 971                                 NVIDIA_HDA_ISTRM_COH,
 972                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 973                 update_pci_byte(chip->pci,
 974                                 NVIDIA_HDA_OSTRM_COH,
 975                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
 976                 break;
 977         case AZX_DRIVER_SCH:
 978                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
 979                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
 980                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
 981                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
 982                         pci_read_config_word(chip->pci,
 983                                 INTEL_SCH_HDA_DEVC, &snoop);
 984                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
 985                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
 986                                 ? "Failed" : "OK");
 987                 }
 988                 break;
 989
 990         }
 991 }
 992
 993
 994 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
 995
 996 /*
 997  * interrupt handler
 998  */
 999 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1000 {
1001         struct azx *chip = dev_id;
1002         struct azx_dev *azx_dev;
1003         u32 status;
1004         int i, ok;
1005
1006         spin_lock(&chip->reg_lock);
1007
1008         status = azx_readl(chip, INTSTS);
1009         if (status == 0) {
1010                 spin_unlock(&chip->reg_lock);
1011                 return IRQ_NONE;
1012         }
1013
1014         for (i = 0; i < chip->num_streams; i++) {
1015                 azx_dev = &chip->azx_dev[i];
1016                 if (status & azx_dev->sd_int_sta_mask) {
1017                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1018                         if (!azx_dev->substream || !azx_dev->running)
1019                                 continue;
1020                         /* check whether this IRQ is really acceptable */
1021                         ok = azx_position_ok(chip, azx_dev);
1022                         if (ok == 1) {
1023                                 azx_dev->irq_pending = 0;
1024                                 spin_unlock(&chip->reg_lock);
1025                                 snd_pcm_period_elapsed(azx_dev->substream);
1026                                 spin_lock(&chip->reg_lock);
1027                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1028                                 /* bogus IRQ, process it later */
1029                                 azx_dev->irq_pending = 1;
1030                                 queue_work(chip->bus->workq,
1031                                            &chip->irq_pending_work);
1032                         }
1033                 }
1034         }
1035
1036         /* clear rirb int */
1037         status = azx_readb(chip, RIRBSTS);
1038         if (status & RIRB_INT_MASK) {
1039                 if (status & RIRB_INT_RESPONSE)
1040                         azx_update_rirb(chip);
1041                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1042         }
1043
1044 #if 0
1045         /* clear state status int */
1046         if (azx_readb(chip, STATESTS) & 0x04)
1047                 azx_writeb(chip, STATESTS, 0x04);
1048 #endif
1049         spin_unlock(&chip->reg_lock);
1050
1051         return IRQ_HANDLED;
1052 }
1053
1054
1055 /*
1056  * set up a BDL entry
1057  */
1058 static int setup_bdle(struct snd_pcm_substream *substream,
1059                       struct azx_dev *azx_dev, u32 **bdlp,
1060                       int ofs, int size, int with_ioc)
1061 {
1062         u32 *bdl = *bdlp;
1063
1064         while (size > 0) {
1065                 dma_addr_t addr;
1066                 int chunk;
1067
1068                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1069                         return -EINVAL;
1070
1071                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1072                 /* program the address field of the BDL entry */
1073                 bdl[0] = cpu_to_le32((u32)addr);
1074                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1075                 /* program the size field of the BDL entry */
1076                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1077                 bdl[2] = cpu_to_le32(chunk);
1078                 /* program the IOC to enable interrupt
1079                  * only when the whole fragment is processed
1080                  */
1081                 size -= chunk;
1082                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1083                 bdl += 4;
1084                 azx_dev->frags++;
1085                 ofs += chunk;
1086         }
1087         *bdlp = bdl;
1088         return ofs;
1089 }
1090
1091 /*
1092  * set up BDL entries
1093  */
1094 static int azx_setup_periods(struct azx *chip,
1095                              struct snd_pcm_substream *substream,
1096                              struct azx_dev *azx_dev)
1097 {
1098         u32 *bdl;
1099         int i, ofs, periods, period_bytes;
1100         int pos_adj;
1101
1102         /* reset BDL address */
1103         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1104         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1105
1106         period_bytes = azx_dev->period_bytes;
1107         periods = azx_dev->bufsize / period_bytes;
1108
1109         /* program the initial BDL entries */
1110         bdl = (u32 *)azx_dev->bdl.area;
1111         ofs = 0;
1112         azx_dev->frags = 0;
1113         pos_adj = bdl_pos_adj[chip->dev_index];
1114         if (pos_adj > 0) {
1115                 struct snd_pcm_runtime *runtime = substream->runtime;
1116                 int pos_align = pos_adj;
1117                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1118                 if (!pos_adj)
1119                         pos_adj = pos_align;
1120                 else
1121                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1122                                 pos_align;
1123                 pos_adj = frames_to_bytes(runtime, pos_adj);
1124                 if (pos_adj >= period_bytes) {
1125                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1126                                    bdl_pos_adj[chip->dev_index]);
1127                         pos_adj = 0;
1128                 } else {
1129                         ofs = setup_bdle(substream, azx_dev,
1130                                          &bdl, ofs, pos_adj, 1);
1131                         if (ofs < 0)
1132                                 goto error;
1133                 }
1134         } else
1135                 pos_adj = 0;
1136         for (i = 0; i < periods; i++) {
1137                 if (i == periods - 1 && pos_adj)
1138                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1139                                          period_bytes - pos_adj, 0);
1140                 else
1141                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1142                                          period_bytes, 1);
1143                 if (ofs < 0)
1144                         goto error;
1145         }
1146         return 0;
1147
1148  error:
1149         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1150                    azx_dev->bufsize, period_bytes);
1151         return -EINVAL;
1152 }
1153
1154 /* reset stream */
1155 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1156 {
1157         unsigned char val;
1158         int timeout;
1159
1160         azx_stream_clear(chip, azx_dev);
1161
1162         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1163                       SD_CTL_STREAM_RESET);
1164         udelay(3);
1165         timeout = 300;
1166         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1167                --timeout)
1168                 ;
1169         val &= ~SD_CTL_STREAM_RESET;
1170         azx_sd_writeb(azx_dev, SD_CTL, val);
1171         udelay(3);
1172
1173         timeout = 300;
1174         /* waiting for hardware to report that the stream is out of reset */
1175         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1176                --timeout)
1177                 ;
1178
1179         /* reset first position - may not be synced with hw at this time */
1180         *azx_dev->posbuf = 0;
1181 }
1182
1183 /*
1184  * set up the SD for streaming
1185  */
1186 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1187 {
1188         /* make sure the run bit is zero for SD */
1189         azx_stream_clear(chip, azx_dev);
1190         /* program the stream_tag */
1191         azx_sd_writel(azx_dev, SD_CTL,
1192                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1193                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1194
1195         /* program the length of samples in cyclic buffer */
1196         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1197
1198         /* program the stream format */
1199         /* this value needs to be the same as the one programmed */
1200         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1201
1202         /* program the stream LVI (last valid index) of the BDL */
1203         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1204
1205         /* program the BDL address */
1206         /* lower BDL address */
1207         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1208         /* upper BDL address */
1209         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1210
1211         /* enable the position buffer */
1212         if (chip->position_fix == POS_FIX_POSBUF ||
1213             chip->position_fix == POS_FIX_AUTO ||
1214             chip->via_dmapos_patch) {
1215                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1216                         azx_writel(chip, DPLBASE,
1217                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1218         }
1219
1220         /* set the interrupt enable bits in the descriptor control register */
1221         azx_sd_writel(azx_dev, SD_CTL,
1222                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1223
1224         return 0;
1225 }
1226
1227 /*
1228  * Probe the given codec address
1229  */
1230 static int probe_codec(struct azx *chip, int addr)
1231 {
1232         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1233                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1234         unsigned int res;
1235
1236         chip->probing = 1;
1237         azx_send_cmd(chip->bus, cmd);
1238         res = azx_get_response(chip->bus);
1239         chip->probing = 0;
1240         if (res == -1)
1241                 return -EIO;
1242         snd_printdd(SFX "codec #%d probed OK\n", addr);
1243         return 0;
1244 }
1245
1246 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1247                                  struct hda_pcm *cpcm);
1248 static void azx_stop_chip(struct azx *chip);
1249
1250 /*
1251  * Codec initialization
1252  */
1253
1254 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1255 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1256         [AZX_DRIVER_TERA] = 1,
1257 };
1258
1259 static int __devinit azx_codec_create(struct azx *chip, const char *model,
1260                                       int no_init)
1261 {
1262         struct hda_bus_template bus_temp;
1263         int c, codecs, err;
1264         int max_slots;
1265
1266         memset(&bus_temp, 0, sizeof(bus_temp));
1267         bus_temp.private_data = chip;
1268         bus_temp.modelname = model;
1269         bus_temp.pci = chip->pci;
1270         bus_temp.ops.command = azx_send_cmd;
1271         bus_temp.ops.get_response = azx_get_response;
1272         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1273 #ifdef CONFIG_SND_HDA_POWER_SAVE
1274         bus_temp.power_save = &power_save;
1275         bus_temp.ops.pm_notify = azx_power_notify;
1276 #endif
1277
1278         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1279         if (err < 0)
1280                 return err;
1281
1282         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1283                 chip->bus->needs_damn_long_delay = 1;
1284
1285         codecs = 0;
1286         max_slots = azx_max_codecs[chip->driver_type];
1287         if (!max_slots)
1288                 max_slots = AZX_MAX_CODECS;
1289
1290         /* First try to probe all given codec slots */
1291         for (c = 0; c < max_slots; c++) {
1292                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1293                         if (probe_codec(chip, c) < 0) {
1294                                 /* Some BIOSen give you wrong codec addresses
1295                                  * that don't exist
1296                                  */
1297                                 snd_printk(KERN_WARNING SFX
1298                                            "Codec #%d probe error; "
1299                                            "disabling it...\n", c);
1300                                 chip->codec_mask &= ~(1 << c);
1301                                 /* More badly, accessing to a non-existing
1302                                  * codec often screws up the controller chip,
1303                                  * and distrubs the further communications.
1304                                  * Thus if an error occurs during probing,
1305                                  * better to reset the controller chip to
1306                                  * get back to the sanity state.
1307                                  */
1308                                 azx_stop_chip(chip);
1309                                 azx_init_chip(chip);
1310                         }
1311                 }
1312         }
1313
1314         /* Then create codec instances */
1315         for (c = 0; c < max_slots; c++) {
1316                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1317                         struct hda_codec *codec;
1318                         err = snd_hda_codec_new(chip->bus, c, !no_init, &codec);
1319                         if (err < 0)
1320                                 continue;
1321                         codecs++;
1322                 }
1323         }
1324         if (!codecs) {
1325                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1326                 return -ENXIO;
1327         }
1328
1329         return 0;
1330 }
1331
1332
1333 /*
1334  * PCM support
1335  */
1336
1337 /* assign a stream for the PCM */
1338 static inline struct azx_dev *azx_assign_device(struct azx *chip, int stream)
1339 {
1340         int dev, i, nums;
1341         if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1342                 dev = chip->playback_index_offset;
1343                 nums = chip->playback_streams;
1344         } else {
1345                 dev = chip->capture_index_offset;
1346                 nums = chip->capture_streams;
1347         }
1348         for (i = 0; i < nums; i++, dev++)
1349                 if (!chip->azx_dev[dev].opened) {
1350                         chip->azx_dev[dev].opened = 1;
1351                         return &chip->azx_dev[dev];
1352                 }
1353         return NULL;
1354 }
1355
1356 /* release the assigned stream */
1357 static inline void azx_release_device(struct azx_dev *azx_dev)
1358 {
1359         azx_dev->opened = 0;
1360 }
1361
1362 static struct snd_pcm_hardware azx_pcm_hw = {
1363         .info =                 (SNDRV_PCM_INFO_MMAP |
1364                                  SNDRV_PCM_INFO_INTERLEAVED |
1365                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1366                                  SNDRV_PCM_INFO_MMAP_VALID |
1367                                  /* No full-resume yet implemented */
1368                                  /* SNDRV_PCM_INFO_RESUME |*/
1369                                  SNDRV_PCM_INFO_PAUSE |
1370                                  SNDRV_PCM_INFO_SYNC_START),
1371         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1372         .rates =                SNDRV_PCM_RATE_48000,
1373         .rate_min =             48000,
1374         .rate_max =             48000,
1375         .channels_min =         2,
1376         .channels_max =         2,
1377         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1378         .period_bytes_min =     128,
1379         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1380         .periods_min =          2,
1381         .periods_max =          AZX_MAX_FRAG,
1382         .fifo_size =            0,
1383 };
1384
1385 struct azx_pcm {
1386         struct azx *chip;
1387         struct hda_codec *codec;
1388         struct hda_pcm_stream *hinfo[2];
1389 };
1390
1391 static int azx_pcm_open(struct snd_pcm_substream *substream)
1392 {
1393         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1394         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1395         struct azx *chip = apcm->chip;
1396         struct azx_dev *azx_dev;
1397         struct snd_pcm_runtime *runtime = substream->runtime;
1398         unsigned long flags;
1399         int err;
1400
1401         mutex_lock(&chip->open_mutex);
1402         azx_dev = azx_assign_device(chip, substream->stream);
1403         if (azx_dev == NULL) {
1404                 mutex_unlock(&chip->open_mutex);
1405                 return -EBUSY;
1406         }
1407         runtime->hw = azx_pcm_hw;
1408         runtime->hw.channels_min = hinfo->channels_min;
1409         runtime->hw.channels_max = hinfo->channels_max;
1410         runtime->hw.formats = hinfo->formats;
1411         runtime->hw.rates = hinfo->rates;
1412         snd_pcm_limit_hw_rates(runtime);
1413         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1414         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1415                                    128);
1416         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1417                                    128);
1418         snd_hda_power_up(apcm->codec);
1419         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1420         if (err < 0) {
1421                 azx_release_device(azx_dev);
1422                 snd_hda_power_down(apcm->codec);
1423                 mutex_unlock(&chip->open_mutex);
1424                 return err;
1425         }
1426         spin_lock_irqsave(&chip->reg_lock, flags);
1427         azx_dev->substream = substream;
1428         azx_dev->running = 0;
1429         spin_unlock_irqrestore(&chip->reg_lock, flags);
1430
1431         runtime->private_data = azx_dev;
1432         snd_pcm_set_sync(substream);
1433         mutex_unlock(&chip->open_mutex);
1434
1435         return 0;
1436 }
1437
1438 static int azx_pcm_close(struct snd_pcm_substream *substream)
1439 {
1440         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1441         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1442         struct azx *chip = apcm->chip;
1443         struct azx_dev *azx_dev = get_azx_dev(substream);
1444         unsigned long flags;
1445
1446         mutex_lock(&chip->open_mutex);
1447         spin_lock_irqsave(&chip->reg_lock, flags);
1448         azx_dev->substream = NULL;
1449         azx_dev->running = 0;
1450         spin_unlock_irqrestore(&chip->reg_lock, flags);
1451         azx_release_device(azx_dev);
1452         hinfo->ops.close(hinfo, apcm->codec, substream);
1453         snd_hda_power_down(apcm->codec);
1454         mutex_unlock(&chip->open_mutex);
1455         return 0;
1456 }
1457
1458 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1459                              struct snd_pcm_hw_params *hw_params)
1460 {
1461         struct azx_dev *azx_dev = get_azx_dev(substream);
1462
1463         azx_dev->bufsize = 0;
1464         azx_dev->period_bytes = 0;
1465         azx_dev->format_val = 0;
1466         return snd_pcm_lib_malloc_pages(substream,
1467                                         params_buffer_bytes(hw_params));
1468 }
1469
1470 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1471 {
1472         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1473         struct azx_dev *azx_dev = get_azx_dev(substream);
1474         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1475
1476         /* reset BDL address */
1477         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1478         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1479         azx_sd_writel(azx_dev, SD_CTL, 0);
1480         azx_dev->bufsize = 0;
1481         azx_dev->period_bytes = 0;
1482         azx_dev->format_val = 0;
1483
1484         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1485
1486         return snd_pcm_lib_free_pages(substream);
1487 }
1488
1489 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1490 {
1491         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1492         struct azx *chip = apcm->chip;
1493         struct azx_dev *azx_dev = get_azx_dev(substream);
1494         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1495         struct snd_pcm_runtime *runtime = substream->runtime;
1496         unsigned int bufsize, period_bytes, format_val;
1497         int err;
1498
1499         azx_stream_reset(chip, azx_dev);
1500         format_val = snd_hda_calc_stream_format(runtime->rate,
1501                                                 runtime->channels,
1502                                                 runtime->format,
1503                                                 hinfo->maxbps);
1504         if (!format_val) {
1505                 snd_printk(KERN_ERR SFX
1506                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1507                            runtime->rate, runtime->channels, runtime->format);
1508                 return -EINVAL;
1509         }
1510
1511         bufsize = snd_pcm_lib_buffer_bytes(substream);
1512         period_bytes = snd_pcm_lib_period_bytes(substream);
1513
1514         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1515                     bufsize, format_val);
1516
1517         if (bufsize != azx_dev->bufsize ||
1518             period_bytes != azx_dev->period_bytes ||
1519             format_val != azx_dev->format_val) {
1520                 azx_dev->bufsize = bufsize;
1521                 azx_dev->period_bytes = period_bytes;
1522                 azx_dev->format_val = format_val;
1523                 err = azx_setup_periods(chip, substream, azx_dev);
1524                 if (err < 0)
1525                         return err;
1526         }
1527
1528         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1529                                                 (runtime->rate * 2);
1530         azx_setup_controller(chip, azx_dev);
1531         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1532                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1533         else
1534                 azx_dev->fifo_size = 0;
1535
1536         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1537                                   azx_dev->format_val, substream);
1538 }
1539
1540 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1541 {
1542         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1543         struct azx *chip = apcm->chip;
1544         struct azx_dev *azx_dev;
1545         struct snd_pcm_substream *s;
1546         int rstart = 0, start, nsync = 0, sbits = 0;
1547         int nwait, timeout;
1548
1549         switch (cmd) {
1550         case SNDRV_PCM_TRIGGER_START:
1551                 rstart = 1;
1552         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1553         case SNDRV_PCM_TRIGGER_RESUME:
1554                 start = 1;
1555                 break;
1556         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1557         case SNDRV_PCM_TRIGGER_SUSPEND:
1558         case SNDRV_PCM_TRIGGER_STOP:
1559                 start = 0;
1560                 break;
1561         default:
1562                 return -EINVAL;
1563         }
1564
1565         snd_pcm_group_for_each_entry(s, substream) {
1566                 if (s->pcm->card != substream->pcm->card)
1567                         continue;
1568                 azx_dev = get_azx_dev(s);
1569                 sbits |= 1 << azx_dev->index;
1570                 nsync++;
1571                 snd_pcm_trigger_done(s, substream);
1572         }
1573
1574         spin_lock(&chip->reg_lock);
1575         if (nsync > 1) {
1576                 /* first, set SYNC bits of corresponding streams */
1577                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1578         }
1579         snd_pcm_group_for_each_entry(s, substream) {
1580                 if (s->pcm->card != substream->pcm->card)
1581                         continue;
1582                 azx_dev = get_azx_dev(s);
1583                 if (rstart) {
1584                         azx_dev->start_flag = 1;
1585                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1586                 }
1587                 if (start)
1588                         azx_stream_start(chip, azx_dev);
1589                 else
1590                         azx_stream_stop(chip, azx_dev);
1591                 azx_dev->running = start;
1592         }
1593         spin_unlock(&chip->reg_lock);
1594         if (start) {
1595                 if (nsync == 1)
1596                         return 0;
1597                 /* wait until all FIFOs get ready */
1598                 for (timeout = 5000; timeout; timeout--) {
1599                         nwait = 0;
1600                         snd_pcm_group_for_each_entry(s, substream) {
1601                                 if (s->pcm->card != substream->pcm->card)
1602                                         continue;
1603                                 azx_dev = get_azx_dev(s);
1604                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1605                                       SD_STS_FIFO_READY))
1606                                         nwait++;
1607                         }
1608                         if (!nwait)
1609                                 break;
1610                         cpu_relax();
1611                 }
1612         } else {
1613                 /* wait until all RUN bits are cleared */
1614                 for (timeout = 5000; timeout; timeout--) {
1615                         nwait = 0;
1616                         snd_pcm_group_for_each_entry(s, substream) {
1617                                 if (s->pcm->card != substream->pcm->card)
1618                                         continue;
1619                                 azx_dev = get_azx_dev(s);
1620                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1621                                     SD_CTL_DMA_START)
1622                                         nwait++;
1623                         }
1624                         if (!nwait)
1625                                 break;
1626                         cpu_relax();
1627                 }
1628         }
1629         if (nsync > 1) {
1630                 spin_lock(&chip->reg_lock);
1631                 /* reset SYNC bits */
1632                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1633                 spin_unlock(&chip->reg_lock);
1634         }
1635         return 0;
1636 }
1637
1638 /* get the current DMA position with correction on VIA chips */
1639 static unsigned int azx_via_get_position(struct azx *chip,
1640                                          struct azx_dev *azx_dev)
1641 {
1642         unsigned int link_pos, mini_pos, bound_pos;
1643         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1644         unsigned int fifo_size;
1645
1646         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1647         if (azx_dev->index >= 4) {
1648                 /* Playback, no problem using link position */
1649                 return link_pos;
1650         }
1651
1652         /* Capture */
1653         /* For new chipset,
1654          * use mod to get the DMA position just like old chipset
1655          */
1656         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1657         mod_dma_pos %= azx_dev->period_bytes;
1658
1659         /* azx_dev->fifo_size can't get FIFO size of in stream.
1660          * Get from base address + offset.
1661          */
1662         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1663
1664         if (azx_dev->insufficient) {
1665                 /* Link position never gather than FIFO size */
1666                 if (link_pos <= fifo_size)
1667                         return 0;
1668
1669                 azx_dev->insufficient = 0;
1670         }
1671
1672         if (link_pos <= fifo_size)
1673                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1674         else
1675                 mini_pos = link_pos - fifo_size;
1676
1677         /* Find nearest previous boudary */
1678         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1679         mod_link_pos = link_pos % azx_dev->period_bytes;
1680         if (mod_link_pos >= fifo_size)
1681                 bound_pos = link_pos - mod_link_pos;
1682         else if (mod_dma_pos >= mod_mini_pos)
1683                 bound_pos = mini_pos - mod_mini_pos;
1684         else {
1685                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1686                 if (bound_pos >= azx_dev->bufsize)
1687                         bound_pos = 0;
1688         }
1689
1690         /* Calculate real DMA position we want */
1691         return bound_pos + mod_dma_pos;
1692 }
1693
1694 static unsigned int azx_get_position(struct azx *chip,
1695                                      struct azx_dev *azx_dev)
1696 {
1697         unsigned int pos;
1698
1699         if (chip->via_dmapos_patch)
1700                 pos = azx_via_get_position(chip, azx_dev);
1701         else if (chip->position_fix == POS_FIX_POSBUF ||
1702                  chip->position_fix == POS_FIX_AUTO) {
1703                 /* use the position buffer */
1704                 pos = le32_to_cpu(*azx_dev->posbuf);
1705         } else {
1706                 /* read LPIB */
1707                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1708         }
1709         if (pos >= azx_dev->bufsize)
1710                 pos = 0;
1711         return pos;
1712 }
1713
1714 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1715 {
1716         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1717         struct azx *chip = apcm->chip;
1718         struct azx_dev *azx_dev = get_azx_dev(substream);
1719         return bytes_to_frames(substream->runtime,
1720                                azx_get_position(chip, azx_dev));
1721 }
1722
1723 /*
1724  * Check whether the current DMA position is acceptable for updating
1725  * periods.  Returns non-zero if it's OK.
1726  *
1727  * Many HD-audio controllers appear pretty inaccurate about
1728  * the update-IRQ timing.  The IRQ is issued before actually the
1729  * data is processed.  So, we need to process it afterwords in a
1730  * workqueue.
1731  */
1732 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1733 {
1734         unsigned int pos;
1735
1736         if (azx_dev->start_flag &&
1737             time_before_eq(jiffies, azx_dev->start_jiffies))
1738                 return -1;      /* bogus (too early) interrupt */
1739         azx_dev->start_flag = 0;
1740
1741         pos = azx_get_position(chip, azx_dev);
1742         if (chip->position_fix == POS_FIX_AUTO) {
1743                 if (!pos) {
1744                         printk(KERN_WARNING
1745                                "hda-intel: Invalid position buffer, "
1746                                "using LPIB read method instead.\n");
1747                         chip->position_fix = POS_FIX_LPIB;
1748                         pos = azx_get_position(chip, azx_dev);
1749                 } else
1750                         chip->position_fix = POS_FIX_POSBUF;
1751         }
1752
1753         if (!bdl_pos_adj[chip->dev_index])
1754                 return 1; /* no delayed ack */
1755         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1756                 return 0; /* NG - it's below the period boundary */
1757         return 1; /* OK, it's fine */
1758 }
1759
1760 /*
1761  * The work for pending PCM period updates.
1762  */
1763 static void azx_irq_pending_work(struct work_struct *work)
1764 {
1765         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1766         int i, pending;
1767
1768         if (!chip->irq_pending_warned) {
1769                 printk(KERN_WARNING
1770                        "hda-intel: IRQ timing workaround is activated "
1771                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1772                        chip->card->number);
1773                 chip->irq_pending_warned = 1;
1774         }
1775
1776         for (;;) {
1777                 pending = 0;
1778                 spin_lock_irq(&chip->reg_lock);
1779                 for (i = 0; i < chip->num_streams; i++) {
1780                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1781                         if (!azx_dev->irq_pending ||
1782                             !azx_dev->substream ||
1783                             !azx_dev->running)
1784                                 continue;
1785                         if (azx_position_ok(chip, azx_dev)) {
1786                                 azx_dev->irq_pending = 0;
1787                                 spin_unlock(&chip->reg_lock);
1788                                 snd_pcm_period_elapsed(azx_dev->substream);
1789                                 spin_lock(&chip->reg_lock);
1790                         } else
1791                                 pending++;
1792                 }
1793                 spin_unlock_irq(&chip->reg_lock);
1794                 if (!pending)
1795                         return;
1796                 cond_resched();
1797         }
1798 }
1799
1800 /* clear irq_pending flags and assure no on-going workq */
1801 static void azx_clear_irq_pending(struct azx *chip)
1802 {
1803         int i;
1804
1805         spin_lock_irq(&chip->reg_lock);
1806         for (i = 0; i < chip->num_streams; i++)
1807                 chip->azx_dev[i].irq_pending = 0;
1808         spin_unlock_irq(&chip->reg_lock);
1809 }
1810
1811 static struct snd_pcm_ops azx_pcm_ops = {
1812         .open = azx_pcm_open,
1813         .close = azx_pcm_close,
1814         .ioctl = snd_pcm_lib_ioctl,
1815         .hw_params = azx_pcm_hw_params,
1816         .hw_free = azx_pcm_hw_free,
1817         .prepare = azx_pcm_prepare,
1818         .trigger = azx_pcm_trigger,
1819         .pointer = azx_pcm_pointer,
1820         .page = snd_pcm_sgbuf_ops_page,
1821 };
1822
1823 static void azx_pcm_free(struct snd_pcm *pcm)
1824 {
1825         struct azx_pcm *apcm = pcm->private_data;
1826         if (apcm) {
1827                 apcm->chip->pcm[pcm->device] = NULL;
1828                 kfree(apcm);
1829         }
1830 }
1831
1832 static int
1833 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1834                       struct hda_pcm *cpcm)
1835 {
1836         struct azx *chip = bus->private_data;
1837         struct snd_pcm *pcm;
1838         struct azx_pcm *apcm;
1839         int pcm_dev = cpcm->device;
1840         int s, err;
1841
1842         if (pcm_dev >= AZX_MAX_PCMS) {
1843                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1844                            pcm_dev);
1845                 return -EINVAL;
1846         }
1847         if (chip->pcm[pcm_dev]) {
1848                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1849                 return -EBUSY;
1850         }
1851         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
1852                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
1853                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
1854                           &pcm);
1855         if (err < 0)
1856                 return err;
1857         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
1858         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
1859         if (apcm == NULL)
1860                 return -ENOMEM;
1861         apcm->chip = chip;
1862         apcm->codec = codec;
1863         pcm->private_data = apcm;
1864         pcm->private_free = azx_pcm_free;
1865         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
1866                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
1867         chip->pcm[pcm_dev] = pcm;
1868         cpcm->pcm = pcm;
1869         for (s = 0; s < 2; s++) {
1870                 apcm->hinfo[s] = &cpcm->stream[s];
1871                 if (cpcm->stream[s].substreams)
1872                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
1873         }
1874         /* buffer pre-allocation */
1875         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
1876                                               snd_dma_pci_data(chip->pci),
1877                                               1024 * 64, 32 * 1024 * 1024);
1878         return 0;
1879 }
1880
1881 /*
1882  * mixer creation - all stuff is implemented in hda module
1883  */
1884 static int __devinit azx_mixer_create(struct azx *chip)
1885 {
1886         return snd_hda_build_controls(chip->bus);
1887 }
1888
1889
1890 /*
1891  * initialize SD streams
1892  */
1893 static int __devinit azx_init_stream(struct azx *chip)
1894 {
1895         int i;
1896
1897         /* initialize each stream (aka device)
1898          * assign the starting bdl address to each stream (device)
1899          * and initialize
1900          */
1901         for (i = 0; i < chip->num_streams; i++) {
1902                 struct azx_dev *azx_dev = &chip->azx_dev[i];
1903                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
1904                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
1905                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
1906                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
1907                 azx_dev->sd_int_sta_mask = 1 << i;
1908                 /* stream tag: must be non-zero and unique */
1909                 azx_dev->index = i;
1910                 azx_dev->stream_tag = i + 1;
1911         }
1912
1913         return 0;
1914 }
1915
1916 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
1917 {
1918         if (request_irq(chip->pci->irq, azx_interrupt,
1919                         chip->msi ? 0 : IRQF_SHARED,
1920                         "HDA Intel", chip)) {
1921                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
1922                        "disabling device\n", chip->pci->irq);
1923                 if (do_disconnect)
1924                         snd_card_disconnect(chip->card);
1925                 return -1;
1926         }
1927         chip->irq = chip->pci->irq;
1928         pci_intx(chip->pci, !chip->msi);
1929         return 0;
1930 }
1931
1932
1933 static void azx_stop_chip(struct azx *chip)
1934 {
1935         if (!chip->initialized)
1936                 return;
1937
1938         /* disable interrupts */
1939         azx_int_disable(chip);
1940         azx_int_clear(chip);
1941
1942         /* disable CORB/RIRB */
1943         azx_free_cmd_io(chip);
1944
1945         /* disable position buffer */
1946         azx_writel(chip, DPLBASE, 0);
1947         azx_writel(chip, DPUBASE, 0);
1948
1949         chip->initialized = 0;
1950 }
1951
1952 #ifdef CONFIG_SND_HDA_POWER_SAVE
1953 /* power-up/down the controller */
1954 static void azx_power_notify(struct hda_bus *bus)
1955 {
1956         struct azx *chip = bus->private_data;
1957         struct hda_codec *c;
1958         int power_on = 0;
1959
1960         list_for_each_entry(c, &bus->codec_list, list) {
1961                 if (c->power_on) {
1962                         power_on = 1;
1963                         break;
1964                 }
1965         }
1966         if (power_on)
1967                 azx_init_chip(chip);
1968         else if (chip->running && power_save_controller)
1969                 azx_stop_chip(chip);
1970 }
1971 #endif /* CONFIG_SND_HDA_POWER_SAVE */
1972
1973 #ifdef CONFIG_PM
1974 /*
1975  * power management
1976  */
1977
1978 static int snd_hda_codecs_inuse(struct hda_bus *bus)
1979 {
1980         struct hda_codec *codec;
1981
1982         list_for_each_entry(codec, &bus->codec_list, list) {
1983                 if (snd_hda_codec_needs_resume(codec))
1984                         return 1;
1985         }
1986         return 0;
1987 }
1988
1989 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
1990 {
1991         struct snd_card *card = pci_get_drvdata(pci);
1992         struct azx *chip = card->private_data;
1993         int i;
1994
1995         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
1996         azx_clear_irq_pending(chip);
1997         for (i = 0; i < AZX_MAX_PCMS; i++)
1998                 snd_pcm_suspend_all(chip->pcm[i]);
1999         if (chip->initialized)
2000                 snd_hda_suspend(chip->bus, state);
2001         azx_stop_chip(chip);
2002         if (chip->irq >= 0) {
2003                 free_irq(chip->irq, chip);
2004                 chip->irq = -1;
2005         }
2006         if (chip->msi)
2007                 pci_disable_msi(chip->pci);
2008         pci_disable_device(pci);
2009         pci_save_state(pci);
2010         pci_set_power_state(pci, pci_choose_state(pci, state));
2011         return 0;
2012 }
2013
2014 static int azx_resume(struct pci_dev *pci)
2015 {
2016         struct snd_card *card = pci_get_drvdata(pci);
2017         struct azx *chip = card->private_data;
2018
2019         pci_set_power_state(pci, PCI_D0);
2020         pci_restore_state(pci);
2021         if (pci_enable_device(pci) < 0) {
2022                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2023                        "disabling device\n");
2024                 snd_card_disconnect(card);
2025                 return -EIO;
2026         }
2027         pci_set_master(pci);
2028         if (chip->msi)
2029                 if (pci_enable_msi(pci) < 0)
2030                         chip->msi = 0;
2031         if (azx_acquire_irq(chip, 1) < 0)
2032                 return -EIO;
2033         azx_init_pci(chip);
2034
2035         if (snd_hda_codecs_inuse(chip->bus))
2036                 azx_init_chip(chip);
2037
2038         snd_hda_resume(chip->bus);
2039         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2040         return 0;
2041 }
2042 #endif /* CONFIG_PM */
2043
2044
2045 /*
2046  * reboot notifier for hang-up problem at power-down
2047  */
2048 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2049 {
2050         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2051         azx_stop_chip(chip);
2052         return NOTIFY_OK;
2053 }
2054
2055 static void azx_notifier_register(struct azx *chip)
2056 {
2057         chip->reboot_notifier.notifier_call = azx_halt;
2058         register_reboot_notifier(&chip->reboot_notifier);
2059 }
2060
2061 static void azx_notifier_unregister(struct azx *chip)
2062 {
2063         if (chip->reboot_notifier.notifier_call)
2064                 unregister_reboot_notifier(&chip->reboot_notifier);
2065 }
2066
2067 /*
2068  * destructor
2069  */
2070 static int azx_free(struct azx *chip)
2071 {
2072         int i;
2073
2074         azx_notifier_unregister(chip);
2075
2076         if (chip->initialized) {
2077                 azx_clear_irq_pending(chip);
2078                 for (i = 0; i < chip->num_streams; i++)
2079                         azx_stream_stop(chip, &chip->azx_dev[i]);
2080                 azx_stop_chip(chip);
2081         }
2082
2083         if (chip->irq >= 0)
2084                 free_irq(chip->irq, (void*)chip);
2085         if (chip->msi)
2086                 pci_disable_msi(chip->pci);
2087         if (chip->remap_addr)
2088                 iounmap(chip->remap_addr);
2089
2090         if (chip->azx_dev) {
2091                 for (i = 0; i < chip->num_streams; i++)
2092                         if (chip->azx_dev[i].bdl.area)
2093                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2094         }
2095         if (chip->rb.area)
2096                 snd_dma_free_pages(&chip->rb);
2097         if (chip->posbuf.area)
2098                 snd_dma_free_pages(&chip->posbuf);
2099         pci_release_regions(chip->pci);
2100         pci_disable_device(chip->pci);
2101         kfree(chip->azx_dev);
2102         kfree(chip);
2103
2104         return 0;
2105 }
2106
2107 static int azx_dev_free(struct snd_device *device)
2108 {
2109         return azx_free(device->device_data);
2110 }
2111
2112 /*
2113  * white/black-listing for position_fix
2114  */
2115 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2116         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2117         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2118         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2119         {}
2120 };
2121
2122 static int __devinit check_position_fix(struct azx *chip, int fix)
2123 {
2124         const struct snd_pci_quirk *q;
2125
2126         switch (fix) {
2127         case POS_FIX_LPIB:
2128         case POS_FIX_POSBUF:
2129                 return fix;
2130         }
2131
2132         /* Check VIA/ATI HD Audio Controller exist */
2133         switch (chip->driver_type) {
2134         case AZX_DRIVER_VIA:
2135         case AZX_DRIVER_ATI:
2136                 chip->via_dmapos_patch = 1;
2137                 /* Use link position directly, avoid any transfer problem. */
2138                 return POS_FIX_LPIB;
2139         }
2140         chip->via_dmapos_patch = 0;
2141
2142         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2143         if (q) {
2144                 printk(KERN_INFO
2145                        "hda_intel: position_fix set to %d "
2146                        "for device %04x:%04x\n",
2147                        q->value, q->subvendor, q->subdevice);
2148                 return q->value;
2149         }
2150         return POS_FIX_AUTO;
2151 }
2152
2153 /*
2154  * black-lists for probe_mask
2155  */
2156 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2157         /* Thinkpad often breaks the controller communication when accessing
2158          * to the non-working (or non-existing) modem codec slot.
2159          */
2160         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2161         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2162         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2163         /* broken BIOS */
2164         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2165         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2166         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2167         /* forced codec slots */
2168         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2169         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2170         {}
2171 };
2172
2173 #define AZX_FORCE_CODEC_MASK    0x100
2174
2175 static void __devinit check_probe_mask(struct azx *chip, int dev)
2176 {
2177         const struct snd_pci_quirk *q;
2178
2179         chip->codec_probe_mask = probe_mask[dev];
2180         if (chip->codec_probe_mask == -1) {
2181                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2182                 if (q) {
2183                         printk(KERN_INFO
2184                                "hda_intel: probe_mask set to 0x%x "
2185                                "for device %04x:%04x\n",
2186                                q->value, q->subvendor, q->subdevice);
2187                         chip->codec_probe_mask = q->value;
2188                 }
2189         }
2190
2191         /* check forced option */
2192         if (chip->codec_probe_mask != -1 &&
2193             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2194                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2195                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2196                        chip->codec_mask);
2197         }
2198 }
2199
2200
2201 /*
2202  * constructor
2203  */
2204 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2205                                 int dev, int driver_type,
2206                                 struct azx **rchip)
2207 {
2208         struct azx *chip;
2209         int i, err;
2210         unsigned short gcap;
2211         static struct snd_device_ops ops = {
2212                 .dev_free = azx_dev_free,
2213         };
2214
2215         *rchip = NULL;
2216
2217         err = pci_enable_device(pci);
2218         if (err < 0)
2219                 return err;
2220
2221         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2222         if (!chip) {
2223                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2224                 pci_disable_device(pci);
2225                 return -ENOMEM;
2226         }
2227
2228         spin_lock_init(&chip->reg_lock);
2229         mutex_init(&chip->open_mutex);
2230         chip->card = card;
2231         chip->pci = pci;
2232         chip->irq = -1;
2233         chip->driver_type = driver_type;
2234         chip->msi = enable_msi;
2235         chip->dev_index = dev;
2236         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2237
2238         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2239         check_probe_mask(chip, dev);
2240
2241         chip->single_cmd = single_cmd;
2242
2243         if (bdl_pos_adj[dev] < 0) {
2244                 switch (chip->driver_type) {
2245                 case AZX_DRIVER_ICH:
2246                         bdl_pos_adj[dev] = 1;
2247                         break;
2248                 default:
2249                         bdl_pos_adj[dev] = 32;
2250                         break;
2251                 }
2252         }
2253
2254 #if BITS_PER_LONG != 64
2255         /* Fix up base address on ULI M5461 */
2256         if (chip->driver_type == AZX_DRIVER_ULI) {
2257                 u16 tmp3;
2258                 pci_read_config_word(pci, 0x40, &tmp3);
2259                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2260                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2261         }
2262 #endif
2263
2264         err = pci_request_regions(pci, "ICH HD audio");
2265         if (err < 0) {
2266                 kfree(chip);
2267                 pci_disable_device(pci);
2268                 return err;
2269         }
2270
2271         chip->addr = pci_resource_start(pci, 0);
2272         chip->remap_addr = pci_ioremap_bar(pci, 0);
2273         if (chip->remap_addr == NULL) {
2274                 snd_printk(KERN_ERR SFX "ioremap error\n");
2275                 err = -ENXIO;
2276                 goto errout;
2277         }
2278
2279         if (chip->msi)
2280                 if (pci_enable_msi(pci) < 0)
2281                         chip->msi = 0;
2282
2283         if (azx_acquire_irq(chip, 0) < 0) {
2284                 err = -EBUSY;
2285                 goto errout;
2286         }
2287
2288         pci_set_master(pci);
2289         synchronize_irq(chip->irq);
2290
2291         gcap = azx_readw(chip, GCAP);
2292         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2293
2294         /* ATI chips seems buggy about 64bit DMA addresses */
2295         if (chip->driver_type == AZX_DRIVER_ATI)
2296                 gcap &= ~ICH6_GCAP_64OK;
2297
2298         /* allow 64bit DMA address if supported by H/W */
2299         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2300                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2301         else {
2302                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2303                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2304         }
2305
2306         /* read number of streams from GCAP register instead of using
2307          * hardcoded value
2308          */
2309         chip->capture_streams = (gcap >> 8) & 0x0f;
2310         chip->playback_streams = (gcap >> 12) & 0x0f;
2311         if (!chip->playback_streams && !chip->capture_streams) {
2312                 /* gcap didn't give any info, switching to old method */
2313
2314                 switch (chip->driver_type) {
2315                 case AZX_DRIVER_ULI:
2316                         chip->playback_streams = ULI_NUM_PLAYBACK;
2317                         chip->capture_streams = ULI_NUM_CAPTURE;
2318                         break;
2319                 case AZX_DRIVER_ATIHDMI:
2320                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2321                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2322                         break;
2323                 case AZX_DRIVER_GENERIC:
2324                 default:
2325                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2326                         chip->capture_streams = ICH6_NUM_CAPTURE;
2327                         break;
2328                 }
2329         }
2330         chip->capture_index_offset = 0;
2331         chip->playback_index_offset = chip->capture_streams;
2332         chip->num_streams = chip->playback_streams + chip->capture_streams;
2333         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2334                                 GFP_KERNEL);
2335         if (!chip->azx_dev) {
2336                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2337                 goto errout;
2338         }
2339
2340         for (i = 0; i < chip->num_streams; i++) {
2341                 /* allocate memory for the BDL for each stream */
2342                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2343                                           snd_dma_pci_data(chip->pci),
2344                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2345                 if (err < 0) {
2346                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2347                         goto errout;
2348                 }
2349         }
2350         /* allocate memory for the position buffer */
2351         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2352                                   snd_dma_pci_data(chip->pci),
2353                                   chip->num_streams * 8, &chip->posbuf);
2354         if (err < 0) {
2355                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2356                 goto errout;
2357         }
2358         /* allocate CORB/RIRB */
2359         err = azx_alloc_cmd_io(chip);
2360         if (err < 0)
2361                 goto errout;
2362
2363         /* initialize streams */
2364         azx_init_stream(chip);
2365
2366         /* initialize chip */
2367         azx_init_pci(chip);
2368         azx_init_chip(chip);
2369
2370         /* codec detection */
2371         if (!chip->codec_mask) {
2372                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2373                 err = -ENODEV;
2374                 goto errout;
2375         }
2376
2377         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2378         if (err <0) {
2379                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2380                 goto errout;
2381         }
2382
2383         strcpy(card->driver, "HDA-Intel");
2384         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2385                 sizeof(card->shortname));
2386         snprintf(card->longname, sizeof(card->longname),
2387                  "%s at 0x%lx irq %i",
2388                  card->shortname, chip->addr, chip->irq);
2389
2390         *rchip = chip;
2391         return 0;
2392
2393  errout:
2394         azx_free(chip);
2395         return err;
2396 }
2397
2398 static void power_down_all_codecs(struct azx *chip)
2399 {
2400 #ifdef CONFIG_SND_HDA_POWER_SAVE
2401         /* The codecs were powered up in snd_hda_codec_new().
2402          * Now all initialization done, so turn them down if possible
2403          */
2404         struct hda_codec *codec;
2405         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2406                 snd_hda_power_down(codec);
2407         }
2408 #endif
2409 }
2410
2411 static int __devinit azx_probe(struct pci_dev *pci,
2412                                const struct pci_device_id *pci_id)
2413 {
2414         static int dev;
2415         struct snd_card *card;
2416         struct azx *chip;
2417         int err;
2418
2419         if (dev >= SNDRV_CARDS)
2420                 return -ENODEV;
2421         if (!enable[dev]) {
2422                 dev++;
2423                 return -ENOENT;
2424         }
2425
2426         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2427         if (err < 0) {
2428                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2429                 return err;
2430         }
2431
2432         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2433         if (err < 0)
2434                 goto out_free;
2435         card->private_data = chip;
2436
2437         /* create codec instances */
2438         err = azx_codec_create(chip, model[dev], probe_only[dev]);
2439         if (err < 0)
2440                 goto out_free;
2441
2442         /* create PCM streams */
2443         err = snd_hda_build_pcms(chip->bus);
2444         if (err < 0)
2445                 goto out_free;
2446
2447         /* create mixer controls */
2448         err = azx_mixer_create(chip);
2449         if (err < 0)
2450                 goto out_free;
2451
2452         snd_card_set_dev(card, &pci->dev);
2453
2454         err = snd_card_register(card);
2455         if (err < 0)
2456                 goto out_free;
2457
2458         pci_set_drvdata(pci, card);
2459         chip->running = 1;
2460         power_down_all_codecs(chip);
2461         azx_notifier_register(chip);
2462
2463         dev++;
2464         return err;
2465 out_free:
2466         snd_card_free(card);
2467         return err;
2468 }
2469
2470 static void __devexit azx_remove(struct pci_dev *pci)
2471 {
2472         snd_card_free(pci_get_drvdata(pci));
2473         pci_set_drvdata(pci, NULL);
2474 }
2475
2476 /* PCI IDs */
2477 static struct pci_device_id azx_ids[] = {
2478         /* ICH 6..10 */
2479         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2480         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2481         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2482         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2483         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2484         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2485         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2486         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2487         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2488         /* PCH */
2489         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2490         /* SCH */
2491         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2492         /* ATI SB 450/600 */
2493         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2494         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2495         /* ATI HDMI */
2496         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2497         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2498         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2499         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2500         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2501         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2502         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2503         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2504         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2505         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2506         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2507         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2508         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2509         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2510         /* VIA VT8251/VT8237A */
2511         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2512         /* SIS966 */
2513         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2514         /* ULI M5461 */
2515         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2516         /* NVIDIA MCP */
2517         { PCI_DEVICE(0x10de, 0x026c), .driver_data = AZX_DRIVER_NVIDIA },
2518         { PCI_DEVICE(0x10de, 0x0371), .driver_data = AZX_DRIVER_NVIDIA },
2519         { PCI_DEVICE(0x10de, 0x03e4), .driver_data = AZX_DRIVER_NVIDIA },
2520         { PCI_DEVICE(0x10de, 0x03f0), .driver_data = AZX_DRIVER_NVIDIA },
2521         { PCI_DEVICE(0x10de, 0x044a), .driver_data = AZX_DRIVER_NVIDIA },
2522         { PCI_DEVICE(0x10de, 0x044b), .driver_data = AZX_DRIVER_NVIDIA },
2523         { PCI_DEVICE(0x10de, 0x055c), .driver_data = AZX_DRIVER_NVIDIA },
2524         { PCI_DEVICE(0x10de, 0x055d), .driver_data = AZX_DRIVER_NVIDIA },
2525         { PCI_DEVICE(0x10de, 0x0774), .driver_data = AZX_DRIVER_NVIDIA },
2526         { PCI_DEVICE(0x10de, 0x0775), .driver_data = AZX_DRIVER_NVIDIA },
2527         { PCI_DEVICE(0x10de, 0x0776), .driver_data = AZX_DRIVER_NVIDIA },
2528         { PCI_DEVICE(0x10de, 0x0777), .driver_data = AZX_DRIVER_NVIDIA },
2529         { PCI_DEVICE(0x10de, 0x07fc), .driver_data = AZX_DRIVER_NVIDIA },
2530         { PCI_DEVICE(0x10de, 0x07fd), .driver_data = AZX_DRIVER_NVIDIA },
2531         { PCI_DEVICE(0x10de, 0x0ac0), .driver_data = AZX_DRIVER_NVIDIA },
2532         { PCI_DEVICE(0x10de, 0x0ac1), .driver_data = AZX_DRIVER_NVIDIA },
2533         { PCI_DEVICE(0x10de, 0x0ac2), .driver_data = AZX_DRIVER_NVIDIA },
2534         { PCI_DEVICE(0x10de, 0x0ac3), .driver_data = AZX_DRIVER_NVIDIA },
2535         { PCI_DEVICE(0x10de, 0x0d94), .driver_data = AZX_DRIVER_NVIDIA },
2536         { PCI_DEVICE(0x10de, 0x0d95), .driver_data = AZX_DRIVER_NVIDIA },
2537         { PCI_DEVICE(0x10de, 0x0d96), .driver_data = AZX_DRIVER_NVIDIA },
2538         { PCI_DEVICE(0x10de, 0x0d97), .driver_data = AZX_DRIVER_NVIDIA },
2539         /* Teradici */
2540         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2541         /* Creative X-Fi (CA0110-IBG) */
2542 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2543         /* the following entry conflicts with snd-ctxfi driver,
2544          * as ctxfi driver mutates from HD-audio to native mode with
2545          * a special command sequence.
2546          */
2547         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2548           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2549           .class_mask = 0xffffff,
2550           .driver_data = AZX_DRIVER_GENERIC },
2551 #else
2552         /* this entry seems still valid -- i.e. without emu20kx chip */
2553         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2554 #endif
2555         /* AMD Generic, PCI class code and Vendor ID for HD Audio */
2556         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2557           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2558           .class_mask = 0xffffff,
2559           .driver_data = AZX_DRIVER_GENERIC },
2560         { 0, }
2561 };
2562 MODULE_DEVICE_TABLE(pci, azx_ids);
2563
2564 /* pci_driver definition */
2565 static struct pci_driver driver = {
2566         .name = "HDA Intel",
2567         .id_table = azx_ids,
2568         .probe = azx_probe,
2569         .remove = __devexit_p(azx_remove),
2570 #ifdef CONFIG_PM
2571         .suspend = azx_suspend,
2572         .resume = azx_resume,
2573 #endif
2574 };
2575
2576 static int __init alsa_card_azx_init(void)
2577 {
2578         return pci_register_driver(&driver);
2579 }
2580
2581 static void __exit alsa_card_azx_exit(void)
2582 {
2583         pci_unregister_driver(&driver);
2584 }
2585
2586 module_init(alsa_card_azx_init)
2587 module_exit(alsa_card_azx_exit)