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   1 /*
   2  *
   3  *  hda_intel.c - Implementation of primary alsa driver code base
   4  *                for Intel HD Audio.
   5  *
   6  *  Copyright(c) 2004 Intel Corporation. All rights reserved.
   7  *
   8  *  Copyright (c) 2004 Takashi Iwai <tiwai@suse.de>
   9  *                     PeiSen Hou <pshou@realtek.com.tw>
  10  *
  11  *  This program is free software; you can redistribute it and/or modify it
  12  *  under the terms of the GNU General Public License as published by the Free
  13  *  Software Foundation; either version 2 of the License, or (at your option)
  14  *  any later version.
  15  *
  16  *  This program is distributed in the hope that it will be useful, but WITHOUT
  17  *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18  *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  19  *  more details.
  20  *
  21  *  You should have received a copy of the GNU General Public License along with
  22  *  this program; if not, write to the Free Software Foundation, Inc., 59
  23  *  Temple Place - Suite 330, Boston, MA  02111-1307, USA.
  24  *
  25  *  CONTACTS:
  26  *
  27  *  Matt Jared          matt.jared@intel.com
  28  *  Andy Kopp           andy.kopp@intel.com
  29  *  Dan Kogan           dan.d.kogan@intel.com
  30  *
  31  *  CHANGES:
  32  *
  33  *  2004.12.01  Major rewrite by tiwai, merged the work of pshou
  34  *
  35  */
  36
  37 #include <asm/io.h>
  38 #include <linux/delay.h>
  39 #include <linux/interrupt.h>
  40 #include <linux/kernel.h>
  41 #include <linux/module.h>
  42 #include <linux/dma-mapping.h>
  43 #include <linux/moduleparam.h>
  44 #include <linux/init.h>
  45 #include <linux/slab.h>
  46 #include <linux/pci.h>
  47 #include <linux/mutex.h>
  48 #include <linux/reboot.h>
  49 #include <sound/core.h>
  50 #include <sound/initval.h>
  51 #include "hda_codec.h"
  52
  53
  54 static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX;
  55 static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR;
  56 static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
  57 static char *model[SNDRV_CARDS];
  58 static int position_fix[SNDRV_CARDS];
  59 static int bdl_pos_adj[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  60 static int probe_mask[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] = -1};
  61 static int probe_only[SNDRV_CARDS];
  62 static int single_cmd;
  63 static int enable_msi = -1;
  64 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  65 static char *patch[SNDRV_CARDS];
  66 #endif
  67 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  68 static int beep_mode[SNDRV_CARDS] = {[0 ... (SNDRV_CARDS-1)] =
  69                                         CONFIG_SND_HDA_INPUT_BEEP_MODE};
  70 #endif
  71
  72 module_param_array(index, int, NULL, 0444);
  73 MODULE_PARM_DESC(index, "Index value for Intel HD audio interface.");
  74 module_param_array(id, charp, NULL, 0444);
  75 MODULE_PARM_DESC(id, "ID string for Intel HD audio interface.");
  76 module_param_array(enable, bool, NULL, 0444);
  77 MODULE_PARM_DESC(enable, "Enable Intel HD audio interface.");
  78 module_param_array(model, charp, NULL, 0444);
  79 MODULE_PARM_DESC(model, "Use the given board model.");
  80 module_param_array(position_fix, int, NULL, 0444);
  81 MODULE_PARM_DESC(position_fix, "Fix DMA pointer "
  82                  "(0 = auto, 1 = none, 2 = POSBUF).");
  83 module_param_array(bdl_pos_adj, int, NULL, 0644);
  84 MODULE_PARM_DESC(bdl_pos_adj, "BDL position adjustment offset.");
  85 module_param_array(probe_mask, int, NULL, 0444);
  86 MODULE_PARM_DESC(probe_mask, "Bitmask to probe codecs (default = -1).");
  87 module_param_array(probe_only, bool, NULL, 0444);
  88 MODULE_PARM_DESC(probe_only, "Only probing and no codec initialization.");
  89 module_param(single_cmd, bool, 0444);
  90 MODULE_PARM_DESC(single_cmd, "Use single command to communicate with codecs "
  91                  "(for debugging only).");
  92 module_param(enable_msi, int, 0444);
  93 MODULE_PARM_DESC(enable_msi, "Enable Message Signaled Interrupt (MSI)");
  94 #ifdef CONFIG_SND_HDA_PATCH_LOADER
  95 module_param_array(patch, charp, NULL, 0444);
  96 MODULE_PARM_DESC(patch, "Patch file for Intel HD audio interface.");
  97 #endif
  98 #ifdef CONFIG_SND_HDA_INPUT_BEEP
  99 module_param_array(beep_mode, int, NULL, 0444);
 100 MODULE_PARM_DESC(beep_mode, "Select HDA Beep registration mode "
 101                             "(0=off, 1=on, 2=mute switch on/off) (default=1).");
 102 #endif
 103
 104 #ifdef CONFIG_SND_HDA_POWER_SAVE
 105 static int power_save = CONFIG_SND_HDA_POWER_SAVE_DEFAULT;
 106 module_param(power_save, int, 0644);
 107 MODULE_PARM_DESC(power_save, "Automatic power-saving timeout "
 108                  "(in second, 0 = disable).");
 109
 110 /* reset the HD-audio controller in power save mode.
 111  * this may give more power-saving, but will take longer time to
 112  * wake up.
 113  */
 114 static int power_save_controller = 1;
 115 module_param(power_save_controller, bool, 0644);
 116 MODULE_PARM_DESC(power_save_controller, "Reset controller in power save mode.");
 117 #endif
 118
 119 MODULE_LICENSE("GPL");
 120 MODULE_SUPPORTED_DEVICE("{{Intel, ICH6},"
 121                          "{Intel, ICH6M},"
 122                          "{Intel, ICH7},"
 123                          "{Intel, ESB2},"
 124                          "{Intel, ICH8},"
 125                          "{Intel, ICH9},"
 126                          "{Intel, ICH10},"
 127                          "{Intel, PCH},"
 128                          "{Intel, CPT},"
 129                          "{Intel, SCH},"
 130                          "{ATI, SB450},"
 131                          "{ATI, SB600},"
 132                          "{ATI, RS600},"
 133                          "{ATI, RS690},"
 134                          "{ATI, RS780},"
 135                          "{ATI, R600},"
 136                          "{ATI, RV630},"
 137                          "{ATI, RV610},"
 138                          "{ATI, RV670},"
 139                          "{ATI, RV635},"
 140                          "{ATI, RV620},"
 141                          "{ATI, RV770},"
 142                          "{VIA, VT8251},"
 143                          "{VIA, VT8237A},"
 144                          "{SiS, SIS966},"
 145                          "{ULI, M5461}}");
 146 MODULE_DESCRIPTION("Intel HDA driver");
 147
 148 #ifdef CONFIG_SND_VERBOSE_PRINTK
 149 #define SFX     /* nop */
 150 #else
 151 #define SFX     "hda-intel: "
 152 #endif
 153
 154 /*
 155  * registers
 156  */
 157 #define ICH6_REG_GCAP                   0x00
 158 #define   ICH6_GCAP_64OK        (1 << 0)   /* 64bit address support */
 159 #define   ICH6_GCAP_NSDO        (3 << 1)   /* # of serial data out signals */
 160 #define   ICH6_GCAP_BSS         (31 << 3)  /* # of bidirectional streams */
 161 #define   ICH6_GCAP_ISS         (15 << 8)  /* # of input streams */
 162 #define   ICH6_GCAP_OSS         (15 << 12) /* # of output streams */
 163 #define ICH6_REG_VMIN                   0x02
 164 #define ICH6_REG_VMAJ                   0x03
 165 #define ICH6_REG_OUTPAY                 0x04
 166 #define ICH6_REG_INPAY                  0x06
 167 #define ICH6_REG_GCTL                   0x08
 168 #define   ICH6_GCTL_RESET       (1 << 0)   /* controller reset */
 169 #define   ICH6_GCTL_FCNTRL      (1 << 1)   /* flush control */
 170 #define   ICH6_GCTL_UNSOL       (1 << 8)   /* accept unsol. response enable */
 171 #define ICH6_REG_WAKEEN                 0x0c
 172 #define ICH6_REG_STATESTS               0x0e
 173 #define ICH6_REG_GSTS                   0x10
 174 #define   ICH6_GSTS_FSTS        (1 << 1)   /* flush status */
 175 #define ICH6_REG_INTCTL                 0x20
 176 #define ICH6_REG_INTSTS                 0x24
 177 #define ICH6_REG_WALCLK                 0x30
 178 #define ICH6_REG_SYNC                   0x34
 179 #define ICH6_REG_CORBLBASE              0x40
 180 #define ICH6_REG_CORBUBASE              0x44
 181 #define ICH6_REG_CORBWP                 0x48
 182 #define ICH6_REG_CORBRP                 0x4a
 183 #define   ICH6_CORBRP_RST       (1 << 15)  /* read pointer reset */
 184 #define ICH6_REG_CORBCTL                0x4c
 185 #define   ICH6_CORBCTL_RUN      (1 << 1)   /* enable DMA */
 186 #define   ICH6_CORBCTL_CMEIE    (1 << 0)   /* enable memory error irq */
 187 #define ICH6_REG_CORBSTS                0x4d
 188 #define   ICH6_CORBSTS_CMEI     (1 << 0)   /* memory error indication */
 189 #define ICH6_REG_CORBSIZE               0x4e
 190
 191 #define ICH6_REG_RIRBLBASE              0x50
 192 #define ICH6_REG_RIRBUBASE              0x54
 193 #define ICH6_REG_RIRBWP                 0x58
 194 #define   ICH6_RIRBWP_RST       (1 << 15)  /* write pointer reset */
 195 #define ICH6_REG_RINTCNT                0x5a
 196 #define ICH6_REG_RIRBCTL                0x5c
 197 #define   ICH6_RBCTL_IRQ_EN     (1 << 0)   /* enable IRQ */
 198 #define   ICH6_RBCTL_DMA_EN     (1 << 1)   /* enable DMA */
 199 #define   ICH6_RBCTL_OVERRUN_EN (1 << 2)   /* enable overrun irq */
 200 #define ICH6_REG_RIRBSTS                0x5d
 201 #define   ICH6_RBSTS_IRQ        (1 << 0)   /* response irq */
 202 #define   ICH6_RBSTS_OVERRUN    (1 << 2)   /* overrun irq */
 203 #define ICH6_REG_RIRBSIZE               0x5e
 204
 205 #define ICH6_REG_IC                     0x60
 206 #define ICH6_REG_IR                     0x64
 207 #define ICH6_REG_IRS                    0x68
 208 #define   ICH6_IRS_VALID        (1<<1)
 209 #define   ICH6_IRS_BUSY         (1<<0)
 210
 211 #define ICH6_REG_DPLBASE                0x70
 212 #define ICH6_REG_DPUBASE                0x74
 213 #define   ICH6_DPLBASE_ENABLE   0x1     /* Enable position buffer */
 214
 215 /* SD offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
 216 enum { SDI0, SDI1, SDI2, SDI3, SDO0, SDO1, SDO2, SDO3 };
 217
 218 /* stream register offsets from stream base */
 219 #define ICH6_REG_SD_CTL                 0x00
 220 #define ICH6_REG_SD_STS                 0x03
 221 #define ICH6_REG_SD_LPIB                0x04
 222 #define ICH6_REG_SD_CBL                 0x08
 223 #define ICH6_REG_SD_LVI                 0x0c
 224 #define ICH6_REG_SD_FIFOW               0x0e
 225 #define ICH6_REG_SD_FIFOSIZE            0x10
 226 #define ICH6_REG_SD_FORMAT              0x12
 227 #define ICH6_REG_SD_BDLPL               0x18
 228 #define ICH6_REG_SD_BDLPU               0x1c
 229
 230 /* PCI space */
 231 #define ICH6_PCIREG_TCSEL       0x44
 232
 233 /*
 234  * other constants
 235  */
 236
 237 /* max number of SDs */
 238 /* ICH, ATI and VIA have 4 playback and 4 capture */
 239 #define ICH6_NUM_CAPTURE        4
 240 #define ICH6_NUM_PLAYBACK       4
 241
 242 /* ULI has 6 playback and 5 capture */
 243 #define ULI_NUM_CAPTURE         5
 244 #define ULI_NUM_PLAYBACK        6
 245
 246 /* ATI HDMI has 1 playback and 0 capture */
 247 #define ATIHDMI_NUM_CAPTURE     0
 248 #define ATIHDMI_NUM_PLAYBACK    1
 249
 250 /* TERA has 4 playback and 3 capture */
 251 #define TERA_NUM_CAPTURE        3
 252 #define TERA_NUM_PLAYBACK       4
 253
 254 /* this number is statically defined for simplicity */
 255 #define MAX_AZX_DEV             16
 256
 257 /* max number of fragments - we may use more if allocating more pages for BDL */
 258 #define BDL_SIZE                4096
 259 #define AZX_MAX_BDL_ENTRIES     (BDL_SIZE / 16)
 260 #define AZX_MAX_FRAG            32
 261 /* max buffer size - no h/w limit, you can increase as you like */
 262 #define AZX_MAX_BUF_SIZE        (1024*1024*1024)
 263
 264 /* RIRB int mask: overrun[2], response[0] */
 265 #define RIRB_INT_RESPONSE       0x01
 266 #define RIRB_INT_OVERRUN        0x04
 267 #define RIRB_INT_MASK           0x05
 268
 269 /* STATESTS int mask: S3,SD2,SD1,SD0 */
 270 #define AZX_MAX_CODECS          8
 271 #define AZX_DEFAULT_CODECS      4
 272 #define STATESTS_INT_MASK       ((1 << AZX_MAX_CODECS) - 1)
 273
 274 /* SD_CTL bits */
 275 #define SD_CTL_STREAM_RESET     0x01    /* stream reset bit */
 276 #define SD_CTL_DMA_START        0x02    /* stream DMA start bit */
 277 #define SD_CTL_STRIPE           (3 << 16)       /* stripe control */
 278 #define SD_CTL_TRAFFIC_PRIO     (1 << 18)       /* traffic priority */
 279 #define SD_CTL_DIR              (1 << 19)       /* bi-directional stream */
 280 #define SD_CTL_STREAM_TAG_MASK  (0xf << 20)
 281 #define SD_CTL_STREAM_TAG_SHIFT 20
 282
 283 /* SD_CTL and SD_STS */
 284 #define SD_INT_DESC_ERR         0x10    /* descriptor error interrupt */
 285 #define SD_INT_FIFO_ERR         0x08    /* FIFO error interrupt */
 286 #define SD_INT_COMPLETE         0x04    /* completion interrupt */
 287 #define SD_INT_MASK             (SD_INT_DESC_ERR|SD_INT_FIFO_ERR|\
 288                                  SD_INT_COMPLETE)
 289
 290 /* SD_STS */
 291 #define SD_STS_FIFO_READY       0x20    /* FIFO ready */
 292
 293 /* INTCTL and INTSTS */
 294 #define ICH6_INT_ALL_STREAM     0xff       /* all stream interrupts */
 295 #define ICH6_INT_CTRL_EN        0x40000000 /* controller interrupt enable bit */
 296 #define ICH6_INT_GLOBAL_EN      0x80000000 /* global interrupt enable bit */
 297
 298 /* below are so far hardcoded - should read registers in future */
 299 #define ICH6_MAX_CORB_ENTRIES   256
 300 #define ICH6_MAX_RIRB_ENTRIES   256
 301
 302 /* position fix mode */
 303 enum {
 304         POS_FIX_AUTO,
 305         POS_FIX_LPIB,
 306         POS_FIX_POSBUF,
 307 };
 308
 309 /* Defines for ATI HD Audio support in SB450 south bridge */
 310 #define ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR   0x42
 311 #define ATI_SB450_HDAUDIO_ENABLE_SNOOP      0x02
 312
 313 /* Defines for Nvidia HDA support */
 314 #define NVIDIA_HDA_TRANSREG_ADDR      0x4e
 315 #define NVIDIA_HDA_ENABLE_COHBITS     0x0f
 316 #define NVIDIA_HDA_ISTRM_COH          0x4d
 317 #define NVIDIA_HDA_OSTRM_COH          0x4c
 318 #define NVIDIA_HDA_ENABLE_COHBIT      0x01
 319
 320 /* Defines for Intel SCH HDA snoop control */
 321 #define INTEL_SCH_HDA_DEVC      0x78
 322 #define INTEL_SCH_HDA_DEVC_NOSNOOP       (0x1<<11)
 323
 324 /* Define IN stream 0 FIFO size offset in VIA controller */
 325 #define VIA_IN_STREAM0_FIFO_SIZE_OFFSET 0x90
 326 /* Define VIA HD Audio Device ID*/
 327 #define VIA_HDAC_DEVICE_ID              0x3288
 328
 329 /* HD Audio class code */
 330 #define PCI_CLASS_MULTIMEDIA_HD_AUDIO   0x0403
 331
 332 /*
 333  */
 334
 335 struct azx_dev {
 336         struct snd_dma_buffer bdl; /* BDL buffer */
 337         u32 *posbuf;            /* position buffer pointer */
 338
 339         unsigned int bufsize;   /* size of the play buffer in bytes */
 340         unsigned int period_bytes; /* size of the period in bytes */
 341         unsigned int frags;     /* number for period in the play buffer */
 342         unsigned int fifo_size; /* FIFO size */
 343         unsigned long start_jiffies;    /* start + minimum jiffies */
 344         unsigned long min_jiffies;      /* minimum jiffies before position is valid */
 345
 346         void __iomem *sd_addr;  /* stream descriptor pointer */
 347
 348         u32 sd_int_sta_mask;    /* stream int status mask */
 349
 350         /* pcm support */
 351         struct snd_pcm_substream *substream;    /* assigned substream,
 352                                                  * set in PCM open
 353                                                  */
 354         unsigned int format_val;        /* format value to be set in the
 355                                          * controller and the codec
 356                                          */
 357         unsigned char stream_tag;       /* assigned stream */
 358         unsigned char index;            /* stream index */
 359         int device;                     /* last device number assigned to */
 360
 361         unsigned int opened :1;
 362         unsigned int running :1;
 363         unsigned int irq_pending :1;
 364         unsigned int start_flag: 1;     /* stream full start flag */
 365         /*
 366          * For VIA:
 367          *  A flag to ensure DMA position is 0
 368          *  when link position is not greater than FIFO size
 369          */
 370         unsigned int insufficient :1;
 371 };
 372
 373 /* CORB/RIRB */
 374 struct azx_rb {
 375         u32 *buf;               /* CORB/RIRB buffer
 376                                  * Each CORB entry is 4byte, RIRB is 8byte
 377                                  */
 378         dma_addr_t addr;        /* physical address of CORB/RIRB buffer */
 379         /* for RIRB */
 380         unsigned short rp, wp;  /* read/write pointers */
 381         int cmds[AZX_MAX_CODECS];       /* number of pending requests */
 382         u32 res[AZX_MAX_CODECS];        /* last read value */
 383 };
 384
 385 struct azx {
 386         struct snd_card *card;
 387         struct pci_dev *pci;
 388         int dev_index;
 389
 390         /* chip type specific */
 391         int driver_type;
 392         int playback_streams;
 393         int playback_index_offset;
 394         int capture_streams;
 395         int capture_index_offset;
 396         int num_streams;
 397
 398         /* pci resources */
 399         unsigned long addr;
 400         void __iomem *remap_addr;
 401         int irq;
 402
 403         /* locks */
 404         spinlock_t reg_lock;
 405         struct mutex open_mutex;
 406
 407         /* streams (x num_streams) */
 408         struct azx_dev *azx_dev;
 409
 410         /* PCM */
 411         struct snd_pcm *pcm[HDA_MAX_PCMS];
 412
 413         /* HD codec */
 414         unsigned short codec_mask;
 415         int  codec_probe_mask; /* copied from probe_mask option */
 416         struct hda_bus *bus;
 417         unsigned int beep_mode;
 418
 419         /* CORB/RIRB */
 420         struct azx_rb corb;
 421         struct azx_rb rirb;
 422
 423         /* CORB/RIRB and position buffers */
 424         struct snd_dma_buffer rb;
 425         struct snd_dma_buffer posbuf;
 426
 427         /* flags */
 428         int position_fix;
 429         int poll_count;
 430         unsigned int running :1;
 431         unsigned int initialized :1;
 432         unsigned int single_cmd :1;
 433         unsigned int polling_mode :1;
 434         unsigned int msi :1;
 435         unsigned int irq_pending_warned :1;
 436         unsigned int via_dmapos_patch :1; /* enable DMA-position fix for VIA */
 437         unsigned int probing :1; /* codec probing phase */
 438
 439         /* for debugging */
 440         unsigned int last_cmd[AZX_MAX_CODECS];
 441
 442         /* for pending irqs */
 443         struct work_struct irq_pending_work;
 444
 445         /* reboot notifier (for mysterious hangup problem at power-down) */
 446         struct notifier_block reboot_notifier;
 447 };
 448
 449 /* driver types */
 450 enum {
 451         AZX_DRIVER_ICH,
 452         AZX_DRIVER_PCH,
 453         AZX_DRIVER_SCH,
 454         AZX_DRIVER_ATI,
 455         AZX_DRIVER_ATIHDMI,
 456         AZX_DRIVER_VIA,
 457         AZX_DRIVER_SIS,
 458         AZX_DRIVER_ULI,
 459         AZX_DRIVER_NVIDIA,
 460         AZX_DRIVER_TERA,
 461         AZX_DRIVER_GENERIC,
 462         AZX_NUM_DRIVERS, /* keep this as last entry */
 463 };
 464
 465 static char *driver_short_names[] __devinitdata = {
 466         [AZX_DRIVER_ICH] = "HDA Intel",
 467         [AZX_DRIVER_PCH] = "HDA Intel PCH",
 468         [AZX_DRIVER_SCH] = "HDA Intel MID",
 469         [AZX_DRIVER_ATI] = "HDA ATI SB",
 470         [AZX_DRIVER_ATIHDMI] = "HDA ATI HDMI",
 471         [AZX_DRIVER_VIA] = "HDA VIA VT82xx",
 472         [AZX_DRIVER_SIS] = "HDA SIS966",
 473         [AZX_DRIVER_ULI] = "HDA ULI M5461",
 474         [AZX_DRIVER_NVIDIA] = "HDA NVidia",
 475         [AZX_DRIVER_TERA] = "HDA Teradici",
 476         [AZX_DRIVER_GENERIC] = "HD-Audio Generic",
 477 };
 478
 479 /*
 480  * macros for easy use
 481  */
 482 #define azx_writel(chip,reg,value) \
 483         writel(value, (chip)->remap_addr + ICH6_REG_##reg)
 484 #define azx_readl(chip,reg) \
 485         readl((chip)->remap_addr + ICH6_REG_##reg)
 486 #define azx_writew(chip,reg,value) \
 487         writew(value, (chip)->remap_addr + ICH6_REG_##reg)
 488 #define azx_readw(chip,reg) \
 489         readw((chip)->remap_addr + ICH6_REG_##reg)
 490 #define azx_writeb(chip,reg,value) \
 491         writeb(value, (chip)->remap_addr + ICH6_REG_##reg)
 492 #define azx_readb(chip,reg) \
 493         readb((chip)->remap_addr + ICH6_REG_##reg)
 494
 495 #define azx_sd_writel(dev,reg,value) \
 496         writel(value, (dev)->sd_addr + ICH6_REG_##reg)
 497 #define azx_sd_readl(dev,reg) \
 498         readl((dev)->sd_addr + ICH6_REG_##reg)
 499 #define azx_sd_writew(dev,reg,value) \
 500         writew(value, (dev)->sd_addr + ICH6_REG_##reg)
 501 #define azx_sd_readw(dev,reg) \
 502         readw((dev)->sd_addr + ICH6_REG_##reg)
 503 #define azx_sd_writeb(dev,reg,value) \
 504         writeb(value, (dev)->sd_addr + ICH6_REG_##reg)
 505 #define azx_sd_readb(dev,reg) \
 506         readb((dev)->sd_addr + ICH6_REG_##reg)
 507
 508 /* for pcm support */
 509 #define get_azx_dev(substream) (substream->runtime->private_data)
 510
 511 static int azx_acquire_irq(struct azx *chip, int do_disconnect);
 512 static int azx_send_cmd(struct hda_bus *bus, unsigned int val);
 513 /*
 514  * Interface for HD codec
 515  */
 516
 517 /*
 518  * CORB / RIRB interface
 519  */
 520 static int azx_alloc_cmd_io(struct azx *chip)
 521 {
 522         int err;
 523
 524         /* single page (at least 4096 bytes) must suffice for both ringbuffes */
 525         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
 526                                   snd_dma_pci_data(chip->pci),
 527                                   PAGE_SIZE, &chip->rb);
 528         if (err < 0) {
 529                 snd_printk(KERN_ERR SFX "cannot allocate CORB/RIRB\n");
 530                 return err;
 531         }
 532         return 0;
 533 }
 534
 535 static void azx_init_cmd_io(struct azx *chip)
 536 {
 537         spin_lock_irq(&chip->reg_lock);
 538         /* CORB set up */
 539         chip->corb.addr = chip->rb.addr;
 540         chip->corb.buf = (u32 *)chip->rb.area;
 541         azx_writel(chip, CORBLBASE, (u32)chip->corb.addr);
 542         azx_writel(chip, CORBUBASE, upper_32_bits(chip->corb.addr));
 543
 544         /* set the corb size to 256 entries (ULI requires explicitly) */
 545         azx_writeb(chip, CORBSIZE, 0x02);
 546         /* set the corb write pointer to 0 */
 547         azx_writew(chip, CORBWP, 0);
 548         /* reset the corb hw read pointer */
 549         azx_writew(chip, CORBRP, ICH6_CORBRP_RST);
 550         /* enable corb dma */
 551         azx_writeb(chip, CORBCTL, ICH6_CORBCTL_RUN);
 552
 553         /* RIRB set up */
 554         chip->rirb.addr = chip->rb.addr + 2048;
 555         chip->rirb.buf = (u32 *)(chip->rb.area + 2048);
 556         chip->rirb.wp = chip->rirb.rp = 0;
 557         memset(chip->rirb.cmds, 0, sizeof(chip->rirb.cmds));
 558         azx_writel(chip, RIRBLBASE, (u32)chip->rirb.addr);
 559         azx_writel(chip, RIRBUBASE, upper_32_bits(chip->rirb.addr));
 560
 561         /* set the rirb size to 256 entries (ULI requires explicitly) */
 562         azx_writeb(chip, RIRBSIZE, 0x02);
 563         /* reset the rirb hw write pointer */
 564         azx_writew(chip, RIRBWP, ICH6_RIRBWP_RST);
 565         /* set N=1, get RIRB response interrupt for new entry */
 566         azx_writew(chip, RINTCNT, 1);
 567         /* enable rirb dma and response irq */
 568         azx_writeb(chip, RIRBCTL, ICH6_RBCTL_DMA_EN | ICH6_RBCTL_IRQ_EN);
 569         spin_unlock_irq(&chip->reg_lock);
 570 }
 571
 572 static void azx_free_cmd_io(struct azx *chip)
 573 {
 574         spin_lock_irq(&chip->reg_lock);
 575         /* disable ringbuffer DMAs */
 576         azx_writeb(chip, RIRBCTL, 0);
 577         azx_writeb(chip, CORBCTL, 0);
 578         spin_unlock_irq(&chip->reg_lock);
 579 }
 580
 581 static unsigned int azx_command_addr(u32 cmd)
 582 {
 583         unsigned int addr = cmd >> 28;
 584
 585         if (addr >= AZX_MAX_CODECS) {
 586                 snd_BUG();
 587                 addr = 0;
 588         }
 589
 590         return addr;
 591 }
 592
 593 static unsigned int azx_response_addr(u32 res)
 594 {
 595         unsigned int addr = res & 0xf;
 596
 597         if (addr >= AZX_MAX_CODECS) {
 598                 snd_BUG();
 599                 addr = 0;
 600         }
 601
 602         return addr;
 603 }
 604
 605 /* send a command */
 606 static int azx_corb_send_cmd(struct hda_bus *bus, u32 val)
 607 {
 608         struct azx *chip = bus->private_data;
 609         unsigned int addr = azx_command_addr(val);
 610         unsigned int wp;
 611
 612         spin_lock_irq(&chip->reg_lock);
 613
 614         /* add command to corb */
 615         wp = azx_readb(chip, CORBWP);
 616         wp++;
 617         wp %= ICH6_MAX_CORB_ENTRIES;
 618
 619         chip->rirb.cmds[addr]++;
 620         chip->corb.buf[wp] = cpu_to_le32(val);
 621         azx_writel(chip, CORBWP, wp);
 622
 623         spin_unlock_irq(&chip->reg_lock);
 624
 625         return 0;
 626 }
 627
 628 #define ICH6_RIRB_EX_UNSOL_EV   (1<<4)
 629
 630 /* retrieve RIRB entry - called from interrupt handler */
 631 static void azx_update_rirb(struct azx *chip)
 632 {
 633         unsigned int rp, wp;
 634         unsigned int addr;
 635         u32 res, res_ex;
 636
 637         wp = azx_readb(chip, RIRBWP);
 638         if (wp == chip->rirb.wp)
 639                 return;
 640         chip->rirb.wp = wp;
 641
 642         while (chip->rirb.rp != wp) {
 643                 chip->rirb.rp++;
 644                 chip->rirb.rp %= ICH6_MAX_RIRB_ENTRIES;
 645
 646                 rp = chip->rirb.rp << 1; /* an RIRB entry is 8-bytes */
 647                 res_ex = le32_to_cpu(chip->rirb.buf[rp + 1]);
 648                 res = le32_to_cpu(chip->rirb.buf[rp]);
 649                 addr = azx_response_addr(res_ex);
 650                 if (res_ex & ICH6_RIRB_EX_UNSOL_EV)
 651                         snd_hda_queue_unsol_event(chip->bus, res, res_ex);
 652                 else if (chip->rirb.cmds[addr]) {
 653                         chip->rirb.res[addr] = res;
 654                         smp_wmb();
 655                         chip->rirb.cmds[addr]--;
 656                 } else
 657                         snd_printk(KERN_ERR SFX "spurious response %#x:%#x, "
 658                                    "last cmd=%#08x\n",
 659                                    res, res_ex,
 660                                    chip->last_cmd[addr]);
 661         }
 662 }
 663
 664 /* receive a response */
 665 static unsigned int azx_rirb_get_response(struct hda_bus *bus,
 666                                           unsigned int addr)
 667 {
 668         struct azx *chip = bus->private_data;
 669         unsigned long timeout;
 670         int do_poll = 0;
 671
 672  again:
 673         timeout = jiffies + msecs_to_jiffies(1000);
 674         for (;;) {
 675                 if (chip->polling_mode || do_poll) {
 676                         spin_lock_irq(&chip->reg_lock);
 677                         azx_update_rirb(chip);
 678                         spin_unlock_irq(&chip->reg_lock);
 679                 }
 680                 if (!chip->rirb.cmds[addr]) {
 681                         smp_rmb();
 682                         bus->rirb_error = 0;
 683
 684                         if (!do_poll)
 685                                 chip->poll_count = 0;
 686                         return chip->rirb.res[addr]; /* the last value */
 687                 }
 688                 if (time_after(jiffies, timeout))
 689                         break;
 690                 if (bus->needs_damn_long_delay)
 691                         msleep(2); /* temporary workaround */
 692                 else {
 693                         udelay(10);
 694                         cond_resched();
 695                 }
 696         }
 697
 698         if (!chip->polling_mode && chip->poll_count < 2) {
 699                 snd_printdd(SFX "azx_get_response timeout, "
 700                            "polling the codec once: last cmd=0x%08x\n",
 701                            chip->last_cmd[addr]);
 702                 do_poll = 1;
 703                 chip->poll_count++;
 704                 goto again;
 705         }
 706
 707
 708         if (!chip->polling_mode) {
 709                 snd_printk(KERN_WARNING SFX "azx_get_response timeout, "
 710                            "switching to polling mode: last cmd=0x%08x\n",
 711                            chip->last_cmd[addr]);
 712                 chip->polling_mode = 1;
 713                 goto again;
 714         }
 715
 716         if (chip->msi) {
 717                 snd_printk(KERN_WARNING SFX "No response from codec, "
 718                            "disabling MSI: last cmd=0x%08x\n",
 719                            chip->last_cmd[addr]);
 720                 free_irq(chip->irq, chip);
 721                 chip->irq = -1;
 722                 pci_disable_msi(chip->pci);
 723                 chip->msi = 0;
 724                 if (azx_acquire_irq(chip, 1) < 0) {
 725                         bus->rirb_error = 1;
 726                         return -1;
 727                 }
 728                 goto again;
 729         }
 730
 731         if (chip->probing) {
 732                 /* If this critical timeout happens during the codec probing
 733                  * phase, this is likely an access to a non-existing codec
 734                  * slot.  Better to return an error and reset the system.
 735                  */
 736                 return -1;
 737         }
 738
 739         /* a fatal communication error; need either to reset or to fallback
 740          * to the single_cmd mode
 741          */
 742         bus->rirb_error = 1;
 743         if (bus->allow_bus_reset && !bus->response_reset && !bus->in_reset) {
 744                 bus->response_reset = 1;
 745                 return -1; /* give a chance to retry */
 746         }
 747
 748         snd_printk(KERN_ERR "hda_intel: azx_get_response timeout, "
 749                    "switching to single_cmd mode: last cmd=0x%08x\n",
 750                    chip->last_cmd[addr]);
 751         chip->single_cmd = 1;
 752         bus->response_reset = 0;
 753         /* release CORB/RIRB */
 754         azx_free_cmd_io(chip);
 755         /* disable unsolicited responses */
 756         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_UNSOL);
 757         return -1;
 758 }
 759
 760 /*
 761  * Use the single immediate command instead of CORB/RIRB for simplicity
 762  *
 763  * Note: according to Intel, this is not preferred use.  The command was
 764  *       intended for the BIOS only, and may get confused with unsolicited
 765  *       responses.  So, we shouldn't use it for normal operation from the
 766  *       driver.
 767  *       I left the codes, however, for debugging/testing purposes.
 768  */
 769
 770 /* receive a response */
 771 static int azx_single_wait_for_response(struct azx *chip, unsigned int addr)
 772 {
 773         int timeout = 50;
 774
 775         while (timeout--) {
 776                 /* check IRV busy bit */
 777                 if (azx_readw(chip, IRS) & ICH6_IRS_VALID) {
 778                         /* reuse rirb.res as the response return value */
 779                         chip->rirb.res[addr] = azx_readl(chip, IR);
 780                         return 0;
 781                 }
 782                 udelay(1);
 783         }
 784         if (printk_ratelimit())
 785                 snd_printd(SFX "get_response timeout: IRS=0x%x\n",
 786                            azx_readw(chip, IRS));
 787         chip->rirb.res[addr] = -1;
 788         return -EIO;
 789 }
 790
 791 /* send a command */
 792 static int azx_single_send_cmd(struct hda_bus *bus, u32 val)
 793 {
 794         struct azx *chip = bus->private_data;
 795         unsigned int addr = azx_command_addr(val);
 796         int timeout = 50;
 797
 798         bus->rirb_error = 0;
 799         while (timeout--) {
 800                 /* check ICB busy bit */
 801                 if (!((azx_readw(chip, IRS) & ICH6_IRS_BUSY))) {
 802                         /* Clear IRV valid bit */
 803                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 804                                    ICH6_IRS_VALID);
 805                         azx_writel(chip, IC, val);
 806                         azx_writew(chip, IRS, azx_readw(chip, IRS) |
 807                                    ICH6_IRS_BUSY);
 808                         return azx_single_wait_for_response(chip, addr);
 809                 }
 810                 udelay(1);
 811         }
 812         if (printk_ratelimit())
 813                 snd_printd(SFX "send_cmd timeout: IRS=0x%x, val=0x%x\n",
 814                            azx_readw(chip, IRS), val);
 815         return -EIO;
 816 }
 817
 818 /* receive a response */
 819 static unsigned int azx_single_get_response(struct hda_bus *bus,
 820                                             unsigned int addr)
 821 {
 822         struct azx *chip = bus->private_data;
 823         return chip->rirb.res[addr];
 824 }
 825
 826 /*
 827  * The below are the main callbacks from hda_codec.
 828  *
 829  * They are just the skeleton to call sub-callbacks according to the
 830  * current setting of chip->single_cmd.
 831  */
 832
 833 /* send a command */
 834 static int azx_send_cmd(struct hda_bus *bus, unsigned int val)
 835 {
 836         struct azx *chip = bus->private_data;
 837
 838         chip->last_cmd[azx_command_addr(val)] = val;
 839         if (chip->single_cmd)
 840                 return azx_single_send_cmd(bus, val);
 841         else
 842                 return azx_corb_send_cmd(bus, val);
 843 }
 844
 845 /* get a response */
 846 static unsigned int azx_get_response(struct hda_bus *bus,
 847                                      unsigned int addr)
 848 {
 849         struct azx *chip = bus->private_data;
 850         if (chip->single_cmd)
 851                 return azx_single_get_response(bus, addr);
 852         else
 853                 return azx_rirb_get_response(bus, addr);
 854 }
 855
 856 #ifdef CONFIG_SND_HDA_POWER_SAVE
 857 static void azx_power_notify(struct hda_bus *bus);
 858 #endif
 859
 860 /* reset codec link */
 861 static int azx_reset(struct azx *chip)
 862 {
 863         int count;
 864
 865         /* clear STATESTS */
 866         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 867
 868         /* reset controller */
 869         azx_writel(chip, GCTL, azx_readl(chip, GCTL) & ~ICH6_GCTL_RESET);
 870
 871         count = 50;
 872         while (azx_readb(chip, GCTL) && --count)
 873                 msleep(1);
 874
 875         /* delay for >= 100us for codec PLL to settle per spec
 876          * Rev 0.9 section 5.5.1
 877          */
 878         msleep(1);
 879
 880         /* Bring controller out of reset */
 881         azx_writeb(chip, GCTL, azx_readb(chip, GCTL) | ICH6_GCTL_RESET);
 882
 883         count = 50;
 884         while (!azx_readb(chip, GCTL) && --count)
 885                 msleep(1);
 886
 887         /* Brent Chartrand said to wait >= 540us for codecs to initialize */
 888         msleep(1);
 889
 890         /* check to see if controller is ready */
 891         if (!azx_readb(chip, GCTL)) {
 892                 snd_printd(SFX "azx_reset: controller not ready!\n");
 893                 return -EBUSY;
 894         }
 895
 896         /* Accept unsolicited responses */
 897         if (!chip->single_cmd)
 898                 azx_writel(chip, GCTL, azx_readl(chip, GCTL) |
 899                            ICH6_GCTL_UNSOL);
 900
 901         /* detect codecs */
 902         if (!chip->codec_mask) {
 903                 chip->codec_mask = azx_readw(chip, STATESTS);
 904                 snd_printdd(SFX "codec_mask = 0x%x\n", chip->codec_mask);
 905         }
 906
 907         return 0;
 908 }
 909
 910
 911 /*
 912  * Lowlevel interface
 913  */
 914
 915 /* enable interrupts */
 916 static void azx_int_enable(struct azx *chip)
 917 {
 918         /* enable controller CIE and GIE */
 919         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) |
 920                    ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN);
 921 }
 922
 923 /* disable interrupts */
 924 static void azx_int_disable(struct azx *chip)
 925 {
 926         int i;
 927
 928         /* disable interrupts in stream descriptor */
 929         for (i = 0; i < chip->num_streams; i++) {
 930                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 931                 azx_sd_writeb(azx_dev, SD_CTL,
 932                               azx_sd_readb(azx_dev, SD_CTL) & ~SD_INT_MASK);
 933         }
 934
 935         /* disable SIE for all streams */
 936         azx_writeb(chip, INTCTL, 0);
 937
 938         /* disable controller CIE and GIE */
 939         azx_writel(chip, INTCTL, azx_readl(chip, INTCTL) &
 940                    ~(ICH6_INT_CTRL_EN | ICH6_INT_GLOBAL_EN));
 941 }
 942
 943 /* clear interrupts */
 944 static void azx_int_clear(struct azx *chip)
 945 {
 946         int i;
 947
 948         /* clear stream status */
 949         for (i = 0; i < chip->num_streams; i++) {
 950                 struct azx_dev *azx_dev = &chip->azx_dev[i];
 951                 azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
 952         }
 953
 954         /* clear STATESTS */
 955         azx_writeb(chip, STATESTS, STATESTS_INT_MASK);
 956
 957         /* clear rirb status */
 958         azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
 959
 960         /* clear int status */
 961         azx_writel(chip, INTSTS, ICH6_INT_CTRL_EN | ICH6_INT_ALL_STREAM);
 962 }
 963
 964 /* start a stream */
 965 static void azx_stream_start(struct azx *chip, struct azx_dev *azx_dev)
 966 {
 967         /*
 968          * Before stream start, initialize parameter
 969          */
 970         azx_dev->insufficient = 1;
 971
 972         /* enable SIE */
 973         azx_writel(chip, INTCTL,
 974                    azx_readl(chip, INTCTL) | (1 << azx_dev->index));
 975         /* set DMA start and interrupt mask */
 976         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
 977                       SD_CTL_DMA_START | SD_INT_MASK);
 978 }
 979
 980 /* stop DMA */
 981 static void azx_stream_clear(struct azx *chip, struct azx_dev *azx_dev)
 982 {
 983         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) &
 984                       ~(SD_CTL_DMA_START | SD_INT_MASK));
 985         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK); /* to be sure */
 986 }
 987
 988 /* stop a stream */
 989 static void azx_stream_stop(struct azx *chip, struct azx_dev *azx_dev)
 990 {
 991         azx_stream_clear(chip, azx_dev);
 992         /* disable SIE */
 993         azx_writel(chip, INTCTL,
 994                    azx_readl(chip, INTCTL) & ~(1 << azx_dev->index));
 995 }
 996
 997
 998 /*
 999  * reset and start the controller registers
1000  */
1001 static void azx_init_chip(struct azx *chip)
1002 {
1003         if (chip->initialized)
1004                 return;
1005
1006         /* reset controller */
1007         azx_reset(chip);
1008
1009         /* initialize interrupts */
1010         azx_int_clear(chip);
1011         azx_int_enable(chip);
1012
1013         /* initialize the codec command I/O */
1014         if (!chip->single_cmd)
1015                 azx_init_cmd_io(chip);
1016
1017         /* program the position buffer */
1018         azx_writel(chip, DPLBASE, (u32)chip->posbuf.addr);
1019         azx_writel(chip, DPUBASE, upper_32_bits(chip->posbuf.addr));
1020
1021         chip->initialized = 1;
1022 }
1023
1024 /*
1025  * initialize the PCI registers
1026  */
1027 /* update bits in a PCI register byte */
1028 static void update_pci_byte(struct pci_dev *pci, unsigned int reg,
1029                             unsigned char mask, unsigned char val)
1030 {
1031         unsigned char data;
1032
1033         pci_read_config_byte(pci, reg, &data);
1034         data &= ~mask;
1035         data |= (val & mask);
1036         pci_write_config_byte(pci, reg, data);
1037 }
1038
1039 static void azx_init_pci(struct azx *chip)
1040 {
1041         unsigned short snoop;
1042
1043         /* Clear bits 0-2 of PCI register TCSEL (at offset 0x44)
1044          * TCSEL == Traffic Class Select Register, which sets PCI express QOS
1045          * Ensuring these bits are 0 clears playback static on some HD Audio
1046          * codecs
1047          */
1048         update_pci_byte(chip->pci, ICH6_PCIREG_TCSEL, 0x07, 0);
1049
1050         switch (chip->driver_type) {
1051         case AZX_DRIVER_ATI:
1052                 /* For ATI SB450 azalia HD audio, we need to enable snoop */
1053                 update_pci_byte(chip->pci,
1054                                 ATI_SB450_HDAUDIO_MISC_CNTR2_ADDR,
1055                                 0x07, ATI_SB450_HDAUDIO_ENABLE_SNOOP);
1056                 break;
1057         case AZX_DRIVER_NVIDIA:
1058                 /* For NVIDIA HDA, enable snoop */
1059                 update_pci_byte(chip->pci,
1060                                 NVIDIA_HDA_TRANSREG_ADDR,
1061                                 0x0f, NVIDIA_HDA_ENABLE_COHBITS);
1062                 update_pci_byte(chip->pci,
1063                                 NVIDIA_HDA_ISTRM_COH,
1064                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1065                 update_pci_byte(chip->pci,
1066                                 NVIDIA_HDA_OSTRM_COH,
1067                                 0x01, NVIDIA_HDA_ENABLE_COHBIT);
1068                 break;
1069         case AZX_DRIVER_SCH:
1070         case AZX_DRIVER_PCH:
1071                 pci_read_config_word(chip->pci, INTEL_SCH_HDA_DEVC, &snoop);
1072                 if (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP) {
1073                         pci_write_config_word(chip->pci, INTEL_SCH_HDA_DEVC,
1074                                 snoop & (~INTEL_SCH_HDA_DEVC_NOSNOOP));
1075                         pci_read_config_word(chip->pci,
1076                                 INTEL_SCH_HDA_DEVC, &snoop);
1077                         snd_printdd(SFX "HDA snoop disabled, enabling ... %s\n",
1078                                 (snoop & INTEL_SCH_HDA_DEVC_NOSNOOP)
1079                                 ? "Failed" : "OK");
1080                 }
1081                 break;
1082
1083         }
1084 }
1085
1086
1087 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev);
1088
1089 /*
1090  * interrupt handler
1091  */
1092 static irqreturn_t azx_interrupt(int irq, void *dev_id)
1093 {
1094         struct azx *chip = dev_id;
1095         struct azx_dev *azx_dev;
1096         u32 status;
1097         int i, ok;
1098
1099         spin_lock(&chip->reg_lock);
1100
1101         status = azx_readl(chip, INTSTS);
1102         if (status == 0) {
1103                 spin_unlock(&chip->reg_lock);
1104                 return IRQ_NONE;
1105         }
1106
1107         for (i = 0; i < chip->num_streams; i++) {
1108                 azx_dev = &chip->azx_dev[i];
1109                 if (status & azx_dev->sd_int_sta_mask) {
1110                         azx_sd_writeb(azx_dev, SD_STS, SD_INT_MASK);
1111                         if (!azx_dev->substream || !azx_dev->running)
1112                                 continue;
1113                         /* check whether this IRQ is really acceptable */
1114                         ok = azx_position_ok(chip, azx_dev);
1115                         if (ok == 1) {
1116                                 azx_dev->irq_pending = 0;
1117                                 spin_unlock(&chip->reg_lock);
1118                                 snd_pcm_period_elapsed(azx_dev->substream);
1119                                 spin_lock(&chip->reg_lock);
1120                         } else if (ok == 0 && chip->bus && chip->bus->workq) {
1121                                 /* bogus IRQ, process it later */
1122                                 azx_dev->irq_pending = 1;
1123                                 queue_work(chip->bus->workq,
1124                                            &chip->irq_pending_work);
1125                         }
1126                 }
1127         }
1128
1129         /* clear rirb int */
1130         status = azx_readb(chip, RIRBSTS);
1131         if (status & RIRB_INT_MASK) {
1132                 if (status & RIRB_INT_RESPONSE)
1133                         azx_update_rirb(chip);
1134                 azx_writeb(chip, RIRBSTS, RIRB_INT_MASK);
1135         }
1136
1137 #if 0
1138         /* clear state status int */
1139         if (azx_readb(chip, STATESTS) & 0x04)
1140                 azx_writeb(chip, STATESTS, 0x04);
1141 #endif
1142         spin_unlock(&chip->reg_lock);
1143
1144         return IRQ_HANDLED;
1145 }
1146
1147
1148 /*
1149  * set up a BDL entry
1150  */
1151 static int setup_bdle(struct snd_pcm_substream *substream,
1152                       struct azx_dev *azx_dev, u32 **bdlp,
1153                       int ofs, int size, int with_ioc)
1154 {
1155         u32 *bdl = *bdlp;
1156
1157         while (size > 0) {
1158                 dma_addr_t addr;
1159                 int chunk;
1160
1161                 if (azx_dev->frags >= AZX_MAX_BDL_ENTRIES)
1162                         return -EINVAL;
1163
1164                 addr = snd_pcm_sgbuf_get_addr(substream, ofs);
1165                 /* program the address field of the BDL entry */
1166                 bdl[0] = cpu_to_le32((u32)addr);
1167                 bdl[1] = cpu_to_le32(upper_32_bits(addr));
1168                 /* program the size field of the BDL entry */
1169                 chunk = snd_pcm_sgbuf_get_chunk_size(substream, ofs, size);
1170                 bdl[2] = cpu_to_le32(chunk);
1171                 /* program the IOC to enable interrupt
1172                  * only when the whole fragment is processed
1173                  */
1174                 size -= chunk;
1175                 bdl[3] = (size || !with_ioc) ? 0 : cpu_to_le32(0x01);
1176                 bdl += 4;
1177                 azx_dev->frags++;
1178                 ofs += chunk;
1179         }
1180         *bdlp = bdl;
1181         return ofs;
1182 }
1183
1184 /*
1185  * set up BDL entries
1186  */
1187 static int azx_setup_periods(struct azx *chip,
1188                              struct snd_pcm_substream *substream,
1189                              struct azx_dev *azx_dev)
1190 {
1191         u32 *bdl;
1192         int i, ofs, periods, period_bytes;
1193         int pos_adj;
1194
1195         /* reset BDL address */
1196         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1197         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1198
1199         period_bytes = azx_dev->period_bytes;
1200         periods = azx_dev->bufsize / period_bytes;
1201
1202         /* program the initial BDL entries */
1203         bdl = (u32 *)azx_dev->bdl.area;
1204         ofs = 0;
1205         azx_dev->frags = 0;
1206         pos_adj = bdl_pos_adj[chip->dev_index];
1207         if (pos_adj > 0) {
1208                 struct snd_pcm_runtime *runtime = substream->runtime;
1209                 int pos_align = pos_adj;
1210                 pos_adj = (pos_adj * runtime->rate + 47999) / 48000;
1211                 if (!pos_adj)
1212                         pos_adj = pos_align;
1213                 else
1214                         pos_adj = ((pos_adj + pos_align - 1) / pos_align) *
1215                                 pos_align;
1216                 pos_adj = frames_to_bytes(runtime, pos_adj);
1217                 if (pos_adj >= period_bytes) {
1218                         snd_printk(KERN_WARNING SFX "Too big adjustment %d\n",
1219                                    bdl_pos_adj[chip->dev_index]);
1220                         pos_adj = 0;
1221                 } else {
1222                         ofs = setup_bdle(substream, azx_dev,
1223                                          &bdl, ofs, pos_adj, 1);
1224                         if (ofs < 0)
1225                                 goto error;
1226                 }
1227         } else
1228                 pos_adj = 0;
1229         for (i = 0; i < periods; i++) {
1230                 if (i == periods - 1 && pos_adj)
1231                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1232                                          period_bytes - pos_adj, 0);
1233                 else
1234                         ofs = setup_bdle(substream, azx_dev, &bdl, ofs,
1235                                          period_bytes, 1);
1236                 if (ofs < 0)
1237                         goto error;
1238         }
1239         return 0;
1240
1241  error:
1242         snd_printk(KERN_ERR SFX "Too many BDL entries: buffer=%d, period=%d\n",
1243                    azx_dev->bufsize, period_bytes);
1244         return -EINVAL;
1245 }
1246
1247 /* reset stream */
1248 static void azx_stream_reset(struct azx *chip, struct azx_dev *azx_dev)
1249 {
1250         unsigned char val;
1251         int timeout;
1252
1253         azx_stream_clear(chip, azx_dev);
1254
1255         azx_sd_writeb(azx_dev, SD_CTL, azx_sd_readb(azx_dev, SD_CTL) |
1256                       SD_CTL_STREAM_RESET);
1257         udelay(3);
1258         timeout = 300;
1259         while (!((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1260                --timeout)
1261                 ;
1262         val &= ~SD_CTL_STREAM_RESET;
1263         azx_sd_writeb(azx_dev, SD_CTL, val);
1264         udelay(3);
1265
1266         timeout = 300;
1267         /* waiting for hardware to report that the stream is out of reset */
1268         while (((val = azx_sd_readb(azx_dev, SD_CTL)) & SD_CTL_STREAM_RESET) &&
1269                --timeout)
1270                 ;
1271
1272         /* reset first position - may not be synced with hw at this time */
1273         *azx_dev->posbuf = 0;
1274 }
1275
1276 /*
1277  * set up the SD for streaming
1278  */
1279 static int azx_setup_controller(struct azx *chip, struct azx_dev *azx_dev)
1280 {
1281         /* make sure the run bit is zero for SD */
1282         azx_stream_clear(chip, azx_dev);
1283         /* program the stream_tag */
1284         azx_sd_writel(azx_dev, SD_CTL,
1285                       (azx_sd_readl(azx_dev, SD_CTL) & ~SD_CTL_STREAM_TAG_MASK)|
1286                       (azx_dev->stream_tag << SD_CTL_STREAM_TAG_SHIFT));
1287
1288         /* program the length of samples in cyclic buffer */
1289         azx_sd_writel(azx_dev, SD_CBL, azx_dev->bufsize);
1290
1291         /* program the stream format */
1292         /* this value needs to be the same as the one programmed */
1293         azx_sd_writew(azx_dev, SD_FORMAT, azx_dev->format_val);
1294
1295         /* program the stream LVI (last valid index) of the BDL */
1296         azx_sd_writew(azx_dev, SD_LVI, azx_dev->frags - 1);
1297
1298         /* program the BDL address */
1299         /* lower BDL address */
1300         azx_sd_writel(azx_dev, SD_BDLPL, (u32)azx_dev->bdl.addr);
1301         /* upper BDL address */
1302         azx_sd_writel(azx_dev, SD_BDLPU, upper_32_bits(azx_dev->bdl.addr));
1303
1304         /* enable the position buffer */
1305         if (chip->position_fix == POS_FIX_POSBUF ||
1306             chip->position_fix == POS_FIX_AUTO ||
1307             chip->via_dmapos_patch) {
1308                 if (!(azx_readl(chip, DPLBASE) & ICH6_DPLBASE_ENABLE))
1309                         azx_writel(chip, DPLBASE,
1310                                 (u32)chip->posbuf.addr | ICH6_DPLBASE_ENABLE);
1311         }
1312
1313         /* set the interrupt enable bits in the descriptor control register */
1314         azx_sd_writel(azx_dev, SD_CTL,
1315                       azx_sd_readl(azx_dev, SD_CTL) | SD_INT_MASK);
1316
1317         return 0;
1318 }
1319
1320 /*
1321  * Probe the given codec address
1322  */
1323 static int probe_codec(struct azx *chip, int addr)
1324 {
1325         unsigned int cmd = (addr << 28) | (AC_NODE_ROOT << 20) |
1326                 (AC_VERB_PARAMETERS << 8) | AC_PAR_VENDOR_ID;
1327         unsigned int res;
1328
1329         mutex_lock(&chip->bus->cmd_mutex);
1330         chip->probing = 1;
1331         azx_send_cmd(chip->bus, cmd);
1332         res = azx_get_response(chip->bus, addr);
1333         chip->probing = 0;
1334         mutex_unlock(&chip->bus->cmd_mutex);
1335         if (res == -1)
1336                 return -EIO;
1337         snd_printdd(SFX "codec #%d probed OK\n", addr);
1338         return 0;
1339 }
1340
1341 static int azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1342                                  struct hda_pcm *cpcm);
1343 static void azx_stop_chip(struct azx *chip);
1344
1345 static void azx_bus_reset(struct hda_bus *bus)
1346 {
1347         struct azx *chip = bus->private_data;
1348
1349         bus->in_reset = 1;
1350         azx_stop_chip(chip);
1351         azx_init_chip(chip);
1352 #ifdef CONFIG_PM
1353         if (chip->initialized) {
1354                 int i;
1355
1356                 for (i = 0; i < HDA_MAX_PCMS; i++)
1357                         snd_pcm_suspend_all(chip->pcm[i]);
1358                 snd_hda_suspend(chip->bus);
1359                 snd_hda_resume(chip->bus);
1360         }
1361 #endif
1362         bus->in_reset = 0;
1363 }
1364
1365 /*
1366  * Codec initialization
1367  */
1368
1369 /* number of codec slots for each chipset: 0 = default slots (i.e. 4) */
1370 static unsigned int azx_max_codecs[AZX_NUM_DRIVERS] __devinitdata = {
1371         [AZX_DRIVER_NVIDIA] = 8,
1372         [AZX_DRIVER_TERA] = 1,
1373 };
1374
1375 static int __devinit azx_codec_create(struct azx *chip, const char *model)
1376 {
1377         struct hda_bus_template bus_temp;
1378         int c, codecs, err;
1379         int max_slots;
1380
1381         memset(&bus_temp, 0, sizeof(bus_temp));
1382         bus_temp.private_data = chip;
1383         bus_temp.modelname = model;
1384         bus_temp.pci = chip->pci;
1385         bus_temp.ops.command = azx_send_cmd;
1386         bus_temp.ops.get_response = azx_get_response;
1387         bus_temp.ops.attach_pcm = azx_attach_pcm_stream;
1388         bus_temp.ops.bus_reset = azx_bus_reset;
1389 #ifdef CONFIG_SND_HDA_POWER_SAVE
1390         bus_temp.power_save = &power_save;
1391         bus_temp.ops.pm_notify = azx_power_notify;
1392 #endif
1393
1394         err = snd_hda_bus_new(chip->card, &bus_temp, &chip->bus);
1395         if (err < 0)
1396                 return err;
1397
1398         if (chip->driver_type == AZX_DRIVER_NVIDIA)
1399                 chip->bus->needs_damn_long_delay = 1;
1400
1401         codecs = 0;
1402         max_slots = azx_max_codecs[chip->driver_type];
1403         if (!max_slots)
1404                 max_slots = AZX_DEFAULT_CODECS;
1405
1406         /* First try to probe all given codec slots */
1407         for (c = 0; c < max_slots; c++) {
1408                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1409                         if (probe_codec(chip, c) < 0) {
1410                                 /* Some BIOSen give you wrong codec addresses
1411                                  * that don't exist
1412                                  */
1413                                 snd_printk(KERN_WARNING SFX
1414                                            "Codec #%d probe error; "
1415                                            "disabling it...\n", c);
1416                                 chip->codec_mask &= ~(1 << c);
1417                                 /* More badly, accessing to a non-existing
1418                                  * codec often screws up the controller chip,
1419                                  * and disturbs the further communications.
1420                                  * Thus if an error occurs during probing,
1421                                  * better to reset the controller chip to
1422                                  * get back to the sanity state.
1423                                  */
1424                                 azx_stop_chip(chip);
1425                                 azx_init_chip(chip);
1426                         }
1427                 }
1428         }
1429
1430         /* Then create codec instances */
1431         for (c = 0; c < max_slots; c++) {
1432                 if ((chip->codec_mask & (1 << c)) & chip->codec_probe_mask) {
1433                         struct hda_codec *codec;
1434                         err = snd_hda_codec_new(chip->bus, c, &codec);
1435                         if (err < 0)
1436                                 continue;
1437                         codec->beep_mode = chip->beep_mode;
1438                         codecs++;
1439                 }
1440         }
1441         if (!codecs) {
1442                 snd_printk(KERN_ERR SFX "no codecs initialized\n");
1443                 return -ENXIO;
1444         }
1445         return 0;
1446 }
1447
1448 /* configure each codec instance */
1449 static int __devinit azx_codec_configure(struct azx *chip)
1450 {
1451         struct hda_codec *codec;
1452         list_for_each_entry(codec, &chip->bus->codec_list, list) {
1453                 snd_hda_codec_configure(codec);
1454         }
1455         return 0;
1456 }
1457
1458
1459 /*
1460  * PCM support
1461  */
1462
1463 /* assign a stream for the PCM */
1464 static inline struct azx_dev *
1465 azx_assign_device(struct azx *chip, struct snd_pcm_substream *substream)
1466 {
1467         int dev, i, nums;
1468         struct azx_dev *res = NULL;
1469
1470         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1471                 dev = chip->playback_index_offset;
1472                 nums = chip->playback_streams;
1473         } else {
1474                 dev = chip->capture_index_offset;
1475                 nums = chip->capture_streams;
1476         }
1477         for (i = 0; i < nums; i++, dev++)
1478                 if (!chip->azx_dev[dev].opened) {
1479                         res = &chip->azx_dev[dev];
1480                         if (res->device == substream->pcm->device)
1481                                 break;
1482                 }
1483         if (res) {
1484                 res->opened = 1;
1485                 res->device = substream->pcm->device;
1486         }
1487         return res;
1488 }
1489
1490 /* release the assigned stream */
1491 static inline void azx_release_device(struct azx_dev *azx_dev)
1492 {
1493         azx_dev->opened = 0;
1494 }
1495
1496 static struct snd_pcm_hardware azx_pcm_hw = {
1497         .info =                 (SNDRV_PCM_INFO_MMAP |
1498                                  SNDRV_PCM_INFO_INTERLEAVED |
1499                                  SNDRV_PCM_INFO_BLOCK_TRANSFER |
1500                                  SNDRV_PCM_INFO_MMAP_VALID |
1501                                  /* No full-resume yet implemented */
1502                                  /* SNDRV_PCM_INFO_RESUME |*/
1503                                  SNDRV_PCM_INFO_PAUSE |
1504                                  SNDRV_PCM_INFO_SYNC_START),
1505         .formats =              SNDRV_PCM_FMTBIT_S16_LE,
1506         .rates =                SNDRV_PCM_RATE_48000,
1507         .rate_min =             48000,
1508         .rate_max =             48000,
1509         .channels_min =         2,
1510         .channels_max =         2,
1511         .buffer_bytes_max =     AZX_MAX_BUF_SIZE,
1512         .period_bytes_min =     128,
1513         .period_bytes_max =     AZX_MAX_BUF_SIZE / 2,
1514         .periods_min =          2,
1515         .periods_max =          AZX_MAX_FRAG,
1516         .fifo_size =            0,
1517 };
1518
1519 struct azx_pcm {
1520         struct azx *chip;
1521         struct hda_codec *codec;
1522         struct hda_pcm_stream *hinfo[2];
1523 };
1524
1525 static int azx_pcm_open(struct snd_pcm_substream *substream)
1526 {
1527         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1528         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1529         struct azx *chip = apcm->chip;
1530         struct azx_dev *azx_dev;
1531         struct snd_pcm_runtime *runtime = substream->runtime;
1532         unsigned long flags;
1533         int err;
1534
1535         mutex_lock(&chip->open_mutex);
1536         azx_dev = azx_assign_device(chip, substream);
1537         if (azx_dev == NULL) {
1538                 mutex_unlock(&chip->open_mutex);
1539                 return -EBUSY;
1540         }
1541         runtime->hw = azx_pcm_hw;
1542         runtime->hw.channels_min = hinfo->channels_min;
1543         runtime->hw.channels_max = hinfo->channels_max;
1544         runtime->hw.formats = hinfo->formats;
1545         runtime->hw.rates = hinfo->rates;
1546         snd_pcm_limit_hw_rates(runtime);
1547         snd_pcm_hw_constraint_integer(runtime, SNDRV_PCM_HW_PARAM_PERIODS);
1548         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_BUFFER_BYTES,
1549                                    128);
1550         snd_pcm_hw_constraint_step(runtime, 0, SNDRV_PCM_HW_PARAM_PERIOD_BYTES,
1551                                    128);
1552         snd_hda_power_up(apcm->codec);
1553         err = hinfo->ops.open(hinfo, apcm->codec, substream);
1554         if (err < 0) {
1555                 azx_release_device(azx_dev);
1556                 snd_hda_power_down(apcm->codec);
1557                 mutex_unlock(&chip->open_mutex);
1558                 return err;
1559         }
1560         snd_pcm_limit_hw_rates(runtime);
1561         /* sanity check */
1562         if (snd_BUG_ON(!runtime->hw.channels_min) ||
1563             snd_BUG_ON(!runtime->hw.channels_max) ||
1564             snd_BUG_ON(!runtime->hw.formats) ||
1565             snd_BUG_ON(!runtime->hw.rates)) {
1566                 azx_release_device(azx_dev);
1567                 hinfo->ops.close(hinfo, apcm->codec, substream);
1568                 snd_hda_power_down(apcm->codec);
1569                 mutex_unlock(&chip->open_mutex);
1570                 return -EINVAL;
1571         }
1572         spin_lock_irqsave(&chip->reg_lock, flags);
1573         azx_dev->substream = substream;
1574         azx_dev->running = 0;
1575         spin_unlock_irqrestore(&chip->reg_lock, flags);
1576
1577         runtime->private_data = azx_dev;
1578         snd_pcm_set_sync(substream);
1579         mutex_unlock(&chip->open_mutex);
1580         return 0;
1581 }
1582
1583 static int azx_pcm_close(struct snd_pcm_substream *substream)
1584 {
1585         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1586         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1587         struct azx *chip = apcm->chip;
1588         struct azx_dev *azx_dev = get_azx_dev(substream);
1589         unsigned long flags;
1590
1591         mutex_lock(&chip->open_mutex);
1592         spin_lock_irqsave(&chip->reg_lock, flags);
1593         azx_dev->substream = NULL;
1594         azx_dev->running = 0;
1595         spin_unlock_irqrestore(&chip->reg_lock, flags);
1596         azx_release_device(azx_dev);
1597         hinfo->ops.close(hinfo, apcm->codec, substream);
1598         snd_hda_power_down(apcm->codec);
1599         mutex_unlock(&chip->open_mutex);
1600         return 0;
1601 }
1602
1603 static int azx_pcm_hw_params(struct snd_pcm_substream *substream,
1604                              struct snd_pcm_hw_params *hw_params)
1605 {
1606         struct azx_dev *azx_dev = get_azx_dev(substream);
1607
1608         azx_dev->bufsize = 0;
1609         azx_dev->period_bytes = 0;
1610         azx_dev->format_val = 0;
1611         return snd_pcm_lib_malloc_pages(substream,
1612                                         params_buffer_bytes(hw_params));
1613 }
1614
1615 static int azx_pcm_hw_free(struct snd_pcm_substream *substream)
1616 {
1617         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1618         struct azx_dev *azx_dev = get_azx_dev(substream);
1619         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1620
1621         /* reset BDL address */
1622         azx_sd_writel(azx_dev, SD_BDLPL, 0);
1623         azx_sd_writel(azx_dev, SD_BDLPU, 0);
1624         azx_sd_writel(azx_dev, SD_CTL, 0);
1625         azx_dev->bufsize = 0;
1626         azx_dev->period_bytes = 0;
1627         azx_dev->format_val = 0;
1628
1629         hinfo->ops.cleanup(hinfo, apcm->codec, substream);
1630
1631         return snd_pcm_lib_free_pages(substream);
1632 }
1633
1634 static int azx_pcm_prepare(struct snd_pcm_substream *substream)
1635 {
1636         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1637         struct azx *chip = apcm->chip;
1638         struct azx_dev *azx_dev = get_azx_dev(substream);
1639         struct hda_pcm_stream *hinfo = apcm->hinfo[substream->stream];
1640         struct snd_pcm_runtime *runtime = substream->runtime;
1641         unsigned int bufsize, period_bytes, format_val;
1642         int err;
1643
1644         azx_stream_reset(chip, azx_dev);
1645         format_val = snd_hda_calc_stream_format(runtime->rate,
1646                                                 runtime->channels,
1647                                                 runtime->format,
1648                                                 hinfo->maxbps);
1649         if (!format_val) {
1650                 snd_printk(KERN_ERR SFX
1651                            "invalid format_val, rate=%d, ch=%d, format=%d\n",
1652                            runtime->rate, runtime->channels, runtime->format);
1653                 return -EINVAL;
1654         }
1655
1656         bufsize = snd_pcm_lib_buffer_bytes(substream);
1657         period_bytes = snd_pcm_lib_period_bytes(substream);
1658
1659         snd_printdd(SFX "azx_pcm_prepare: bufsize=0x%x, format=0x%x\n",
1660                     bufsize, format_val);
1661
1662         if (bufsize != azx_dev->bufsize ||
1663             period_bytes != azx_dev->period_bytes ||
1664             format_val != azx_dev->format_val) {
1665                 azx_dev->bufsize = bufsize;
1666                 azx_dev->period_bytes = period_bytes;
1667                 azx_dev->format_val = format_val;
1668                 err = azx_setup_periods(chip, substream, azx_dev);
1669                 if (err < 0)
1670                         return err;
1671         }
1672
1673         azx_dev->min_jiffies = (runtime->period_size * HZ) /
1674                                                 (runtime->rate * 2);
1675         azx_setup_controller(chip, azx_dev);
1676         if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK)
1677                 azx_dev->fifo_size = azx_sd_readw(azx_dev, SD_FIFOSIZE) + 1;
1678         else
1679                 azx_dev->fifo_size = 0;
1680
1681         return hinfo->ops.prepare(hinfo, apcm->codec, azx_dev->stream_tag,
1682                                   azx_dev->format_val, substream);
1683 }
1684
1685 static int azx_pcm_trigger(struct snd_pcm_substream *substream, int cmd)
1686 {
1687         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1688         struct azx *chip = apcm->chip;
1689         struct azx_dev *azx_dev;
1690         struct snd_pcm_substream *s;
1691         int rstart = 0, start, nsync = 0, sbits = 0;
1692         int nwait, timeout;
1693
1694         switch (cmd) {
1695         case SNDRV_PCM_TRIGGER_START:
1696                 rstart = 1;
1697         case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
1698         case SNDRV_PCM_TRIGGER_RESUME:
1699                 start = 1;
1700                 break;
1701         case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
1702         case SNDRV_PCM_TRIGGER_SUSPEND:
1703         case SNDRV_PCM_TRIGGER_STOP:
1704                 start = 0;
1705                 break;
1706         default:
1707                 return -EINVAL;
1708         }
1709
1710         snd_pcm_group_for_each_entry(s, substream) {
1711                 if (s->pcm->card != substream->pcm->card)
1712                         continue;
1713                 azx_dev = get_azx_dev(s);
1714                 sbits |= 1 << azx_dev->index;
1715                 nsync++;
1716                 snd_pcm_trigger_done(s, substream);
1717         }
1718
1719         spin_lock(&chip->reg_lock);
1720         if (nsync > 1) {
1721                 /* first, set SYNC bits of corresponding streams */
1722                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) | sbits);
1723         }
1724         snd_pcm_group_for_each_entry(s, substream) {
1725                 if (s->pcm->card != substream->pcm->card)
1726                         continue;
1727                 azx_dev = get_azx_dev(s);
1728                 if (rstart) {
1729                         azx_dev->start_flag = 1;
1730                         azx_dev->start_jiffies = jiffies + azx_dev->min_jiffies;
1731                 }
1732                 if (start)
1733                         azx_stream_start(chip, azx_dev);
1734                 else
1735                         azx_stream_stop(chip, azx_dev);
1736                 azx_dev->running = start;
1737         }
1738         spin_unlock(&chip->reg_lock);
1739         if (start) {
1740                 if (nsync == 1)
1741                         return 0;
1742                 /* wait until all FIFOs get ready */
1743                 for (timeout = 5000; timeout; timeout--) {
1744                         nwait = 0;
1745                         snd_pcm_group_for_each_entry(s, substream) {
1746                                 if (s->pcm->card != substream->pcm->card)
1747                                         continue;
1748                                 azx_dev = get_azx_dev(s);
1749                                 if (!(azx_sd_readb(azx_dev, SD_STS) &
1750                                       SD_STS_FIFO_READY))
1751                                         nwait++;
1752                         }
1753                         if (!nwait)
1754                                 break;
1755                         cpu_relax();
1756                 }
1757         } else {
1758                 /* wait until all RUN bits are cleared */
1759                 for (timeout = 5000; timeout; timeout--) {
1760                         nwait = 0;
1761                         snd_pcm_group_for_each_entry(s, substream) {
1762                                 if (s->pcm->card != substream->pcm->card)
1763                                         continue;
1764                                 azx_dev = get_azx_dev(s);
1765                                 if (azx_sd_readb(azx_dev, SD_CTL) &
1766                                     SD_CTL_DMA_START)
1767                                         nwait++;
1768                         }
1769                         if (!nwait)
1770                                 break;
1771                         cpu_relax();
1772                 }
1773         }
1774         if (nsync > 1) {
1775                 spin_lock(&chip->reg_lock);
1776                 /* reset SYNC bits */
1777                 azx_writel(chip, SYNC, azx_readl(chip, SYNC) & ~sbits);
1778                 spin_unlock(&chip->reg_lock);
1779         }
1780         return 0;
1781 }
1782
1783 /* get the current DMA position with correction on VIA chips */
1784 static unsigned int azx_via_get_position(struct azx *chip,
1785                                          struct azx_dev *azx_dev)
1786 {
1787         unsigned int link_pos, mini_pos, bound_pos;
1788         unsigned int mod_link_pos, mod_dma_pos, mod_mini_pos;
1789         unsigned int fifo_size;
1790
1791         link_pos = azx_sd_readl(azx_dev, SD_LPIB);
1792         if (azx_dev->index >= 4) {
1793                 /* Playback, no problem using link position */
1794                 return link_pos;
1795         }
1796
1797         /* Capture */
1798         /* For new chipset,
1799          * use mod to get the DMA position just like old chipset
1800          */
1801         mod_dma_pos = le32_to_cpu(*azx_dev->posbuf);
1802         mod_dma_pos %= azx_dev->period_bytes;
1803
1804         /* azx_dev->fifo_size can't get FIFO size of in stream.
1805          * Get from base address + offset.
1806          */
1807         fifo_size = readw(chip->remap_addr + VIA_IN_STREAM0_FIFO_SIZE_OFFSET);
1808
1809         if (azx_dev->insufficient) {
1810                 /* Link position never gather than FIFO size */
1811                 if (link_pos <= fifo_size)
1812                         return 0;
1813
1814                 azx_dev->insufficient = 0;
1815         }
1816
1817         if (link_pos <= fifo_size)
1818                 mini_pos = azx_dev->bufsize + link_pos - fifo_size;
1819         else
1820                 mini_pos = link_pos - fifo_size;
1821
1822         /* Find nearest previous boudary */
1823         mod_mini_pos = mini_pos % azx_dev->period_bytes;
1824         mod_link_pos = link_pos % azx_dev->period_bytes;
1825         if (mod_link_pos >= fifo_size)
1826                 bound_pos = link_pos - mod_link_pos;
1827         else if (mod_dma_pos >= mod_mini_pos)
1828                 bound_pos = mini_pos - mod_mini_pos;
1829         else {
1830                 bound_pos = mini_pos - mod_mini_pos + azx_dev->period_bytes;
1831                 if (bound_pos >= azx_dev->bufsize)
1832                         bound_pos = 0;
1833         }
1834
1835         /* Calculate real DMA position we want */
1836         return bound_pos + mod_dma_pos;
1837 }
1838
1839 static unsigned int azx_get_position(struct azx *chip,
1840                                      struct azx_dev *azx_dev)
1841 {
1842         unsigned int pos;
1843
1844         if (chip->via_dmapos_patch)
1845                 pos = azx_via_get_position(chip, azx_dev);
1846         else if (chip->position_fix == POS_FIX_POSBUF ||
1847                  chip->position_fix == POS_FIX_AUTO) {
1848                 /* use the position buffer */
1849                 pos = le32_to_cpu(*azx_dev->posbuf);
1850         } else {
1851                 /* read LPIB */
1852                 pos = azx_sd_readl(azx_dev, SD_LPIB);
1853         }
1854         if (pos >= azx_dev->bufsize)
1855                 pos = 0;
1856         return pos;
1857 }
1858
1859 static snd_pcm_uframes_t azx_pcm_pointer(struct snd_pcm_substream *substream)
1860 {
1861         struct azx_pcm *apcm = snd_pcm_substream_chip(substream);
1862         struct azx *chip = apcm->chip;
1863         struct azx_dev *azx_dev = get_azx_dev(substream);
1864         return bytes_to_frames(substream->runtime,
1865                                azx_get_position(chip, azx_dev));
1866 }
1867
1868 /*
1869  * Check whether the current DMA position is acceptable for updating
1870  * periods.  Returns non-zero if it's OK.
1871  *
1872  * Many HD-audio controllers appear pretty inaccurate about
1873  * the update-IRQ timing.  The IRQ is issued before actually the
1874  * data is processed.  So, we need to process it afterwords in a
1875  * workqueue.
1876  */
1877 static int azx_position_ok(struct azx *chip, struct azx_dev *azx_dev)
1878 {
1879         unsigned int pos;
1880
1881         if (azx_dev->start_flag &&
1882             time_before_eq(jiffies, azx_dev->start_jiffies))
1883                 return -1;      /* bogus (too early) interrupt */
1884         azx_dev->start_flag = 0;
1885
1886         pos = azx_get_position(chip, azx_dev);
1887         if (chip->position_fix == POS_FIX_AUTO) {
1888                 if (!pos) {
1889                         printk(KERN_WARNING
1890                                "hda-intel: Invalid position buffer, "
1891                                "using LPIB read method instead.\n");
1892                         chip->position_fix = POS_FIX_LPIB;
1893                         pos = azx_get_position(chip, azx_dev);
1894                 } else
1895                         chip->position_fix = POS_FIX_POSBUF;
1896         }
1897
1898         if (!bdl_pos_adj[chip->dev_index])
1899                 return 1; /* no delayed ack */
1900         if (WARN_ONCE(!azx_dev->period_bytes,
1901                       "hda-intel: zero azx_dev->period_bytes"))
1902                 return 0; /* this shouldn't happen! */
1903         if (pos % azx_dev->period_bytes > azx_dev->period_bytes / 2)
1904                 return 0; /* NG - it's below the period boundary */
1905         return 1; /* OK, it's fine */
1906 }
1907
1908 /*
1909  * The work for pending PCM period updates.
1910  */
1911 static void azx_irq_pending_work(struct work_struct *work)
1912 {
1913         struct azx *chip = container_of(work, struct azx, irq_pending_work);
1914         int i, pending;
1915
1916         if (!chip->irq_pending_warned) {
1917                 printk(KERN_WARNING
1918                        "hda-intel: IRQ timing workaround is activated "
1919                        "for card #%d. Suggest a bigger bdl_pos_adj.\n",
1920                        chip->card->number);
1921                 chip->irq_pending_warned = 1;
1922         }
1923
1924         for (;;) {
1925                 pending = 0;
1926                 spin_lock_irq(&chip->reg_lock);
1927                 for (i = 0; i < chip->num_streams; i++) {
1928                         struct azx_dev *azx_dev = &chip->azx_dev[i];
1929                         if (!azx_dev->irq_pending ||
1930                             !azx_dev->substream ||
1931                             !azx_dev->running)
1932                                 continue;
1933                         if (azx_position_ok(chip, azx_dev)) {
1934                                 azx_dev->irq_pending = 0;
1935                                 spin_unlock(&chip->reg_lock);
1936                                 snd_pcm_period_elapsed(azx_dev->substream);
1937                                 spin_lock(&chip->reg_lock);
1938                         } else
1939                                 pending++;
1940                 }
1941                 spin_unlock_irq(&chip->reg_lock);
1942                 if (!pending)
1943                         return;
1944                 cond_resched();
1945         }
1946 }
1947
1948 /* clear irq_pending flags and assure no on-going workq */
1949 static void azx_clear_irq_pending(struct azx *chip)
1950 {
1951         int i;
1952
1953         spin_lock_irq(&chip->reg_lock);
1954         for (i = 0; i < chip->num_streams; i++)
1955                 chip->azx_dev[i].irq_pending = 0;
1956         spin_unlock_irq(&chip->reg_lock);
1957 }
1958
1959 static struct snd_pcm_ops azx_pcm_ops = {
1960         .open = azx_pcm_open,
1961         .close = azx_pcm_close,
1962         .ioctl = snd_pcm_lib_ioctl,
1963         .hw_params = azx_pcm_hw_params,
1964         .hw_free = azx_pcm_hw_free,
1965         .prepare = azx_pcm_prepare,
1966         .trigger = azx_pcm_trigger,
1967         .pointer = azx_pcm_pointer,
1968         .page = snd_pcm_sgbuf_ops_page,
1969 };
1970
1971 static void azx_pcm_free(struct snd_pcm *pcm)
1972 {
1973         struct azx_pcm *apcm = pcm->private_data;
1974         if (apcm) {
1975                 apcm->chip->pcm[pcm->device] = NULL;
1976                 kfree(apcm);
1977         }
1978 }
1979
1980 static int
1981 azx_attach_pcm_stream(struct hda_bus *bus, struct hda_codec *codec,
1982                       struct hda_pcm *cpcm)
1983 {
1984         struct azx *chip = bus->private_data;
1985         struct snd_pcm *pcm;
1986         struct azx_pcm *apcm;
1987         int pcm_dev = cpcm->device;
1988         int s, err;
1989
1990         if (pcm_dev >= HDA_MAX_PCMS) {
1991                 snd_printk(KERN_ERR SFX "Invalid PCM device number %d\n",
1992                            pcm_dev);
1993                 return -EINVAL;
1994         }
1995         if (chip->pcm[pcm_dev]) {
1996                 snd_printk(KERN_ERR SFX "PCM %d already exists\n", pcm_dev);
1997                 return -EBUSY;
1998         }
1999         err = snd_pcm_new(chip->card, cpcm->name, pcm_dev,
2000                           cpcm->stream[SNDRV_PCM_STREAM_PLAYBACK].substreams,
2001                           cpcm->stream[SNDRV_PCM_STREAM_CAPTURE].substreams,
2002                           &pcm);
2003         if (err < 0)
2004                 return err;
2005         strlcpy(pcm->name, cpcm->name, sizeof(pcm->name));
2006         apcm = kzalloc(sizeof(*apcm), GFP_KERNEL);
2007         if (apcm == NULL)
2008                 return -ENOMEM;
2009         apcm->chip = chip;
2010         apcm->codec = codec;
2011         pcm->private_data = apcm;
2012         pcm->private_free = azx_pcm_free;
2013         if (cpcm->pcm_type == HDA_PCM_TYPE_MODEM)
2014                 pcm->dev_class = SNDRV_PCM_CLASS_MODEM;
2015         chip->pcm[pcm_dev] = pcm;
2016         cpcm->pcm = pcm;
2017         for (s = 0; s < 2; s++) {
2018                 apcm->hinfo[s] = &cpcm->stream[s];
2019                 if (cpcm->stream[s].substreams)
2020                         snd_pcm_set_ops(pcm, s, &azx_pcm_ops);
2021         }
2022         /* buffer pre-allocation */
2023         snd_pcm_lib_preallocate_pages_for_all(pcm, SNDRV_DMA_TYPE_DEV_SG,
2024                                               snd_dma_pci_data(chip->pci),
2025                                               1024 * 64, 32 * 1024 * 1024);
2026         return 0;
2027 }
2028
2029 /*
2030  * mixer creation - all stuff is implemented in hda module
2031  */
2032 static int __devinit azx_mixer_create(struct azx *chip)
2033 {
2034         return snd_hda_build_controls(chip->bus);
2035 }
2036
2037
2038 /*
2039  * initialize SD streams
2040  */
2041 static int __devinit azx_init_stream(struct azx *chip)
2042 {
2043         int i;
2044
2045         /* initialize each stream (aka device)
2046          * assign the starting bdl address to each stream (device)
2047          * and initialize
2048          */
2049         for (i = 0; i < chip->num_streams; i++) {
2050                 struct azx_dev *azx_dev = &chip->azx_dev[i];
2051                 azx_dev->posbuf = (u32 __iomem *)(chip->posbuf.area + i * 8);
2052                 /* offset: SDI0=0x80, SDI1=0xa0, ... SDO3=0x160 */
2053                 azx_dev->sd_addr = chip->remap_addr + (0x20 * i + 0x80);
2054                 /* int mask: SDI0=0x01, SDI1=0x02, ... SDO3=0x80 */
2055                 azx_dev->sd_int_sta_mask = 1 << i;
2056                 /* stream tag: must be non-zero and unique */
2057                 azx_dev->index = i;
2058                 azx_dev->stream_tag = i + 1;
2059         }
2060
2061         return 0;
2062 }
2063
2064 static int azx_acquire_irq(struct azx *chip, int do_disconnect)
2065 {
2066         if (request_irq(chip->pci->irq, azx_interrupt,
2067                         chip->msi ? 0 : IRQF_SHARED,
2068                         "hda_intel", chip)) {
2069                 printk(KERN_ERR "hda-intel: unable to grab IRQ %d, "
2070                        "disabling device\n", chip->pci->irq);
2071                 if (do_disconnect)
2072                         snd_card_disconnect(chip->card);
2073                 return -1;
2074         }
2075         chip->irq = chip->pci->irq;
2076         pci_intx(chip->pci, !chip->msi);
2077         return 0;
2078 }
2079
2080
2081 static void azx_stop_chip(struct azx *chip)
2082 {
2083         if (!chip->initialized)
2084                 return;
2085
2086         /* disable interrupts */
2087         azx_int_disable(chip);
2088         azx_int_clear(chip);
2089
2090         /* disable CORB/RIRB */
2091         azx_free_cmd_io(chip);
2092
2093         /* disable position buffer */
2094         azx_writel(chip, DPLBASE, 0);
2095         azx_writel(chip, DPUBASE, 0);
2096
2097         chip->initialized = 0;
2098 }
2099
2100 #ifdef CONFIG_SND_HDA_POWER_SAVE
2101 /* power-up/down the controller */
2102 static void azx_power_notify(struct hda_bus *bus)
2103 {
2104         struct azx *chip = bus->private_data;
2105         struct hda_codec *c;
2106         int power_on = 0;
2107
2108         list_for_each_entry(c, &bus->codec_list, list) {
2109                 if (c->power_on) {
2110                         power_on = 1;
2111                         break;
2112                 }
2113         }
2114         if (power_on)
2115                 azx_init_chip(chip);
2116         else if (chip->running && power_save_controller &&
2117                  !bus->power_keep_link_on)
2118                 azx_stop_chip(chip);
2119 }
2120 #endif /* CONFIG_SND_HDA_POWER_SAVE */
2121
2122 #ifdef CONFIG_PM
2123 /*
2124  * power management
2125  */
2126
2127 static int snd_hda_codecs_inuse(struct hda_bus *bus)
2128 {
2129         struct hda_codec *codec;
2130
2131         list_for_each_entry(codec, &bus->codec_list, list) {
2132                 if (snd_hda_codec_needs_resume(codec))
2133                         return 1;
2134         }
2135         return 0;
2136 }
2137
2138 static int azx_suspend(struct pci_dev *pci, pm_message_t state)
2139 {
2140         struct snd_card *card = pci_get_drvdata(pci);
2141         struct azx *chip = card->private_data;
2142         int i;
2143
2144         snd_power_change_state(card, SNDRV_CTL_POWER_D3hot);
2145         azx_clear_irq_pending(chip);
2146         for (i = 0; i < HDA_MAX_PCMS; i++)
2147                 snd_pcm_suspend_all(chip->pcm[i]);
2148         if (chip->initialized)
2149                 snd_hda_suspend(chip->bus);
2150         azx_stop_chip(chip);
2151         if (chip->irq >= 0) {
2152                 free_irq(chip->irq, chip);
2153                 chip->irq = -1;
2154         }
2155         if (chip->msi)
2156                 pci_disable_msi(chip->pci);
2157         pci_disable_device(pci);
2158         pci_save_state(pci);
2159         pci_set_power_state(pci, pci_choose_state(pci, state));
2160         return 0;
2161 }
2162
2163 static int azx_resume(struct pci_dev *pci)
2164 {
2165         struct snd_card *card = pci_get_drvdata(pci);
2166         struct azx *chip = card->private_data;
2167
2168         pci_set_power_state(pci, PCI_D0);
2169         pci_restore_state(pci);
2170         if (pci_enable_device(pci) < 0) {
2171                 printk(KERN_ERR "hda-intel: pci_enable_device failed, "
2172                        "disabling device\n");
2173                 snd_card_disconnect(card);
2174                 return -EIO;
2175         }
2176         pci_set_master(pci);
2177         if (chip->msi)
2178                 if (pci_enable_msi(pci) < 0)
2179                         chip->msi = 0;
2180         if (azx_acquire_irq(chip, 1) < 0)
2181                 return -EIO;
2182         azx_init_pci(chip);
2183
2184         if (snd_hda_codecs_inuse(chip->bus))
2185                 azx_init_chip(chip);
2186
2187         snd_hda_resume(chip->bus);
2188         snd_power_change_state(card, SNDRV_CTL_POWER_D0);
2189         return 0;
2190 }
2191 #endif /* CONFIG_PM */
2192
2193
2194 /*
2195  * reboot notifier for hang-up problem at power-down
2196  */
2197 static int azx_halt(struct notifier_block *nb, unsigned long event, void *buf)
2198 {
2199         struct azx *chip = container_of(nb, struct azx, reboot_notifier);
2200         snd_hda_bus_reboot_notify(chip->bus);
2201         azx_stop_chip(chip);
2202         return NOTIFY_OK;
2203 }
2204
2205 static void azx_notifier_register(struct azx *chip)
2206 {
2207         chip->reboot_notifier.notifier_call = azx_halt;
2208         register_reboot_notifier(&chip->reboot_notifier);
2209 }
2210
2211 static void azx_notifier_unregister(struct azx *chip)
2212 {
2213         if (chip->reboot_notifier.notifier_call)
2214                 unregister_reboot_notifier(&chip->reboot_notifier);
2215 }
2216
2217 /*
2218  * destructor
2219  */
2220 static int azx_free(struct azx *chip)
2221 {
2222         int i;
2223
2224         azx_notifier_unregister(chip);
2225
2226         if (chip->initialized) {
2227                 azx_clear_irq_pending(chip);
2228                 for (i = 0; i < chip->num_streams; i++)
2229                         azx_stream_stop(chip, &chip->azx_dev[i]);
2230                 azx_stop_chip(chip);
2231         }
2232
2233         if (chip->irq >= 0)
2234                 free_irq(chip->irq, (void*)chip);
2235         if (chip->msi)
2236                 pci_disable_msi(chip->pci);
2237         if (chip->remap_addr)
2238                 iounmap(chip->remap_addr);
2239
2240         if (chip->azx_dev) {
2241                 for (i = 0; i < chip->num_streams; i++)
2242                         if (chip->azx_dev[i].bdl.area)
2243                                 snd_dma_free_pages(&chip->azx_dev[i].bdl);
2244         }
2245         if (chip->rb.area)
2246                 snd_dma_free_pages(&chip->rb);
2247         if (chip->posbuf.area)
2248                 snd_dma_free_pages(&chip->posbuf);
2249         pci_release_regions(chip->pci);
2250         pci_disable_device(chip->pci);
2251         kfree(chip->azx_dev);
2252         kfree(chip);
2253
2254         return 0;
2255 }
2256
2257 static int azx_dev_free(struct snd_device *device)
2258 {
2259         return azx_free(device->device_data);
2260 }
2261
2262 /*
2263  * white/black-listing for position_fix
2264  */
2265 static struct snd_pci_quirk position_fix_list[] __devinitdata = {
2266         SND_PCI_QUIRK(0x1028, 0x01cc, "Dell D820", POS_FIX_LPIB),
2267         SND_PCI_QUIRK(0x1028, 0x01de, "Dell Precision 390", POS_FIX_LPIB),
2268         SND_PCI_QUIRK(0x1028, 0x01f6, "Dell Latitude 131L", POS_FIX_LPIB),
2269         SND_PCI_QUIRK(0x103c, 0x306d, "HP dv3", POS_FIX_LPIB),
2270         SND_PCI_QUIRK(0x1106, 0x3288, "ASUS M2V-MX SE", POS_FIX_LPIB),
2271         SND_PCI_QUIRK(0x1043, 0x813d, "ASUS P5AD2", POS_FIX_LPIB),
2272         SND_PCI_QUIRK(0x1462, 0x1002, "MSI Wind U115", POS_FIX_LPIB),
2273         SND_PCI_QUIRK(0x1565, 0x820f, "Biostar Microtech", POS_FIX_LPIB),
2274         {}
2275 };
2276
2277 static int __devinit check_position_fix(struct azx *chip, int fix)
2278 {
2279         const struct snd_pci_quirk *q;
2280
2281         switch (fix) {
2282         case POS_FIX_LPIB:
2283         case POS_FIX_POSBUF:
2284                 return fix;
2285         }
2286
2287         /* Check VIA/ATI HD Audio Controller exist */
2288         switch (chip->driver_type) {
2289         case AZX_DRIVER_VIA:
2290         case AZX_DRIVER_ATI:
2291                 chip->via_dmapos_patch = 1;
2292                 /* Use link position directly, avoid any transfer problem. */
2293                 return POS_FIX_LPIB;
2294         }
2295         chip->via_dmapos_patch = 0;
2296
2297         q = snd_pci_quirk_lookup(chip->pci, position_fix_list);
2298         if (q) {
2299                 printk(KERN_INFO
2300                        "hda_intel: position_fix set to %d "
2301                        "for device %04x:%04x\n",
2302                        q->value, q->subvendor, q->subdevice);
2303                 return q->value;
2304         }
2305         return POS_FIX_AUTO;
2306 }
2307
2308 /*
2309  * black-lists for probe_mask
2310  */
2311 static struct snd_pci_quirk probe_mask_list[] __devinitdata = {
2312         /* Thinkpad often breaks the controller communication when accessing
2313          * to the non-working (or non-existing) modem codec slot.
2314          */
2315         SND_PCI_QUIRK(0x1014, 0x05b7, "Thinkpad Z60", 0x01),
2316         SND_PCI_QUIRK(0x17aa, 0x2010, "Thinkpad X/T/R60", 0x01),
2317         SND_PCI_QUIRK(0x17aa, 0x20ac, "Thinkpad X/T/R61", 0x01),
2318         /* broken BIOS */
2319         SND_PCI_QUIRK(0x1028, 0x20ac, "Dell Studio Desktop", 0x01),
2320         /* including bogus ALC268 in slot#2 that conflicts with ALC888 */
2321         SND_PCI_QUIRK(0x17c0, 0x4085, "Medion MD96630", 0x01),
2322         /* forced codec slots */
2323         SND_PCI_QUIRK(0x1043, 0x1262, "ASUS W5Fm", 0x103),
2324         SND_PCI_QUIRK(0x1046, 0x1262, "ASUS W5F", 0x103),
2325         {}
2326 };
2327
2328 #define AZX_FORCE_CODEC_MASK    0x100
2329
2330 static void __devinit check_probe_mask(struct azx *chip, int dev)
2331 {
2332         const struct snd_pci_quirk *q;
2333
2334         chip->codec_probe_mask = probe_mask[dev];
2335         if (chip->codec_probe_mask == -1) {
2336                 q = snd_pci_quirk_lookup(chip->pci, probe_mask_list);
2337                 if (q) {
2338                         printk(KERN_INFO
2339                                "hda_intel: probe_mask set to 0x%x "
2340                                "for device %04x:%04x\n",
2341                                q->value, q->subvendor, q->subdevice);
2342                         chip->codec_probe_mask = q->value;
2343                 }
2344         }
2345
2346         /* check forced option */
2347         if (chip->codec_probe_mask != -1 &&
2348             (chip->codec_probe_mask & AZX_FORCE_CODEC_MASK)) {
2349                 chip->codec_mask = chip->codec_probe_mask & 0xff;
2350                 printk(KERN_INFO "hda_intel: codec_mask forced to 0x%x\n",
2351                        chip->codec_mask);
2352         }
2353 }
2354
2355 /*
2356  * white/black-list for enable_msi
2357  */
2358 static struct snd_pci_quirk msi_black_list[] __devinitdata = {
2359         SND_PCI_QUIRK(0x1043, 0x81f2, "ASUS", 0), /* Athlon64 X2 + nvidia */
2360         SND_PCI_QUIRK(0x1043, 0x81f6, "ASUS", 0), /* nvidia */
2361         SND_PCI_QUIRK(0x1043, 0x822d, "ASUS", 0), /* Athlon64 X2 + nvidia MCP55 */
2362         SND_PCI_QUIRK(0x1849, 0x0888, "ASRock", 0), /* Athlon64 X2 + nvidia */
2363         {}
2364 };
2365
2366 static void __devinit check_msi(struct azx *chip)
2367 {
2368         const struct snd_pci_quirk *q;
2369
2370         if (enable_msi >= 0) {
2371                 chip->msi = !!enable_msi;
2372                 return;
2373         }
2374         chip->msi = 1;  /* enable MSI as default */
2375         q = snd_pci_quirk_lookup(chip->pci, msi_black_list);
2376         if (q) {
2377                 printk(KERN_INFO
2378                        "hda_intel: msi for device %04x:%04x set to %d\n",
2379                        q->subvendor, q->subdevice, q->value);
2380                 chip->msi = q->value;
2381         }
2382 }
2383
2384
2385 /*
2386  * constructor
2387  */
2388 static int __devinit azx_create(struct snd_card *card, struct pci_dev *pci,
2389                                 int dev, int driver_type,
2390                                 struct azx **rchip)
2391 {
2392         struct azx *chip;
2393         int i, err;
2394         unsigned short gcap;
2395         static struct snd_device_ops ops = {
2396                 .dev_free = azx_dev_free,
2397         };
2398
2399         *rchip = NULL;
2400
2401         err = pci_enable_device(pci);
2402         if (err < 0)
2403                 return err;
2404
2405         chip = kzalloc(sizeof(*chip), GFP_KERNEL);
2406         if (!chip) {
2407                 snd_printk(KERN_ERR SFX "cannot allocate chip\n");
2408                 pci_disable_device(pci);
2409                 return -ENOMEM;
2410         }
2411
2412         spin_lock_init(&chip->reg_lock);
2413         mutex_init(&chip->open_mutex);
2414         chip->card = card;
2415         chip->pci = pci;
2416         chip->irq = -1;
2417         chip->driver_type = driver_type;
2418         check_msi(chip);
2419         chip->dev_index = dev;
2420         INIT_WORK(&chip->irq_pending_work, azx_irq_pending_work);
2421
2422         chip->position_fix = check_position_fix(chip, position_fix[dev]);
2423         check_probe_mask(chip, dev);
2424
2425         chip->single_cmd = single_cmd;
2426
2427         if (bdl_pos_adj[dev] < 0) {
2428                 switch (chip->driver_type) {
2429                 case AZX_DRIVER_ICH:
2430                 case AZX_DRIVER_PCH:
2431                         bdl_pos_adj[dev] = 1;
2432                         break;
2433                 default:
2434                         bdl_pos_adj[dev] = 32;
2435                         break;
2436                 }
2437         }
2438
2439 #if BITS_PER_LONG != 64
2440         /* Fix up base address on ULI M5461 */
2441         if (chip->driver_type == AZX_DRIVER_ULI) {
2442                 u16 tmp3;
2443                 pci_read_config_word(pci, 0x40, &tmp3);
2444                 pci_write_config_word(pci, 0x40, tmp3 | 0x10);
2445                 pci_write_config_dword(pci, PCI_BASE_ADDRESS_1, 0);
2446         }
2447 #endif
2448
2449         err = pci_request_regions(pci, "ICH HD audio");
2450         if (err < 0) {
2451                 kfree(chip);
2452                 pci_disable_device(pci);
2453                 return err;
2454         }
2455
2456         chip->addr = pci_resource_start(pci, 0);
2457         chip->remap_addr = pci_ioremap_bar(pci, 0);
2458         if (chip->remap_addr == NULL) {
2459                 snd_printk(KERN_ERR SFX "ioremap error\n");
2460                 err = -ENXIO;
2461                 goto errout;
2462         }
2463
2464         if (chip->msi)
2465                 if (pci_enable_msi(pci) < 0)
2466                         chip->msi = 0;
2467
2468         if (azx_acquire_irq(chip, 0) < 0) {
2469                 err = -EBUSY;
2470                 goto errout;
2471         }
2472
2473         pci_set_master(pci);
2474         synchronize_irq(chip->irq);
2475
2476         gcap = azx_readw(chip, GCAP);
2477         snd_printdd(SFX "chipset global capabilities = 0x%x\n", gcap);
2478
2479         /* disable SB600 64bit support for safety */
2480         if ((chip->driver_type == AZX_DRIVER_ATI) ||
2481             (chip->driver_type == AZX_DRIVER_ATIHDMI)) {
2482                 struct pci_dev *p_smbus;
2483                 p_smbus = pci_get_device(PCI_VENDOR_ID_ATI,
2484                                          PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2485                                          NULL);
2486                 if (p_smbus) {
2487                         if (p_smbus->revision < 0x30)
2488                                 gcap &= ~ICH6_GCAP_64OK;
2489                         pci_dev_put(p_smbus);
2490                 }
2491         }
2492
2493         /* disable 64bit DMA address for Teradici */
2494         /* it does not work with device 6549:1200 subsys e4a2:040b */
2495         if (chip->driver_type == AZX_DRIVER_TERA)
2496                 gcap &= ~ICH6_GCAP_64OK;
2497
2498         /* allow 64bit DMA address if supported by H/W */
2499         if ((gcap & ICH6_GCAP_64OK) && !pci_set_dma_mask(pci, DMA_BIT_MASK(64)))
2500                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(64));
2501         else {
2502                 pci_set_dma_mask(pci, DMA_BIT_MASK(32));
2503                 pci_set_consistent_dma_mask(pci, DMA_BIT_MASK(32));
2504         }
2505
2506         /* read number of streams from GCAP register instead of using
2507          * hardcoded value
2508          */
2509         chip->capture_streams = (gcap >> 8) & 0x0f;
2510         chip->playback_streams = (gcap >> 12) & 0x0f;
2511         if (!chip->playback_streams && !chip->capture_streams) {
2512                 /* gcap didn't give any info, switching to old method */
2513
2514                 switch (chip->driver_type) {
2515                 case AZX_DRIVER_ULI:
2516                         chip->playback_streams = ULI_NUM_PLAYBACK;
2517                         chip->capture_streams = ULI_NUM_CAPTURE;
2518                         break;
2519                 case AZX_DRIVER_ATIHDMI:
2520                         chip->playback_streams = ATIHDMI_NUM_PLAYBACK;
2521                         chip->capture_streams = ATIHDMI_NUM_CAPTURE;
2522                         break;
2523                 case AZX_DRIVER_GENERIC:
2524                 default:
2525                         chip->playback_streams = ICH6_NUM_PLAYBACK;
2526                         chip->capture_streams = ICH6_NUM_CAPTURE;
2527                         break;
2528                 }
2529         }
2530         chip->capture_index_offset = 0;
2531         chip->playback_index_offset = chip->capture_streams;
2532         chip->num_streams = chip->playback_streams + chip->capture_streams;
2533         chip->azx_dev = kcalloc(chip->num_streams, sizeof(*chip->azx_dev),
2534                                 GFP_KERNEL);
2535         if (!chip->azx_dev) {
2536                 snd_printk(KERN_ERR SFX "cannot malloc azx_dev\n");
2537                 goto errout;
2538         }
2539
2540         for (i = 0; i < chip->num_streams; i++) {
2541                 /* allocate memory for the BDL for each stream */
2542                 err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2543                                           snd_dma_pci_data(chip->pci),
2544                                           BDL_SIZE, &chip->azx_dev[i].bdl);
2545                 if (err < 0) {
2546                         snd_printk(KERN_ERR SFX "cannot allocate BDL\n");
2547                         goto errout;
2548                 }
2549         }
2550         /* allocate memory for the position buffer */
2551         err = snd_dma_alloc_pages(SNDRV_DMA_TYPE_DEV,
2552                                   snd_dma_pci_data(chip->pci),
2553                                   chip->num_streams * 8, &chip->posbuf);
2554         if (err < 0) {
2555                 snd_printk(KERN_ERR SFX "cannot allocate posbuf\n");
2556                 goto errout;
2557         }
2558         /* allocate CORB/RIRB */
2559         err = azx_alloc_cmd_io(chip);
2560         if (err < 0)
2561                 goto errout;
2562
2563         /* initialize streams */
2564         azx_init_stream(chip);
2565
2566         /* initialize chip */
2567         azx_init_pci(chip);
2568         azx_init_chip(chip);
2569
2570         /* codec detection */
2571         if (!chip->codec_mask) {
2572                 snd_printk(KERN_ERR SFX "no codecs found!\n");
2573                 err = -ENODEV;
2574                 goto errout;
2575         }
2576
2577         err = snd_device_new(card, SNDRV_DEV_LOWLEVEL, chip, &ops);
2578         if (err <0) {
2579                 snd_printk(KERN_ERR SFX "Error creating device [card]!\n");
2580                 goto errout;
2581         }
2582
2583         strcpy(card->driver, "HDA-Intel");
2584         strlcpy(card->shortname, driver_short_names[chip->driver_type],
2585                 sizeof(card->shortname));
2586         snprintf(card->longname, sizeof(card->longname),
2587                  "%s at 0x%lx irq %i",
2588                  card->shortname, chip->addr, chip->irq);
2589
2590         *rchip = chip;
2591         return 0;
2592
2593  errout:
2594         azx_free(chip);
2595         return err;
2596 }
2597
2598 static void power_down_all_codecs(struct azx *chip)
2599 {
2600 #ifdef CONFIG_SND_HDA_POWER_SAVE
2601         /* The codecs were powered up in snd_hda_codec_new().
2602          * Now all initialization done, so turn them down if possible
2603          */
2604         struct hda_codec *codec;
2605         list_for_each_entry(codec, &chip->bus->codec_list, list) {
2606                 snd_hda_power_down(codec);
2607         }
2608 #endif
2609 }
2610
2611 static int __devinit azx_probe(struct pci_dev *pci,
2612                                const struct pci_device_id *pci_id)
2613 {
2614         static int dev;
2615         struct snd_card *card;
2616         struct azx *chip;
2617         int err;
2618
2619         if (dev >= SNDRV_CARDS)
2620                 return -ENODEV;
2621         if (!enable[dev]) {
2622                 dev++;
2623                 return -ENOENT;
2624         }
2625
2626         err = snd_card_create(index[dev], id[dev], THIS_MODULE, 0, &card);
2627         if (err < 0) {
2628                 snd_printk(KERN_ERR SFX "Error creating card!\n");
2629                 return err;
2630         }
2631
2632         /* set this here since it's referred in snd_hda_load_patch() */
2633         snd_card_set_dev(card, &pci->dev);
2634
2635         err = azx_create(card, pci, dev, pci_id->driver_data, &chip);
2636         if (err < 0)
2637                 goto out_free;
2638         card->private_data = chip;
2639
2640 #ifdef CONFIG_SND_HDA_INPUT_BEEP
2641         chip->beep_mode = beep_mode[dev];
2642 #endif
2643
2644         /* create codec instances */
2645         err = azx_codec_create(chip, model[dev]);
2646         if (err < 0)
2647                 goto out_free;
2648 #ifdef CONFIG_SND_HDA_PATCH_LOADER
2649         if (patch[dev]) {
2650                 snd_printk(KERN_ERR SFX "Applying patch firmware '%s'\n",
2651                            patch[dev]);
2652                 err = snd_hda_load_patch(chip->bus, patch[dev]);
2653                 if (err < 0)
2654                         goto out_free;
2655         }
2656 #endif
2657         if (!probe_only[dev]) {
2658                 err = azx_codec_configure(chip);
2659                 if (err < 0)
2660                         goto out_free;
2661         }
2662
2663         /* create PCM streams */
2664         err = snd_hda_build_pcms(chip->bus);
2665         if (err < 0)
2666                 goto out_free;
2667
2668         /* create mixer controls */
2669         err = azx_mixer_create(chip);
2670         if (err < 0)
2671                 goto out_free;
2672
2673         err = snd_card_register(card);
2674         if (err < 0)
2675                 goto out_free;
2676
2677         pci_set_drvdata(pci, card);
2678         chip->running = 1;
2679         power_down_all_codecs(chip);
2680         azx_notifier_register(chip);
2681
2682         dev++;
2683         return err;
2684 out_free:
2685         snd_card_free(card);
2686         return err;
2687 }
2688
2689 static void __devexit azx_remove(struct pci_dev *pci)
2690 {
2691         snd_card_free(pci_get_drvdata(pci));
2692         pci_set_drvdata(pci, NULL);
2693 }
2694
2695 /* PCI IDs */
2696 static DEFINE_PCI_DEVICE_TABLE(azx_ids) = {
2697         /* ICH 6..10 */
2698         { PCI_DEVICE(0x8086, 0x2668), .driver_data = AZX_DRIVER_ICH },
2699         { PCI_DEVICE(0x8086, 0x27d8), .driver_data = AZX_DRIVER_ICH },
2700         { PCI_DEVICE(0x8086, 0x269a), .driver_data = AZX_DRIVER_ICH },
2701         { PCI_DEVICE(0x8086, 0x284b), .driver_data = AZX_DRIVER_ICH },
2702         { PCI_DEVICE(0x8086, 0x2911), .driver_data = AZX_DRIVER_ICH },
2703         { PCI_DEVICE(0x8086, 0x293e), .driver_data = AZX_DRIVER_ICH },
2704         { PCI_DEVICE(0x8086, 0x293f), .driver_data = AZX_DRIVER_ICH },
2705         { PCI_DEVICE(0x8086, 0x3a3e), .driver_data = AZX_DRIVER_ICH },
2706         { PCI_DEVICE(0x8086, 0x3a6e), .driver_data = AZX_DRIVER_ICH },
2707         /* PCH */
2708         { PCI_DEVICE(0x8086, 0x3b56), .driver_data = AZX_DRIVER_ICH },
2709         /* CPT */
2710         { PCI_DEVICE(0x8086, 0x1c20), .driver_data = AZX_DRIVER_PCH },
2711         /* SCH */
2712         { PCI_DEVICE(0x8086, 0x811b), .driver_data = AZX_DRIVER_SCH },
2713         /* ATI SB 450/600 */
2714         { PCI_DEVICE(0x1002, 0x437b), .driver_data = AZX_DRIVER_ATI },
2715         { PCI_DEVICE(0x1002, 0x4383), .driver_data = AZX_DRIVER_ATI },
2716         /* ATI HDMI */
2717         { PCI_DEVICE(0x1002, 0x793b), .driver_data = AZX_DRIVER_ATIHDMI },
2718         { PCI_DEVICE(0x1002, 0x7919), .driver_data = AZX_DRIVER_ATIHDMI },
2719         { PCI_DEVICE(0x1002, 0x960f), .driver_data = AZX_DRIVER_ATIHDMI },
2720         { PCI_DEVICE(0x1002, 0x970f), .driver_data = AZX_DRIVER_ATIHDMI },
2721         { PCI_DEVICE(0x1002, 0xaa00), .driver_data = AZX_DRIVER_ATIHDMI },
2722         { PCI_DEVICE(0x1002, 0xaa08), .driver_data = AZX_DRIVER_ATIHDMI },
2723         { PCI_DEVICE(0x1002, 0xaa10), .driver_data = AZX_DRIVER_ATIHDMI },
2724         { PCI_DEVICE(0x1002, 0xaa18), .driver_data = AZX_DRIVER_ATIHDMI },
2725         { PCI_DEVICE(0x1002, 0xaa20), .driver_data = AZX_DRIVER_ATIHDMI },
2726         { PCI_DEVICE(0x1002, 0xaa28), .driver_data = AZX_DRIVER_ATIHDMI },
2727         { PCI_DEVICE(0x1002, 0xaa30), .driver_data = AZX_DRIVER_ATIHDMI },
2728         { PCI_DEVICE(0x1002, 0xaa38), .driver_data = AZX_DRIVER_ATIHDMI },
2729         { PCI_DEVICE(0x1002, 0xaa40), .driver_data = AZX_DRIVER_ATIHDMI },
2730         { PCI_DEVICE(0x1002, 0xaa48), .driver_data = AZX_DRIVER_ATIHDMI },
2731         /* VIA VT8251/VT8237A */
2732         { PCI_DEVICE(0x1106, 0x3288), .driver_data = AZX_DRIVER_VIA },
2733         /* SIS966 */
2734         { PCI_DEVICE(0x1039, 0x7502), .driver_data = AZX_DRIVER_SIS },
2735         /* ULI M5461 */
2736         { PCI_DEVICE(0x10b9, 0x5461), .driver_data = AZX_DRIVER_ULI },
2737         /* NVIDIA MCP */
2738         { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID),
2739           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2740           .class_mask = 0xffffff,
2741           .driver_data = AZX_DRIVER_NVIDIA },
2742         /* Teradici */
2743         { PCI_DEVICE(0x6549, 0x1200), .driver_data = AZX_DRIVER_TERA },
2744         /* Creative X-Fi (CA0110-IBG) */
2745 #if !defined(CONFIG_SND_CTXFI) && !defined(CONFIG_SND_CTXFI_MODULE)
2746         /* the following entry conflicts with snd-ctxfi driver,
2747          * as ctxfi driver mutates from HD-audio to native mode with
2748          * a special command sequence.
2749          */
2750         { PCI_DEVICE(PCI_VENDOR_ID_CREATIVE, PCI_ANY_ID),
2751           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2752           .class_mask = 0xffffff,
2753           .driver_data = AZX_DRIVER_GENERIC },
2754 #else
2755         /* this entry seems still valid -- i.e. without emu20kx chip */
2756         { PCI_DEVICE(0x1102, 0x0009), .driver_data = AZX_DRIVER_GENERIC },
2757 #endif
2758         /* AMD/ATI Generic, PCI class code and Vendor ID for HD Audio */
2759         { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_ANY_ID),
2760           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2761           .class_mask = 0xffffff,
2762           .driver_data = AZX_DRIVER_GENERIC },
2763         { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_ANY_ID),
2764           .class = PCI_CLASS_MULTIMEDIA_HD_AUDIO << 8,
2765           .class_mask = 0xffffff,
2766           .driver_data = AZX_DRIVER_GENERIC },
2767         { 0, }
2768 };
2769 MODULE_DEVICE_TABLE(pci, azx_ids);
2770
2771 /* pci_driver definition */
2772 static struct pci_driver driver = {
2773         .name = "HDA Intel",
2774         .id_table = azx_ids,
2775         .probe = azx_probe,
2776         .remove = __devexit_p(azx_remove),
2777 #ifdef CONFIG_PM
2778         .suspend = azx_suspend,
2779         .resume = azx_resume,
2780 #endif
2781 };
2782
2783 static int __init alsa_card_azx_init(void)
2784 {
2785         return pci_register_driver(&driver);
2786 }
2787
2788 static void __exit alsa_card_azx_exit(void)
2789 {
2790         pci_unregister_driver(&driver);
2791 }
2792
2793 module_init(alsa_card_azx_init)
2794 module_exit(alsa_card_azx_exit)