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   1 /* linux/drivers/video/s3c2410fb.c
   2  *      Copyright (c) 2004,2005 Arnaud Patard
   3  *      Copyright (c) 2004-2008 Ben Dooks
   4  *
   5  * S3C2410 LCD Framebuffer Driver
   6  *
   7  * This file is subject to the terms and conditions of the GNU General Public
   8  * License.  See the file COPYING in the main directory of this archive for
   9  * more details.
  10  *
  11  * Driver based on skeletonfb.c, sa1100fb.c and others.
  12 */
  13
  14 #include <linux/module.h>
  15 #include <linux/kernel.h>
  16 #include <linux/errno.h>
  17 #include <linux/string.h>
  18 #include <linux/mm.h>
  19 #include <linux/slab.h>
  20 #include <linux/delay.h>
  21 #include <linux/fb.h>
  22 #include <linux/init.h>
  23 #include <linux/dma-mapping.h>
  24 #include <linux/interrupt.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpufreq.h>
  28
  29 #include <asm/io.h>
  30 #include <asm/div64.h>
  31
  32 #include <asm/mach/map.h>
  33 #include <mach/regs-lcd.h>
  34 #include <mach/regs-gpio.h>
  35 #include <mach/fb.h>
  36
  37 #ifdef CONFIG_PM
  38 #include <linux/pm.h>
  39 #endif
  40
  41 #include "s3c2410fb.h"
  42
  43 /* Debugging stuff */
  44 #ifdef CONFIG_FB_S3C2410_DEBUG
  45 static int debug        = 1;
  46 #else
  47 static int debug        = 0;
  48 #endif
  49
  50 #define dprintk(msg...) if (debug) { printk(KERN_DEBUG "s3c2410fb: " msg); }
  51
  52 /* useful functions */
  53
  54 static int is_s3c2412(struct s3c2410fb_info *fbi)
  55 {
  56         return (fbi->drv_type == DRV_S3C2412);
  57 }
  58
  59 /* s3c2410fb_set_lcdaddr
  60  *
  61  * initialise lcd controller address pointers
  62  */
  63 static void s3c2410fb_set_lcdaddr(struct fb_info *info)
  64 {
  65         unsigned long saddr1, saddr2, saddr3;
  66         struct s3c2410fb_info *fbi = info->par;
  67         void __iomem *regs = fbi->io;
  68
  69         saddr1  = info->fix.smem_start >> 1;
  70         saddr2  = info->fix.smem_start;
  71         saddr2 += info->fix.line_length * info->var.yres;
  72         saddr2 >>= 1;
  73
  74         saddr3 = S3C2410_OFFSIZE(0) |
  75                  S3C2410_PAGEWIDTH((info->fix.line_length / 2) & 0x3ff);
  76
  77         dprintk("LCDSADDR1 = 0x%08lx\n", saddr1);
  78         dprintk("LCDSADDR2 = 0x%08lx\n", saddr2);
  79         dprintk("LCDSADDR3 = 0x%08lx\n", saddr3);
  80
  81         writel(saddr1, regs + S3C2410_LCDSADDR1);
  82         writel(saddr2, regs + S3C2410_LCDSADDR2);
  83         writel(saddr3, regs + S3C2410_LCDSADDR3);
  84 }
  85
  86 /* s3c2410fb_calc_pixclk()
  87  *
  88  * calculate divisor for clk->pixclk
  89  */
  90 static unsigned int s3c2410fb_calc_pixclk(struct s3c2410fb_info *fbi,
  91                                           unsigned long pixclk)
  92 {
  93         unsigned long clk = fbi->clk_rate;
  94         unsigned long long div;
  95
  96         /* pixclk is in picoseconds, our clock is in Hz
  97          *
  98          * Hz -> picoseconds is / 10^-12
  99          */
 100
 101         div = (unsigned long long)clk * pixclk;
 102         div >>= 12;                     /* div / 2^12 */
 103         do_div(div, 625 * 625UL * 625); /* div / 5^12 */
 104
 105         dprintk("pixclk %ld, divisor is %ld\n", pixclk, (long)div);
 106         return div;
 107 }
 108
 109 /*
 110  *      s3c2410fb_check_var():
 111  *      Get the video params out of 'var'. If a value doesn't fit, round it up,
 112  *      if it's too big, return -EINVAL.
 113  *
 114  */
 115 static int s3c2410fb_check_var(struct fb_var_screeninfo *var,
 116                                struct fb_info *info)
 117 {
 118         struct s3c2410fb_info *fbi = info->par;
 119         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 120         struct s3c2410fb_display *display = NULL;
 121         struct s3c2410fb_display *default_display = mach_info->displays +
 122                                                     mach_info->default_display;
 123         int type = default_display->type;
 124         unsigned i;
 125
 126         dprintk("check_var(var=%p, info=%p)\n", var, info);
 127
 128         /* validate x/y resolution */
 129         /* choose default mode if possible */
 130         if (var->yres == default_display->yres &&
 131             var->xres == default_display->xres &&
 132             var->bits_per_pixel == default_display->bpp)
 133                 display = default_display;
 134         else
 135                 for (i = 0; i < mach_info->num_displays; i++)
 136                         if (type == mach_info->displays[i].type &&
 137                             var->yres == mach_info->displays[i].yres &&
 138                             var->xres == mach_info->displays[i].xres &&
 139                             var->bits_per_pixel == mach_info->displays[i].bpp) {
 140                                 display = mach_info->displays + i;
 141                                 break;
 142                         }
 143
 144         if (!display) {
 145                 dprintk("wrong resolution or depth %dx%d at %d bpp\n",
 146                         var->xres, var->yres, var->bits_per_pixel);
 147                 return -EINVAL;
 148         }
 149
 150         /* it is always the size as the display */
 151         var->xres_virtual = display->xres;
 152         var->yres_virtual = display->yres;
 153         var->height = display->height;
 154         var->width = display->width;
 155
 156         /* copy lcd settings */
 157         var->pixclock = display->pixclock;
 158         var->left_margin = display->left_margin;
 159         var->right_margin = display->right_margin;
 160         var->upper_margin = display->upper_margin;
 161         var->lower_margin = display->lower_margin;
 162         var->vsync_len = display->vsync_len;
 163         var->hsync_len = display->hsync_len;
 164
 165         fbi->regs.lcdcon5 = display->lcdcon5;
 166         /* set display type */
 167         fbi->regs.lcdcon1 = display->type;
 168
 169         var->transp.offset = 0;
 170         var->transp.length = 0;
 171         /* set r/g/b positions */
 172         switch (var->bits_per_pixel) {
 173         case 1:
 174         case 2:
 175         case 4:
 176                 var->red.offset = 0;
 177                 var->red.length = var->bits_per_pixel;
 178                 var->green      = var->red;
 179                 var->blue       = var->red;
 180                 break;
 181         case 8:
 182                 if (display->type != S3C2410_LCDCON1_TFT) {
 183                         /* 8 bpp 332 */
 184                         var->red.length         = 3;
 185                         var->red.offset         = 5;
 186                         var->green.length       = 3;
 187                         var->green.offset       = 2;
 188                         var->blue.length        = 2;
 189                         var->blue.offset        = 0;
 190                 } else {
 191                         var->red.offset         = 0;
 192                         var->red.length         = 8;
 193                         var->green              = var->red;
 194                         var->blue               = var->red;
 195                 }
 196                 break;
 197         case 12:
 198                 /* 12 bpp 444 */
 199                 var->red.length         = 4;
 200                 var->red.offset         = 8;
 201                 var->green.length       = 4;
 202                 var->green.offset       = 4;
 203                 var->blue.length        = 4;
 204                 var->blue.offset        = 0;
 205                 break;
 206
 207         default:
 208         case 16:
 209                 if (display->lcdcon5 & S3C2410_LCDCON5_FRM565) {
 210                         /* 16 bpp, 565 format */
 211                         var->red.offset         = 11;
 212                         var->green.offset       = 5;
 213                         var->blue.offset        = 0;
 214                         var->red.length         = 5;
 215                         var->green.length       = 6;
 216                         var->blue.length        = 5;
 217                 } else {
 218                         /* 16 bpp, 5551 format */
 219                         var->red.offset         = 11;
 220                         var->green.offset       = 6;
 221                         var->blue.offset        = 1;
 222                         var->red.length         = 5;
 223                         var->green.length       = 5;
 224                         var->blue.length        = 5;
 225                 }
 226                 break;
 227         case 32:
 228                 /* 24 bpp 888 and 8 dummy */
 229                 var->red.length         = 8;
 230                 var->red.offset         = 16;
 231                 var->green.length       = 8;
 232                 var->green.offset       = 8;
 233                 var->blue.length        = 8;
 234                 var->blue.offset        = 0;
 235                 break;
 236         }
 237         return 0;
 238 }
 239
 240 /* s3c2410fb_calculate_stn_lcd_regs
 241  *
 242  * calculate register values from var settings
 243  */
 244 static void s3c2410fb_calculate_stn_lcd_regs(const struct fb_info *info,
 245                                              struct s3c2410fb_hw *regs)
 246 {
 247         const struct s3c2410fb_info *fbi = info->par;
 248         const struct fb_var_screeninfo *var = &info->var;
 249         int type = regs->lcdcon1 & ~S3C2410_LCDCON1_TFT;
 250         int hs = var->xres >> 2;
 251         unsigned wdly = (var->left_margin >> 4) - 1;
 252         unsigned wlh = (var->hsync_len >> 4) - 1;
 253
 254         if (type != S3C2410_LCDCON1_STN4)
 255                 hs >>= 1;
 256
 257         switch (var->bits_per_pixel) {
 258         case 1:
 259                 regs->lcdcon1 |= S3C2410_LCDCON1_STN1BPP;
 260                 break;
 261         case 2:
 262                 regs->lcdcon1 |= S3C2410_LCDCON1_STN2GREY;
 263                 break;
 264         case 4:
 265                 regs->lcdcon1 |= S3C2410_LCDCON1_STN4GREY;
 266                 break;
 267         case 8:
 268                 regs->lcdcon1 |= S3C2410_LCDCON1_STN8BPP;
 269                 hs *= 3;
 270                 break;
 271         case 12:
 272                 regs->lcdcon1 |= S3C2410_LCDCON1_STN12BPP;
 273                 hs *= 3;
 274                 break;
 275
 276         default:
 277                 /* invalid pixel depth */
 278                 dev_err(fbi->dev, "invalid bpp %d\n",
 279                         var->bits_per_pixel);
 280         }
 281         /* update X/Y info */
 282         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 283                 var->left_margin, var->right_margin, var->hsync_len);
 284
 285         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1);
 286
 287         if (wdly > 3)
 288                 wdly = 3;
 289
 290         if (wlh > 3)
 291                 wlh = 3;
 292
 293         regs->lcdcon3 = S3C2410_LCDCON3_WDLY(wdly) |
 294                         S3C2410_LCDCON3_LINEBLANK(var->right_margin / 8) |
 295                         S3C2410_LCDCON3_HOZVAL(hs - 1);
 296
 297         regs->lcdcon4 = S3C2410_LCDCON4_WLH(wlh);
 298 }
 299
 300 /* s3c2410fb_calculate_tft_lcd_regs
 301  *
 302  * calculate register values from var settings
 303  */
 304 static void s3c2410fb_calculate_tft_lcd_regs(const struct fb_info *info,
 305                                              struct s3c2410fb_hw *regs)
 306 {
 307         const struct s3c2410fb_info *fbi = info->par;
 308         const struct fb_var_screeninfo *var = &info->var;
 309
 310         switch (var->bits_per_pixel) {
 311         case 1:
 312                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT1BPP;
 313                 break;
 314         case 2:
 315                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT2BPP;
 316                 break;
 317         case 4:
 318                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT4BPP;
 319                 break;
 320         case 8:
 321                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT8BPP;
 322                 regs->lcdcon5 |= S3C2410_LCDCON5_BSWP |
 323                                  S3C2410_LCDCON5_FRM565;
 324                 regs->lcdcon5 &= ~S3C2410_LCDCON5_HWSWP;
 325                 break;
 326         case 16:
 327                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT16BPP;
 328                 regs->lcdcon5 &= ~S3C2410_LCDCON5_BSWP;
 329                 regs->lcdcon5 |= S3C2410_LCDCON5_HWSWP;
 330                 break;
 331         case 32:
 332                 regs->lcdcon1 |= S3C2410_LCDCON1_TFT24BPP;
 333                 regs->lcdcon5 &= ~(S3C2410_LCDCON5_BSWP |
 334                                    S3C2410_LCDCON5_HWSWP |
 335                                    S3C2410_LCDCON5_BPP24BL);
 336                 break;
 337         default:
 338                 /* invalid pixel depth */
 339                 dev_err(fbi->dev, "invalid bpp %d\n",
 340                         var->bits_per_pixel);
 341         }
 342         /* update X/Y info */
 343         dprintk("setting vert: up=%d, low=%d, sync=%d\n",
 344                 var->upper_margin, var->lower_margin, var->vsync_len);
 345
 346         dprintk("setting horz: lft=%d, rt=%d, sync=%d\n",
 347                 var->left_margin, var->right_margin, var->hsync_len);
 348
 349         regs->lcdcon2 = S3C2410_LCDCON2_LINEVAL(var->yres - 1) |
 350                         S3C2410_LCDCON2_VBPD(var->upper_margin - 1) |
 351                         S3C2410_LCDCON2_VFPD(var->lower_margin - 1) |
 352                         S3C2410_LCDCON2_VSPW(var->vsync_len - 1);
 353
 354         regs->lcdcon3 = S3C2410_LCDCON3_HBPD(var->right_margin - 1) |
 355                         S3C2410_LCDCON3_HFPD(var->left_margin - 1) |
 356                         S3C2410_LCDCON3_HOZVAL(var->xres - 1);
 357
 358         regs->lcdcon4 = S3C2410_LCDCON4_HSPW(var->hsync_len - 1);
 359 }
 360
 361 /* s3c2410fb_activate_var
 362  *
 363  * activate (set) the controller from the given framebuffer
 364  * information
 365  */
 366 static void s3c2410fb_activate_var(struct fb_info *info)
 367 {
 368         struct s3c2410fb_info *fbi = info->par;
 369         void __iomem *regs = fbi->io;
 370         int type = fbi->regs.lcdcon1 & S3C2410_LCDCON1_TFT;
 371         struct fb_var_screeninfo *var = &info->var;
 372         int clkdiv;
 373
 374         clkdiv = DIV_ROUND_UP(s3c2410fb_calc_pixclk(fbi, var->pixclock), 2);
 375
 376         dprintk("%s: var->xres  = %d\n", __func__, var->xres);
 377         dprintk("%s: var->yres  = %d\n", __func__, var->yres);
 378         dprintk("%s: var->bpp   = %d\n", __func__, var->bits_per_pixel);
 379
 380         if (type == S3C2410_LCDCON1_TFT) {
 381                 s3c2410fb_calculate_tft_lcd_regs(info, &fbi->regs);
 382                 --clkdiv;
 383                 if (clkdiv < 0)
 384                         clkdiv = 0;
 385         } else {
 386                 s3c2410fb_calculate_stn_lcd_regs(info, &fbi->regs);
 387                 if (clkdiv < 2)
 388                         clkdiv = 2;
 389         }
 390
 391         fbi->regs.lcdcon1 |=  S3C2410_LCDCON1_CLKVAL(clkdiv);
 392
 393         /* write new registers */
 394
 395         dprintk("new register set:\n");
 396         dprintk("lcdcon[1] = 0x%08lx\n", fbi->regs.lcdcon1);
 397         dprintk("lcdcon[2] = 0x%08lx\n", fbi->regs.lcdcon2);
 398         dprintk("lcdcon[3] = 0x%08lx\n", fbi->regs.lcdcon3);
 399         dprintk("lcdcon[4] = 0x%08lx\n", fbi->regs.lcdcon4);
 400         dprintk("lcdcon[5] = 0x%08lx\n", fbi->regs.lcdcon5);
 401
 402         writel(fbi->regs.lcdcon1 & ~S3C2410_LCDCON1_ENVID,
 403                 regs + S3C2410_LCDCON1);
 404         writel(fbi->regs.lcdcon2, regs + S3C2410_LCDCON2);
 405         writel(fbi->regs.lcdcon3, regs + S3C2410_LCDCON3);
 406         writel(fbi->regs.lcdcon4, regs + S3C2410_LCDCON4);
 407         writel(fbi->regs.lcdcon5, regs + S3C2410_LCDCON5);
 408
 409         /* set lcd address pointers */
 410         s3c2410fb_set_lcdaddr(info);
 411
 412         fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID,
 413         writel(fbi->regs.lcdcon1, regs + S3C2410_LCDCON1);
 414 }
 415
 416 /*
 417  *      s3c2410fb_set_par - Alters the hardware state.
 418  *      @info: frame buffer structure that represents a single frame buffer
 419  *
 420  */
 421 static int s3c2410fb_set_par(struct fb_info *info)
 422 {
 423         struct fb_var_screeninfo *var = &info->var;
 424
 425         switch (var->bits_per_pixel) {
 426         case 32:
 427         case 16:
 428         case 12:
 429                 info->fix.visual = FB_VISUAL_TRUECOLOR;
 430                 break;
 431         case 1:
 432                 info->fix.visual = FB_VISUAL_MONO01;
 433                 break;
 434         default:
 435                 info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
 436                 break;
 437         }
 438
 439         info->fix.line_length = (var->xres_virtual * var->bits_per_pixel) / 8;
 440
 441         /* activate this new configuration */
 442
 443         s3c2410fb_activate_var(info);
 444         return 0;
 445 }
 446
 447 static void schedule_palette_update(struct s3c2410fb_info *fbi,
 448                                     unsigned int regno, unsigned int val)
 449 {
 450         unsigned long flags;
 451         unsigned long irqen;
 452         void __iomem *irq_base = fbi->irq_base;
 453
 454         local_irq_save(flags);
 455
 456         fbi->palette_buffer[regno] = val;
 457
 458         if (!fbi->palette_ready) {
 459                 fbi->palette_ready = 1;
 460
 461                 /* enable IRQ */
 462                 irqen = readl(irq_base + S3C24XX_LCDINTMSK);
 463                 irqen &= ~S3C2410_LCDINT_FRSYNC;
 464                 writel(irqen, irq_base + S3C24XX_LCDINTMSK);
 465         }
 466
 467         local_irq_restore(flags);
 468 }
 469
 470 /* from pxafb.c */
 471 static inline unsigned int chan_to_field(unsigned int chan,
 472                                          struct fb_bitfield *bf)
 473 {
 474         chan &= 0xffff;
 475         chan >>= 16 - bf->length;
 476         return chan << bf->offset;
 477 }
 478
 479 static int s3c2410fb_setcolreg(unsigned regno,
 480                                unsigned red, unsigned green, unsigned blue,
 481                                unsigned transp, struct fb_info *info)
 482 {
 483         struct s3c2410fb_info *fbi = info->par;
 484         void __iomem *regs = fbi->io;
 485         unsigned int val;
 486
 487         /* dprintk("setcol: regno=%d, rgb=%d,%d,%d\n",
 488                    regno, red, green, blue); */
 489
 490         switch (info->fix.visual) {
 491         case FB_VISUAL_TRUECOLOR:
 492                 /* true-colour, use pseudo-palette */
 493
 494                 if (regno < 16) {
 495                         u32 *pal = info->pseudo_palette;
 496
 497                         val  = chan_to_field(red,   &info->var.red);
 498                         val |= chan_to_field(green, &info->var.green);
 499                         val |= chan_to_field(blue,  &info->var.blue);
 500
 501                         pal[regno] = val;
 502                 }
 503                 break;
 504
 505         case FB_VISUAL_PSEUDOCOLOR:
 506                 if (regno < 256) {
 507                         /* currently assume RGB 5-6-5 mode */
 508
 509                         val  = (red   >>  0) & 0xf800;
 510                         val |= (green >>  5) & 0x07e0;
 511                         val |= (blue  >> 11) & 0x001f;
 512
 513                         writel(val, regs + S3C2410_TFTPAL(regno));
 514                         schedule_palette_update(fbi, regno, val);
 515                 }
 516
 517                 break;
 518
 519         default:
 520                 return 1;       /* unknown type */
 521         }
 522
 523         return 0;
 524 }
 525
 526 /* s3c2410fb_lcd_enable
 527  *
 528  * shutdown the lcd controller
 529  */
 530 static void s3c2410fb_lcd_enable(struct s3c2410fb_info *fbi, int enable)
 531 {
 532         unsigned long flags;
 533
 534         local_irq_save(flags);
 535
 536         if (enable)
 537                 fbi->regs.lcdcon1 |= S3C2410_LCDCON1_ENVID;
 538         else
 539                 fbi->regs.lcdcon1 &= ~S3C2410_LCDCON1_ENVID;
 540
 541         writel(fbi->regs.lcdcon1, fbi->io + S3C2410_LCDCON1);
 542
 543         local_irq_restore(flags);
 544 }
 545
 546
 547 /*
 548  *      s3c2410fb_blank
 549  *      @blank_mode: the blank mode we want.
 550  *      @info: frame buffer structure that represents a single frame buffer
 551  *
 552  *      Blank the screen if blank_mode != 0, else unblank. Return 0 if
 553  *      blanking succeeded, != 0 if un-/blanking failed due to e.g. a
 554  *      video mode which doesn't support it. Implements VESA suspend
 555  *      and powerdown modes on hardware that supports disabling hsync/vsync:
 556  *
 557  *      Returns negative errno on error, or zero on success.
 558  *
 559  */
 560 static int s3c2410fb_blank(int blank_mode, struct fb_info *info)
 561 {
 562         struct s3c2410fb_info *fbi = info->par;
 563         void __iomem *tpal_reg = fbi->io;
 564
 565         dprintk("blank(mode=%d, info=%p)\n", blank_mode, info);
 566
 567         tpal_reg += is_s3c2412(fbi) ? S3C2412_TPAL : S3C2410_TPAL;
 568
 569         if (blank_mode == FB_BLANK_POWERDOWN) {
 570                 s3c2410fb_lcd_enable(fbi, 0);
 571         } else {
 572                 s3c2410fb_lcd_enable(fbi, 1);
 573         }
 574
 575         if (blank_mode == FB_BLANK_UNBLANK)
 576                 writel(0x0, tpal_reg);
 577         else {
 578                 dprintk("setting TPAL to output 0x000000\n");
 579                 writel(S3C2410_TPAL_EN, tpal_reg);
 580         }
 581
 582         return 0;
 583 }
 584
 585 static int s3c2410fb_debug_show(struct device *dev,
 586                                 struct device_attribute *attr, char *buf)
 587 {
 588         return snprintf(buf, PAGE_SIZE, "%s\n", debug ? "on" : "off");
 589 }
 590
 591 static int s3c2410fb_debug_store(struct device *dev,
 592                                  struct device_attribute *attr,
 593                                  const char *buf, size_t len)
 594 {
 595         if (len < 1)
 596                 return -EINVAL;
 597
 598         if (strnicmp(buf, "on", 2) == 0 ||
 599             strnicmp(buf, "1", 1) == 0) {
 600                 debug = 1;
 601                 printk(KERN_DEBUG "s3c2410fb: Debug On");
 602         } else if (strnicmp(buf, "off", 3) == 0 ||
 603                    strnicmp(buf, "0", 1) == 0) {
 604                 debug = 0;
 605                 printk(KERN_DEBUG "s3c2410fb: Debug Off");
 606         } else {
 607                 return -EINVAL;
 608         }
 609
 610         return len;
 611 }
 612
 613 static DEVICE_ATTR(debug, 0666, s3c2410fb_debug_show, s3c2410fb_debug_store);
 614
 615 static struct fb_ops s3c2410fb_ops = {
 616         .owner          = THIS_MODULE,
 617         .fb_check_var   = s3c2410fb_check_var,
 618         .fb_set_par     = s3c2410fb_set_par,
 619         .fb_blank       = s3c2410fb_blank,
 620         .fb_setcolreg   = s3c2410fb_setcolreg,
 621         .fb_fillrect    = cfb_fillrect,
 622         .fb_copyarea    = cfb_copyarea,
 623         .fb_imageblit   = cfb_imageblit,
 624 };
 625
 626 /*
 627  * s3c2410fb_map_video_memory():
 628  *      Allocates the DRAM memory for the frame buffer.  This buffer is
 629  *      remapped into a non-cached, non-buffered, memory region to
 630  *      allow palette and pixel writes to occur without flushing the
 631  *      cache.  Once this area is remapped, all virtual memory
 632  *      access to the video memory should occur at the new region.
 633  */
 634 static int __init s3c2410fb_map_video_memory(struct fb_info *info)
 635 {
 636         struct s3c2410fb_info *fbi = info->par;
 637         dma_addr_t map_dma;
 638         unsigned map_size = PAGE_ALIGN(info->fix.smem_len);
 639
 640         dprintk("map_video_memory(fbi=%p) map_size %u\n", fbi, map_size);
 641
 642         info->screen_base = dma_alloc_writecombine(fbi->dev, map_size,
 643                                                    &map_dma, GFP_KERNEL);
 644
 645         if (info->screen_base) {
 646                 /* prevent initial garbage on screen */
 647                 dprintk("map_video_memory: clear %p:%08x\n",
 648                         info->screen_base, map_size);
 649                 memset(info->screen_base, 0x00, map_size);
 650
 651                 info->fix.smem_start = map_dma;
 652
 653                 dprintk("map_video_memory: dma=%08lx cpu=%p size=%08x\n",
 654                         info->fix.smem_start, info->screen_base, map_size);
 655         }
 656
 657         return info->screen_base ? 0 : -ENOMEM;
 658 }
 659
 660 static inline void s3c2410fb_unmap_video_memory(struct fb_info *info)
 661 {
 662         struct s3c2410fb_info *fbi = info->par;
 663
 664         dma_free_writecombine(fbi->dev, PAGE_ALIGN(info->fix.smem_len),
 665                               info->screen_base, info->fix.smem_start);
 666 }
 667
 668 static inline void modify_gpio(void __iomem *reg,
 669                                unsigned long set, unsigned long mask)
 670 {
 671         unsigned long tmp;
 672
 673         tmp = readl(reg) & ~mask;
 674         writel(tmp | set, reg);
 675 }
 676
 677 /*
 678  * s3c2410fb_init_registers - Initialise all LCD-related registers
 679  */
 680 static int s3c2410fb_init_registers(struct fb_info *info)
 681 {
 682         struct s3c2410fb_info *fbi = info->par;
 683         struct s3c2410fb_mach_info *mach_info = fbi->dev->platform_data;
 684         unsigned long flags;
 685         void __iomem *regs = fbi->io;
 686         void __iomem *tpal;
 687         void __iomem *lpcsel;
 688
 689         if (is_s3c2412(fbi)) {
 690                 tpal = regs + S3C2412_TPAL;
 691                 lpcsel = regs + S3C2412_TCONSEL;
 692         } else {
 693                 tpal = regs + S3C2410_TPAL;
 694                 lpcsel = regs + S3C2410_LPCSEL;
 695         }
 696
 697         /* Initialise LCD with values from haret */
 698
 699         local_irq_save(flags);
 700
 701         /* modify the gpio(s) with interrupts set (bjd) */
 702
 703         modify_gpio(S3C2410_GPCUP,  mach_info->gpcup,  mach_info->gpcup_mask);
 704         modify_gpio(S3C2410_GPCCON, mach_info->gpccon, mach_info->gpccon_mask);
 705         modify_gpio(S3C2410_GPDUP,  mach_info->gpdup,  mach_info->gpdup_mask);
 706         modify_gpio(S3C2410_GPDCON, mach_info->gpdcon, mach_info->gpdcon_mask);
 707
 708         local_irq_restore(flags);
 709
 710         dprintk("LPCSEL    = 0x%08lx\n", mach_info->lpcsel);
 711         writel(mach_info->lpcsel, lpcsel);
 712
 713         dprintk("replacing TPAL %08x\n", readl(tpal));
 714
 715         /* ensure temporary palette disabled */
 716         writel(0x00, tpal);
 717
 718         return 0;
 719 }
 720
 721 static void s3c2410fb_write_palette(struct s3c2410fb_info *fbi)
 722 {
 723         unsigned int i;
 724         void __iomem *regs = fbi->io;
 725
 726         fbi->palette_ready = 0;
 727
 728         for (i = 0; i < 256; i++) {
 729                 unsigned long ent = fbi->palette_buffer[i];
 730                 if (ent == PALETTE_BUFF_CLEAR)
 731                         continue;
 732
 733                 writel(ent, regs + S3C2410_TFTPAL(i));
 734
 735                 /* it seems the only way to know exactly
 736                  * if the palette wrote ok, is to check
 737                  * to see if the value verifies ok
 738                  */
 739
 740                 if (readw(regs + S3C2410_TFTPAL(i)) == ent)
 741                         fbi->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 742                 else
 743                         fbi->palette_ready = 1;   /* retry */
 744         }
 745 }
 746
 747 static irqreturn_t s3c2410fb_irq(int irq, void *dev_id)
 748 {
 749         struct s3c2410fb_info *fbi = dev_id;
 750         void __iomem *irq_base = fbi->irq_base;
 751         unsigned long lcdirq = readl(irq_base + S3C24XX_LCDINTPND);
 752
 753         if (lcdirq & S3C2410_LCDINT_FRSYNC) {
 754                 if (fbi->palette_ready)
 755                         s3c2410fb_write_palette(fbi);
 756
 757                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDINTPND);
 758                 writel(S3C2410_LCDINT_FRSYNC, irq_base + S3C24XX_LCDSRCPND);
 759         }
 760
 761         return IRQ_HANDLED;
 762 }
 763
 764 #ifdef CONFIG_CPU_FREQ
 765
 766 static int s3c2410fb_cpufreq_transition(struct notifier_block *nb,
 767                                         unsigned long val, void *data)
 768 {
 769         struct cpufreq_freqs *freqs = data;
 770         struct s3c2410fb_info *info;
 771         struct fb_info *fbinfo;
 772         long delta_f;
 773
 774         info = container_of(nb, struct s3c2410fb_info, freq_transition);
 775         fbinfo = platform_get_drvdata(to_platform_device(info->dev));
 776
 777         /* work out change, <0 for speed-up */
 778         delta_f = info->clk_rate - clk_get_rate(info->clk);
 779
 780         if ((val == CPUFREQ_POSTCHANGE && delta_f > 0) ||
 781             (val == CPUFREQ_PRECHANGE && delta_f < 0)) {
 782                 info->clk_rate = clk_get_rate(info->clk);
 783                 s3c2410fb_activate_var(fbinfo);
 784         }
 785
 786         return 0;
 787 }
 788
 789 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 790 {
 791         info->freq_transition.notifier_call = s3c2410fb_cpufreq_transition;
 792
 793         return cpufreq_register_notifier(&info->freq_transition,
 794                                          CPUFREQ_TRANSITION_NOTIFIER);
 795 }
 796
 797 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 798 {
 799         cpufreq_unregister_notifier(&info->freq_transition,
 800                                     CPUFREQ_TRANSITION_NOTIFIER);
 801 }
 802
 803 #else
 804 static inline int s3c2410fb_cpufreq_register(struct s3c2410fb_info *info)
 805 {
 806         return 0;
 807 }
 808
 809 static inline void s3c2410fb_cpufreq_deregister(struct s3c2410fb_info *info)
 810 {
 811 }
 812 #endif
 813
 814
 815 static char driver_name[] = "s3c2410fb";
 816
 817 static int __init s3c24xxfb_probe(struct platform_device *pdev,
 818                                   enum s3c_drv_type drv_type)
 819 {
 820         struct s3c2410fb_info *info;
 821         struct s3c2410fb_display *display;
 822         struct fb_info *fbinfo;
 823         struct s3c2410fb_mach_info *mach_info;
 824         struct resource *res;
 825         int ret;
 826         int irq;
 827         int i;
 828         int size;
 829         u32 lcdcon1;
 830
 831         mach_info = pdev->dev.platform_data;
 832         if (mach_info == NULL) {
 833                 dev_err(&pdev->dev,
 834                         "no platform data for lcd, cannot attach\n");
 835                 return -EINVAL;
 836         }
 837
 838         if (mach_info->default_display >= mach_info->num_displays) {
 839                 dev_err(&pdev->dev, "default is %d but only %d displays\n",
 840                         mach_info->default_display, mach_info->num_displays);
 841                 return -EINVAL;
 842         }
 843
 844         display = mach_info->displays + mach_info->default_display;
 845
 846         irq = platform_get_irq(pdev, 0);
 847         if (irq < 0) {
 848                 dev_err(&pdev->dev, "no irq for device\n");
 849                 return -ENOENT;
 850         }
 851
 852         fbinfo = framebuffer_alloc(sizeof(struct s3c2410fb_info), &pdev->dev);
 853         if (!fbinfo)
 854                 return -ENOMEM;
 855
 856         platform_set_drvdata(pdev, fbinfo);
 857
 858         info = fbinfo->par;
 859         info->dev = &pdev->dev;
 860         info->drv_type = drv_type;
 861
 862         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 863         if (res == NULL) {
 864                 dev_err(&pdev->dev, "failed to get memory registers\n");
 865                 ret = -ENXIO;
 866                 goto dealloc_fb;
 867         }
 868
 869         size = (res->end - res->start) + 1;
 870         info->mem = request_mem_region(res->start, size, pdev->name);
 871         if (info->mem == NULL) {
 872                 dev_err(&pdev->dev, "failed to get memory region\n");
 873                 ret = -ENOENT;
 874                 goto dealloc_fb;
 875         }
 876
 877         info->io = ioremap(res->start, size);
 878         if (info->io == NULL) {
 879                 dev_err(&pdev->dev, "ioremap() of registers failed\n");
 880                 ret = -ENXIO;
 881                 goto release_mem;
 882         }
 883
 884         info->irq_base = info->io + ((drv_type == DRV_S3C2412) ? S3C2412_LCDINTBASE : S3C2410_LCDINTBASE);
 885
 886         dprintk("devinit\n");
 887
 888         strcpy(fbinfo->fix.id, driver_name);
 889
 890         /* Stop the video */
 891         lcdcon1 = readl(info->io + S3C2410_LCDCON1);
 892         writel(lcdcon1 & ~S3C2410_LCDCON1_ENVID, info->io + S3C2410_LCDCON1);
 893
 894         fbinfo->fix.type            = FB_TYPE_PACKED_PIXELS;
 895         fbinfo->fix.type_aux        = 0;
 896         fbinfo->fix.xpanstep        = 0;
 897         fbinfo->fix.ypanstep        = 0;
 898         fbinfo->fix.ywrapstep       = 0;
 899         fbinfo->fix.accel           = FB_ACCEL_NONE;
 900
 901         fbinfo->var.nonstd          = 0;
 902         fbinfo->var.activate        = FB_ACTIVATE_NOW;
 903         fbinfo->var.accel_flags     = 0;
 904         fbinfo->var.vmode           = FB_VMODE_NONINTERLACED;
 905
 906         fbinfo->fbops               = &s3c2410fb_ops;
 907         fbinfo->flags               = FBINFO_FLAG_DEFAULT;
 908         fbinfo->pseudo_palette      = &info->pseudo_pal;
 909
 910         for (i = 0; i < 256; i++)
 911                 info->palette_buffer[i] = PALETTE_BUFF_CLEAR;
 912
 913         ret = request_irq(irq, s3c2410fb_irq, IRQF_DISABLED, pdev->name, info);
 914         if (ret) {
 915                 dev_err(&pdev->dev, "cannot get irq %d - err %d\n", irq, ret);
 916                 ret = -EBUSY;
 917                 goto release_regs;
 918         }
 919
 920         info->clk = clk_get(NULL, "lcd");
 921         if (!info->clk || IS_ERR(info->clk)) {
 922                 printk(KERN_ERR "failed to get lcd clock source\n");
 923                 ret = -ENOENT;
 924                 goto release_irq;
 925         }
 926
 927         clk_enable(info->clk);
 928         dprintk("got and enabled clock\n");
 929
 930         msleep(1);
 931
 932         info->clk_rate = clk_get_rate(info->clk);
 933
 934         /* find maximum required memory size for display */
 935         for (i = 0; i < mach_info->num_displays; i++) {
 936                 unsigned long smem_len = mach_info->displays[i].xres;
 937
 938                 smem_len *= mach_info->displays[i].yres;
 939                 smem_len *= mach_info->displays[i].bpp;
 940                 smem_len >>= 3;
 941                 if (fbinfo->fix.smem_len < smem_len)
 942                         fbinfo->fix.smem_len = smem_len;
 943         }
 944
 945         /* Initialize video memory */
 946         ret = s3c2410fb_map_video_memory(fbinfo);
 947         if (ret) {
 948                 printk(KERN_ERR "Failed to allocate video RAM: %d\n", ret);
 949                 ret = -ENOMEM;
 950                 goto release_clock;
 951         }
 952
 953         dprintk("got video memory\n");
 954
 955         fbinfo->var.xres = display->xres;
 956         fbinfo->var.yres = display->yres;
 957         fbinfo->var.bits_per_pixel = display->bpp;
 958
 959         s3c2410fb_init_registers(fbinfo);
 960
 961         s3c2410fb_check_var(&fbinfo->var, fbinfo);
 962
 963         ret = s3c2410fb_cpufreq_register(info);
 964         if (ret < 0) {
 965                 dev_err(&pdev->dev, "Failed to register cpufreq\n");
 966                 goto free_video_memory;
 967         }
 968
 969         ret = register_framebuffer(fbinfo);
 970         if (ret < 0) {
 971                 printk(KERN_ERR "Failed to register framebuffer device: %d\n",
 972                         ret);
 973                 goto free_cpufreq;
 974         }
 975
 976         /* create device files */
 977         ret = device_create_file(&pdev->dev, &dev_attr_debug);
 978         if (ret) {
 979                 printk(KERN_ERR "failed to add debug attribute\n");
 980         }
 981
 982         printk(KERN_INFO "fb%d: %s frame buffer device\n",
 983                 fbinfo->node, fbinfo->fix.id);
 984
 985         return 0;
 986
 987  free_cpufreq:
 988         s3c2410fb_cpufreq_deregister(info);
 989 free_video_memory:
 990         s3c2410fb_unmap_video_memory(fbinfo);
 991 release_clock:
 992         clk_disable(info->clk);
 993         clk_put(info->clk);
 994 release_irq:
 995         free_irq(irq, info);
 996 release_regs:
 997         iounmap(info->io);
 998 release_mem:
 999         release_resource(info->mem);
1000         kfree(info->mem);
1001 dealloc_fb:
1002         platform_set_drvdata(pdev, NULL);
1003         framebuffer_release(fbinfo);
1004         return ret;
1005 }
1006
1007 static int __devinit s3c2410fb_probe(struct platform_device *pdev)
1008 {
1009         return s3c24xxfb_probe(pdev, DRV_S3C2410);
1010 }
1011
1012 static int __devinit s3c2412fb_probe(struct platform_device *pdev)
1013 {
1014         return s3c24xxfb_probe(pdev, DRV_S3C2412);
1015 }
1016
1017
1018 /*
1019  *  Cleanup
1020  */
1021 static int s3c2410fb_remove(struct platform_device *pdev)
1022 {
1023         struct fb_info *fbinfo = platform_get_drvdata(pdev);
1024         struct s3c2410fb_info *info = fbinfo->par;
1025         int irq;
1026
1027         unregister_framebuffer(fbinfo);
1028         s3c2410fb_cpufreq_deregister(info);
1029
1030         s3c2410fb_lcd_enable(info, 0);
1031         msleep(1);
1032
1033         s3c2410fb_unmap_video_memory(fbinfo);
1034
1035         if (info->clk) {
1036                 clk_disable(info->clk);
1037                 clk_put(info->clk);
1038                 info->clk = NULL;
1039         }
1040
1041         irq = platform_get_irq(pdev, 0);
1042         free_irq(irq, info);
1043
1044         iounmap(info->io);
1045
1046         release_resource(info->mem);
1047         kfree(info->mem);
1048
1049         platform_set_drvdata(pdev, NULL);
1050         framebuffer_release(fbinfo);
1051
1052         return 0;
1053 }
1054
1055 #ifdef CONFIG_PM
1056
1057 /* suspend and resume support for the lcd controller */
1058 static int s3c2410fb_suspend(struct platform_device *dev, pm_message_t state)
1059 {
1060         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1061         struct s3c2410fb_info *info = fbinfo->par;
1062
1063         s3c2410fb_lcd_enable(info, 0);
1064
1065         /* sleep before disabling the clock, we need to ensure
1066          * the LCD DMA engine is not going to get back on the bus
1067          * before the clock goes off again (bjd) */
1068
1069         msleep(1);
1070         clk_disable(info->clk);
1071
1072         return 0;
1073 }
1074
1075 static int s3c2410fb_resume(struct platform_device *dev)
1076 {
1077         struct fb_info     *fbinfo = platform_get_drvdata(dev);
1078         struct s3c2410fb_info *info = fbinfo->par;
1079
1080         clk_enable(info->clk);
1081         msleep(1);
1082
1083         s3c2410fb_init_registers(fbinfo);
1084
1085         /* re-activate our display after resume */
1086         s3c2410fb_activate_var(fbinfo);
1087         s3c2410fb_blank(FB_BLANK_UNBLANK, fbinfo);
1088
1089         return 0;
1090 }
1091
1092 #else
1093 #define s3c2410fb_suspend NULL
1094 #define s3c2410fb_resume  NULL
1095 #endif
1096
1097 static struct platform_driver s3c2410fb_driver = {
1098         .probe          = s3c2410fb_probe,
1099         .remove         = s3c2410fb_remove,
1100         .suspend        = s3c2410fb_suspend,
1101         .resume         = s3c2410fb_resume,
1102         .driver         = {
1103                 .name   = "s3c2410-lcd",
1104                 .owner  = THIS_MODULE,
1105         },
1106 };
1107
1108 static struct platform_driver s3c2412fb_driver = {
1109         .probe          = s3c2412fb_probe,
1110         .remove         = s3c2410fb_remove,
1111         .suspend        = s3c2410fb_suspend,
1112         .resume         = s3c2410fb_resume,
1113         .driver         = {
1114                 .name   = "s3c2412-lcd",
1115                 .owner  = THIS_MODULE,
1116         },
1117 };
1118
1119 int __init s3c2410fb_init(void)
1120 {
1121         int ret = platform_driver_register(&s3c2410fb_driver);
1122
1123         if (ret == 0)
1124                 ret = platform_driver_register(&s3c2412fb_driver);
1125
1126         return ret;
1127 }
1128
1129 static void __exit s3c2410fb_cleanup(void)
1130 {
1131         platform_driver_unregister(&s3c2410fb_driver);
1132         platform_driver_unregister(&s3c2412fb_driver);
1133 }
1134
1135 module_init(s3c2410fb_init);
1136 module_exit(s3c2410fb_cleanup);
1137
1138 MODULE_AUTHOR("Arnaud Patard <arnaud.patard@rtp-net.org>, "
1139               "Ben Dooks <ben-linux@fluff.org>");
1140 MODULE_DESCRIPTION("Framebuffer driver for the s3c2410");
1141 MODULE_LICENSE("GPL");
1142 MODULE_ALIAS("platform:s3c2410-lcd");
1143 MODULE_ALIAS("platform:s3c2412-lcd");