SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco_freq, max_vco_freq;
  51         int p_transition_clock;
  52         int p_inc_lo, p_inc_hi;
  53 };
  54
  55 #define PLLS_I8xx 0
  56 #define PLLS_I9xx 1
  57 #define PLLS_MAX 2
  58
  59 struct pll_min_max plls[PLLS_MAX] = {
  60         { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
  61         {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 }  //I9xx
  62 };
  63
  64 int
  65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  66 {
  67         u32 tmp;
  68         if (!pdev || !dinfo)
  69                 return 1;
  70
  71         switch (pdev->device) {
  72         case PCI_DEVICE_ID_INTEL_830M:
  73                 dinfo->name = "Intel(R) 830M";
  74                 dinfo->chipset = INTEL_830M;
  75                 dinfo->mobile = 1;
  76                 dinfo->pll_index = PLLS_I8xx;
  77                 return 0;
  78         case PCI_DEVICE_ID_INTEL_845G:
  79                 dinfo->name = "Intel(R) 845G";
  80                 dinfo->chipset = INTEL_845G;
  81                 dinfo->mobile = 0;
  82                 dinfo->pll_index = PLLS_I8xx;
  83                 return 0;
  84         case PCI_DEVICE_ID_INTEL_85XGM:
  85                 tmp = 0;
  86                 dinfo->mobile = 1;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  89                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  90                         INTEL_85X_VARIANT_MASK) {
  91                 case INTEL_VAR_855GME:
  92                         dinfo->name = "Intel(R) 855GME";
  93                         dinfo->chipset = INTEL_855GME;
  94                         return 0;
  95                 case INTEL_VAR_855GM:
  96                         dinfo->name = "Intel(R) 855GM";
  97                         dinfo->chipset = INTEL_855GM;
  98                         return 0;
  99                 case INTEL_VAR_852GME:
 100                         dinfo->name = "Intel(R) 852GME";
 101                         dinfo->chipset = INTEL_852GME;
 102                         return 0;
 103                 case INTEL_VAR_852GM:
 104                         dinfo->name = "Intel(R) 852GM";
 105                         dinfo->chipset = INTEL_852GM;
 106                         return 0;
 107                 default:
 108                         dinfo->name = "Intel(R) 852GM/855GM";
 109                         dinfo->chipset = INTEL_85XGM;
 110                         return 0;
 111                 }
 112                 break;
 113         case PCI_DEVICE_ID_INTEL_865G:
 114                 dinfo->name = "Intel(R) 865G";
 115                 dinfo->chipset = INTEL_865G;
 116                 dinfo->mobile = 0;
 117                 dinfo->pll_index = PLLS_I8xx;
 118                 return 0;
 119         case PCI_DEVICE_ID_INTEL_915G:
 120                 dinfo->name = "Intel(R) 915G";
 121                 dinfo->chipset = INTEL_915G;
 122                 dinfo->mobile = 0;
 123                 dinfo->pll_index = PLLS_I9xx;
 124                 return 0;
 125         case PCI_DEVICE_ID_INTEL_915GM:
 126                 dinfo->name = "Intel(R) 915GM";
 127                 dinfo->chipset = INTEL_915GM;
 128                 dinfo->mobile = 1;
 129                 dinfo->pll_index = PLLS_I9xx;
 130                 return 0;
 131         case PCI_DEVICE_ID_INTEL_945G:
 132                 dinfo->name = "Intel(R) 945G";
 133                 dinfo->chipset = INTEL_945G;
 134                 dinfo->mobile = 0;
 135                 dinfo->pll_index = PLLS_I9xx;
 136                 return 0;
 137         default:
 138                 return 1;
 139         }
 140 }
 141
 142 int
 143 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 144                      int *stolen_size)
 145 {
 146         struct pci_dev *bridge_dev;
 147         u16 tmp;
 148
 149         if (!pdev || !aperture_size || !stolen_size)
 150                 return 1;
 151
 152         /* Find the bridge device.  It is always 0:0.0 */
 153         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 154                 ERR_MSG("cannot find bridge device\n");
 155                 return 1;
 156         }
 157
 158         /* Get the fb aperture size and "stolen" memory amount. */
 159         tmp = 0;
 160         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 161         switch (pdev->device) {
 162         case PCI_DEVICE_ID_INTEL_830M:
 163         case PCI_DEVICE_ID_INTEL_845G:
 164                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 165                         *aperture_size = MB(64);
 166                 else
 167                         *aperture_size = MB(128);
 168                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 169                 case INTEL_830_GMCH_GMS_STOLEN_512:
 170                         *stolen_size = KB(512) - KB(132);
 171                         return 0;
 172                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 173                         *stolen_size = MB(1) - KB(132);
 174                         return 0;
 175                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 176                         *stolen_size = MB(8) - KB(132);
 177                         return 0;
 178                 case INTEL_830_GMCH_GMS_LOCAL:
 179                         ERR_MSG("only local memory found\n");
 180                         return 1;
 181                 case INTEL_830_GMCH_GMS_DISABLED:
 182                         ERR_MSG("video memory is disabled\n");
 183                         return 1;
 184                 default:
 185                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 186                                 tmp & INTEL_830_GMCH_GMS_MASK);
 187                         return 1;
 188                 }
 189                 break;
 190         default:
 191                 *aperture_size = MB(128);
 192                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 193                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 194                         *stolen_size = MB(1) - KB(132);
 195                         return 0;
 196                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 197                         *stolen_size = MB(4) - KB(132);
 198                         return 0;
 199                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 200                         *stolen_size = MB(8) - KB(132);
 201                         return 0;
 202                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 203                         *stolen_size = MB(16) - KB(132);
 204                         return 0;
 205                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 206                         *stolen_size = MB(32) - KB(132);
 207                         return 0;
 208                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 209                         *stolen_size = MB(48) - KB(132);
 210                         return 0;
 211                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 212                         *stolen_size = MB(64) - KB(132);
 213                         return 0;
 214                 case INTEL_855_GMCH_GMS_DISABLED:
 215                         ERR_MSG("video memory is disabled\n");
 216                         return 0;
 217                 default:
 218                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 219                                 tmp & INTEL_855_GMCH_GMS_MASK);
 220                         return 1;
 221                 }
 222         }
 223 }
 224
 225 int
 226 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 227 {
 228         int dvo = 0;
 229
 230         if (INREG(LVDS) & PORT_ENABLE)
 231                 dvo |= LVDS_PORT;
 232         if (INREG(DVOA) & PORT_ENABLE)
 233                 dvo |= DVOA_PORT;
 234         if (INREG(DVOB) & PORT_ENABLE)
 235                 dvo |= DVOB_PORT;
 236         if (INREG(DVOC) & PORT_ENABLE)
 237                 dvo |= DVOC_PORT;
 238
 239         return dvo;
 240 }
 241
 242 const char *
 243 intelfbhw_dvo_to_string(int dvo)
 244 {
 245         if (dvo & DVOA_PORT)
 246                 return "DVO port A";
 247         else if (dvo & DVOB_PORT)
 248                 return "DVO port B";
 249         else if (dvo & DVOC_PORT)
 250                 return "DVO port C";
 251         else if (dvo & LVDS_PORT)
 252                 return "LVDS port";
 253         else
 254                 return NULL;
 255 }
 256
 257
 258 int
 259 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 260                         struct fb_var_screeninfo *var)
 261 {
 262         int bytes_per_pixel;
 263         int tmp;
 264
 265 #if VERBOSE > 0
 266         DBG_MSG("intelfbhw_validate_mode\n");
 267 #endif
 268
 269         bytes_per_pixel = var->bits_per_pixel / 8;
 270         if (bytes_per_pixel == 3)
 271                 bytes_per_pixel = 4;
 272
 273         /* Check if enough video memory. */
 274         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 275         if (tmp > dinfo->fb.size) {
 276                 WRN_MSG("Not enough video ram for mode "
 277                         "(%d KByte vs %d KByte).\n",
 278                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 279                 return 1;
 280         }
 281
 282         /* Check if x/y limits are OK. */
 283         if (var->xres - 1 > HACTIVE_MASK) {
 284                 WRN_MSG("X resolution too large (%d vs %d).\n",
 285                         var->xres, HACTIVE_MASK + 1);
 286                 return 1;
 287         }
 288         if (var->yres - 1 > VACTIVE_MASK) {
 289                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 290                         var->yres, VACTIVE_MASK + 1);
 291                 return 1;
 292         }
 293
 294         /* Check for interlaced/doublescan modes. */
 295         if (var->vmode & FB_VMODE_INTERLACED) {
 296                 WRN_MSG("Mode is interlaced.\n");
 297                 return 1;
 298         }
 299         if (var->vmode & FB_VMODE_DOUBLE) {
 300                 WRN_MSG("Mode is double-scan.\n");
 301                 return 1;
 302         }
 303
 304         /* Check if clock is OK. */
 305         tmp = 1000000000 / var->pixclock;
 306         if (tmp < MIN_CLOCK) {
 307                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 308                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 309                 return 1;
 310         }
 311         if (tmp > MAX_CLOCK) {
 312                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 313                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 314                 return 1;
 315         }
 316
 317         return 0;
 318 }
 319
 320 int
 321 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 322 {
 323         struct intelfb_info *dinfo = GET_DINFO(info);
 324         u32 offset, xoffset, yoffset;
 325
 326 #if VERBOSE > 0
 327         DBG_MSG("intelfbhw_pan_display\n");
 328 #endif
 329
 330         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 331         yoffset = var->yoffset;
 332
 333         if ((xoffset + var->xres > var->xres_virtual) ||
 334             (yoffset + var->yres > var->yres_virtual))
 335                 return -EINVAL;
 336
 337         offset = (yoffset * dinfo->pitch) +
 338                  (xoffset * var->bits_per_pixel) / 8;
 339
 340         offset += dinfo->fb.offset << 12;
 341
 342         OUTREG(DSPABASE, offset);
 343
 344         return 0;
 345 }
 346
 347 /* Blank the screen. */
 348 void
 349 intelfbhw_do_blank(int blank, struct fb_info *info)
 350 {
 351         struct intelfb_info *dinfo = GET_DINFO(info);
 352         u32 tmp;
 353
 354 #if VERBOSE > 0
 355         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 356 #endif
 357
 358         /* Turn plane A on or off */
 359         tmp = INREG(DSPACNTR);
 360         if (blank)
 361                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 362         else
 363                 tmp |= DISPPLANE_PLANE_ENABLE;
 364         OUTREG(DSPACNTR, tmp);
 365         /* Flush */
 366         tmp = INREG(DSPABASE);
 367         OUTREG(DSPABASE, tmp);
 368
 369         /* Turn off/on the HW cursor */
 370 #if VERBOSE > 0
 371         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 372 #endif
 373         if (dinfo->cursor_on) {
 374                 if (blank) {
 375                         intelfbhw_cursor_hide(dinfo);
 376                 } else {
 377                         intelfbhw_cursor_show(dinfo);
 378                 }
 379                 dinfo->cursor_on = 1;
 380         }
 381         dinfo->cursor_blanked = blank;
 382
 383         /* Set DPMS level */
 384         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 385         switch (blank) {
 386         case FB_BLANK_UNBLANK:
 387         case FB_BLANK_NORMAL:
 388                 tmp |= ADPA_DPMS_D0;
 389                 break;
 390         case FB_BLANK_VSYNC_SUSPEND:
 391                 tmp |= ADPA_DPMS_D1;
 392                 break;
 393         case FB_BLANK_HSYNC_SUSPEND:
 394                 tmp |= ADPA_DPMS_D2;
 395                 break;
 396         case FB_BLANK_POWERDOWN:
 397                 tmp |= ADPA_DPMS_D3;
 398                 break;
 399         }
 400         OUTREG(ADPA, tmp);
 401
 402         return;
 403 }
 404
 405
 406 void
 407 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 408                     unsigned red, unsigned green, unsigned blue,
 409                     unsigned transp)
 410 {
 411 #if VERBOSE > 0
 412         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 413                 regno, red, green, blue);
 414 #endif
 415
 416         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 417                           PALETTE_A : PALETTE_B;
 418
 419         OUTREG(palette_reg + (regno << 2),
 420                (red << PALETTE_8_RED_SHIFT) |
 421                (green << PALETTE_8_GREEN_SHIFT) |
 422                (blue << PALETTE_8_BLUE_SHIFT));
 423 }
 424
 425
 426 int
 427 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 428                         int flag)
 429 {
 430         int i;
 431
 432 #if VERBOSE > 0
 433         DBG_MSG("intelfbhw_read_hw_state\n");
 434 #endif
 435
 436         if (!hw || !dinfo)
 437                 return -1;
 438
 439         /* Read in as much of the HW state as possible. */
 440         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 441         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 442         hw->vga_pd = INREG(VGAPD);
 443         hw->dpll_a = INREG(DPLL_A);
 444         hw->dpll_b = INREG(DPLL_B);
 445         hw->fpa0 = INREG(FPA0);
 446         hw->fpa1 = INREG(FPA1);
 447         hw->fpb0 = INREG(FPB0);
 448         hw->fpb1 = INREG(FPB1);
 449
 450         if (flag == 1)
 451                 return flag;
 452
 453 #if 0
 454         /* This seems to be a problem with the 852GM/855GM */
 455         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 456                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 457                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 458         }
 459 #endif
 460
 461         if (flag == 2)
 462                 return flag;
 463
 464         hw->htotal_a = INREG(HTOTAL_A);
 465         hw->hblank_a = INREG(HBLANK_A);
 466         hw->hsync_a = INREG(HSYNC_A);
 467         hw->vtotal_a = INREG(VTOTAL_A);
 468         hw->vblank_a = INREG(VBLANK_A);
 469         hw->vsync_a = INREG(VSYNC_A);
 470         hw->src_size_a = INREG(SRC_SIZE_A);
 471         hw->bclrpat_a = INREG(BCLRPAT_A);
 472         hw->htotal_b = INREG(HTOTAL_B);
 473         hw->hblank_b = INREG(HBLANK_B);
 474         hw->hsync_b = INREG(HSYNC_B);
 475         hw->vtotal_b = INREG(VTOTAL_B);
 476         hw->vblank_b = INREG(VBLANK_B);
 477         hw->vsync_b = INREG(VSYNC_B);
 478         hw->src_size_b = INREG(SRC_SIZE_B);
 479         hw->bclrpat_b = INREG(BCLRPAT_B);
 480
 481         if (flag == 3)
 482                 return flag;
 483
 484         hw->adpa = INREG(ADPA);
 485         hw->dvoa = INREG(DVOA);
 486         hw->dvob = INREG(DVOB);
 487         hw->dvoc = INREG(DVOC);
 488         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 489         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 490         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 491         hw->lvds = INREG(LVDS);
 492
 493         if (flag == 4)
 494                 return flag;
 495
 496         hw->pipe_a_conf = INREG(PIPEACONF);
 497         hw->pipe_b_conf = INREG(PIPEBCONF);
 498         hw->disp_arb = INREG(DISPARB);
 499
 500         if (flag == 5)
 501                 return flag;
 502
 503         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 504         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 505         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 506         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 507
 508         if (flag == 6)
 509                 return flag;
 510
 511         for (i = 0; i < 4; i++) {
 512                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 513                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 514         }
 515
 516         if (flag == 7)
 517                 return flag;
 518
 519         hw->cursor_size = INREG(CURSOR_SIZE);
 520
 521         if (flag == 8)
 522                 return flag;
 523
 524         hw->disp_a_ctrl = INREG(DSPACNTR);
 525         hw->disp_b_ctrl = INREG(DSPBCNTR);
 526         hw->disp_a_base = INREG(DSPABASE);
 527         hw->disp_b_base = INREG(DSPBBASE);
 528         hw->disp_a_stride = INREG(DSPASTRIDE);
 529         hw->disp_b_stride = INREG(DSPBSTRIDE);
 530
 531         if (flag == 9)
 532                 return flag;
 533
 534         hw->vgacntrl = INREG(VGACNTRL);
 535
 536         if (flag == 10)
 537                 return flag;
 538
 539         hw->add_id = INREG(ADD_ID);
 540
 541         if (flag == 11)
 542                 return flag;
 543
 544         for (i = 0; i < 7; i++) {
 545                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 546                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 547                 if (i < 3)
 548                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 549         }
 550
 551         for (i = 0; i < 8; i++)
 552                 hw->fence[i] = INREG(FENCE + (i << 2));
 553
 554         hw->instpm = INREG(INSTPM);
 555         hw->mem_mode = INREG(MEM_MODE);
 556         hw->fw_blc_0 = INREG(FW_BLC_0);
 557         hw->fw_blc_1 = INREG(FW_BLC_1);
 558
 559         return 0;
 560 }
 561
 562
 563 static int calc_vclock3(int index, int m, int n, int p)
 564 {
 565         if (p == 0 || n == 0)
 566                 return 0;
 567         return PLL_REFCLK * m / n / p;
 568 }
 569
 570 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
 571 {
 572         switch(index)
 573         {
 574         case PLLS_I9xx:
 575                 if (p1 == 0)
 576                         return 0;
 577                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 578                          ((p1)) * (p2 ? 10 : 5)));
 579         case PLLS_I8xx:
 580         default:
 581                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 582                          ((p1+2) * (1 << (p2 + 1)))));
 583         }
 584 }
 585
 586 void
 587 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 588 {
 589 #if REGDUMP
 590         int i, m1, m2, n, p1, p2;
 591         int index = dinfo->pll_index;
 592         DBG_MSG("intelfbhw_print_hw_state\n");
 593
 594         if (!hw || !dinfo)
 595                 return;
 596         /* Read in as much of the HW state as possible. */
 597         printk("hw state dump start\n");
 598         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 599         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 600         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 601         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 602         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 603         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 604         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 605                 p1 = 0;
 606         else
 607                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 608         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 609         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 610                m1, m2, n, p1, p2);
 611         printk("        VGA0: clock is %d\n",
 612                calc_vclock(index, m1, m2, n, p1, p2));
 613
 614         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 615         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 616         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 617         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 618                 p1 = 0;
 619         else
 620                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 621         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 622         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 623                m1, m2, n, p1, p2);
 624         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 625
 626         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 627         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 628         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 629         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 630         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 631         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 632
 633         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 634         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 635         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 636         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 637                 p1 = 0;
 638         else
 639                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 640         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 641         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 642                m1, m2, n, p1, p2);
 643         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 644
 645         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 646         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 647         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 648         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 649                 p1 = 0;
 650         else
 651                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 652         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 653         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 654                m1, m2, n, p1, p2);
 655         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 656
 657 #if 0
 658         printk("        PALETTE_A:\n");
 659         for (i = 0; i < PALETTE_8_ENTRIES)
 660                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 661         printk("        PALETTE_B:\n");
 662         for (i = 0; i < PALETTE_8_ENTRIES)
 663                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 664 #endif
 665
 666         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 667         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 668         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 669         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 670         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 671         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 672         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 673         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 674         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 675         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 676         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 677         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 678         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 679         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 680         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 681         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 682
 683         printk("        ADPA:                   0x%08x\n", hw->adpa);
 684         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 685         printk("        DVOB:                   0x%08x\n", hw->dvob);
 686         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 687         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 688         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 689         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 690         printk("        LVDS:                   0x%08x\n", hw->lvds);
 691
 692         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 693         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 694         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 695
 696         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 697         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 698         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 699         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 700
 701         printk("        CURSOR_A_PALETTE:       ");
 702         for (i = 0; i < 4; i++) {
 703                 printk("0x%08x", hw->cursor_a_palette[i]);
 704                 if (i < 3)
 705                         printk(", ");
 706         }
 707         printk("\n");
 708         printk("        CURSOR_B_PALETTE:       ");
 709         for (i = 0; i < 4; i++) {
 710                 printk("0x%08x", hw->cursor_b_palette[i]);
 711                 if (i < 3)
 712                         printk(", ");
 713         }
 714         printk("\n");
 715
 716         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 717
 718         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 719         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 720         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 721         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 722         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 723         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 724
 725         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 726         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 727
 728         for (i = 0; i < 7; i++) {
 729                 printk("        SWF0%d                  0x%08x\n", i,
 730                         hw->swf0x[i]);
 731         }
 732         for (i = 0; i < 7; i++) {
 733                 printk("        SWF1%d                  0x%08x\n", i,
 734                         hw->swf1x[i]);
 735         }
 736         for (i = 0; i < 3; i++) {
 737                 printk("        SWF3%d                  0x%08x\n", i,
 738                        hw->swf3x[i]);
 739         }
 740         for (i = 0; i < 8; i++)
 741                 printk("        FENCE%d                 0x%08x\n", i,
 742                        hw->fence[i]);
 743
 744         printk("        INSTPM                  0x%08x\n", hw->instpm);
 745         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 746         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 747         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 748
 749         printk("hw state dump end\n");
 750 #endif
 751 }
 752
 753
 754
 755 /* Split the M parameter into M1 and M2. */
 756 static int
 757 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 758 {
 759         int m1, m2;
 760         int testm;
 761         /* no point optimising too much - brute force m */
 762         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
 763         {
 764           for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
 765           {
 766             testm  = ( 5 * ( m1 + 2 )) + (m2 + 2);
 767             if (testm == m)
 768             {
 769                 *retm1 = (unsigned int)m1;
 770                 *retm2 = (unsigned int)m2;
 771                 return 0;
 772             }
 773           }
 774         }
 775         return 1;
 776 }
 777
 778 /* Split the P parameter into P1 and P2. */
 779 static int
 780 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 781 {
 782         int p1, p2;
 783
 784         if (index == PLLS_I9xx)
 785         {
 786                 switch (p) {
 787                 case 10:
 788                         p1 = 2;
 789                         p2 = 0;
 790                         break;
 791                 case 20:
 792                         p1 = 1;
 793                         p2 = 0;
 794                         break;
 795                 default:
 796                         p1 = (p / 10) + 1;
 797                         p2 = 0;
 798                         break;
 799                 }
 800
 801                 *retp1 = (unsigned int)p1;
 802                 *retp2 = (unsigned int)p2;
 803                 return 0;
 804         }
 805
 806         if (index == PLLS_I8xx)
 807         {
 808                 if (p % 4 == 0)
 809                         p2 = 1;
 810                 else
 811                         p2 = 0;
 812                 p1 = (p / (1 << (p2 + 1))) - 2;
 813                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 814                         p2 = 0;
 815                         p1 = (p / (1 << (p2 + 1))) - 2;
 816                 }
 817                 if (p1  < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
 818                         return 1;
 819                 } else {
 820                         *retp1 = (unsigned int)p1;
 821                         *retp2 = (unsigned int)p2;
 822                         return 0;
 823                 }
 824         }
 825         return 1;
 826 }
 827
 828 static int
 829 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 830                 u32 *retp2, u32 *retclock)
 831 {
 832         u32 m1, m2, n, p1, p2, n1, testm;
 833         u32 f_vco, p, p_best = 0, m, f_out = 0;
 834         u32 err_max, err_target, err_best = 10000000;
 835         u32 n_best = 0, m_best = 0, f_best, f_err;
 836         u32 p_min, p_max, p_inc, div_min, div_max;
 837
 838         /* Accept 0.5% difference, but aim for 0.1% */
 839         err_max = 5 * clock / 1000;
 840         err_target = clock / 1000;
 841
 842         DBG_MSG("Clock is %d\n", clock);
 843
 844         div_max = plls[index].max_vco_freq / clock;
 845         if (index == PLLS_I9xx)
 846                 div_min = 5;
 847         else
 848                 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 849
 850         if (clock <= plls[index].p_transition_clock)
 851                 p_inc = plls[index].p_inc_lo;
 852         else
 853                 p_inc = plls[index].p_inc_hi;
 854         p_min = ROUND_UP_TO(div_min, p_inc);
 855         p_max = ROUND_DOWN_TO(div_max, p_inc);
 856         if (p_min < plls[index].min_p)
 857                 p_min = plls[index].min_p;
 858         if (p_max > plls[index].max_p)
 859                 p_max = plls[index].max_p;
 860
 861         if (clock < PLL_REFCLK && index==PLLS_I9xx)
 862         {
 863           p_min = 10;
 864           p_max = 20;
 865           /* this makes 640x480 work it really shouldn't
 866              - SOMEONE WITHOUT DOCS WOZ HERE */
 867           if (clock < 30000)
 868             clock *= 4;
 869         }
 870
 871         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 872
 873         p = p_min;
 874         do {
 875                 if (splitp(index, p, &p1, &p2)) {
 876                         WRN_MSG("cannot split p = %d\n", p);
 877                         p += p_inc;
 878                         continue;
 879                 }
 880                 n = plls[index].min_n;
 881                 f_vco = clock * p;
 882
 883                 do {
 884                         m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
 885                         if (m < plls[index].min_m)
 886                                 m = plls[index].min_m + 1;
 887                         if (m > plls[index].max_m)
 888                                 m = plls[index].max_m - 1;
 889                         for (testm = m - 1; testm <= m; testm++) {
 890                                 f_out = calc_vclock3(index, m, n, p);
 891                                 if (splitm(index, m, &m1, &m2)) {
 892                                         WRN_MSG("cannot split m = %d\n", m);
 893                                         n++;
 894                                         continue;
 895                                 }
 896                                 if (clock > f_out)
 897                                         f_err = clock - f_out;
 898                                 else/* slightly bias the error for bigger clocks */
 899                                         f_err = f_out - clock + 1;
 900
 901                                 if (f_err < err_best) {
 902                                         m_best = m;
 903                                         n_best = n;
 904                                         p_best = p;
 905                                         f_best = f_out;
 906                                         err_best = f_err;
 907                                 }
 908                         }
 909                         n++;
 910                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 911                 p += p_inc;
 912         } while ((p <= p_max));
 913
 914         if (!m_best) {
 915                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 916                 return 1;
 917         }
 918         m = m_best;
 919         n = n_best;
 920         p = p_best;
 921         splitm(index, m, &m1, &m2);
 922         splitp(index, p, &p1, &p2);
 923         n1 = n - 2;
 924
 925         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 926                 "f: %d (%d), VCO: %d\n",
 927                 m, m1, m2, n, n1, p, p1, p2,
 928                 calc_vclock3(index, m, n, p),
 929                 calc_vclock(index, m1, m2, n1, p1, p2),
 930                 calc_vclock3(index, m, n, p) * p);
 931         *retm1 = m1;
 932         *retm2 = m2;
 933         *retn = n1;
 934         *retp1 = p1;
 935         *retp2 = p2;
 936         *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
 937
 938         return 0;
 939 }
 940
 941 static __inline__ int
 942 check_overflow(u32 value, u32 limit, const char *description)
 943 {
 944         if (value > limit) {
 945                 WRN_MSG("%s value %d exceeds limit %d\n",
 946                         description, value, limit);
 947                 return 1;
 948         }
 949         return 0;
 950 }
 951
 952 /* It is assumed that hw is filled in with the initial state information. */
 953 int
 954 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 955                      struct fb_var_screeninfo *var)
 956 {
 957         int pipe = PIPE_A;
 958         u32 *dpll, *fp0, *fp1;
 959         u32 m1, m2, n, p1, p2, clock_target, clock;
 960         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 961         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 962         u32 vsync_pol, hsync_pol;
 963         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 964
 965         DBG_MSG("intelfbhw_mode_to_hw\n");
 966
 967         /* Disable VGA */
 968         hw->vgacntrl |= VGA_DISABLE;
 969
 970         /* Check whether pipe A or pipe B is enabled. */
 971         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 972                 pipe = PIPE_A;
 973         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
 974                 pipe = PIPE_B;
 975
 976         /* Set which pipe's registers will be set. */
 977         if (pipe == PIPE_B) {
 978                 dpll = &hw->dpll_b;
 979                 fp0 = &hw->fpb0;
 980                 fp1 = &hw->fpb1;
 981                 hs = &hw->hsync_b;
 982                 hb = &hw->hblank_b;
 983                 ht = &hw->htotal_b;
 984                 vs = &hw->vsync_b;
 985                 vb = &hw->vblank_b;
 986                 vt = &hw->vtotal_b;
 987                 ss = &hw->src_size_b;
 988                 pipe_conf = &hw->pipe_b_conf;
 989         } else {
 990                 dpll = &hw->dpll_a;
 991                 fp0 = &hw->fpa0;
 992                 fp1 = &hw->fpa1;
 993                 hs = &hw->hsync_a;
 994                 hb = &hw->hblank_a;
 995                 ht = &hw->htotal_a;
 996                 vs = &hw->vsync_a;
 997                 vb = &hw->vblank_a;
 998                 vt = &hw->vtotal_a;
 999                 ss = &hw->src_size_a;
1000                 pipe_conf = &hw->pipe_a_conf;
1001         }
1002
1003         /* Use ADPA register for sync control. */
1004         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1005
1006         /* sync polarity */
1007         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1008                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1009         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1010                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1011         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1012                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1013         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1014                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1015
1016         /* Connect correct pipe to the analog port DAC */
1017         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1018         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1019
1020         /* Set DPMS state to D0 (on) */
1021         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1022         hw->adpa |= ADPA_DPMS_D0;
1023
1024         hw->adpa |= ADPA_DAC_ENABLE;
1025
1026         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1027         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1028         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1029
1030         /* Desired clock in kHz */
1031         clock_target = 1000000000 / var->pixclock;
1032
1033         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
1034                 WRN_MSG("calc_pll_params failed\n");
1035                 return 1;
1036         }
1037
1038         /* Check for overflow. */
1039         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1040                 return 1;
1041         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1042                 return 1;
1043         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1044                 return 1;
1045         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1046                 return 1;
1047         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1048                 return 1;
1049
1050         *dpll &= ~DPLL_P1_FORCE_DIV2;
1051         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1052                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1053         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1054         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1055                (m1 << FP_M1_DIVISOR_SHIFT) |
1056                (m2 << FP_M2_DIVISOR_SHIFT);
1057         *fp1 = *fp0;
1058
1059         hw->dvob &= ~PORT_ENABLE;
1060         hw->dvoc &= ~PORT_ENABLE;
1061
1062         /* Use display plane A. */
1063         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1064         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1065         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1066         switch (intelfb_var_to_depth(var)) {
1067         case 8:
1068                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1069                 break;
1070         case 15:
1071                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1072                 break;
1073         case 16:
1074                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1075                 break;
1076         case 24:
1077                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1078                 break;
1079         }
1080         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1081         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1082
1083         /* Set CRTC registers. */
1084         hactive = var->xres;
1085         hsync_start = hactive + var->right_margin;
1086         hsync_end = hsync_start + var->hsync_len;
1087         htotal = hsync_end + var->left_margin;
1088         hblank_start = hactive;
1089         hblank_end = htotal;
1090
1091         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1092                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1093                 hblank_end);
1094
1095         vactive = var->yres;
1096         vsync_start = vactive + var->lower_margin;
1097         vsync_end = vsync_start + var->vsync_len;
1098         vtotal = vsync_end + var->upper_margin;
1099         vblank_start = vactive;
1100         vblank_end = vtotal;
1101         vblank_end = vsync_end + 1;
1102
1103         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1104                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1105                 vblank_end);
1106
1107         /* Adjust for register values, and check for overflow. */
1108         hactive--;
1109         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1110                 return 1;
1111         hsync_start--;
1112         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1113                 return 1;
1114         hsync_end--;
1115         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1116                 return 1;
1117         htotal--;
1118         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1119                 return 1;
1120         hblank_start--;
1121         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1122                 return 1;
1123         hblank_end--;
1124         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1125                 return 1;
1126
1127         vactive--;
1128         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1129                 return 1;
1130         vsync_start--;
1131         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1132                 return 1;
1133         vsync_end--;
1134         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1135                 return 1;
1136         vtotal--;
1137         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1138                 return 1;
1139         vblank_start--;
1140         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1141                 return 1;
1142         vblank_end--;
1143         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1144                 return 1;
1145
1146         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1147         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1148               (hblank_end << HSYNCEND_SHIFT);
1149         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1150
1151         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1152         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1153               (vblank_end << VSYNCEND_SHIFT);
1154         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1155         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1156               (vactive << SRC_SIZE_VERT_SHIFT);
1157
1158         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1159         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1160
1161         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1162                           var->xoffset * var->bits_per_pixel / 8;
1163
1164         hw->disp_a_base += dinfo->fb.offset << 12;
1165
1166         /* Check stride alignment. */
1167         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1168                 WRN_MSG("display stride %d has bad alignment %d\n",
1169                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1170                 return 1;
1171         }
1172
1173         /* Set the palette to 8-bit mode. */
1174         *pipe_conf &= ~PIPECONF_GAMMA;
1175         return 0;
1176 }
1177
1178 /* Program a (non-VGA) video mode. */
1179 int
1180 intelfbhw_program_mode(struct intelfb_info *dinfo,
1181                      const struct intelfb_hwstate *hw, int blank)
1182 {
1183         int pipe = PIPE_A;
1184         u32 tmp;
1185         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1186         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1187         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1188         u32 hsync_reg, htotal_reg, hblank_reg;
1189         u32 vsync_reg, vtotal_reg, vblank_reg;
1190         u32 src_size_reg;
1191         u32 count, tmp_val[3];
1192
1193         /* Assume single pipe, display plane A, analog CRT. */
1194
1195 #if VERBOSE > 0
1196         DBG_MSG("intelfbhw_program_mode\n");
1197 #endif
1198
1199         /* Disable VGA */
1200         tmp = INREG(VGACNTRL);
1201         tmp |= VGA_DISABLE;
1202         OUTREG(VGACNTRL, tmp);
1203
1204         /* Check whether pipe A or pipe B is enabled. */
1205         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1206                 pipe = PIPE_A;
1207         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1208                 pipe = PIPE_B;
1209
1210         dinfo->pipe = pipe;
1211
1212         if (pipe == PIPE_B) {
1213                 dpll = &hw->dpll_b;
1214                 fp0 = &hw->fpb0;
1215                 fp1 = &hw->fpb1;
1216                 pipe_conf = &hw->pipe_b_conf;
1217                 hs = &hw->hsync_b;
1218                 hb = &hw->hblank_b;
1219                 ht = &hw->htotal_b;
1220                 vs = &hw->vsync_b;
1221                 vb = &hw->vblank_b;
1222                 vt = &hw->vtotal_b;
1223                 ss = &hw->src_size_b;
1224                 dpll_reg = DPLL_B;
1225                 fp0_reg = FPB0;
1226                 fp1_reg = FPB1;
1227                 pipe_conf_reg = PIPEBCONF;
1228                 hsync_reg = HSYNC_B;
1229                 htotal_reg = HTOTAL_B;
1230                 hblank_reg = HBLANK_B;
1231                 vsync_reg = VSYNC_B;
1232                 vtotal_reg = VTOTAL_B;
1233                 vblank_reg = VBLANK_B;
1234                 src_size_reg = SRC_SIZE_B;
1235         } else {
1236                 dpll = &hw->dpll_a;
1237                 fp0 = &hw->fpa0;
1238                 fp1 = &hw->fpa1;
1239                 pipe_conf = &hw->pipe_a_conf;
1240                 hs = &hw->hsync_a;
1241                 hb = &hw->hblank_a;
1242                 ht = &hw->htotal_a;
1243                 vs = &hw->vsync_a;
1244                 vb = &hw->vblank_a;
1245                 vt = &hw->vtotal_a;
1246                 ss = &hw->src_size_a;
1247                 dpll_reg = DPLL_A;
1248                 fp0_reg = FPA0;
1249                 fp1_reg = FPA1;
1250                 pipe_conf_reg = PIPEACONF;
1251                 hsync_reg = HSYNC_A;
1252                 htotal_reg = HTOTAL_A;
1253                 hblank_reg = HBLANK_A;
1254                 vsync_reg = VSYNC_A;
1255                 vtotal_reg = VTOTAL_A;
1256                 vblank_reg = VBLANK_A;
1257                 src_size_reg = SRC_SIZE_A;
1258         }
1259
1260         /* turn off pipe */
1261         tmp = INREG(pipe_conf_reg);
1262         tmp &= ~PIPECONF_ENABLE;
1263         OUTREG(pipe_conf_reg, tmp);
1264
1265         count = 0;
1266         do{
1267           tmp_val[count%3] = INREG(0x70000);
1268           if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1269             break;
1270           count++;
1271           udelay(1);
1272           if (count % 200 == 0)
1273           {
1274             tmp = INREG(pipe_conf_reg);
1275             tmp &= ~PIPECONF_ENABLE;
1276             OUTREG(pipe_conf_reg, tmp);
1277           }
1278         } while(count < 2000);
1279
1280         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1281
1282         /* Disable planes A and B. */
1283         tmp = INREG(DSPACNTR);
1284         tmp &= ~DISPPLANE_PLANE_ENABLE;
1285         OUTREG(DSPACNTR, tmp);
1286         tmp = INREG(DSPBCNTR);
1287         tmp &= ~DISPPLANE_PLANE_ENABLE;
1288         OUTREG(DSPBCNTR, tmp);
1289
1290         /* Wait for vblank.  For now, just wait for a 50Hz cycle (20ms)) */
1291         mdelay(20);
1292
1293         /* Disable Sync */
1294         tmp = INREG(ADPA);
1295         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1296         tmp |= ADPA_DPMS_D3;
1297         OUTREG(ADPA, tmp);
1298
1299         /* do some funky magic - xyzzy */
1300         OUTREG(0x61204, 0xabcd0000);
1301
1302         /* turn off PLL */
1303         tmp = INREG(dpll_reg);
1304         dpll_reg &= ~DPLL_VCO_ENABLE;
1305         OUTREG(dpll_reg, tmp);
1306
1307         /* Set PLL parameters */
1308         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1309         OUTREG(fp0_reg, *fp0);
1310         OUTREG(fp1_reg, *fp1);
1311
1312         /* Enable PLL */
1313         tmp = INREG(dpll_reg);
1314         tmp |= DPLL_VCO_ENABLE;
1315         OUTREG(dpll_reg, tmp);
1316
1317         /* Set DVOs B/C */
1318         OUTREG(DVOB, hw->dvob);
1319         OUTREG(DVOC, hw->dvoc);
1320
1321         /* undo funky magic */
1322         OUTREG(0x61204, 0x00000000);
1323
1324         /* Set ADPA */
1325         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1326         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1327
1328         /* Set pipe parameters */
1329         OUTREG(hsync_reg, *hs);
1330         OUTREG(hblank_reg, *hb);
1331         OUTREG(htotal_reg, *ht);
1332         OUTREG(vsync_reg, *vs);
1333         OUTREG(vblank_reg, *vb);
1334         OUTREG(vtotal_reg, *vt);
1335         OUTREG(src_size_reg, *ss);
1336
1337         /* Enable pipe */
1338         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1339
1340         /* Enable sync */
1341         tmp = INREG(ADPA);
1342         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1343         tmp |= ADPA_DPMS_D0;
1344         OUTREG(ADPA, tmp);
1345
1346         /* setup display plane */
1347         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1348                 /*
1349                  *      i830M errata: the display plane must be enabled
1350                  *      to allow writes to the other bits in the plane
1351                  *      control register.
1352                  */
1353                 tmp = INREG(DSPACNTR);
1354                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1355                         tmp |= DISPPLANE_PLANE_ENABLE;
1356                         OUTREG(DSPACNTR, tmp);
1357                         OUTREG(DSPACNTR,
1358                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1359                         mdelay(1);
1360               }
1361         }
1362
1363         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1364         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1365         OUTREG(DSPABASE, hw->disp_a_base);
1366
1367         /* Enable plane */
1368         if (!blank) {
1369                 tmp = INREG(DSPACNTR);
1370                 tmp |= DISPPLANE_PLANE_ENABLE;
1371                 OUTREG(DSPACNTR, tmp);
1372                 OUTREG(DSPABASE, hw->disp_a_base);
1373         }
1374
1375         return 0;
1376 }
1377
1378 /* forward declarations */
1379 static void refresh_ring(struct intelfb_info *dinfo);
1380 static void reset_state(struct intelfb_info *dinfo);
1381 static void do_flush(struct intelfb_info *dinfo);
1382
1383 static int
1384 wait_ring(struct intelfb_info *dinfo, int n)
1385 {
1386         int i = 0;
1387         unsigned long end;
1388         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1389
1390 #if VERBOSE > 0
1391         DBG_MSG("wait_ring: %d\n", n);
1392 #endif
1393
1394         end = jiffies + (HZ * 3);
1395         while (dinfo->ring_space < n) {
1396                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1397                                                    RING_HEAD_MASK);
1398                 if (dinfo->ring_tail + RING_MIN_FREE <
1399                     (u32 __iomem) dinfo->ring_head)
1400                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1401                                 - (dinfo->ring_tail + RING_MIN_FREE);
1402                 else
1403                         dinfo->ring_space = (dinfo->ring.size +
1404                                              (u32 __iomem) dinfo->ring_head)
1405                                 - (dinfo->ring_tail + RING_MIN_FREE);
1406                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1407                         end = jiffies + (HZ * 3);
1408                         last_head = (u32 __iomem) dinfo->ring_head;
1409                 }
1410                 i++;
1411                 if (time_before(end, jiffies)) {
1412                         if (!i) {
1413                                 /* Try again */
1414                                 reset_state(dinfo);
1415                                 refresh_ring(dinfo);
1416                                 do_flush(dinfo);
1417                                 end = jiffies + (HZ * 3);
1418                                 i = 1;
1419                         } else {
1420                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1421                                         dinfo->ring_space, n);
1422                                 WRN_MSG("lockup - turning off hardware "
1423                                         "acceleration\n");
1424                                 dinfo->ring_lockup = 1;
1425                                 break;
1426                         }
1427                 }
1428                 udelay(1);
1429         }
1430         return i;
1431 }
1432
1433 static void
1434 do_flush(struct intelfb_info *dinfo) {
1435         START_RING(2);
1436         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1437         OUT_RING(MI_NOOP);
1438         ADVANCE_RING();
1439 }
1440
1441 void
1442 intelfbhw_do_sync(struct intelfb_info *dinfo)
1443 {
1444 #if VERBOSE > 0
1445         DBG_MSG("intelfbhw_do_sync\n");
1446 #endif
1447
1448         if (!dinfo->accel)
1449                 return;
1450
1451         /*
1452          * Send a flush, then wait until the ring is empty.  This is what
1453          * the XFree86 driver does, and actually it doesn't seem a lot worse
1454          * than the recommended method (both have problems).
1455          */
1456         do_flush(dinfo);
1457         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1458         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1459 }
1460
1461 static void
1462 refresh_ring(struct intelfb_info *dinfo)
1463 {
1464 #if VERBOSE > 0
1465         DBG_MSG("refresh_ring\n");
1466 #endif
1467
1468         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1469                                            RING_HEAD_MASK);
1470         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1471         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1472                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1473                         - (dinfo->ring_tail + RING_MIN_FREE);
1474         else
1475                 dinfo->ring_space = (dinfo->ring.size +
1476                                      (u32 __iomem) dinfo->ring_head)
1477                         - (dinfo->ring_tail + RING_MIN_FREE);
1478 }
1479
1480 static void
1481 reset_state(struct intelfb_info *dinfo)
1482 {
1483         int i;
1484         u32 tmp;
1485
1486 #if VERBOSE > 0
1487         DBG_MSG("reset_state\n");
1488 #endif
1489
1490         for (i = 0; i < FENCE_NUM; i++)
1491                 OUTREG(FENCE + (i << 2), 0);
1492
1493         /* Flush the ring buffer if it's enabled. */
1494         tmp = INREG(PRI_RING_LENGTH);
1495         if (tmp & RING_ENABLE) {
1496 #if VERBOSE > 0
1497                 DBG_MSG("reset_state: ring was enabled\n");
1498 #endif
1499                 refresh_ring(dinfo);
1500                 intelfbhw_do_sync(dinfo);
1501                 DO_RING_IDLE();
1502         }
1503
1504         OUTREG(PRI_RING_LENGTH, 0);
1505         OUTREG(PRI_RING_HEAD, 0);
1506         OUTREG(PRI_RING_TAIL, 0);
1507         OUTREG(PRI_RING_START, 0);
1508 }
1509
1510 /* Stop the 2D engine, and turn off the ring buffer. */
1511 void
1512 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1513 {
1514 #if VERBOSE > 0
1515         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1516                 dinfo->ring_active);
1517 #endif
1518
1519         if (!dinfo->accel)
1520                 return;
1521
1522         dinfo->ring_active = 0;
1523         reset_state(dinfo);
1524 }
1525
1526 /*
1527  * Enable the ring buffer, and initialise the 2D engine.
1528  * It is assumed that the graphics engine has been stopped by previously
1529  * calling intelfb_2d_stop().
1530  */
1531 void
1532 intelfbhw_2d_start(struct intelfb_info *dinfo)
1533 {
1534 #if VERBOSE > 0
1535         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1536                 dinfo->accel, dinfo->ring_active);
1537 #endif
1538
1539         if (!dinfo->accel)
1540                 return;
1541
1542         /* Initialise the primary ring buffer. */
1543         OUTREG(PRI_RING_LENGTH, 0);
1544         OUTREG(PRI_RING_TAIL, 0);
1545         OUTREG(PRI_RING_HEAD, 0);
1546
1547         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1548         OUTREG(PRI_RING_LENGTH,
1549                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1550                 RING_NO_REPORT | RING_ENABLE);
1551         refresh_ring(dinfo);
1552         dinfo->ring_active = 1;
1553 }
1554
1555 /* 2D fillrect (solid fill or invert) */
1556 void
1557 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1558                       u32 color, u32 pitch, u32 bpp, u32 rop)
1559 {
1560         u32 br00, br09, br13, br14, br16;
1561
1562 #if VERBOSE > 0
1563         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1564                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1565 #endif
1566
1567         br00 = COLOR_BLT_CMD;
1568         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1569         br13 = (rop << ROP_SHIFT) | pitch;
1570         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1571         br16 = color;
1572
1573         switch (bpp) {
1574         case 8:
1575                 br13 |= COLOR_DEPTH_8;
1576                 break;
1577         case 16:
1578                 br13 |= COLOR_DEPTH_16;
1579                 break;
1580         case 32:
1581                 br13 |= COLOR_DEPTH_32;
1582                 br00 |= WRITE_ALPHA | WRITE_RGB;
1583                 break;
1584         }
1585
1586         START_RING(6);
1587         OUT_RING(br00);
1588         OUT_RING(br13);
1589         OUT_RING(br14);
1590         OUT_RING(br09);
1591         OUT_RING(br16);
1592         OUT_RING(MI_NOOP);
1593         ADVANCE_RING();
1594
1595 #if VERBOSE > 0
1596         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1597                 dinfo->ring_tail, dinfo->ring_space);
1598 #endif
1599 }
1600
1601 void
1602 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1603                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1604 {
1605         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1606
1607 #if VERBOSE > 0
1608         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1609                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1610 #endif
1611
1612         br00 = XY_SRC_COPY_BLT_CMD;
1613         br09 = dinfo->fb_start;
1614         br11 = (pitch << PITCH_SHIFT);
1615         br12 = dinfo->fb_start;
1616         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1617         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1618         br23 = ((dstx + w) << WIDTH_SHIFT) |
1619                ((dsty + h) << HEIGHT_SHIFT);
1620         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1621
1622         switch (bpp) {
1623         case 8:
1624                 br13 |= COLOR_DEPTH_8;
1625                 break;
1626         case 16:
1627                 br13 |= COLOR_DEPTH_16;
1628                 break;
1629         case 32:
1630                 br13 |= COLOR_DEPTH_32;
1631                 br00 |= WRITE_ALPHA | WRITE_RGB;
1632                 break;
1633         }
1634
1635         START_RING(8);
1636         OUT_RING(br00);
1637         OUT_RING(br13);
1638         OUT_RING(br22);
1639         OUT_RING(br23);
1640         OUT_RING(br09);
1641         OUT_RING(br26);
1642         OUT_RING(br11);
1643         OUT_RING(br12);
1644         ADVANCE_RING();
1645 }
1646
1647 int
1648 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1649                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1650 {
1651         int nbytes, ndwords, pad, tmp;
1652         u32 br00, br09, br13, br18, br19, br22, br23;
1653         int dat, ix, iy, iw;
1654         int i, j;
1655
1656 #if VERBOSE > 0
1657         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1658 #endif
1659
1660         /* size in bytes of a padded scanline */
1661         nbytes = ROUND_UP_TO(w, 16) / 8;
1662
1663         /* Total bytes of padded scanline data to write out. */
1664         nbytes = nbytes * h;
1665
1666         /*
1667          * Check if the glyph data exceeds the immediate mode limit.
1668          * It would take a large font (1K pixels) to hit this limit.
1669          */
1670         if (nbytes > MAX_MONO_IMM_SIZE)
1671                 return 0;
1672
1673         /* Src data is packaged a dword (32-bit) at a time. */
1674         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1675
1676         /*
1677          * Ring has to be padded to a quad word. But because the command starts
1678            with 7 bytes, pad only if there is an even number of ndwords
1679          */
1680         pad = !(ndwords % 2);
1681
1682         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1683         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1684         br09 = dinfo->fb_start;
1685         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1686         br18 = bg;
1687         br19 = fg;
1688         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1689         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1690
1691         switch (bpp) {
1692         case 8:
1693                 br13 |= COLOR_DEPTH_8;
1694                 break;
1695         case 16:
1696                 br13 |= COLOR_DEPTH_16;
1697                 break;
1698         case 32:
1699                 br13 |= COLOR_DEPTH_32;
1700                 br00 |= WRITE_ALPHA | WRITE_RGB;
1701                 break;
1702         }
1703
1704         START_RING(8 + ndwords);
1705         OUT_RING(br00);
1706         OUT_RING(br13);
1707         OUT_RING(br22);
1708         OUT_RING(br23);
1709         OUT_RING(br09);
1710         OUT_RING(br18);
1711         OUT_RING(br19);
1712         ix = iy = 0;
1713         iw = ROUND_UP_TO(w, 8) / 8;
1714         while (ndwords--) {
1715                 dat = 0;
1716                 for (j = 0; j < 2; ++j) {
1717                         for (i = 0; i < 2; ++i) {
1718                                 if (ix != iw || i == 0)
1719                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1720                         }
1721                         if (ix == iw && iy != (h-1)) {
1722                                 ix = 0;
1723                                 ++iy;
1724                         }
1725                 }
1726                 OUT_RING(dat);
1727         }
1728         if (pad)
1729                 OUT_RING(MI_NOOP);
1730         ADVANCE_RING();
1731
1732         return 1;
1733 }
1734
1735 /* HW cursor functions. */
1736 void
1737 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1738 {
1739         u32 tmp;
1740
1741 #if VERBOSE > 0
1742         DBG_MSG("intelfbhw_cursor_init\n");
1743 #endif
1744
1745         if (dinfo->mobile || IS_I9xx(dinfo)) {
1746                 if (!dinfo->cursor.physical)
1747                         return;
1748                 tmp = INREG(CURSOR_A_CONTROL);
1749                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1750                          CURSOR_MEM_TYPE_LOCAL |
1751                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1752                 tmp |= CURSOR_MODE_DISABLE;
1753                 OUTREG(CURSOR_A_CONTROL, tmp);
1754                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1755         } else {
1756                 tmp = INREG(CURSOR_CONTROL);
1757                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1758                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1759                 tmp = CURSOR_FORMAT_3C;
1760                 OUTREG(CURSOR_CONTROL, tmp);
1761                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1762                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1763                       (64 << CURSOR_SIZE_V_SHIFT);
1764                 OUTREG(CURSOR_SIZE, tmp);
1765         }
1766 }
1767
1768 void
1769 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1770 {
1771         u32 tmp;
1772
1773 #if VERBOSE > 0
1774         DBG_MSG("intelfbhw_cursor_hide\n");
1775 #endif
1776
1777         dinfo->cursor_on = 0;
1778         if (dinfo->mobile || IS_I9xx(dinfo)) {
1779                 if (!dinfo->cursor.physical)
1780                         return;
1781                 tmp = INREG(CURSOR_A_CONTROL);
1782                 tmp &= ~CURSOR_MODE_MASK;
1783                 tmp |= CURSOR_MODE_DISABLE;
1784                 OUTREG(CURSOR_A_CONTROL, tmp);
1785                 /* Flush changes */
1786                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1787         } else {
1788                 tmp = INREG(CURSOR_CONTROL);
1789                 tmp &= ~CURSOR_ENABLE;
1790                 OUTREG(CURSOR_CONTROL, tmp);
1791         }
1792 }
1793
1794 void
1795 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1796 {
1797         u32 tmp;
1798
1799 #if VERBOSE > 0
1800         DBG_MSG("intelfbhw_cursor_show\n");
1801 #endif
1802
1803         dinfo->cursor_on = 1;
1804
1805         if (dinfo->cursor_blanked)
1806                 return;
1807
1808         if (dinfo->mobile || IS_I9xx(dinfo)) {
1809                 if (!dinfo->cursor.physical)
1810                         return;
1811                 tmp = INREG(CURSOR_A_CONTROL);
1812                 tmp &= ~CURSOR_MODE_MASK;
1813                 tmp |= CURSOR_MODE_64_4C_AX;
1814                 OUTREG(CURSOR_A_CONTROL, tmp);
1815                 /* Flush changes */
1816                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1817         } else {
1818                 tmp = INREG(CURSOR_CONTROL);
1819                 tmp |= CURSOR_ENABLE;
1820                 OUTREG(CURSOR_CONTROL, tmp);
1821         }
1822 }
1823
1824 void
1825 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1826 {
1827         u32 tmp;
1828
1829 #if VERBOSE > 0
1830         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1831 #endif
1832
1833         /*
1834          * Sets the position.  The coordinates are assumed to already
1835          * have any offset adjusted.  Assume that the cursor is never
1836          * completely off-screen, and that x, y are always >= 0.
1837          */
1838
1839         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1840               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1841         OUTREG(CURSOR_A_POSITION, tmp);
1842
1843         if (IS_I9xx(dinfo)) {
1844                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1845         }
1846 }
1847
1848 void
1849 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1850 {
1851 #if VERBOSE > 0
1852         DBG_MSG("intelfbhw_cursor_setcolor\n");
1853 #endif
1854
1855         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1856         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1857         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1858         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1859 }
1860
1861 void
1862 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1863                       u8 *data)
1864 {
1865         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1866         int i, j, w = width / 8;
1867         int mod = width % 8, t_mask, d_mask;
1868
1869 #if VERBOSE > 0
1870         DBG_MSG("intelfbhw_cursor_load\n");
1871 #endif
1872
1873         if (!dinfo->cursor.virtual)
1874                 return;
1875
1876         t_mask = 0xff >> mod;
1877         d_mask = ~(0xff >> mod);
1878         for (i = height; i--; ) {
1879                 for (j = 0; j < w; j++) {
1880                         writeb(0x00, addr + j);
1881                         writeb(*(data++), addr + j+8);
1882                 }
1883                 if (mod) {
1884                         writeb(t_mask, addr + j);
1885                         writeb(*(data++) & d_mask, addr + j+8);
1886                 }
1887                 addr += 16;
1888         }
1889 }
1890
1891 void
1892 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1893         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1894         int i, j;
1895
1896 #if VERBOSE > 0
1897         DBG_MSG("intelfbhw_cursor_reset\n");
1898 #endif
1899
1900         if (!dinfo->cursor.virtual)
1901                 return;
1902
1903         for (i = 64; i--; ) {
1904                 for (j = 0; j < 8; j++) {
1905                         writeb(0xff, addr + j+0);
1906                         writeb(0x00, addr + j+8);
1907                 }
1908                 addr += 16;
1909         }
1910 }