SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco_freq, max_vco_freq;
  51         int p_transition_clock;
  52         int p_inc_lo, p_inc_hi;
  53 };
  54
  55 #define PLLS_I8xx 0
  56 #define PLLS_I9xx 1
  57 #define PLLS_MAX 2
  58
  59 struct pll_min_max plls[PLLS_MAX] = {
  60         { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
  61         {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 }  //I9xx
  62 };
  63
  64 int
  65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  66 {
  67         u32 tmp;
  68         if (!pdev || !dinfo)
  69                 return 1;
  70
  71         switch (pdev->device) {
  72         case PCI_DEVICE_ID_INTEL_830M:
  73                 dinfo->name = "Intel(R) 830M";
  74                 dinfo->chipset = INTEL_830M;
  75                 dinfo->mobile = 1;
  76                 dinfo->pll_index = PLLS_I8xx;
  77                 return 0;
  78         case PCI_DEVICE_ID_INTEL_845G:
  79                 dinfo->name = "Intel(R) 845G";
  80                 dinfo->chipset = INTEL_845G;
  81                 dinfo->mobile = 0;
  82                 dinfo->pll_index = PLLS_I8xx;
  83                 return 0;
  84         case PCI_DEVICE_ID_INTEL_85XGM:
  85                 tmp = 0;
  86                 dinfo->mobile = 1;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  89                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  90                         INTEL_85X_VARIANT_MASK) {
  91                 case INTEL_VAR_855GME:
  92                         dinfo->name = "Intel(R) 855GME";
  93                         dinfo->chipset = INTEL_855GME;
  94                         return 0;
  95                 case INTEL_VAR_855GM:
  96                         dinfo->name = "Intel(R) 855GM";
  97                         dinfo->chipset = INTEL_855GM;
  98                         return 0;
  99                 case INTEL_VAR_852GME:
 100                         dinfo->name = "Intel(R) 852GME";
 101                         dinfo->chipset = INTEL_852GME;
 102                         return 0;
 103                 case INTEL_VAR_852GM:
 104                         dinfo->name = "Intel(R) 852GM";
 105                         dinfo->chipset = INTEL_852GM;
 106                         return 0;
 107                 default:
 108                         dinfo->name = "Intel(R) 852GM/855GM";
 109                         dinfo->chipset = INTEL_85XGM;
 110                         return 0;
 111                 }
 112                 break;
 113         case PCI_DEVICE_ID_INTEL_865G:
 114                 dinfo->name = "Intel(R) 865G";
 115                 dinfo->chipset = INTEL_865G;
 116                 dinfo->mobile = 0;
 117                 dinfo->pll_index = PLLS_I8xx;
 118                 return 0;
 119         case PCI_DEVICE_ID_INTEL_915G:
 120                 dinfo->name = "Intel(R) 915G";
 121                 dinfo->chipset = INTEL_915G;
 122                 dinfo->mobile = 0;
 123                 dinfo->pll_index = PLLS_I9xx;
 124                 return 0;
 125         case PCI_DEVICE_ID_INTEL_915GM:
 126                 dinfo->name = "Intel(R) 915GM";
 127                 dinfo->chipset = INTEL_915GM;
 128                 dinfo->mobile = 1;
 129                 dinfo->pll_index = PLLS_I9xx;
 130                 return 0;
 131         case PCI_DEVICE_ID_INTEL_945G:
 132                 dinfo->name = "Intel(R) 945G";
 133                 dinfo->chipset = INTEL_945G;
 134                 dinfo->mobile = 0;
 135                 dinfo->pll_index = PLLS_I9xx;
 136                 return 0;
 137         default:
 138                 return 1;
 139         }
 140 }
 141
 142 int
 143 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 144                      int *stolen_size)
 145 {
 146         struct pci_dev *bridge_dev;
 147         u16 tmp;
 148
 149         if (!pdev || !aperture_size || !stolen_size)
 150                 return 1;
 151
 152         /* Find the bridge device.  It is always 0:0.0 */
 153         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 154                 ERR_MSG("cannot find bridge device\n");
 155                 return 1;
 156         }
 157
 158         /* Get the fb aperture size and "stolen" memory amount. */
 159         tmp = 0;
 160         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 161         switch (pdev->device) {
 162         case PCI_DEVICE_ID_INTEL_830M:
 163         case PCI_DEVICE_ID_INTEL_845G:
 164                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 165                         *aperture_size = MB(64);
 166                 else
 167                         *aperture_size = MB(128);
 168                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 169                 case INTEL_830_GMCH_GMS_STOLEN_512:
 170                         *stolen_size = KB(512) - KB(132);
 171                         return 0;
 172                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 173                         *stolen_size = MB(1) - KB(132);
 174                         return 0;
 175                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 176                         *stolen_size = MB(8) - KB(132);
 177                         return 0;
 178                 case INTEL_830_GMCH_GMS_LOCAL:
 179                         ERR_MSG("only local memory found\n");
 180                         return 1;
 181                 case INTEL_830_GMCH_GMS_DISABLED:
 182                         ERR_MSG("video memory is disabled\n");
 183                         return 1;
 184                 default:
 185                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 186                                 tmp & INTEL_830_GMCH_GMS_MASK);
 187                         return 1;
 188                 }
 189                 break;
 190         default:
 191                 *aperture_size = MB(128);
 192                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 193                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 194                         *stolen_size = MB(1) - KB(132);
 195                         return 0;
 196                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 197                         *stolen_size = MB(4) - KB(132);
 198                         return 0;
 199                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 200                         *stolen_size = MB(8) - KB(132);
 201                         return 0;
 202                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 203                         *stolen_size = MB(16) - KB(132);
 204                         return 0;
 205                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 206                         *stolen_size = MB(32) - KB(132);
 207                         return 0;
 208                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 209                         *stolen_size = MB(48) - KB(132);
 210                         return 0;
 211                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 212                         *stolen_size = MB(64) - KB(132);
 213                         return 0;
 214                 case INTEL_855_GMCH_GMS_DISABLED:
 215                         ERR_MSG("video memory is disabled\n");
 216                         return 0;
 217                 default:
 218                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 219                                 tmp & INTEL_855_GMCH_GMS_MASK);
 220                         return 1;
 221                 }
 222         }
 223 }
 224
 225 int
 226 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 227 {
 228         int dvo = 0;
 229
 230         if (INREG(LVDS) & PORT_ENABLE)
 231                 dvo |= LVDS_PORT;
 232         if (INREG(DVOA) & PORT_ENABLE)
 233                 dvo |= DVOA_PORT;
 234         if (INREG(DVOB) & PORT_ENABLE)
 235                 dvo |= DVOB_PORT;
 236         if (INREG(DVOC) & PORT_ENABLE)
 237                 dvo |= DVOC_PORT;
 238
 239         return dvo;
 240 }
 241
 242 const char *
 243 intelfbhw_dvo_to_string(int dvo)
 244 {
 245         if (dvo & DVOA_PORT)
 246                 return "DVO port A";
 247         else if (dvo & DVOB_PORT)
 248                 return "DVO port B";
 249         else if (dvo & DVOC_PORT)
 250                 return "DVO port C";
 251         else if (dvo & LVDS_PORT)
 252                 return "LVDS port";
 253         else
 254                 return NULL;
 255 }
 256
 257
 258 int
 259 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 260                         struct fb_var_screeninfo *var)
 261 {
 262         int bytes_per_pixel;
 263         int tmp;
 264
 265 #if VERBOSE > 0
 266         DBG_MSG("intelfbhw_validate_mode\n");
 267 #endif
 268
 269         bytes_per_pixel = var->bits_per_pixel / 8;
 270         if (bytes_per_pixel == 3)
 271                 bytes_per_pixel = 4;
 272
 273         /* Check if enough video memory. */
 274         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 275         if (tmp > dinfo->fb.size) {
 276                 WRN_MSG("Not enough video ram for mode "
 277                         "(%d KByte vs %d KByte).\n",
 278                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 279                 return 1;
 280         }
 281
 282         /* Check if x/y limits are OK. */
 283         if (var->xres - 1 > HACTIVE_MASK) {
 284                 WRN_MSG("X resolution too large (%d vs %d).\n",
 285                         var->xres, HACTIVE_MASK + 1);
 286                 return 1;
 287         }
 288         if (var->yres - 1 > VACTIVE_MASK) {
 289                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 290                         var->yres, VACTIVE_MASK + 1);
 291                 return 1;
 292         }
 293
 294         /* Check for interlaced/doublescan modes. */
 295         if (var->vmode & FB_VMODE_INTERLACED) {
 296                 WRN_MSG("Mode is interlaced.\n");
 297                 return 1;
 298         }
 299         if (var->vmode & FB_VMODE_DOUBLE) {
 300                 WRN_MSG("Mode is double-scan.\n");
 301                 return 1;
 302         }
 303
 304         /* Check if clock is OK. */
 305         tmp = 1000000000 / var->pixclock;
 306         if (tmp < MIN_CLOCK) {
 307                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 308                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 309                 return 1;
 310         }
 311         if (tmp > MAX_CLOCK) {
 312                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 313                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 314                 return 1;
 315         }
 316
 317         return 0;
 318 }
 319
 320 int
 321 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 322 {
 323         struct intelfb_info *dinfo = GET_DINFO(info);
 324         u32 offset, xoffset, yoffset;
 325
 326 #if VERBOSE > 0
 327         DBG_MSG("intelfbhw_pan_display\n");
 328 #endif
 329
 330         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 331         yoffset = var->yoffset;
 332
 333         if ((xoffset + var->xres > var->xres_virtual) ||
 334             (yoffset + var->yres > var->yres_virtual))
 335                 return -EINVAL;
 336
 337         offset = (yoffset * dinfo->pitch) +
 338                  (xoffset * var->bits_per_pixel) / 8;
 339
 340         offset += dinfo->fb.offset << 12;
 341
 342         OUTREG(DSPABASE, offset);
 343
 344         return 0;
 345 }
 346
 347 /* Blank the screen. */
 348 void
 349 intelfbhw_do_blank(int blank, struct fb_info *info)
 350 {
 351         struct intelfb_info *dinfo = GET_DINFO(info);
 352         u32 tmp;
 353
 354 #if VERBOSE > 0
 355         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 356 #endif
 357
 358         /* Turn plane A on or off */
 359         tmp = INREG(DSPACNTR);
 360         if (blank)
 361                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 362         else
 363                 tmp |= DISPPLANE_PLANE_ENABLE;
 364         OUTREG(DSPACNTR, tmp);
 365         /* Flush */
 366         tmp = INREG(DSPABASE);
 367         OUTREG(DSPABASE, tmp);
 368
 369         /* Turn off/on the HW cursor */
 370 #if VERBOSE > 0
 371         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 372 #endif
 373         if (dinfo->cursor_on) {
 374                 if (blank) {
 375                         intelfbhw_cursor_hide(dinfo);
 376                 } else {
 377                         intelfbhw_cursor_show(dinfo);
 378                 }
 379                 dinfo->cursor_on = 1;
 380         }
 381         dinfo->cursor_blanked = blank;
 382
 383         /* Set DPMS level */
 384         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 385         switch (blank) {
 386         case FB_BLANK_UNBLANK:
 387         case FB_BLANK_NORMAL:
 388                 tmp |= ADPA_DPMS_D0;
 389                 break;
 390         case FB_BLANK_VSYNC_SUSPEND:
 391                 tmp |= ADPA_DPMS_D1;
 392                 break;
 393         case FB_BLANK_HSYNC_SUSPEND:
 394                 tmp |= ADPA_DPMS_D2;
 395                 break;
 396         case FB_BLANK_POWERDOWN:
 397                 tmp |= ADPA_DPMS_D3;
 398                 break;
 399         }
 400         OUTREG(ADPA, tmp);
 401
 402         return;
 403 }
 404
 405
 406 void
 407 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 408                     unsigned red, unsigned green, unsigned blue,
 409                     unsigned transp)
 410 {
 411 #if VERBOSE > 0
 412         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 413                 regno, red, green, blue);
 414 #endif
 415
 416         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 417                           PALETTE_A : PALETTE_B;
 418
 419         OUTREG(palette_reg + (regno << 2),
 420                (red << PALETTE_8_RED_SHIFT) |
 421                (green << PALETTE_8_GREEN_SHIFT) |
 422                (blue << PALETTE_8_BLUE_SHIFT));
 423 }
 424
 425
 426 int
 427 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 428                         int flag)
 429 {
 430         int i;
 431
 432 #if VERBOSE > 0
 433         DBG_MSG("intelfbhw_read_hw_state\n");
 434 #endif
 435
 436         if (!hw || !dinfo)
 437                 return -1;
 438
 439         /* Read in as much of the HW state as possible. */
 440         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 441         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 442         hw->vga_pd = INREG(VGAPD);
 443         hw->dpll_a = INREG(DPLL_A);
 444         hw->dpll_b = INREG(DPLL_B);
 445         hw->fpa0 = INREG(FPA0);
 446         hw->fpa1 = INREG(FPA1);
 447         hw->fpb0 = INREG(FPB0);
 448         hw->fpb1 = INREG(FPB1);
 449
 450         if (flag == 1)
 451                 return flag;
 452
 453 #if 0
 454         /* This seems to be a problem with the 852GM/855GM */
 455         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 456                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 457                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 458         }
 459 #endif
 460
 461         if (flag == 2)
 462                 return flag;
 463
 464         hw->htotal_a = INREG(HTOTAL_A);
 465         hw->hblank_a = INREG(HBLANK_A);
 466         hw->hsync_a = INREG(HSYNC_A);
 467         hw->vtotal_a = INREG(VTOTAL_A);
 468         hw->vblank_a = INREG(VBLANK_A);
 469         hw->vsync_a = INREG(VSYNC_A);
 470         hw->src_size_a = INREG(SRC_SIZE_A);
 471         hw->bclrpat_a = INREG(BCLRPAT_A);
 472         hw->htotal_b = INREG(HTOTAL_B);
 473         hw->hblank_b = INREG(HBLANK_B);
 474         hw->hsync_b = INREG(HSYNC_B);
 475         hw->vtotal_b = INREG(VTOTAL_B);
 476         hw->vblank_b = INREG(VBLANK_B);
 477         hw->vsync_b = INREG(VSYNC_B);
 478         hw->src_size_b = INREG(SRC_SIZE_B);
 479         hw->bclrpat_b = INREG(BCLRPAT_B);
 480
 481         if (flag == 3)
 482                 return flag;
 483
 484         hw->adpa = INREG(ADPA);
 485         hw->dvoa = INREG(DVOA);
 486         hw->dvob = INREG(DVOB);
 487         hw->dvoc = INREG(DVOC);
 488         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 489         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 490         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 491         hw->lvds = INREG(LVDS);
 492
 493         if (flag == 4)
 494                 return flag;
 495
 496         hw->pipe_a_conf = INREG(PIPEACONF);
 497         hw->pipe_b_conf = INREG(PIPEBCONF);
 498         hw->disp_arb = INREG(DISPARB);
 499
 500         if (flag == 5)
 501                 return flag;
 502
 503         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 504         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 505         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 506         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 507
 508         if (flag == 6)
 509                 return flag;
 510
 511         for (i = 0; i < 4; i++) {
 512                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 513                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 514         }
 515
 516         if (flag == 7)
 517                 return flag;
 518
 519         hw->cursor_size = INREG(CURSOR_SIZE);
 520
 521         if (flag == 8)
 522                 return flag;
 523
 524         hw->disp_a_ctrl = INREG(DSPACNTR);
 525         hw->disp_b_ctrl = INREG(DSPBCNTR);
 526         hw->disp_a_base = INREG(DSPABASE);
 527         hw->disp_b_base = INREG(DSPBBASE);
 528         hw->disp_a_stride = INREG(DSPASTRIDE);
 529         hw->disp_b_stride = INREG(DSPBSTRIDE);
 530
 531         if (flag == 9)
 532                 return flag;
 533
 534         hw->vgacntrl = INREG(VGACNTRL);
 535
 536         if (flag == 10)
 537                 return flag;
 538
 539         hw->add_id = INREG(ADD_ID);
 540
 541         if (flag == 11)
 542                 return flag;
 543
 544         for (i = 0; i < 7; i++) {
 545                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 546                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 547                 if (i < 3)
 548                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 549         }
 550
 551         for (i = 0; i < 8; i++)
 552                 hw->fence[i] = INREG(FENCE + (i << 2));
 553
 554         hw->instpm = INREG(INSTPM);
 555         hw->mem_mode = INREG(MEM_MODE);
 556         hw->fw_blc_0 = INREG(FW_BLC_0);
 557         hw->fw_blc_1 = INREG(FW_BLC_1);
 558
 559         return 0;
 560 }
 561
 562
 563 static int calc_vclock3(int index, int m, int n, int p)
 564 {
 565         if (p == 0 || n == 0)
 566                 return 0;
 567         return PLL_REFCLK * m / n / p;
 568 }
 569
 570 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
 571 {
 572         switch(index)
 573         {
 574         case PLLS_I9xx:
 575                 if (p1 == 0)
 576                         return 0;
 577                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 578                          ((p1)) * (p2 ? 10 : 5)));
 579         case PLLS_I8xx:
 580         default:
 581                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 582                          ((p1+2) * (1 << (p2 + 1)))));
 583         }
 584 }
 585
 586 void
 587 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 588 {
 589 #if REGDUMP
 590         int i, m1, m2, n, p1, p2;
 591         int index = dinfo->pll_index;
 592         DBG_MSG("intelfbhw_print_hw_state\n");
 593
 594         if (!hw || !dinfo)
 595                 return;
 596         /* Read in as much of the HW state as possible. */
 597         printk("hw state dump start\n");
 598         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 599         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 600         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 601         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 602         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 603         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 604         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 605                 p1 = 0;
 606         else
 607                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 608         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 609         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 610                m1, m2, n, p1, p2);
 611         printk("        VGA0: clock is %d\n",
 612                calc_vclock(index, m1, m2, n, p1, p2));
 613
 614         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 615         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 616         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 617         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 618                 p1 = 0;
 619         else
 620                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 621         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 622         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 623                m1, m2, n, p1, p2);
 624         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 625
 626         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 627         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 628         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 629         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 630         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 631         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 632
 633         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 634         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 635         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 636         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 637                 p1 = 0;
 638         else
 639                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 640         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 641         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 642                m1, m2, n, p1, p2);
 643         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 644
 645         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 646         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 647         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 648         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 649                 p1 = 0;
 650         else
 651                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 652         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 653         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 654                m1, m2, n, p1, p2);
 655         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 656
 657 #if 0
 658         printk("        PALETTE_A:\n");
 659         for (i = 0; i < PALETTE_8_ENTRIES)
 660                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 661         printk("        PALETTE_B:\n");
 662         for (i = 0; i < PALETTE_8_ENTRIES)
 663                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 664 #endif
 665
 666         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 667         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 668         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 669         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 670         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 671         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 672         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 673         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 674         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 675         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 676         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 677         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 678         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 679         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 680         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 681         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 682
 683         printk("        ADPA:                   0x%08x\n", hw->adpa);
 684         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 685         printk("        DVOB:                   0x%08x\n", hw->dvob);
 686         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 687         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 688         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 689         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 690         printk("        LVDS:                   0x%08x\n", hw->lvds);
 691
 692         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 693         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 694         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 695
 696         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 697         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 698         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 699         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 700
 701         printk("        CURSOR_A_PALETTE:       ");
 702         for (i = 0; i < 4; i++) {
 703                 printk("0x%08x", hw->cursor_a_palette[i]);
 704                 if (i < 3)
 705                         printk(", ");
 706         }
 707         printk("\n");
 708         printk("        CURSOR_B_PALETTE:       ");
 709         for (i = 0; i < 4; i++) {
 710                 printk("0x%08x", hw->cursor_b_palette[i]);
 711                 if (i < 3)
 712                         printk(", ");
 713         }
 714         printk("\n");
 715
 716         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 717
 718         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 719         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 720         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 721         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 722         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 723         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 724
 725         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 726         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 727
 728         for (i = 0; i < 7; i++) {
 729                 printk("        SWF0%d                  0x%08x\n", i,
 730                         hw->swf0x[i]);
 731         }
 732         for (i = 0; i < 7; i++) {
 733                 printk("        SWF1%d                  0x%08x\n", i,
 734                         hw->swf1x[i]);
 735         }
 736         for (i = 0; i < 3; i++) {
 737                 printk("        SWF3%d                  0x%08x\n", i,
 738                        hw->swf3x[i]);
 739         }
 740         for (i = 0; i < 8; i++)
 741                 printk("        FENCE%d                 0x%08x\n", i,
 742                        hw->fence[i]);
 743
 744         printk("        INSTPM                  0x%08x\n", hw->instpm);
 745         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 746         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 747         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 748
 749         printk("hw state dump end\n");
 750 #endif
 751 }
 752
 753
 754
 755 /* Split the M parameter into M1 and M2. */
 756 static int
 757 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 758 {
 759         int m1, m2;
 760         int testm;
 761         /* no point optimising too much - brute force m */
 762         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 763                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 764                         testm  = ( 5 * ( m1 + 2 )) + (m2 + 2);
 765                         if (testm == m) {
 766                                 *retm1 = (unsigned int)m1;
 767                                 *retm2 = (unsigned int)m2;
 768                                 return 0;
 769                         }
 770                 }
 771         }
 772         return 1;
 773 }
 774
 775 /* Split the P parameter into P1 and P2. */
 776 static int
 777 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 778 {
 779         int p1, p2;
 780
 781         if (index == PLLS_I9xx) {
 782                 switch (p) {
 783                 case 10:
 784                         p1 = 2;
 785                         p2 = 0;
 786                         break;
 787                 case 20:
 788                         p1 = 1;
 789                         p2 = 0;
 790                         break;
 791                 default:
 792                         p1 = (p / 10) + 1;
 793                         p2 = 0;
 794                         break;
 795                 }
 796
 797                 *retp1 = (unsigned int)p1;
 798                 *retp2 = (unsigned int)p2;
 799                 return 0;
 800         }
 801
 802         if (index == PLLS_I8xx) {
 803                 if (p % 4 == 0)
 804                         p2 = 1;
 805                 else
 806                         p2 = 0;
 807                 p1 = (p / (1 << (p2 + 1))) - 2;
 808                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 809                         p2 = 0;
 810                         p1 = (p / (1 << (p2 + 1))) - 2;
 811                 }
 812                 if (p1 < plls[index].min_p1 ||
 813                     p1 > plls[index].max_p1 ||
 814                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 815                         return 1;
 816                 } else {
 817                         *retp1 = (unsigned int)p1;
 818                         *retp2 = (unsigned int)p2;
 819                         return 0;
 820                 }
 821         }
 822         return 1;
 823 }
 824
 825 static int
 826 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 827                 u32 *retp2, u32 *retclock)
 828 {
 829         u32 m1, m2, n, p1, p2, n1, testm;
 830         u32 f_vco, p, p_best = 0, m, f_out = 0;
 831         u32 err_max, err_target, err_best = 10000000;
 832         u32 n_best = 0, m_best = 0, f_best, f_err;
 833         u32 p_min, p_max, p_inc, div_min, div_max;
 834
 835         /* Accept 0.5% difference, but aim for 0.1% */
 836         err_max = 5 * clock / 1000;
 837         err_target = clock / 1000;
 838
 839         DBG_MSG("Clock is %d\n", clock);
 840
 841         div_max = plls[index].max_vco_freq / clock;
 842         if (index == PLLS_I9xx)
 843                 div_min = 5;
 844         else
 845                 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 846
 847         if (clock <= plls[index].p_transition_clock)
 848                 p_inc = plls[index].p_inc_lo;
 849         else
 850                 p_inc = plls[index].p_inc_hi;
 851         p_min = ROUND_UP_TO(div_min, p_inc);
 852         p_max = ROUND_DOWN_TO(div_max, p_inc);
 853         if (p_min < plls[index].min_p)
 854                 p_min = plls[index].min_p;
 855         if (p_max > plls[index].max_p)
 856                 p_max = plls[index].max_p;
 857
 858         if (clock < PLL_REFCLK && index == PLLS_I9xx) {
 859                 p_min = 10;
 860                 p_max = 20;
 861                 /* this makes 640x480 work it really shouldn't
 862                    - SOMEONE WITHOUT DOCS WOZ HERE */
 863                 if (clock < 30000)
 864                         clock *= 4;
 865         }
 866
 867         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 868
 869         p = p_min;
 870         do {
 871                 if (splitp(index, p, &p1, &p2)) {
 872                         WRN_MSG("cannot split p = %d\n", p);
 873                         p += p_inc;
 874                         continue;
 875                 }
 876                 n = plls[index].min_n;
 877                 f_vco = clock * p;
 878
 879                 do {
 880                         m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
 881                         if (m < plls[index].min_m)
 882                                 m = plls[index].min_m + 1;
 883                         if (m > plls[index].max_m)
 884                                 m = plls[index].max_m - 1;
 885                         for (testm = m - 1; testm <= m; testm++) {
 886                                 f_out = calc_vclock3(index, m, n, p);
 887                                 if (splitm(index, m, &m1, &m2)) {
 888                                         WRN_MSG("cannot split m = %d\n", m);
 889                                         n++;
 890                                         continue;
 891                                 }
 892                                 if (clock > f_out)
 893                                         f_err = clock - f_out;
 894                                 else/* slightly bias the error for bigger clocks */
 895                                         f_err = f_out - clock + 1;
 896
 897                                 if (f_err < err_best) {
 898                                         m_best = m;
 899                                         n_best = n;
 900                                         p_best = p;
 901                                         f_best = f_out;
 902                                         err_best = f_err;
 903                                 }
 904                         }
 905                         n++;
 906                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 907                 p += p_inc;
 908         } while ((p <= p_max));
 909
 910         if (!m_best) {
 911                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 912                 return 1;
 913         }
 914         m = m_best;
 915         n = n_best;
 916         p = p_best;
 917         splitm(index, m, &m1, &m2);
 918         splitp(index, p, &p1, &p2);
 919         n1 = n - 2;
 920
 921         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 922                 "f: %d (%d), VCO: %d\n",
 923                 m, m1, m2, n, n1, p, p1, p2,
 924                 calc_vclock3(index, m, n, p),
 925                 calc_vclock(index, m1, m2, n1, p1, p2),
 926                 calc_vclock3(index, m, n, p) * p);
 927         *retm1 = m1;
 928         *retm2 = m2;
 929         *retn = n1;
 930         *retp1 = p1;
 931         *retp2 = p2;
 932         *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
 933
 934         return 0;
 935 }
 936
 937 static __inline__ int
 938 check_overflow(u32 value, u32 limit, const char *description)
 939 {
 940         if (value > limit) {
 941                 WRN_MSG("%s value %d exceeds limit %d\n",
 942                         description, value, limit);
 943                 return 1;
 944         }
 945         return 0;
 946 }
 947
 948 /* It is assumed that hw is filled in with the initial state information. */
 949 int
 950 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 951                      struct fb_var_screeninfo *var)
 952 {
 953         int pipe = PIPE_A;
 954         u32 *dpll, *fp0, *fp1;
 955         u32 m1, m2, n, p1, p2, clock_target, clock;
 956         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 957         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 958         u32 vsync_pol, hsync_pol;
 959         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 960
 961         DBG_MSG("intelfbhw_mode_to_hw\n");
 962
 963         /* Disable VGA */
 964         hw->vgacntrl |= VGA_DISABLE;
 965
 966         /* Check whether pipe A or pipe B is enabled. */
 967         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 968                 pipe = PIPE_A;
 969         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
 970                 pipe = PIPE_B;
 971
 972         /* Set which pipe's registers will be set. */
 973         if (pipe == PIPE_B) {
 974                 dpll = &hw->dpll_b;
 975                 fp0 = &hw->fpb0;
 976                 fp1 = &hw->fpb1;
 977                 hs = &hw->hsync_b;
 978                 hb = &hw->hblank_b;
 979                 ht = &hw->htotal_b;
 980                 vs = &hw->vsync_b;
 981                 vb = &hw->vblank_b;
 982                 vt = &hw->vtotal_b;
 983                 ss = &hw->src_size_b;
 984                 pipe_conf = &hw->pipe_b_conf;
 985         } else {
 986                 dpll = &hw->dpll_a;
 987                 fp0 = &hw->fpa0;
 988                 fp1 = &hw->fpa1;
 989                 hs = &hw->hsync_a;
 990                 hb = &hw->hblank_a;
 991                 ht = &hw->htotal_a;
 992                 vs = &hw->vsync_a;
 993                 vb = &hw->vblank_a;
 994                 vt = &hw->vtotal_a;
 995                 ss = &hw->src_size_a;
 996                 pipe_conf = &hw->pipe_a_conf;
 997         }
 998
 999         /* Use ADPA register for sync control. */
1000         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1001
1002         /* sync polarity */
1003         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1004                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1005         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1006                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1007         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1008                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1009         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1010                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1011
1012         /* Connect correct pipe to the analog port DAC */
1013         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1014         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1015
1016         /* Set DPMS state to D0 (on) */
1017         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1018         hw->adpa |= ADPA_DPMS_D0;
1019
1020         hw->adpa |= ADPA_DAC_ENABLE;
1021
1022         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1023         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1024         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1025
1026         /* Desired clock in kHz */
1027         clock_target = 1000000000 / var->pixclock;
1028
1029         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1030                             &n, &p1, &p2, &clock)) {
1031                 WRN_MSG("calc_pll_params failed\n");
1032                 return 1;
1033         }
1034
1035         /* Check for overflow. */
1036         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1037                 return 1;
1038         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1039                 return 1;
1040         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1041                 return 1;
1042         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1043                 return 1;
1044         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1045                 return 1;
1046
1047         *dpll &= ~DPLL_P1_FORCE_DIV2;
1048         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1049                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1050         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1051         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1052                (m1 << FP_M1_DIVISOR_SHIFT) |
1053                (m2 << FP_M2_DIVISOR_SHIFT);
1054         *fp1 = *fp0;
1055
1056         hw->dvob &= ~PORT_ENABLE;
1057         hw->dvoc &= ~PORT_ENABLE;
1058
1059         /* Use display plane A. */
1060         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1061         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1062         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1063         switch (intelfb_var_to_depth(var)) {
1064         case 8:
1065                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1066                 break;
1067         case 15:
1068                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1069                 break;
1070         case 16:
1071                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1072                 break;
1073         case 24:
1074                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1075                 break;
1076         }
1077         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1078         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1079
1080         /* Set CRTC registers. */
1081         hactive = var->xres;
1082         hsync_start = hactive + var->right_margin;
1083         hsync_end = hsync_start + var->hsync_len;
1084         htotal = hsync_end + var->left_margin;
1085         hblank_start = hactive;
1086         hblank_end = htotal;
1087
1088         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1089                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1090                 hblank_end);
1091
1092         vactive = var->yres;
1093         vsync_start = vactive + var->lower_margin;
1094         vsync_end = vsync_start + var->vsync_len;
1095         vtotal = vsync_end + var->upper_margin;
1096         vblank_start = vactive;
1097         vblank_end = vtotal;
1098         vblank_end = vsync_end + 1;
1099
1100         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1101                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1102                 vblank_end);
1103
1104         /* Adjust for register values, and check for overflow. */
1105         hactive--;
1106         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1107                 return 1;
1108         hsync_start--;
1109         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1110                 return 1;
1111         hsync_end--;
1112         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1113                 return 1;
1114         htotal--;
1115         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1116                 return 1;
1117         hblank_start--;
1118         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1119                 return 1;
1120         hblank_end--;
1121         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1122                 return 1;
1123
1124         vactive--;
1125         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1126                 return 1;
1127         vsync_start--;
1128         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1129                 return 1;
1130         vsync_end--;
1131         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1132                 return 1;
1133         vtotal--;
1134         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1135                 return 1;
1136         vblank_start--;
1137         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1138                 return 1;
1139         vblank_end--;
1140         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1141                 return 1;
1142
1143         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1144         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1145               (hblank_end << HSYNCEND_SHIFT);
1146         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1147
1148         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1149         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1150               (vblank_end << VSYNCEND_SHIFT);
1151         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1152         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1153               (vactive << SRC_SIZE_VERT_SHIFT);
1154
1155         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1156         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1157
1158         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1159                           var->xoffset * var->bits_per_pixel / 8;
1160
1161         hw->disp_a_base += dinfo->fb.offset << 12;
1162
1163         /* Check stride alignment. */
1164         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1165                 WRN_MSG("display stride %d has bad alignment %d\n",
1166                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1167                 return 1;
1168         }
1169
1170         /* Set the palette to 8-bit mode. */
1171         *pipe_conf &= ~PIPECONF_GAMMA;
1172         return 0;
1173 }
1174
1175 /* Program a (non-VGA) video mode. */
1176 int
1177 intelfbhw_program_mode(struct intelfb_info *dinfo,
1178                      const struct intelfb_hwstate *hw, int blank)
1179 {
1180         int pipe = PIPE_A;
1181         u32 tmp;
1182         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1183         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1184         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1185         u32 hsync_reg, htotal_reg, hblank_reg;
1186         u32 vsync_reg, vtotal_reg, vblank_reg;
1187         u32 src_size_reg;
1188         u32 count, tmp_val[3];
1189
1190         /* Assume single pipe, display plane A, analog CRT. */
1191
1192 #if VERBOSE > 0
1193         DBG_MSG("intelfbhw_program_mode\n");
1194 #endif
1195
1196         /* Disable VGA */
1197         tmp = INREG(VGACNTRL);
1198         tmp |= VGA_DISABLE;
1199         OUTREG(VGACNTRL, tmp);
1200
1201         /* Check whether pipe A or pipe B is enabled. */
1202         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1203                 pipe = PIPE_A;
1204         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1205                 pipe = PIPE_B;
1206
1207         dinfo->pipe = pipe;
1208
1209         if (pipe == PIPE_B) {
1210                 dpll = &hw->dpll_b;
1211                 fp0 = &hw->fpb0;
1212                 fp1 = &hw->fpb1;
1213                 pipe_conf = &hw->pipe_b_conf;
1214                 hs = &hw->hsync_b;
1215                 hb = &hw->hblank_b;
1216                 ht = &hw->htotal_b;
1217                 vs = &hw->vsync_b;
1218                 vb = &hw->vblank_b;
1219                 vt = &hw->vtotal_b;
1220                 ss = &hw->src_size_b;
1221                 dpll_reg = DPLL_B;
1222                 fp0_reg = FPB0;
1223                 fp1_reg = FPB1;
1224                 pipe_conf_reg = PIPEBCONF;
1225                 hsync_reg = HSYNC_B;
1226                 htotal_reg = HTOTAL_B;
1227                 hblank_reg = HBLANK_B;
1228                 vsync_reg = VSYNC_B;
1229                 vtotal_reg = VTOTAL_B;
1230                 vblank_reg = VBLANK_B;
1231                 src_size_reg = SRC_SIZE_B;
1232         } else {
1233                 dpll = &hw->dpll_a;
1234                 fp0 = &hw->fpa0;
1235                 fp1 = &hw->fpa1;
1236                 pipe_conf = &hw->pipe_a_conf;
1237                 hs = &hw->hsync_a;
1238                 hb = &hw->hblank_a;
1239                 ht = &hw->htotal_a;
1240                 vs = &hw->vsync_a;
1241                 vb = &hw->vblank_a;
1242                 vt = &hw->vtotal_a;
1243                 ss = &hw->src_size_a;
1244                 dpll_reg = DPLL_A;
1245                 fp0_reg = FPA0;
1246                 fp1_reg = FPA1;
1247                 pipe_conf_reg = PIPEACONF;
1248                 hsync_reg = HSYNC_A;
1249                 htotal_reg = HTOTAL_A;
1250                 hblank_reg = HBLANK_A;
1251                 vsync_reg = VSYNC_A;
1252                 vtotal_reg = VTOTAL_A;
1253                 vblank_reg = VBLANK_A;
1254                 src_size_reg = SRC_SIZE_A;
1255         }
1256
1257         /* turn off pipe */
1258         tmp = INREG(pipe_conf_reg);
1259         tmp &= ~PIPECONF_ENABLE;
1260         OUTREG(pipe_conf_reg, tmp);
1261
1262         count = 0;
1263         do {
1264           tmp_val[count%3] = INREG(0x70000);
1265           if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1266             break;
1267           count++;
1268           udelay(1);
1269           if (count % 200 == 0) {
1270             tmp = INREG(pipe_conf_reg);
1271             tmp &= ~PIPECONF_ENABLE;
1272             OUTREG(pipe_conf_reg, tmp);
1273           }
1274         } while(count < 2000);
1275
1276         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1277
1278         /* Disable planes A and B. */
1279         tmp = INREG(DSPACNTR);
1280         tmp &= ~DISPPLANE_PLANE_ENABLE;
1281         OUTREG(DSPACNTR, tmp);
1282         tmp = INREG(DSPBCNTR);
1283         tmp &= ~DISPPLANE_PLANE_ENABLE;
1284         OUTREG(DSPBCNTR, tmp);
1285
1286         /* Wait for vblank.  For now, just wait for a 50Hz cycle (20ms)) */
1287         mdelay(20);
1288
1289         /* Disable Sync */
1290         tmp = INREG(ADPA);
1291         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1292         tmp |= ADPA_DPMS_D3;
1293         OUTREG(ADPA, tmp);
1294
1295         /* do some funky magic - xyzzy */
1296         OUTREG(0x61204, 0xabcd0000);
1297
1298         /* turn off PLL */
1299         tmp = INREG(dpll_reg);
1300         dpll_reg &= ~DPLL_VCO_ENABLE;
1301         OUTREG(dpll_reg, tmp);
1302
1303         /* Set PLL parameters */
1304         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1305         OUTREG(fp0_reg, *fp0);
1306         OUTREG(fp1_reg, *fp1);
1307
1308         /* Enable PLL */
1309         tmp = INREG(dpll_reg);
1310         tmp |= DPLL_VCO_ENABLE;
1311         OUTREG(dpll_reg, tmp);
1312
1313         /* Set DVOs B/C */
1314         OUTREG(DVOB, hw->dvob);
1315         OUTREG(DVOC, hw->dvoc);
1316
1317         /* undo funky magic */
1318         OUTREG(0x61204, 0x00000000);
1319
1320         /* Set ADPA */
1321         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1322         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1323
1324         /* Set pipe parameters */
1325         OUTREG(hsync_reg, *hs);
1326         OUTREG(hblank_reg, *hb);
1327         OUTREG(htotal_reg, *ht);
1328         OUTREG(vsync_reg, *vs);
1329         OUTREG(vblank_reg, *vb);
1330         OUTREG(vtotal_reg, *vt);
1331         OUTREG(src_size_reg, *ss);
1332
1333         /* Enable pipe */
1334         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1335
1336         /* Enable sync */
1337         tmp = INREG(ADPA);
1338         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1339         tmp |= ADPA_DPMS_D0;
1340         OUTREG(ADPA, tmp);
1341
1342         /* setup display plane */
1343         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1344                 /*
1345                  *      i830M errata: the display plane must be enabled
1346                  *      to allow writes to the other bits in the plane
1347                  *      control register.
1348                  */
1349                 tmp = INREG(DSPACNTR);
1350                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1351                         tmp |= DISPPLANE_PLANE_ENABLE;
1352                         OUTREG(DSPACNTR, tmp);
1353                         OUTREG(DSPACNTR,
1354                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1355                         mdelay(1);
1356               }
1357         }
1358
1359         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1360         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1361         OUTREG(DSPABASE, hw->disp_a_base);
1362
1363         /* Enable plane */
1364         if (!blank) {
1365                 tmp = INREG(DSPACNTR);
1366                 tmp |= DISPPLANE_PLANE_ENABLE;
1367                 OUTREG(DSPACNTR, tmp);
1368                 OUTREG(DSPABASE, hw->disp_a_base);
1369         }
1370
1371         return 0;
1372 }
1373
1374 /* forward declarations */
1375 static void refresh_ring(struct intelfb_info *dinfo);
1376 static void reset_state(struct intelfb_info *dinfo);
1377 static void do_flush(struct intelfb_info *dinfo);
1378
1379 static int
1380 wait_ring(struct intelfb_info *dinfo, int n)
1381 {
1382         int i = 0;
1383         unsigned long end;
1384         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1385
1386 #if VERBOSE > 0
1387         DBG_MSG("wait_ring: %d\n", n);
1388 #endif
1389
1390         end = jiffies + (HZ * 3);
1391         while (dinfo->ring_space < n) {
1392                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1393                                                    RING_HEAD_MASK);
1394                 if (dinfo->ring_tail + RING_MIN_FREE <
1395                     (u32 __iomem) dinfo->ring_head)
1396                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1397                                 - (dinfo->ring_tail + RING_MIN_FREE);
1398                 else
1399                         dinfo->ring_space = (dinfo->ring.size +
1400                                              (u32 __iomem) dinfo->ring_head)
1401                                 - (dinfo->ring_tail + RING_MIN_FREE);
1402                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1403                         end = jiffies + (HZ * 3);
1404                         last_head = (u32 __iomem) dinfo->ring_head;
1405                 }
1406                 i++;
1407                 if (time_before(end, jiffies)) {
1408                         if (!i) {
1409                                 /* Try again */
1410                                 reset_state(dinfo);
1411                                 refresh_ring(dinfo);
1412                                 do_flush(dinfo);
1413                                 end = jiffies + (HZ * 3);
1414                                 i = 1;
1415                         } else {
1416                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1417                                         dinfo->ring_space, n);
1418                                 WRN_MSG("lockup - turning off hardware "
1419                                         "acceleration\n");
1420                                 dinfo->ring_lockup = 1;
1421                                 break;
1422                         }
1423                 }
1424                 udelay(1);
1425         }
1426         return i;
1427 }
1428
1429 static void
1430 do_flush(struct intelfb_info *dinfo) {
1431         START_RING(2);
1432         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1433         OUT_RING(MI_NOOP);
1434         ADVANCE_RING();
1435 }
1436
1437 void
1438 intelfbhw_do_sync(struct intelfb_info *dinfo)
1439 {
1440 #if VERBOSE > 0
1441         DBG_MSG("intelfbhw_do_sync\n");
1442 #endif
1443
1444         if (!dinfo->accel)
1445                 return;
1446
1447         /*
1448          * Send a flush, then wait until the ring is empty.  This is what
1449          * the XFree86 driver does, and actually it doesn't seem a lot worse
1450          * than the recommended method (both have problems).
1451          */
1452         do_flush(dinfo);
1453         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1454         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1455 }
1456
1457 static void
1458 refresh_ring(struct intelfb_info *dinfo)
1459 {
1460 #if VERBOSE > 0
1461         DBG_MSG("refresh_ring\n");
1462 #endif
1463
1464         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1465                                            RING_HEAD_MASK);
1466         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1467         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1468                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1469                         - (dinfo->ring_tail + RING_MIN_FREE);
1470         else
1471                 dinfo->ring_space = (dinfo->ring.size +
1472                                      (u32 __iomem) dinfo->ring_head)
1473                         - (dinfo->ring_tail + RING_MIN_FREE);
1474 }
1475
1476 static void
1477 reset_state(struct intelfb_info *dinfo)
1478 {
1479         int i;
1480         u32 tmp;
1481
1482 #if VERBOSE > 0
1483         DBG_MSG("reset_state\n");
1484 #endif
1485
1486         for (i = 0; i < FENCE_NUM; i++)
1487                 OUTREG(FENCE + (i << 2), 0);
1488
1489         /* Flush the ring buffer if it's enabled. */
1490         tmp = INREG(PRI_RING_LENGTH);
1491         if (tmp & RING_ENABLE) {
1492 #if VERBOSE > 0
1493                 DBG_MSG("reset_state: ring was enabled\n");
1494 #endif
1495                 refresh_ring(dinfo);
1496                 intelfbhw_do_sync(dinfo);
1497                 DO_RING_IDLE();
1498         }
1499
1500         OUTREG(PRI_RING_LENGTH, 0);
1501         OUTREG(PRI_RING_HEAD, 0);
1502         OUTREG(PRI_RING_TAIL, 0);
1503         OUTREG(PRI_RING_START, 0);
1504 }
1505
1506 /* Stop the 2D engine, and turn off the ring buffer. */
1507 void
1508 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1509 {
1510 #if VERBOSE > 0
1511         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1512                 dinfo->ring_active);
1513 #endif
1514
1515         if (!dinfo->accel)
1516                 return;
1517
1518         dinfo->ring_active = 0;
1519         reset_state(dinfo);
1520 }
1521
1522 /*
1523  * Enable the ring buffer, and initialise the 2D engine.
1524  * It is assumed that the graphics engine has been stopped by previously
1525  * calling intelfb_2d_stop().
1526  */
1527 void
1528 intelfbhw_2d_start(struct intelfb_info *dinfo)
1529 {
1530 #if VERBOSE > 0
1531         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1532                 dinfo->accel, dinfo->ring_active);
1533 #endif
1534
1535         if (!dinfo->accel)
1536                 return;
1537
1538         /* Initialise the primary ring buffer. */
1539         OUTREG(PRI_RING_LENGTH, 0);
1540         OUTREG(PRI_RING_TAIL, 0);
1541         OUTREG(PRI_RING_HEAD, 0);
1542
1543         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1544         OUTREG(PRI_RING_LENGTH,
1545                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1546                 RING_NO_REPORT | RING_ENABLE);
1547         refresh_ring(dinfo);
1548         dinfo->ring_active = 1;
1549 }
1550
1551 /* 2D fillrect (solid fill or invert) */
1552 void
1553 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1554                       u32 color, u32 pitch, u32 bpp, u32 rop)
1555 {
1556         u32 br00, br09, br13, br14, br16;
1557
1558 #if VERBOSE > 0
1559         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1560                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1561 #endif
1562
1563         br00 = COLOR_BLT_CMD;
1564         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1565         br13 = (rop << ROP_SHIFT) | pitch;
1566         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1567         br16 = color;
1568
1569         switch (bpp) {
1570         case 8:
1571                 br13 |= COLOR_DEPTH_8;
1572                 break;
1573         case 16:
1574                 br13 |= COLOR_DEPTH_16;
1575                 break;
1576         case 32:
1577                 br13 |= COLOR_DEPTH_32;
1578                 br00 |= WRITE_ALPHA | WRITE_RGB;
1579                 break;
1580         }
1581
1582         START_RING(6);
1583         OUT_RING(br00);
1584         OUT_RING(br13);
1585         OUT_RING(br14);
1586         OUT_RING(br09);
1587         OUT_RING(br16);
1588         OUT_RING(MI_NOOP);
1589         ADVANCE_RING();
1590
1591 #if VERBOSE > 0
1592         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1593                 dinfo->ring_tail, dinfo->ring_space);
1594 #endif
1595 }
1596
1597 void
1598 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1599                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1600 {
1601         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1602
1603 #if VERBOSE > 0
1604         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1605                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1606 #endif
1607
1608         br00 = XY_SRC_COPY_BLT_CMD;
1609         br09 = dinfo->fb_start;
1610         br11 = (pitch << PITCH_SHIFT);
1611         br12 = dinfo->fb_start;
1612         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1613         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1614         br23 = ((dstx + w) << WIDTH_SHIFT) |
1615                ((dsty + h) << HEIGHT_SHIFT);
1616         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1617
1618         switch (bpp) {
1619         case 8:
1620                 br13 |= COLOR_DEPTH_8;
1621                 break;
1622         case 16:
1623                 br13 |= COLOR_DEPTH_16;
1624                 break;
1625         case 32:
1626                 br13 |= COLOR_DEPTH_32;
1627                 br00 |= WRITE_ALPHA | WRITE_RGB;
1628                 break;
1629         }
1630
1631         START_RING(8);
1632         OUT_RING(br00);
1633         OUT_RING(br13);
1634         OUT_RING(br22);
1635         OUT_RING(br23);
1636         OUT_RING(br09);
1637         OUT_RING(br26);
1638         OUT_RING(br11);
1639         OUT_RING(br12);
1640         ADVANCE_RING();
1641 }
1642
1643 int
1644 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1645                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1646 {
1647         int nbytes, ndwords, pad, tmp;
1648         u32 br00, br09, br13, br18, br19, br22, br23;
1649         int dat, ix, iy, iw;
1650         int i, j;
1651
1652 #if VERBOSE > 0
1653         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1654 #endif
1655
1656         /* size in bytes of a padded scanline */
1657         nbytes = ROUND_UP_TO(w, 16) / 8;
1658
1659         /* Total bytes of padded scanline data to write out. */
1660         nbytes = nbytes * h;
1661
1662         /*
1663          * Check if the glyph data exceeds the immediate mode limit.
1664          * It would take a large font (1K pixels) to hit this limit.
1665          */
1666         if (nbytes > MAX_MONO_IMM_SIZE)
1667                 return 0;
1668
1669         /* Src data is packaged a dword (32-bit) at a time. */
1670         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1671
1672         /*
1673          * Ring has to be padded to a quad word. But because the command starts
1674            with 7 bytes, pad only if there is an even number of ndwords
1675          */
1676         pad = !(ndwords % 2);
1677
1678         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1679         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1680         br09 = dinfo->fb_start;
1681         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1682         br18 = bg;
1683         br19 = fg;
1684         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1685         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1686
1687         switch (bpp) {
1688         case 8:
1689                 br13 |= COLOR_DEPTH_8;
1690                 break;
1691         case 16:
1692                 br13 |= COLOR_DEPTH_16;
1693                 break;
1694         case 32:
1695                 br13 |= COLOR_DEPTH_32;
1696                 br00 |= WRITE_ALPHA | WRITE_RGB;
1697                 break;
1698         }
1699
1700         START_RING(8 + ndwords);
1701         OUT_RING(br00);
1702         OUT_RING(br13);
1703         OUT_RING(br22);
1704         OUT_RING(br23);
1705         OUT_RING(br09);
1706         OUT_RING(br18);
1707         OUT_RING(br19);
1708         ix = iy = 0;
1709         iw = ROUND_UP_TO(w, 8) / 8;
1710         while (ndwords--) {
1711                 dat = 0;
1712                 for (j = 0; j < 2; ++j) {
1713                         for (i = 0; i < 2; ++i) {
1714                                 if (ix != iw || i == 0)
1715                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1716                         }
1717                         if (ix == iw && iy != (h-1)) {
1718                                 ix = 0;
1719                                 ++iy;
1720                         }
1721                 }
1722                 OUT_RING(dat);
1723         }
1724         if (pad)
1725                 OUT_RING(MI_NOOP);
1726         ADVANCE_RING();
1727
1728         return 1;
1729 }
1730
1731 /* HW cursor functions. */
1732 void
1733 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1734 {
1735         u32 tmp;
1736
1737 #if VERBOSE > 0
1738         DBG_MSG("intelfbhw_cursor_init\n");
1739 #endif
1740
1741         if (dinfo->mobile || IS_I9xx(dinfo)) {
1742                 if (!dinfo->cursor.physical)
1743                         return;
1744                 tmp = INREG(CURSOR_A_CONTROL);
1745                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1746                          CURSOR_MEM_TYPE_LOCAL |
1747                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1748                 tmp |= CURSOR_MODE_DISABLE;
1749                 OUTREG(CURSOR_A_CONTROL, tmp);
1750                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1751         } else {
1752                 tmp = INREG(CURSOR_CONTROL);
1753                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1754                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1755                 tmp = CURSOR_FORMAT_3C;
1756                 OUTREG(CURSOR_CONTROL, tmp);
1757                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1758                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1759                       (64 << CURSOR_SIZE_V_SHIFT);
1760                 OUTREG(CURSOR_SIZE, tmp);
1761         }
1762 }
1763
1764 void
1765 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1766 {
1767         u32 tmp;
1768
1769 #if VERBOSE > 0
1770         DBG_MSG("intelfbhw_cursor_hide\n");
1771 #endif
1772
1773         dinfo->cursor_on = 0;
1774         if (dinfo->mobile || IS_I9xx(dinfo)) {
1775                 if (!dinfo->cursor.physical)
1776                         return;
1777                 tmp = INREG(CURSOR_A_CONTROL);
1778                 tmp &= ~CURSOR_MODE_MASK;
1779                 tmp |= CURSOR_MODE_DISABLE;
1780                 OUTREG(CURSOR_A_CONTROL, tmp);
1781                 /* Flush changes */
1782                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1783         } else {
1784                 tmp = INREG(CURSOR_CONTROL);
1785                 tmp &= ~CURSOR_ENABLE;
1786                 OUTREG(CURSOR_CONTROL, tmp);
1787         }
1788 }
1789
1790 void
1791 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1792 {
1793         u32 tmp;
1794
1795 #if VERBOSE > 0
1796         DBG_MSG("intelfbhw_cursor_show\n");
1797 #endif
1798
1799         dinfo->cursor_on = 1;
1800
1801         if (dinfo->cursor_blanked)
1802                 return;
1803
1804         if (dinfo->mobile || IS_I9xx(dinfo)) {
1805                 if (!dinfo->cursor.physical)
1806                         return;
1807                 tmp = INREG(CURSOR_A_CONTROL);
1808                 tmp &= ~CURSOR_MODE_MASK;
1809                 tmp |= CURSOR_MODE_64_4C_AX;
1810                 OUTREG(CURSOR_A_CONTROL, tmp);
1811                 /* Flush changes */
1812                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1813         } else {
1814                 tmp = INREG(CURSOR_CONTROL);
1815                 tmp |= CURSOR_ENABLE;
1816                 OUTREG(CURSOR_CONTROL, tmp);
1817         }
1818 }
1819
1820 void
1821 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1822 {
1823         u32 tmp;
1824
1825 #if VERBOSE > 0
1826         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1827 #endif
1828
1829         /*
1830          * Sets the position.  The coordinates are assumed to already
1831          * have any offset adjusted.  Assume that the cursor is never
1832          * completely off-screen, and that x, y are always >= 0.
1833          */
1834
1835         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1836               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1837         OUTREG(CURSOR_A_POSITION, tmp);
1838
1839         if (IS_I9xx(dinfo)) {
1840                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1841         }
1842 }
1843
1844 void
1845 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1846 {
1847 #if VERBOSE > 0
1848         DBG_MSG("intelfbhw_cursor_setcolor\n");
1849 #endif
1850
1851         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1852         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1853         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1854         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1855 }
1856
1857 void
1858 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1859                       u8 *data)
1860 {
1861         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1862         int i, j, w = width / 8;
1863         int mod = width % 8, t_mask, d_mask;
1864
1865 #if VERBOSE > 0
1866         DBG_MSG("intelfbhw_cursor_load\n");
1867 #endif
1868
1869         if (!dinfo->cursor.virtual)
1870                 return;
1871
1872         t_mask = 0xff >> mod;
1873         d_mask = ~(0xff >> mod);
1874         for (i = height; i--; ) {
1875                 for (j = 0; j < w; j++) {
1876                         writeb(0x00, addr + j);
1877                         writeb(*(data++), addr + j+8);
1878                 }
1879                 if (mod) {
1880                         writeb(t_mask, addr + j);
1881                         writeb(*(data++) & d_mask, addr + j+8);
1882                 }
1883                 addr += 16;
1884         }
1885 }
1886
1887 void
1888 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1889         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1890         int i, j;
1891
1892 #if VERBOSE > 0
1893         DBG_MSG("intelfbhw_cursor_reset\n");
1894 #endif
1895
1896         if (!dinfo->cursor.virtual)
1897                 return;
1898
1899         for (i = 64; i--; ) {
1900                 for (j = 0; j < 8; j++) {
1901                         writeb(0xff, addr + j+0);
1902                         writeb(0x00, addr + j+8);
1903                 }
1904                 addr += 16;
1905         }
1906 }