SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco_freq, max_vco_freq;
  51         int p_transition_clock;
  52 };
  53
  54 #define PLLS_I8xx 0
  55 #define PLLS_I9xx 1
  56 #define PLLS_MAX 2
  57
  58 struct pll_min_max plls[PLLS_MAX] = {
  59         { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000 }, //I8xx
  60         {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000 }  //I9xx
  61 };
  62
  63 int
  64 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  65 {
  66         u32 tmp;
  67         if (!pdev || !dinfo)
  68                 return 1;
  69
  70         switch (pdev->device) {
  71         case PCI_DEVICE_ID_INTEL_830M:
  72                 dinfo->name = "Intel(R) 830M";
  73                 dinfo->chipset = INTEL_830M;
  74                 dinfo->mobile = 1;
  75                 dinfo->pll_index = PLLS_I8xx;
  76                 return 0;
  77         case PCI_DEVICE_ID_INTEL_845G:
  78                 dinfo->name = "Intel(R) 845G";
  79                 dinfo->chipset = INTEL_845G;
  80                 dinfo->mobile = 0;
  81                 dinfo->pll_index = PLLS_I8xx;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_85XGM:
  84                 tmp = 0;
  85                 dinfo->mobile = 1;
  86                 dinfo->pll_index = PLLS_I8xx;
  87                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  88                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  89                         INTEL_85X_VARIANT_MASK) {
  90                 case INTEL_VAR_855GME:
  91                         dinfo->name = "Intel(R) 855GME";
  92                         dinfo->chipset = INTEL_855GME;
  93                         return 0;
  94                 case INTEL_VAR_855GM:
  95                         dinfo->name = "Intel(R) 855GM";
  96                         dinfo->chipset = INTEL_855GM;
  97                         return 0;
  98                 case INTEL_VAR_852GME:
  99                         dinfo->name = "Intel(R) 852GME";
 100                         dinfo->chipset = INTEL_852GME;
 101                         return 0;
 102                 case INTEL_VAR_852GM:
 103                         dinfo->name = "Intel(R) 852GM";
 104                         dinfo->chipset = INTEL_852GM;
 105                         return 0;
 106                 default:
 107                         dinfo->name = "Intel(R) 852GM/855GM";
 108                         dinfo->chipset = INTEL_85XGM;
 109                         return 0;
 110                 }
 111                 break;
 112         case PCI_DEVICE_ID_INTEL_865G:
 113                 dinfo->name = "Intel(R) 865G";
 114                 dinfo->chipset = INTEL_865G;
 115                 dinfo->mobile = 0;
 116                 dinfo->pll_index = PLLS_I8xx;
 117                 return 0;
 118         case PCI_DEVICE_ID_INTEL_915G:
 119                 dinfo->name = "Intel(R) 915G";
 120                 dinfo->chipset = INTEL_915G;
 121                 dinfo->mobile = 0;
 122                 dinfo->pll_index = PLLS_I9xx;
 123                 return 0;
 124         case PCI_DEVICE_ID_INTEL_915GM:
 125                 dinfo->name = "Intel(R) 915GM";
 126                 dinfo->chipset = INTEL_915GM;
 127                 dinfo->mobile = 1;
 128                 dinfo->pll_index = PLLS_I9xx;
 129                 return 0;
 130         default:
 131                 return 1;
 132         }
 133 }
 134
 135 int
 136 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 137                      int *stolen_size)
 138 {
 139         struct pci_dev *bridge_dev;
 140         u16 tmp;
 141
 142         if (!pdev || !aperture_size || !stolen_size)
 143                 return 1;
 144
 145         /* Find the bridge device.  It is always 0:0.0 */
 146         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 147                 ERR_MSG("cannot find bridge device\n");
 148                 return 1;
 149         }
 150
 151         /* Get the fb aperture size and "stolen" memory amount. */
 152         tmp = 0;
 153         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 154         switch (pdev->device) {
 155         case PCI_DEVICE_ID_INTEL_830M:
 156         case PCI_DEVICE_ID_INTEL_845G:
 157                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 158                         *aperture_size = MB(64);
 159                 else
 160                         *aperture_size = MB(128);
 161                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 162                 case INTEL_830_GMCH_GMS_STOLEN_512:
 163                         *stolen_size = KB(512) - KB(132);
 164                         return 0;
 165                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 166                         *stolen_size = MB(1) - KB(132);
 167                         return 0;
 168                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 169                         *stolen_size = MB(8) - KB(132);
 170                         return 0;
 171                 case INTEL_830_GMCH_GMS_LOCAL:
 172                         ERR_MSG("only local memory found\n");
 173                         return 1;
 174                 case INTEL_830_GMCH_GMS_DISABLED:
 175                         ERR_MSG("video memory is disabled\n");
 176                         return 1;
 177                 default:
 178                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 179                                 tmp & INTEL_830_GMCH_GMS_MASK);
 180                         return 1;
 181                 }
 182                 break;
 183         default:
 184                 *aperture_size = MB(128);
 185                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 186                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 187                         *stolen_size = MB(1) - KB(132);
 188                         return 0;
 189                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 190                         *stolen_size = MB(4) - KB(132);
 191                         return 0;
 192                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 193                         *stolen_size = MB(8) - KB(132);
 194                         return 0;
 195                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 196                         *stolen_size = MB(16) - KB(132);
 197                         return 0;
 198                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 199                         *stolen_size = MB(32) - KB(132);
 200                         return 0;
 201                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 202                         *stolen_size = MB(48) - KB(132);
 203                         return 0;
 204                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 205                         *stolen_size = MB(64) - KB(132);
 206                         return 0;
 207                 case INTEL_855_GMCH_GMS_DISABLED:
 208                         ERR_MSG("video memory is disabled\n");
 209                         return 0;
 210                 default:
 211                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 212                                 tmp & INTEL_855_GMCH_GMS_MASK);
 213                         return 1;
 214                 }
 215         }
 216 }
 217
 218 int
 219 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 220 {
 221         int dvo = 0;
 222
 223         if (INREG(LVDS) & PORT_ENABLE)
 224                 dvo |= LVDS_PORT;
 225         if (INREG(DVOA) & PORT_ENABLE)
 226                 dvo |= DVOA_PORT;
 227         if (INREG(DVOB) & PORT_ENABLE)
 228                 dvo |= DVOB_PORT;
 229         if (INREG(DVOC) & PORT_ENABLE)
 230                 dvo |= DVOC_PORT;
 231
 232         return dvo;
 233 }
 234
 235 const char *
 236 intelfbhw_dvo_to_string(int dvo)
 237 {
 238         if (dvo & DVOA_PORT)
 239                 return "DVO port A";
 240         else if (dvo & DVOB_PORT)
 241                 return "DVO port B";
 242         else if (dvo & DVOC_PORT)
 243                 return "DVO port C";
 244         else if (dvo & LVDS_PORT)
 245                 return "LVDS port";
 246         else
 247                 return NULL;
 248 }
 249
 250
 251 int
 252 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 253                         struct fb_var_screeninfo *var)
 254 {
 255         int bytes_per_pixel;
 256         int tmp;
 257
 258 #if VERBOSE > 0
 259         DBG_MSG("intelfbhw_validate_mode\n");
 260 #endif
 261
 262         bytes_per_pixel = var->bits_per_pixel / 8;
 263         if (bytes_per_pixel == 3)
 264                 bytes_per_pixel = 4;
 265
 266         /* Check if enough video memory. */
 267         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 268         if (tmp > dinfo->fb.size) {
 269                 WRN_MSG("Not enough video ram for mode "
 270                         "(%d KByte vs %d KByte).\n",
 271                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 272                 return 1;
 273         }
 274
 275         /* Check if x/y limits are OK. */
 276         if (var->xres - 1 > HACTIVE_MASK) {
 277                 WRN_MSG("X resolution too large (%d vs %d).\n",
 278                         var->xres, HACTIVE_MASK + 1);
 279                 return 1;
 280         }
 281         if (var->yres - 1 > VACTIVE_MASK) {
 282                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 283                         var->yres, VACTIVE_MASK + 1);
 284                 return 1;
 285         }
 286
 287         /* Check for interlaced/doublescan modes. */
 288         if (var->vmode & FB_VMODE_INTERLACED) {
 289                 WRN_MSG("Mode is interlaced.\n");
 290                 return 1;
 291         }
 292         if (var->vmode & FB_VMODE_DOUBLE) {
 293                 WRN_MSG("Mode is double-scan.\n");
 294                 return 1;
 295         }
 296
 297         /* Check if clock is OK. */
 298         tmp = 1000000000 / var->pixclock;
 299         if (tmp < MIN_CLOCK) {
 300                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 301                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 302                 return 1;
 303         }
 304         if (tmp > MAX_CLOCK) {
 305                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 306                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 307                 return 1;
 308         }
 309
 310         return 0;
 311 }
 312
 313 int
 314 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 315 {
 316         struct intelfb_info *dinfo = GET_DINFO(info);
 317         u32 offset, xoffset, yoffset;
 318
 319 #if VERBOSE > 0
 320         DBG_MSG("intelfbhw_pan_display\n");
 321 #endif
 322
 323         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 324         yoffset = var->yoffset;
 325
 326         if ((xoffset + var->xres > var->xres_virtual) ||
 327             (yoffset + var->yres > var->yres_virtual))
 328                 return -EINVAL;
 329
 330         offset = (yoffset * dinfo->pitch) +
 331                  (xoffset * var->bits_per_pixel) / 8;
 332
 333         offset += dinfo->fb.offset << 12;
 334
 335         OUTREG(DSPABASE, offset);
 336
 337         return 0;
 338 }
 339
 340 /* Blank the screen. */
 341 void
 342 intelfbhw_do_blank(int blank, struct fb_info *info)
 343 {
 344         struct intelfb_info *dinfo = GET_DINFO(info);
 345         u32 tmp;
 346
 347 #if VERBOSE > 0
 348         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 349 #endif
 350
 351         /* Turn plane A on or off */
 352         tmp = INREG(DSPACNTR);
 353         if (blank)
 354                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 355         else
 356                 tmp |= DISPPLANE_PLANE_ENABLE;
 357         OUTREG(DSPACNTR, tmp);
 358         /* Flush */
 359         tmp = INREG(DSPABASE);
 360         OUTREG(DSPABASE, tmp);
 361
 362         /* Turn off/on the HW cursor */
 363 #if VERBOSE > 0
 364         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 365 #endif
 366         if (dinfo->cursor_on) {
 367                 if (blank) {
 368                         intelfbhw_cursor_hide(dinfo);
 369                 } else {
 370                         intelfbhw_cursor_show(dinfo);
 371                 }
 372                 dinfo->cursor_on = 1;
 373         }
 374         dinfo->cursor_blanked = blank;
 375
 376         /* Set DPMS level */
 377         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 378         switch (blank) {
 379         case FB_BLANK_UNBLANK:
 380         case FB_BLANK_NORMAL:
 381                 tmp |= ADPA_DPMS_D0;
 382                 break;
 383         case FB_BLANK_VSYNC_SUSPEND:
 384                 tmp |= ADPA_DPMS_D1;
 385                 break;
 386         case FB_BLANK_HSYNC_SUSPEND:
 387                 tmp |= ADPA_DPMS_D2;
 388                 break;
 389         case FB_BLANK_POWERDOWN:
 390                 tmp |= ADPA_DPMS_D3;
 391                 break;
 392         }
 393         OUTREG(ADPA, tmp);
 394
 395         return;
 396 }
 397
 398
 399 void
 400 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 401                     unsigned red, unsigned green, unsigned blue,
 402                     unsigned transp)
 403 {
 404 #if VERBOSE > 0
 405         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 406                 regno, red, green, blue);
 407 #endif
 408
 409         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 410                           PALETTE_A : PALETTE_B;
 411
 412         OUTREG(palette_reg + (regno << 2),
 413                (red << PALETTE_8_RED_SHIFT) |
 414                (green << PALETTE_8_GREEN_SHIFT) |
 415                (blue << PALETTE_8_BLUE_SHIFT));
 416 }
 417
 418
 419 int
 420 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 421                         int flag)
 422 {
 423         int i;
 424
 425 #if VERBOSE > 0
 426         DBG_MSG("intelfbhw_read_hw_state\n");
 427 #endif
 428
 429         if (!hw || !dinfo)
 430                 return -1;
 431
 432         /* Read in as much of the HW state as possible. */
 433         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 434         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 435         hw->vga_pd = INREG(VGAPD);
 436         hw->dpll_a = INREG(DPLL_A);
 437         hw->dpll_b = INREG(DPLL_B);
 438         hw->fpa0 = INREG(FPA0);
 439         hw->fpa1 = INREG(FPA1);
 440         hw->fpb0 = INREG(FPB0);
 441         hw->fpb1 = INREG(FPB1);
 442
 443         if (flag == 1)
 444                 return flag;
 445
 446 #if 0
 447         /* This seems to be a problem with the 852GM/855GM */
 448         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 449                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 450                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 451         }
 452 #endif
 453
 454         if (flag == 2)
 455                 return flag;
 456
 457         hw->htotal_a = INREG(HTOTAL_A);
 458         hw->hblank_a = INREG(HBLANK_A);
 459         hw->hsync_a = INREG(HSYNC_A);
 460         hw->vtotal_a = INREG(VTOTAL_A);
 461         hw->vblank_a = INREG(VBLANK_A);
 462         hw->vsync_a = INREG(VSYNC_A);
 463         hw->src_size_a = INREG(SRC_SIZE_A);
 464         hw->bclrpat_a = INREG(BCLRPAT_A);
 465         hw->htotal_b = INREG(HTOTAL_B);
 466         hw->hblank_b = INREG(HBLANK_B);
 467         hw->hsync_b = INREG(HSYNC_B);
 468         hw->vtotal_b = INREG(VTOTAL_B);
 469         hw->vblank_b = INREG(VBLANK_B);
 470         hw->vsync_b = INREG(VSYNC_B);
 471         hw->src_size_b = INREG(SRC_SIZE_B);
 472         hw->bclrpat_b = INREG(BCLRPAT_B);
 473
 474         if (flag == 3)
 475                 return flag;
 476
 477         hw->adpa = INREG(ADPA);
 478         hw->dvoa = INREG(DVOA);
 479         hw->dvob = INREG(DVOB);
 480         hw->dvoc = INREG(DVOC);
 481         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 482         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 483         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 484         hw->lvds = INREG(LVDS);
 485
 486         if (flag == 4)
 487                 return flag;
 488
 489         hw->pipe_a_conf = INREG(PIPEACONF);
 490         hw->pipe_b_conf = INREG(PIPEBCONF);
 491         hw->disp_arb = INREG(DISPARB);
 492
 493         if (flag == 5)
 494                 return flag;
 495
 496         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 497         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 498         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 499         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 500
 501         if (flag == 6)
 502                 return flag;
 503
 504         for (i = 0; i < 4; i++) {
 505                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 506                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 507         }
 508
 509         if (flag == 7)
 510                 return flag;
 511
 512         hw->cursor_size = INREG(CURSOR_SIZE);
 513
 514         if (flag == 8)
 515                 return flag;
 516
 517         hw->disp_a_ctrl = INREG(DSPACNTR);
 518         hw->disp_b_ctrl = INREG(DSPBCNTR);
 519         hw->disp_a_base = INREG(DSPABASE);
 520         hw->disp_b_base = INREG(DSPBBASE);
 521         hw->disp_a_stride = INREG(DSPASTRIDE);
 522         hw->disp_b_stride = INREG(DSPBSTRIDE);
 523
 524         if (flag == 9)
 525                 return flag;
 526
 527         hw->vgacntrl = INREG(VGACNTRL);
 528
 529         if (flag == 10)
 530                 return flag;
 531
 532         hw->add_id = INREG(ADD_ID);
 533
 534         if (flag == 11)
 535                 return flag;
 536
 537         for (i = 0; i < 7; i++) {
 538                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 539                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 540                 if (i < 3)
 541                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 542         }
 543
 544         for (i = 0; i < 8; i++)
 545                 hw->fence[i] = INREG(FENCE + (i << 2));
 546
 547         hw->instpm = INREG(INSTPM);
 548         hw->mem_mode = INREG(MEM_MODE);
 549         hw->fw_blc_0 = INREG(FW_BLC_0);
 550         hw->fw_blc_1 = INREG(FW_BLC_1);
 551
 552         return 0;
 553 }
 554
 555
 556 static int calc_vclock3(int index, int m, int n, int p)
 557 {
 558         return PLL_REFCLK * m / n / p;
 559 }
 560
 561 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
 562 {
 563         switch(index)
 564         {
 565         case PLLS_I9xx:
 566                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 567                          ((p1)) * (p2 ? 10 : 5)));
 568         case PLLS_I8xx:
 569         default:
 570                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 571                          ((p1+2) * (1 << (p2 + 1)))));
 572         }
 573 }
 574
 575 void
 576 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 577 {
 578 #if REGDUMP
 579         int i, m1, m2, n, p1, p2;
 580         int index = dinfo->pll_index;
 581         DBG_MSG("intelfbhw_print_hw_state\n");
 582
 583         if (!hw || !dinfo)
 584                 return;
 585         /* Read in as much of the HW state as possible. */
 586         printk("hw state dump start\n");
 587         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 588         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 589         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 590         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 591         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 592         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 593         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 594                 p1 = 0;
 595         else
 596                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 597         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 598         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 599                m1, m2, n, p1, p2);
 600         printk("        VGA0: clock is %d\n",
 601                calc_vclock(index, m1, m2, n, p1, p2));
 602
 603         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 604         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 605         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 606         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 607                 p1 = 0;
 608         else
 609                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 610         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 611         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 612                m1, m2, n, p1, p2);
 613         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 614
 615         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 616         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 617         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 618         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 619         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 620         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 621
 622         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 623         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 624         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 625         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 626                 p1 = 0;
 627         else
 628                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 629         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 630         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 631                m1, m2, n, p1, p2);
 632         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 633
 634         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 635         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 636         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 637         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 638                 p1 = 0;
 639         else
 640                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 641         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 642         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 643                m1, m2, n, p1, p2);
 644         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 645
 646 #if 0
 647         printk("        PALETTE_A:\n");
 648         for (i = 0; i < PALETTE_8_ENTRIES)
 649                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 650         printk("        PALETTE_B:\n");
 651         for (i = 0; i < PALETTE_8_ENTRIES)
 652                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 653 #endif
 654
 655         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 656         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 657         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 658         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 659         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 660         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 661         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 662         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 663         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 664         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 665         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 666         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 667         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 668         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 669         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 670         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 671
 672         printk("        ADPA:                   0x%08x\n", hw->adpa);
 673         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 674         printk("        DVOB:                   0x%08x\n", hw->dvob);
 675         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 676         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 677         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 678         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 679         printk("        LVDS:                   0x%08x\n", hw->lvds);
 680
 681         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 682         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 683         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 684
 685         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 686         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 687         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 688         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 689
 690         printk("        CURSOR_A_PALETTE:       ");
 691         for (i = 0; i < 4; i++) {
 692                 printk("0x%08x", hw->cursor_a_palette[i]);
 693                 if (i < 3)
 694                         printk(", ");
 695         }
 696         printk("\n");
 697         printk("        CURSOR_B_PALETTE:       ");
 698         for (i = 0; i < 4; i++) {
 699                 printk("0x%08x", hw->cursor_b_palette[i]);
 700                 if (i < 3)
 701                         printk(", ");
 702         }
 703         printk("\n");
 704
 705         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 706
 707         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 708         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 709         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 710         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 711         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 712         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 713
 714         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 715         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 716
 717         for (i = 0; i < 7; i++) {
 718                 printk("        SWF0%d                  0x%08x\n", i,
 719                         hw->swf0x[i]);
 720         }
 721         for (i = 0; i < 7; i++) {
 722                 printk("        SWF1%d                  0x%08x\n", i,
 723                         hw->swf1x[i]);
 724         }
 725         for (i = 0; i < 3; i++) {
 726                 printk("        SWF3%d                  0x%08x\n", i,
 727                        hw->swf3x[i]);
 728         }
 729         for (i = 0; i < 8; i++)
 730                 printk("        FENCE%d                 0x%08x\n", i,
 731                        hw->fence[i]);
 732
 733         printk("        INSTPM                  0x%08x\n", hw->instpm);
 734         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 735         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 736         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 737
 738         printk("hw state dump end\n");
 739 #endif
 740 }
 741
 742
 743
 744 /* Split the M parameter into M1 and M2. */
 745 static int
 746 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 747 {
 748         int m1, m2;
 749         int testm;
 750         /* no point optimising too much - brute force m */
 751         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
 752         {
 753           for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
 754           {
 755             testm  = ( 5 * ( m1 + 2 )) + (m2 + 2);
 756             if (testm == m)
 757             {
 758                 *retm1 = (unsigned int)m1;
 759                 *retm2 = (unsigned int)m2;
 760                 return 0;
 761             }
 762           }
 763         }
 764         return 1;
 765 }
 766
 767 /* Split the P parameter into P1 and P2. */
 768 static int
 769 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 770 {
 771         int p1, p2;
 772
 773         if (index == PLLS_I9xx)
 774         {
 775                 p1 = (p / 10) + 1;
 776                 p2 = 0;
 777
 778                 *retp1 = (unsigned int)p1;
 779                 *retp2 = (unsigned int)p2;
 780                 return 0;
 781         }
 782
 783         if (index == PLLS_I8xx)
 784         {
 785                 if (p % 4 == 0)
 786                         p2 = 1;
 787                 else
 788                         p2 = 0;
 789                 p1 = (p / (1 << (p2 + 1))) - 2;
 790                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 791                         p2 = 0;
 792                         p1 = (p / (1 << (p2 + 1))) - 2;
 793                 }
 794                 if (p1  < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
 795                         return 1;
 796                 } else {
 797                         *retp1 = (unsigned int)p1;
 798                         *retp2 = (unsigned int)p2;
 799                         return 0;
 800                 }
 801         }
 802         return 1;
 803 }
 804
 805 static int
 806 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 807                 u32 *retp2, u32 *retclock)
 808 {
 809         u32 m1, m2, n, p1, p2, n1;
 810         u32 f_vco, p, p_best = 0, m, f_out;
 811         u32 err_max, err_target, err_best = 10000000;
 812         u32 n_best = 0, m_best = 0, f_best, f_err;
 813         u32 p_min, p_max, p_inc, div_min, div_max;
 814
 815         /* Accept 0.5% difference, but aim for 0.1% */
 816         err_max = 5 * clock / 1000;
 817         err_target = clock / 1000;
 818
 819         DBG_MSG("Clock is %d\n", clock);
 820
 821         div_max = plls[index].max_vco_freq / clock;
 822         div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 823
 824         if (clock <= plls[index].p_transition_clock)
 825                 p_inc = 4;
 826         else
 827                 p_inc = 2;
 828         p_min = ROUND_UP_TO(div_min, p_inc);
 829         p_max = ROUND_DOWN_TO(div_max, p_inc);
 830         if (p_min < plls[index].min_p)
 831                 p_min = 4;
 832         if (p_max > plls[index].max_p)
 833                 p_max = 128;
 834
 835         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 836
 837         p = p_min;
 838         do {
 839                 if (splitp(index, p, &p1, &p2)) {
 840                         WRN_MSG("cannot split p = %d\n", p);
 841                         p += p_inc;
 842                         continue;
 843                 }
 844                 n = plls[index].min_n;
 845                 f_vco = clock * p;
 846
 847                 do {
 848                         m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
 849                         if (m < plls[index].min_m)
 850                                 m = plls[index].min_m;
 851                         if (m > plls[index].max_m)
 852                                 m = plls[index].max_m;
 853                         f_out = calc_vclock3(index, m, n, p);
 854                         if (splitm(index, m, &m1, &m2)) {
 855                                 WRN_MSG("cannot split m = %d\n", m);
 856                                 n++;
 857                                 continue;
 858                         }
 859                         if (clock > f_out)
 860                                 f_err = clock - f_out;
 861                         else
 862                                 f_err = f_out - clock;
 863
 864                         if (f_err < err_best) {
 865                                 m_best = m;
 866                                 n_best = n;
 867                                 p_best = p;
 868                                 f_best = f_out;
 869                                 err_best = f_err;
 870                         }
 871                         n++;
 872                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 873                 p += p_inc;
 874         } while ((p <= p_max));
 875
 876         if (!m_best) {
 877                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 878                 return 1;
 879         }
 880         m = m_best;
 881         n = n_best;
 882         p = p_best;
 883         splitm(index, m, &m1, &m2);
 884         splitp(index, p, &p1, &p2);
 885         n1 = n - 2;
 886
 887         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 888                 "f: %d (%d), VCO: %d\n",
 889                 m, m1, m2, n, n1, p, p1, p2,
 890                 calc_vclock3(index, m, n, p),
 891                 calc_vclock(index, m1, m2, n1, p1, p2),
 892                 calc_vclock3(index, m, n, p) * p);
 893         *retm1 = m1;
 894         *retm2 = m2;
 895         *retn = n1;
 896         *retp1 = p1;
 897         *retp2 = p2;
 898         *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
 899
 900         return 0;
 901 }
 902
 903 static __inline__ int
 904 check_overflow(u32 value, u32 limit, const char *description)
 905 {
 906         if (value > limit) {
 907                 WRN_MSG("%s value %d exceeds limit %d\n",
 908                         description, value, limit);
 909                 return 1;
 910         }
 911         return 0;
 912 }
 913
 914 /* It is assumed that hw is filled in with the initial state information. */
 915 int
 916 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 917                      struct fb_var_screeninfo *var)
 918 {
 919         int pipe = PIPE_A;
 920         u32 *dpll, *fp0, *fp1;
 921         u32 m1, m2, n, p1, p2, clock_target, clock;
 922         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 923         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 924         u32 vsync_pol, hsync_pol;
 925         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 926
 927         DBG_MSG("intelfbhw_mode_to_hw\n");
 928
 929         /* Disable VGA */
 930         hw->vgacntrl |= VGA_DISABLE;
 931
 932         /* Check whether pipe A or pipe B is enabled. */
 933         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 934                 pipe = PIPE_A;
 935         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
 936                 pipe = PIPE_B;
 937
 938         /* Set which pipe's registers will be set. */
 939         if (pipe == PIPE_B) {
 940                 dpll = &hw->dpll_b;
 941                 fp0 = &hw->fpb0;
 942                 fp1 = &hw->fpb1;
 943                 hs = &hw->hsync_b;
 944                 hb = &hw->hblank_b;
 945                 ht = &hw->htotal_b;
 946                 vs = &hw->vsync_b;
 947                 vb = &hw->vblank_b;
 948                 vt = &hw->vtotal_b;
 949                 ss = &hw->src_size_b;
 950                 pipe_conf = &hw->pipe_b_conf;
 951         } else {
 952                 dpll = &hw->dpll_a;
 953                 fp0 = &hw->fpa0;
 954                 fp1 = &hw->fpa1;
 955                 hs = &hw->hsync_a;
 956                 hb = &hw->hblank_a;
 957                 ht = &hw->htotal_a;
 958                 vs = &hw->vsync_a;
 959                 vb = &hw->vblank_a;
 960                 vt = &hw->vtotal_a;
 961                 ss = &hw->src_size_a;
 962                 pipe_conf = &hw->pipe_a_conf;
 963         }
 964
 965         /* Use ADPA register for sync control. */
 966         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
 967
 968         /* sync polarity */
 969         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
 970                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
 971         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
 972                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
 973         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
 974                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
 975         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
 976                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
 977
 978         /* Connect correct pipe to the analog port DAC */
 979         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
 980         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
 981
 982         /* Set DPMS state to D0 (on) */
 983         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
 984         hw->adpa |= ADPA_DPMS_D0;
 985
 986         hw->adpa |= ADPA_DAC_ENABLE;
 987
 988         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
 989         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
 990         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
 991
 992         /* Desired clock in kHz */
 993         clock_target = 1000000000 / var->pixclock;
 994
 995         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
 996                 WRN_MSG("calc_pll_params failed\n");
 997                 return 1;
 998         }
 999
1000         /* Check for overflow. */
1001         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1002                 return 1;
1003         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1004                 return 1;
1005         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1006                 return 1;
1007         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1008                 return 1;
1009         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1010                 return 1;
1011
1012         *dpll &= ~DPLL_P1_FORCE_DIV2;
1013         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1014                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1015         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1016         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1017                (m1 << FP_M1_DIVISOR_SHIFT) |
1018                (m2 << FP_M2_DIVISOR_SHIFT);
1019         *fp1 = *fp0;
1020
1021         hw->dvob &= ~PORT_ENABLE;
1022         hw->dvoc &= ~PORT_ENABLE;
1023
1024         /* Use display plane A. */
1025         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1026         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1027         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1028         switch (intelfb_var_to_depth(var)) {
1029         case 8:
1030                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1031                 break;
1032         case 15:
1033                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1034                 break;
1035         case 16:
1036                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1037                 break;
1038         case 24:
1039                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1040                 break;
1041         }
1042         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1043         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1044
1045         /* Set CRTC registers. */
1046         hactive = var->xres;
1047         hsync_start = hactive + var->right_margin;
1048         hsync_end = hsync_start + var->hsync_len;
1049         htotal = hsync_end + var->left_margin;
1050         hblank_start = hactive;
1051         hblank_end = htotal;
1052
1053         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1054                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1055                 hblank_end);
1056
1057         vactive = var->yres;
1058         vsync_start = vactive + var->lower_margin;
1059         vsync_end = vsync_start + var->vsync_len;
1060         vtotal = vsync_end + var->upper_margin;
1061         vblank_start = vactive;
1062         vblank_end = vtotal;
1063         vblank_end = vsync_end + 1;
1064
1065         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1066                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1067                 vblank_end);
1068
1069         /* Adjust for register values, and check for overflow. */
1070         hactive--;
1071         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1072                 return 1;
1073         hsync_start--;
1074         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1075                 return 1;
1076         hsync_end--;
1077         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1078                 return 1;
1079         htotal--;
1080         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1081                 return 1;
1082         hblank_start--;
1083         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1084                 return 1;
1085         hblank_end--;
1086         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1087                 return 1;
1088
1089         vactive--;
1090         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1091                 return 1;
1092         vsync_start--;
1093         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1094                 return 1;
1095         vsync_end--;
1096         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1097                 return 1;
1098         vtotal--;
1099         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1100                 return 1;
1101         vblank_start--;
1102         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1103                 return 1;
1104         vblank_end--;
1105         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1106                 return 1;
1107
1108         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1109         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1110               (hblank_end << HSYNCEND_SHIFT);
1111         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1112
1113         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1114         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1115               (vblank_end << VSYNCEND_SHIFT);
1116         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1117         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1118               (vactive << SRC_SIZE_VERT_SHIFT);
1119
1120         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1121         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1122
1123         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1124                           var->xoffset * var->bits_per_pixel / 8;
1125
1126         hw->disp_a_base += dinfo->fb.offset << 12;
1127
1128         /* Check stride alignment. */
1129         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1130                 WRN_MSG("display stride %d has bad alignment %d\n",
1131                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1132                 return 1;
1133         }
1134
1135         /* Set the palette to 8-bit mode. */
1136         *pipe_conf &= ~PIPECONF_GAMMA;
1137         return 0;
1138 }
1139
1140 /* Program a (non-VGA) video mode. */
1141 int
1142 intelfbhw_program_mode(struct intelfb_info *dinfo,
1143                      const struct intelfb_hwstate *hw, int blank)
1144 {
1145         int pipe = PIPE_A;
1146         u32 tmp;
1147         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1148         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1149         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1150         u32 hsync_reg, htotal_reg, hblank_reg;
1151         u32 vsync_reg, vtotal_reg, vblank_reg;
1152         u32 src_size_reg;
1153
1154         /* Assume single pipe, display plane A, analog CRT. */
1155
1156 #if VERBOSE > 0
1157         DBG_MSG("intelfbhw_program_mode\n");
1158 #endif
1159
1160         /* Disable VGA */
1161         tmp = INREG(VGACNTRL);
1162         tmp |= VGA_DISABLE;
1163         OUTREG(VGACNTRL, tmp);
1164
1165         /* Check whether pipe A or pipe B is enabled. */
1166         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1167                 pipe = PIPE_A;
1168         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1169                 pipe = PIPE_B;
1170
1171         dinfo->pipe = pipe;
1172
1173         if (pipe == PIPE_B) {
1174                 dpll = &hw->dpll_b;
1175                 fp0 = &hw->fpb0;
1176                 fp1 = &hw->fpb1;
1177                 pipe_conf = &hw->pipe_b_conf;
1178                 hs = &hw->hsync_b;
1179                 hb = &hw->hblank_b;
1180                 ht = &hw->htotal_b;
1181                 vs = &hw->vsync_b;
1182                 vb = &hw->vblank_b;
1183                 vt = &hw->vtotal_b;
1184                 ss = &hw->src_size_b;
1185                 dpll_reg = DPLL_B;
1186                 fp0_reg = FPB0;
1187                 fp1_reg = FPB1;
1188                 pipe_conf_reg = PIPEBCONF;
1189                 hsync_reg = HSYNC_B;
1190                 htotal_reg = HTOTAL_B;
1191                 hblank_reg = HBLANK_B;
1192                 vsync_reg = VSYNC_B;
1193                 vtotal_reg = VTOTAL_B;
1194                 vblank_reg = VBLANK_B;
1195                 src_size_reg = SRC_SIZE_B;
1196         } else {
1197                 dpll = &hw->dpll_a;
1198                 fp0 = &hw->fpa0;
1199                 fp1 = &hw->fpa1;
1200                 pipe_conf = &hw->pipe_a_conf;
1201                 hs = &hw->hsync_a;
1202                 hb = &hw->hblank_a;
1203                 ht = &hw->htotal_a;
1204                 vs = &hw->vsync_a;
1205                 vb = &hw->vblank_a;
1206                 vt = &hw->vtotal_a;
1207                 ss = &hw->src_size_a;
1208                 dpll_reg = DPLL_A;
1209                 fp0_reg = FPA0;
1210                 fp1_reg = FPA1;
1211                 pipe_conf_reg = PIPEACONF;
1212                 hsync_reg = HSYNC_A;
1213                 htotal_reg = HTOTAL_A;
1214                 hblank_reg = HBLANK_A;
1215                 vsync_reg = VSYNC_A;
1216                 vtotal_reg = VTOTAL_A;
1217                 vblank_reg = VBLANK_A;
1218                 src_size_reg = SRC_SIZE_A;
1219         }
1220
1221         /* Disable planes A and B. */
1222         tmp = INREG(DSPACNTR);
1223         tmp &= ~DISPPLANE_PLANE_ENABLE;
1224         OUTREG(DSPACNTR, tmp);
1225         tmp = INREG(DSPBCNTR);
1226         tmp &= ~DISPPLANE_PLANE_ENABLE;
1227         OUTREG(DSPBCNTR, tmp);
1228
1229         /* Wait for vblank.  For now, just wait for a 50Hz cycle (20ms)) */
1230         mdelay(20);
1231
1232         /* Disable Sync */
1233         tmp = INREG(ADPA);
1234         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1235         tmp |= ADPA_DPMS_D3;
1236         OUTREG(ADPA, tmp);
1237
1238         /* turn off pipe */
1239         tmp = INREG(pipe_conf_reg);
1240         tmp &= ~PIPECONF_ENABLE;
1241         OUTREG(pipe_conf_reg, tmp);
1242
1243         /* turn off PLL */
1244         tmp = INREG(dpll_reg);
1245         dpll_reg &= ~DPLL_VCO_ENABLE;
1246         OUTREG(dpll_reg, tmp);
1247
1248         /* Set PLL parameters */
1249         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1250         OUTREG(fp0_reg, *fp0);
1251         OUTREG(fp1_reg, *fp1);
1252
1253         /* Set pipe parameters */
1254         OUTREG(hsync_reg, *hs);
1255         OUTREG(hblank_reg, *hb);
1256         OUTREG(htotal_reg, *ht);
1257         OUTREG(vsync_reg, *vs);
1258         OUTREG(vblank_reg, *vb);
1259         OUTREG(vtotal_reg, *vt);
1260         OUTREG(src_size_reg, *ss);
1261
1262         /* Set DVOs B/C */
1263         OUTREG(DVOB, hw->dvob);
1264         OUTREG(DVOC, hw->dvoc);
1265
1266         /* Set ADPA */
1267         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1268
1269         /* Enable PLL */
1270         tmp = INREG(dpll_reg);
1271         tmp |= DPLL_VCO_ENABLE;
1272         OUTREG(dpll_reg, tmp);
1273
1274         /* Enable pipe */
1275         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1276
1277         /* Enable sync */
1278         tmp = INREG(ADPA);
1279         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1280         tmp |= ADPA_DPMS_D0;
1281         OUTREG(ADPA, tmp);
1282
1283         /* setup display plane */
1284         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1285                 /*
1286                  *      i830M errata: the display plane must be enabled
1287                  *      to allow writes to the other bits in the plane
1288                  *      control register.
1289                  */
1290                 tmp = INREG(DSPACNTR);
1291                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1292                         tmp |= DISPPLANE_PLANE_ENABLE;
1293                         OUTREG(DSPACNTR, tmp);
1294                         OUTREG(DSPACNTR,
1295                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1296                         mdelay(1);
1297               }
1298         }
1299
1300         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1301         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1302         OUTREG(DSPABASE, hw->disp_a_base);
1303
1304         /* Enable plane */
1305         if (!blank) {
1306                 tmp = INREG(DSPACNTR);
1307                 tmp |= DISPPLANE_PLANE_ENABLE;
1308                 OUTREG(DSPACNTR, tmp);
1309                 OUTREG(DSPABASE, hw->disp_a_base);
1310         }
1311
1312         return 0;
1313 }
1314
1315 /* forward declarations */
1316 static void refresh_ring(struct intelfb_info *dinfo);
1317 static void reset_state(struct intelfb_info *dinfo);
1318 static void do_flush(struct intelfb_info *dinfo);
1319
1320 static int
1321 wait_ring(struct intelfb_info *dinfo, int n)
1322 {
1323         int i = 0;
1324         unsigned long end;
1325         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1326
1327 #if VERBOSE > 0
1328         DBG_MSG("wait_ring: %d\n", n);
1329 #endif
1330
1331         end = jiffies + (HZ * 3);
1332         while (dinfo->ring_space < n) {
1333                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1334                                                    RING_HEAD_MASK);
1335                 if (dinfo->ring_tail + RING_MIN_FREE <
1336                     (u32 __iomem) dinfo->ring_head)
1337                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1338                                 - (dinfo->ring_tail + RING_MIN_FREE);
1339                 else
1340                         dinfo->ring_space = (dinfo->ring.size +
1341                                              (u32 __iomem) dinfo->ring_head)
1342                                 - (dinfo->ring_tail + RING_MIN_FREE);
1343                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1344                         end = jiffies + (HZ * 3);
1345                         last_head = (u32 __iomem) dinfo->ring_head;
1346                 }
1347                 i++;
1348                 if (time_before(end, jiffies)) {
1349                         if (!i) {
1350                                 /* Try again */
1351                                 reset_state(dinfo);
1352                                 refresh_ring(dinfo);
1353                                 do_flush(dinfo);
1354                                 end = jiffies + (HZ * 3);
1355                                 i = 1;
1356                         } else {
1357                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1358                                         dinfo->ring_space, n);
1359                                 WRN_MSG("lockup - turning off hardware "
1360                                         "acceleration\n");
1361                                 dinfo->ring_lockup = 1;
1362                                 break;
1363                         }
1364                 }
1365                 udelay(1);
1366         }
1367         return i;
1368 }
1369
1370 static void
1371 do_flush(struct intelfb_info *dinfo) {
1372         START_RING(2);
1373         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1374         OUT_RING(MI_NOOP);
1375         ADVANCE_RING();
1376 }
1377
1378 void
1379 intelfbhw_do_sync(struct intelfb_info *dinfo)
1380 {
1381 #if VERBOSE > 0
1382         DBG_MSG("intelfbhw_do_sync\n");
1383 #endif
1384
1385         if (!dinfo->accel)
1386                 return;
1387
1388         /*
1389          * Send a flush, then wait until the ring is empty.  This is what
1390          * the XFree86 driver does, and actually it doesn't seem a lot worse
1391          * than the recommended method (both have problems).
1392          */
1393         do_flush(dinfo);
1394         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1395         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1396 }
1397
1398 static void
1399 refresh_ring(struct intelfb_info *dinfo)
1400 {
1401 #if VERBOSE > 0
1402         DBG_MSG("refresh_ring\n");
1403 #endif
1404
1405         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1406                                            RING_HEAD_MASK);
1407         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1408         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1409                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1410                         - (dinfo->ring_tail + RING_MIN_FREE);
1411         else
1412                 dinfo->ring_space = (dinfo->ring.size +
1413                                      (u32 __iomem) dinfo->ring_head)
1414                         - (dinfo->ring_tail + RING_MIN_FREE);
1415 }
1416
1417 static void
1418 reset_state(struct intelfb_info *dinfo)
1419 {
1420         int i;
1421         u32 tmp;
1422
1423 #if VERBOSE > 0
1424         DBG_MSG("reset_state\n");
1425 #endif
1426
1427         for (i = 0; i < FENCE_NUM; i++)
1428                 OUTREG(FENCE + (i << 2), 0);
1429
1430         /* Flush the ring buffer if it's enabled. */
1431         tmp = INREG(PRI_RING_LENGTH);
1432         if (tmp & RING_ENABLE) {
1433 #if VERBOSE > 0
1434                 DBG_MSG("reset_state: ring was enabled\n");
1435 #endif
1436                 refresh_ring(dinfo);
1437                 intelfbhw_do_sync(dinfo);
1438                 DO_RING_IDLE();
1439         }
1440
1441         OUTREG(PRI_RING_LENGTH, 0);
1442         OUTREG(PRI_RING_HEAD, 0);
1443         OUTREG(PRI_RING_TAIL, 0);
1444         OUTREG(PRI_RING_START, 0);
1445 }
1446
1447 /* Stop the 2D engine, and turn off the ring buffer. */
1448 void
1449 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1450 {
1451 #if VERBOSE > 0
1452         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1453                 dinfo->ring_active);
1454 #endif
1455
1456         if (!dinfo->accel)
1457                 return;
1458
1459         dinfo->ring_active = 0;
1460         reset_state(dinfo);
1461 }
1462
1463 /*
1464  * Enable the ring buffer, and initialise the 2D engine.
1465  * It is assumed that the graphics engine has been stopped by previously
1466  * calling intelfb_2d_stop().
1467  */
1468 void
1469 intelfbhw_2d_start(struct intelfb_info *dinfo)
1470 {
1471 #if VERBOSE > 0
1472         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1473                 dinfo->accel, dinfo->ring_active);
1474 #endif
1475
1476         if (!dinfo->accel)
1477                 return;
1478
1479         /* Initialise the primary ring buffer. */
1480         OUTREG(PRI_RING_LENGTH, 0);
1481         OUTREG(PRI_RING_TAIL, 0);
1482         OUTREG(PRI_RING_HEAD, 0);
1483
1484         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1485         OUTREG(PRI_RING_LENGTH,
1486                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1487                 RING_NO_REPORT | RING_ENABLE);
1488         refresh_ring(dinfo);
1489         dinfo->ring_active = 1;
1490 }
1491
1492 /* 2D fillrect (solid fill or invert) */
1493 void
1494 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1495                       u32 color, u32 pitch, u32 bpp, u32 rop)
1496 {
1497         u32 br00, br09, br13, br14, br16;
1498
1499 #if VERBOSE > 0
1500         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1501                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1502 #endif
1503
1504         br00 = COLOR_BLT_CMD;
1505         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1506         br13 = (rop << ROP_SHIFT) | pitch;
1507         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1508         br16 = color;
1509
1510         switch (bpp) {
1511         case 8:
1512                 br13 |= COLOR_DEPTH_8;
1513                 break;
1514         case 16:
1515                 br13 |= COLOR_DEPTH_16;
1516                 break;
1517         case 32:
1518                 br13 |= COLOR_DEPTH_32;
1519                 br00 |= WRITE_ALPHA | WRITE_RGB;
1520                 break;
1521         }
1522
1523         START_RING(6);
1524         OUT_RING(br00);
1525         OUT_RING(br13);
1526         OUT_RING(br14);
1527         OUT_RING(br09);
1528         OUT_RING(br16);
1529         OUT_RING(MI_NOOP);
1530         ADVANCE_RING();
1531
1532 #if VERBOSE > 0
1533         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1534                 dinfo->ring_tail, dinfo->ring_space);
1535 #endif
1536 }
1537
1538 void
1539 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1540                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1541 {
1542         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1543
1544 #if VERBOSE > 0
1545         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1546                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1547 #endif
1548
1549         br00 = XY_SRC_COPY_BLT_CMD;
1550         br09 = dinfo->fb_start;
1551         br11 = (pitch << PITCH_SHIFT);
1552         br12 = dinfo->fb_start;
1553         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1554         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1555         br23 = ((dstx + w) << WIDTH_SHIFT) |
1556                ((dsty + h) << HEIGHT_SHIFT);
1557         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1558
1559         switch (bpp) {
1560         case 8:
1561                 br13 |= COLOR_DEPTH_8;
1562                 break;
1563         case 16:
1564                 br13 |= COLOR_DEPTH_16;
1565                 break;
1566         case 32:
1567                 br13 |= COLOR_DEPTH_32;
1568                 br00 |= WRITE_ALPHA | WRITE_RGB;
1569                 break;
1570         }
1571
1572         START_RING(8);
1573         OUT_RING(br00);
1574         OUT_RING(br13);
1575         OUT_RING(br22);
1576         OUT_RING(br23);
1577         OUT_RING(br09);
1578         OUT_RING(br26);
1579         OUT_RING(br11);
1580         OUT_RING(br12);
1581         ADVANCE_RING();
1582 }
1583
1584 int
1585 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1586                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1587 {
1588         int nbytes, ndwords, pad, tmp;
1589         u32 br00, br09, br13, br18, br19, br22, br23;
1590         int dat, ix, iy, iw;
1591         int i, j;
1592
1593 #if VERBOSE > 0
1594         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1595 #endif
1596
1597         /* size in bytes of a padded scanline */
1598         nbytes = ROUND_UP_TO(w, 16) / 8;
1599
1600         /* Total bytes of padded scanline data to write out. */
1601         nbytes = nbytes * h;
1602
1603         /*
1604          * Check if the glyph data exceeds the immediate mode limit.
1605          * It would take a large font (1K pixels) to hit this limit.
1606          */
1607         if (nbytes > MAX_MONO_IMM_SIZE)
1608                 return 0;
1609
1610         /* Src data is packaged a dword (32-bit) at a time. */
1611         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1612
1613         /*
1614          * Ring has to be padded to a quad word. But because the command starts
1615            with 7 bytes, pad only if there is an even number of ndwords
1616          */
1617         pad = !(ndwords % 2);
1618
1619         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1620         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1621         br09 = dinfo->fb_start;
1622         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1623         br18 = bg;
1624         br19 = fg;
1625         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1626         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1627
1628         switch (bpp) {
1629         case 8:
1630                 br13 |= COLOR_DEPTH_8;
1631                 break;
1632         case 16:
1633                 br13 |= COLOR_DEPTH_16;
1634                 break;
1635         case 32:
1636                 br13 |= COLOR_DEPTH_32;
1637                 br00 |= WRITE_ALPHA | WRITE_RGB;
1638                 break;
1639         }
1640
1641         START_RING(8 + ndwords);
1642         OUT_RING(br00);
1643         OUT_RING(br13);
1644         OUT_RING(br22);
1645         OUT_RING(br23);
1646         OUT_RING(br09);
1647         OUT_RING(br18);
1648         OUT_RING(br19);
1649         ix = iy = 0;
1650         iw = ROUND_UP_TO(w, 8) / 8;
1651         while (ndwords--) {
1652                 dat = 0;
1653                 for (j = 0; j < 2; ++j) {
1654                         for (i = 0; i < 2; ++i) {
1655                                 if (ix != iw || i == 0)
1656                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1657                         }
1658                         if (ix == iw && iy != (h-1)) {
1659                                 ix = 0;
1660                                 ++iy;
1661                         }
1662                 }
1663                 OUT_RING(dat);
1664         }
1665         if (pad)
1666                 OUT_RING(MI_NOOP);
1667         ADVANCE_RING();
1668
1669         return 1;
1670 }
1671
1672 /* HW cursor functions. */
1673 void
1674 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1675 {
1676         u32 tmp;
1677
1678 #if VERBOSE > 0
1679         DBG_MSG("intelfbhw_cursor_init\n");
1680 #endif
1681
1682         if (dinfo->mobile) {
1683                 if (!dinfo->cursor.physical)
1684                         return;
1685                 tmp = INREG(CURSOR_A_CONTROL);
1686                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1687                          CURSOR_MEM_TYPE_LOCAL |
1688                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1689                 tmp |= CURSOR_MODE_DISABLE;
1690                 OUTREG(CURSOR_A_CONTROL, tmp);
1691                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1692         } else {
1693                 tmp = INREG(CURSOR_CONTROL);
1694                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1695                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1696                 tmp = CURSOR_FORMAT_3C;
1697                 OUTREG(CURSOR_CONTROL, tmp);
1698                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1699                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1700                       (64 << CURSOR_SIZE_V_SHIFT);
1701                 OUTREG(CURSOR_SIZE, tmp);
1702         }
1703 }
1704
1705 void
1706 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1707 {
1708         u32 tmp;
1709
1710 #if VERBOSE > 0
1711         DBG_MSG("intelfbhw_cursor_hide\n");
1712 #endif
1713
1714         dinfo->cursor_on = 0;
1715         if (dinfo->mobile) {
1716                 if (!dinfo->cursor.physical)
1717                         return;
1718                 tmp = INREG(CURSOR_A_CONTROL);
1719                 tmp &= ~CURSOR_MODE_MASK;
1720                 tmp |= CURSOR_MODE_DISABLE;
1721                 OUTREG(CURSOR_A_CONTROL, tmp);
1722                 /* Flush changes */
1723                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1724         } else {
1725                 tmp = INREG(CURSOR_CONTROL);
1726                 tmp &= ~CURSOR_ENABLE;
1727                 OUTREG(CURSOR_CONTROL, tmp);
1728         }
1729 }
1730
1731 void
1732 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1733 {
1734         u32 tmp;
1735
1736 #if VERBOSE > 0
1737         DBG_MSG("intelfbhw_cursor_show\n");
1738 #endif
1739
1740         dinfo->cursor_on = 1;
1741
1742         if (dinfo->cursor_blanked)
1743                 return;
1744
1745         if (dinfo->mobile) {
1746                 if (!dinfo->cursor.physical)
1747                         return;
1748                 tmp = INREG(CURSOR_A_CONTROL);
1749                 tmp &= ~CURSOR_MODE_MASK;
1750                 tmp |= CURSOR_MODE_64_4C_AX;
1751                 OUTREG(CURSOR_A_CONTROL, tmp);
1752                 /* Flush changes */
1753                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1754         } else {
1755                 tmp = INREG(CURSOR_CONTROL);
1756                 tmp |= CURSOR_ENABLE;
1757                 OUTREG(CURSOR_CONTROL, tmp);
1758         }
1759 }
1760
1761 void
1762 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1763 {
1764         u32 tmp;
1765
1766 #if VERBOSE > 0
1767         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1768 #endif
1769
1770         /*
1771          * Sets the position.  The coordinates are assumed to already
1772          * have any offset adjusted.  Assume that the cursor is never
1773          * completely off-screen, and that x, y are always >= 0.
1774          */
1775
1776         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1777               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1778         OUTREG(CURSOR_A_POSITION, tmp);
1779 }
1780
1781 void
1782 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1783 {
1784 #if VERBOSE > 0
1785         DBG_MSG("intelfbhw_cursor_setcolor\n");
1786 #endif
1787
1788         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1789         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1790         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1791         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1792 }
1793
1794 void
1795 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1796                       u8 *data)
1797 {
1798         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1799         int i, j, w = width / 8;
1800         int mod = width % 8, t_mask, d_mask;
1801
1802 #if VERBOSE > 0
1803         DBG_MSG("intelfbhw_cursor_load\n");
1804 #endif
1805
1806         if (!dinfo->cursor.virtual)
1807                 return;
1808
1809         t_mask = 0xff >> mod;
1810         d_mask = ~(0xff >> mod);
1811         for (i = height; i--; ) {
1812                 for (j = 0; j < w; j++) {
1813                         writeb(0x00, addr + j);
1814                         writeb(*(data++), addr + j+8);
1815                 }
1816                 if (mod) {
1817                         writeb(t_mask, addr + j);
1818                         writeb(*(data++) & d_mask, addr + j+8);
1819                 }
1820                 addr += 16;
1821         }
1822 }
1823
1824 void
1825 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1826         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1827         int i, j;
1828
1829 #if VERBOSE > 0
1830         DBG_MSG("intelfbhw_cursor_reset\n");
1831 #endif
1832
1833         if (!dinfo->cursor.virtual)
1834                 return;
1835
1836         for (i = 64; i--; ) {
1837                 for (j = 0; j < 8; j++) {
1838                         writeb(0xff, addr + j+0);
1839                         writeb(0x00, addr + j+8);
1840                 }
1841                 addr += 16;
1842         }
1843 }