SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco_freq, max_vco_freq;
  51         int p_transition_clock;
  52 };
  53
  54 #define PLLS_I8xx 0
  55 #define PLLS_I9xx 1
  56 #define PLLS_MAX 2
  57
  58 struct pll_min_max plls[PLLS_MAX] = {
  59         { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000 }, //I8xx
  60         {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000 }  //I9xx
  61 };
  62
  63 int
  64 intelfbhw_get_chipset(struct pci_dev *pdev, const char **name, int *chipset,
  65                       int *mobile)
  66 {
  67         u32 tmp;
  68
  69         if (!pdev || !name || !chipset || !mobile)
  70                 return 1;
  71
  72         switch (pdev->device) {
  73         case PCI_DEVICE_ID_INTEL_830M:
  74                 *name = "Intel(R) 830M";
  75                 *chipset = INTEL_830M;
  76                 *mobile = 1;
  77                 return 0;
  78         case PCI_DEVICE_ID_INTEL_845G:
  79                 *name = "Intel(R) 845G";
  80                 *chipset = INTEL_845G;
  81                 *mobile = 0;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_85XGM:
  84                 tmp = 0;
  85                 *mobile = 1;
  86                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  87                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  88                         INTEL_85X_VARIANT_MASK) {
  89                 case INTEL_VAR_855GME:
  90                         *name = "Intel(R) 855GME";
  91                         *chipset = INTEL_855GME;
  92                         return 0;
  93                 case INTEL_VAR_855GM:
  94                         *name = "Intel(R) 855GM";
  95                         *chipset = INTEL_855GM;
  96                         return 0;
  97                 case INTEL_VAR_852GME:
  98                         *name = "Intel(R) 852GME";
  99                         *chipset = INTEL_852GME;
 100                         return 0;
 101                 case INTEL_VAR_852GM:
 102                         *name = "Intel(R) 852GM";
 103                         *chipset = INTEL_852GM;
 104                         return 0;
 105                 default:
 106                         *name = "Intel(R) 852GM/855GM";
 107                         *chipset = INTEL_85XGM;
 108                         return 0;
 109                 }
 110                 break;
 111         case PCI_DEVICE_ID_INTEL_865G:
 112                 *name = "Intel(R) 865G";
 113                 *chipset = INTEL_865G;
 114                 *mobile = 0;
 115                 return 0;
 116         case PCI_DEVICE_ID_INTEL_915G:
 117                 *name = "Intel(R) 915G";
 118                 *chipset = INTEL_915G;
 119                 *mobile = 0;
 120                 return 0;
 121         case PCI_DEVICE_ID_INTEL_915GM:
 122                 *name = "Intel(R) 915GM";
 123                 *chipset = INTEL_915GM;
 124                 *mobile = 1;
 125                 return 0;
 126         default:
 127                 return 1;
 128         }
 129 }
 130
 131 int
 132 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 133                      int *stolen_size)
 134 {
 135         struct pci_dev *bridge_dev;
 136         u16 tmp;
 137
 138         if (!pdev || !aperture_size || !stolen_size)
 139                 return 1;
 140
 141         /* Find the bridge device.  It is always 0:0.0 */
 142         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 143                 ERR_MSG("cannot find bridge device\n");
 144                 return 1;
 145         }
 146
 147         /* Get the fb aperture size and "stolen" memory amount. */
 148         tmp = 0;
 149         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 150         switch (pdev->device) {
 151         case PCI_DEVICE_ID_INTEL_830M:
 152         case PCI_DEVICE_ID_INTEL_845G:
 153                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 154                         *aperture_size = MB(64);
 155                 else
 156                         *aperture_size = MB(128);
 157                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 158                 case INTEL_830_GMCH_GMS_STOLEN_512:
 159                         *stolen_size = KB(512) - KB(132);
 160                         return 0;
 161                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 162                         *stolen_size = MB(1) - KB(132);
 163                         return 0;
 164                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 165                         *stolen_size = MB(8) - KB(132);
 166                         return 0;
 167                 case INTEL_830_GMCH_GMS_LOCAL:
 168                         ERR_MSG("only local memory found\n");
 169                         return 1;
 170                 case INTEL_830_GMCH_GMS_DISABLED:
 171                         ERR_MSG("video memory is disabled\n");
 172                         return 1;
 173                 default:
 174                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 175                                 tmp & INTEL_830_GMCH_GMS_MASK);
 176                         return 1;
 177                 }
 178                 break;
 179         default:
 180                 *aperture_size = MB(128);
 181                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 182                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 183                         *stolen_size = MB(1) - KB(132);
 184                         return 0;
 185                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 186                         *stolen_size = MB(4) - KB(132);
 187                         return 0;
 188                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 189                         *stolen_size = MB(8) - KB(132);
 190                         return 0;
 191                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 192                         *stolen_size = MB(16) - KB(132);
 193                         return 0;
 194                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 195                         *stolen_size = MB(32) - KB(132);
 196                         return 0;
 197                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 198                         *stolen_size = MB(48) - KB(132);
 199                         return 0;
 200                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 201                         *stolen_size = MB(64) - KB(132);
 202                         return 0;
 203                 case INTEL_855_GMCH_GMS_DISABLED:
 204                         ERR_MSG("video memory is disabled\n");
 205                         return 0;
 206                 default:
 207                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 208                                 tmp & INTEL_855_GMCH_GMS_MASK);
 209                         return 1;
 210                 }
 211         }
 212 }
 213
 214 int
 215 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 216 {
 217         int dvo = 0;
 218
 219         if (INREG(LVDS) & PORT_ENABLE)
 220                 dvo |= LVDS_PORT;
 221         if (INREG(DVOA) & PORT_ENABLE)
 222                 dvo |= DVOA_PORT;
 223         if (INREG(DVOB) & PORT_ENABLE)
 224                 dvo |= DVOB_PORT;
 225         if (INREG(DVOC) & PORT_ENABLE)
 226                 dvo |= DVOC_PORT;
 227
 228         return dvo;
 229 }
 230
 231 const char *
 232 intelfbhw_dvo_to_string(int dvo)
 233 {
 234         if (dvo & DVOA_PORT)
 235                 return "DVO port A";
 236         else if (dvo & DVOB_PORT)
 237                 return "DVO port B";
 238         else if (dvo & DVOC_PORT)
 239                 return "DVO port C";
 240         else if (dvo & LVDS_PORT)
 241                 return "LVDS port";
 242         else
 243                 return NULL;
 244 }
 245
 246
 247 int
 248 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 249                         struct fb_var_screeninfo *var)
 250 {
 251         int bytes_per_pixel;
 252         int tmp;
 253
 254 #if VERBOSE > 0
 255         DBG_MSG("intelfbhw_validate_mode\n");
 256 #endif
 257
 258         bytes_per_pixel = var->bits_per_pixel / 8;
 259         if (bytes_per_pixel == 3)
 260                 bytes_per_pixel = 4;
 261
 262         /* Check if enough video memory. */
 263         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 264         if (tmp > dinfo->fb.size) {
 265                 WRN_MSG("Not enough video ram for mode "
 266                         "(%d KByte vs %d KByte).\n",
 267                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 268                 return 1;
 269         }
 270
 271         /* Check if x/y limits are OK. */
 272         if (var->xres - 1 > HACTIVE_MASK) {
 273                 WRN_MSG("X resolution too large (%d vs %d).\n",
 274                         var->xres, HACTIVE_MASK + 1);
 275                 return 1;
 276         }
 277         if (var->yres - 1 > VACTIVE_MASK) {
 278                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 279                         var->yres, VACTIVE_MASK + 1);
 280                 return 1;
 281         }
 282
 283         /* Check for interlaced/doublescan modes. */
 284         if (var->vmode & FB_VMODE_INTERLACED) {
 285                 WRN_MSG("Mode is interlaced.\n");
 286                 return 1;
 287         }
 288         if (var->vmode & FB_VMODE_DOUBLE) {
 289                 WRN_MSG("Mode is double-scan.\n");
 290                 return 1;
 291         }
 292
 293         /* Check if clock is OK. */
 294         tmp = 1000000000 / var->pixclock;
 295         if (tmp < MIN_CLOCK) {
 296                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 297                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 298                 return 1;
 299         }
 300         if (tmp > MAX_CLOCK) {
 301                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 302                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 303                 return 1;
 304         }
 305
 306         return 0;
 307 }
 308
 309 int
 310 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 311 {
 312         struct intelfb_info *dinfo = GET_DINFO(info);
 313         u32 offset, xoffset, yoffset;
 314
 315 #if VERBOSE > 0
 316         DBG_MSG("intelfbhw_pan_display\n");
 317 #endif
 318
 319         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 320         yoffset = var->yoffset;
 321
 322         if ((xoffset + var->xres > var->xres_virtual) ||
 323             (yoffset + var->yres > var->yres_virtual))
 324                 return -EINVAL;
 325
 326         offset = (yoffset * dinfo->pitch) +
 327                  (xoffset * var->bits_per_pixel) / 8;
 328
 329         offset += dinfo->fb.offset << 12;
 330
 331         OUTREG(DSPABASE, offset);
 332
 333         return 0;
 334 }
 335
 336 /* Blank the screen. */
 337 void
 338 intelfbhw_do_blank(int blank, struct fb_info *info)
 339 {
 340         struct intelfb_info *dinfo = GET_DINFO(info);
 341         u32 tmp;
 342
 343 #if VERBOSE > 0
 344         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 345 #endif
 346
 347         /* Turn plane A on or off */
 348         tmp = INREG(DSPACNTR);
 349         if (blank)
 350                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 351         else
 352                 tmp |= DISPPLANE_PLANE_ENABLE;
 353         OUTREG(DSPACNTR, tmp);
 354         /* Flush */
 355         tmp = INREG(DSPABASE);
 356         OUTREG(DSPABASE, tmp);
 357
 358         /* Turn off/on the HW cursor */
 359 #if VERBOSE > 0
 360         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 361 #endif
 362         if (dinfo->cursor_on) {
 363                 if (blank) {
 364                         intelfbhw_cursor_hide(dinfo);
 365                 } else {
 366                         intelfbhw_cursor_show(dinfo);
 367                 }
 368                 dinfo->cursor_on = 1;
 369         }
 370         dinfo->cursor_blanked = blank;
 371
 372         /* Set DPMS level */
 373         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 374         switch (blank) {
 375         case FB_BLANK_UNBLANK:
 376         case FB_BLANK_NORMAL:
 377                 tmp |= ADPA_DPMS_D0;
 378                 break;
 379         case FB_BLANK_VSYNC_SUSPEND:
 380                 tmp |= ADPA_DPMS_D1;
 381                 break;
 382         case FB_BLANK_HSYNC_SUSPEND:
 383                 tmp |= ADPA_DPMS_D2;
 384                 break;
 385         case FB_BLANK_POWERDOWN:
 386                 tmp |= ADPA_DPMS_D3;
 387                 break;
 388         }
 389         OUTREG(ADPA, tmp);
 390
 391         return;
 392 }
 393
 394
 395 void
 396 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 397                     unsigned red, unsigned green, unsigned blue,
 398                     unsigned transp)
 399 {
 400 #if VERBOSE > 0
 401         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 402                 regno, red, green, blue);
 403 #endif
 404
 405         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 406                           PALETTE_A : PALETTE_B;
 407
 408         OUTREG(palette_reg + (regno << 2),
 409                (red << PALETTE_8_RED_SHIFT) |
 410                (green << PALETTE_8_GREEN_SHIFT) |
 411                (blue << PALETTE_8_BLUE_SHIFT));
 412 }
 413
 414
 415 int
 416 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 417                         int flag)
 418 {
 419         int i;
 420
 421 #if VERBOSE > 0
 422         DBG_MSG("intelfbhw_read_hw_state\n");
 423 #endif
 424
 425         if (!hw || !dinfo)
 426                 return -1;
 427
 428         /* Read in as much of the HW state as possible. */
 429         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 430         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 431         hw->vga_pd = INREG(VGAPD);
 432         hw->dpll_a = INREG(DPLL_A);
 433         hw->dpll_b = INREG(DPLL_B);
 434         hw->fpa0 = INREG(FPA0);
 435         hw->fpa1 = INREG(FPA1);
 436         hw->fpb0 = INREG(FPB0);
 437         hw->fpb1 = INREG(FPB1);
 438
 439         if (flag == 1)
 440                 return flag;
 441
 442 #if 0
 443         /* This seems to be a problem with the 852GM/855GM */
 444         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 445                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 446                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 447         }
 448 #endif
 449
 450         if (flag == 2)
 451                 return flag;
 452
 453         hw->htotal_a = INREG(HTOTAL_A);
 454         hw->hblank_a = INREG(HBLANK_A);
 455         hw->hsync_a = INREG(HSYNC_A);
 456         hw->vtotal_a = INREG(VTOTAL_A);
 457         hw->vblank_a = INREG(VBLANK_A);
 458         hw->vsync_a = INREG(VSYNC_A);
 459         hw->src_size_a = INREG(SRC_SIZE_A);
 460         hw->bclrpat_a = INREG(BCLRPAT_A);
 461         hw->htotal_b = INREG(HTOTAL_B);
 462         hw->hblank_b = INREG(HBLANK_B);
 463         hw->hsync_b = INREG(HSYNC_B);
 464         hw->vtotal_b = INREG(VTOTAL_B);
 465         hw->vblank_b = INREG(VBLANK_B);
 466         hw->vsync_b = INREG(VSYNC_B);
 467         hw->src_size_b = INREG(SRC_SIZE_B);
 468         hw->bclrpat_b = INREG(BCLRPAT_B);
 469
 470         if (flag == 3)
 471                 return flag;
 472
 473         hw->adpa = INREG(ADPA);
 474         hw->dvoa = INREG(DVOA);
 475         hw->dvob = INREG(DVOB);
 476         hw->dvoc = INREG(DVOC);
 477         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 478         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 479         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 480         hw->lvds = INREG(LVDS);
 481
 482         if (flag == 4)
 483                 return flag;
 484
 485         hw->pipe_a_conf = INREG(PIPEACONF);
 486         hw->pipe_b_conf = INREG(PIPEBCONF);
 487         hw->disp_arb = INREG(DISPARB);
 488
 489         if (flag == 5)
 490                 return flag;
 491
 492         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 493         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 494         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 495         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 496
 497         if (flag == 6)
 498                 return flag;
 499
 500         for (i = 0; i < 4; i++) {
 501                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 502                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 503         }
 504
 505         if (flag == 7)
 506                 return flag;
 507
 508         hw->cursor_size = INREG(CURSOR_SIZE);
 509
 510         if (flag == 8)
 511                 return flag;
 512
 513         hw->disp_a_ctrl = INREG(DSPACNTR);
 514         hw->disp_b_ctrl = INREG(DSPBCNTR);
 515         hw->disp_a_base = INREG(DSPABASE);
 516         hw->disp_b_base = INREG(DSPBBASE);
 517         hw->disp_a_stride = INREG(DSPASTRIDE);
 518         hw->disp_b_stride = INREG(DSPBSTRIDE);
 519
 520         if (flag == 9)
 521                 return flag;
 522
 523         hw->vgacntrl = INREG(VGACNTRL);
 524
 525         if (flag == 10)
 526                 return flag;
 527
 528         hw->add_id = INREG(ADD_ID);
 529
 530         if (flag == 11)
 531                 return flag;
 532
 533         for (i = 0; i < 7; i++) {
 534                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 535                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 536                 if (i < 3)
 537                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 538         }
 539
 540         for (i = 0; i < 8; i++)
 541                 hw->fence[i] = INREG(FENCE + (i << 2));
 542
 543         hw->instpm = INREG(INSTPM);
 544         hw->mem_mode = INREG(MEM_MODE);
 545         hw->fw_blc_0 = INREG(FW_BLC_0);
 546         hw->fw_blc_1 = INREG(FW_BLC_1);
 547
 548         return 0;
 549 }
 550
 551
 552 void
 553 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 554 {
 555 #if REGDUMP
 556         int i, m1, m2, n, p1, p2;
 557
 558         DBG_MSG("intelfbhw_print_hw_state\n");
 559
 560         if (!hw || !dinfo)
 561                 return;
 562         /* Read in as much of the HW state as possible. */
 563         printk("hw state dump start\n");
 564         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 565         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 566         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 567         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 568         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 569         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 570         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 571                 p1 = 0;
 572         else
 573                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 574         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 575         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 576                 m1, m2, n, p1, p2);
 577         printk("        VGA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
 578
 579         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 580         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 581         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 582         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 583                 p1 = 0;
 584         else
 585                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 586         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 587         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 588                 m1, m2, n, p1, p2);
 589         printk("        VGA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
 590
 591         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 592         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 593         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 594         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 595         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 596         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 597
 598         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 599         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 600         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 601         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 602                 p1 = 0;
 603         else
 604                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 605         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 606         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 607                 m1, m2, n, p1, p2);
 608         printk("        PLLA0: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
 609
 610         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 611         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 612         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 613         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 614                 p1 = 0;
 615         else
 616                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 617         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 618         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 619                 m1, m2, n, p1, p2);
 620         printk("        PLLA1: clock is %d\n", CALC_VCLOCK(m1, m2, n, p1, p2));
 621
 622 #if 0
 623         printk("        PALETTE_A:\n");
 624         for (i = 0; i < PALETTE_8_ENTRIES)
 625                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i];
 626         printk("        PALETTE_B:\n");
 627         for (i = 0; i < PALETTE_8_ENTRIES)
 628                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i];
 629 #endif
 630
 631         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 632         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 633         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 634         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 635         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 636         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 637         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 638         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 639         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 640         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 641         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 642         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 643         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 644         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 645         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 646         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 647
 648         printk("        ADPA:                   0x%08x\n", hw->adpa);
 649         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 650         printk("        DVOB:                   0x%08x\n", hw->dvob);
 651         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 652         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 653         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 654         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 655         printk("        LVDS:                   0x%08x\n", hw->lvds);
 656
 657         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 658         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 659         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 660
 661         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 662         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 663         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 664         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 665
 666         printk("        CURSOR_A_PALETTE:       ");
 667         for (i = 0; i < 4; i++) {
 668                 printk("0x%08x", hw->cursor_a_palette[i]);
 669                 if (i < 3)
 670                         printk(", ");
 671         }
 672         printk("\n");
 673         printk("        CURSOR_B_PALETTE:       ");
 674         for (i = 0; i < 4; i++) {
 675                 printk("0x%08x", hw->cursor_b_palette[i]);
 676                 if (i < 3)
 677                         printk(", ");
 678         }
 679         printk("\n");
 680
 681         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 682
 683         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 684         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 685         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 686         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 687         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 688         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 689
 690         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 691         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 692
 693         for (i = 0; i < 7; i++) {
 694                 printk("        SWF0%d                  0x%08x\n", i,
 695                         hw->swf0x[i]);
 696         }
 697         for (i = 0; i < 7; i++) {
 698                 printk("        SWF1%d                  0x%08x\n", i,
 699                         hw->swf1x[i]);
 700         }
 701         for (i = 0; i < 3; i++) {
 702                 printk("        SWF3%d                  0x%08x\n", i,
 703                         hw->swf3x[i]);
 704         }
 705         for (i = 0; i < 8; i++)
 706                 printk("        FENCE%d                 0x%08x\n", i,
 707                         hw->fence[i]);
 708
 709         printk("        INSTPM                  0x%08x\n", hw->instpm);
 710         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 711         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 712         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 713
 714         printk("hw state dump end\n");
 715 #endif
 716 }
 717
 718 /* Split the M parameter into M1 and M2. */
 719 static int
 720 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 721 {
 722         int m1, m2;
 723
 724         m1 = (m - 2 - (plls[index].min_m1 + plls[index].max_m2) / 2) / 5 - 2;
 725         if (m1 < plls[index].min_m1)
 726                 m1 = plls[index].min_m1;
 727         if (m1 > plls[index].max_m1)
 728                 m1 = plls[index].max_m1;
 729         m2 = m - 5 * (m1 + 2) - 2;
 730         if (m2 < plls[index].min_m2 || m2 > plls[index].max_m2 || m2 >= m1) {
 731                 return 1;
 732         } else {
 733                 *retm1 = (unsigned int)m1;
 734                 *retm2 = (unsigned int)m2;
 735                 return 0;
 736         }
 737 }
 738
 739 /* Split the P parameter into P1 and P2. */
 740 static int
 741 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 742 {
 743         int p1, p2;
 744
 745         if (index==PLLS_I8xx)
 746         {
 747                 if (p % 4 == 0)
 748                         p2 = 1;
 749                 else
 750                         p2 = 0;
 751                 p1 = (p / (1 << (p2 + 1))) - 2;
 752                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 753                         p2 = 0;
 754                         p1 = (p / (1 << (p2 + 1))) - 2;
 755                 }
 756                 if (p1  < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
 757                         return 1;
 758                 } else {
 759                         *retp1 = (unsigned int)p1;
 760                         *retp2 = (unsigned int)p2;
 761                         return 0;
 762                 }
 763         }
 764         return 1;
 765 }
 766
 767 static int
 768 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 769                 u32 *retp2, u32 *retclock)
 770 {
 771         u32 m1, m2, n, p1, p2, n1;
 772         u32 f_vco, p, p_best = 0, m, f_out;
 773         u32 err_max, err_target, err_best = 10000000;
 774         u32 n_best = 0, m_best = 0, f_best, f_err;
 775         u32 p_min, p_max, p_inc, div_min, div_max;
 776
 777         /* Accept 0.5% difference, but aim for 0.1% */
 778         err_max = 5 * clock / 1000;
 779         err_target = clock / 1000;
 780
 781         DBG_MSG("Clock is %d\n", clock);
 782
 783         div_max = plls[index].max_vco_freq / clock;
 784         div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 785
 786         if (clock <= plls[index].p_transition_clock)
 787                 p_inc = 4;
 788         else
 789                 p_inc = 2;
 790         p_min = ROUND_UP_TO(div_min, p_inc);
 791         p_max = ROUND_DOWN_TO(div_max, p_inc);
 792         if (p_min < plls[index].min_p)
 793                 p_min = 4;
 794         if (p_max > plls[index].max_p)
 795                 p_max = 128;
 796
 797         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 798
 799         p = p_min;
 800         do {
 801                 if (splitp(index, p, &p1, &p2)) {
 802                         WRN_MSG("cannot split p = %d\n", p);
 803                         p += p_inc;
 804                         continue;
 805                 }
 806                 n = plls[index].min_n;
 807                 f_vco = clock * p;
 808
 809                 do {
 810                         m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
 811                         if (m < plls[index].min_m)
 812                                 m = plls[index].min_m;
 813                         if (m > plls[index].max_m)
 814                                 m = plls[index].max_m;
 815                         f_out = CALC_VCLOCK3(m, n, p);
 816                         if (splitm(index, m, &m1, &m2)) {
 817                                 WRN_MSG("cannot split m = %d\n", m);
 818                                 n++;
 819                                 continue;
 820                         }
 821                         if (clock > f_out)
 822                                 f_err = clock - f_out;
 823                         else
 824                                 f_err = f_out - clock;
 825
 826                         if (f_err < err_best) {
 827                                 m_best = m;
 828                                 n_best = n;
 829                                 p_best = p;
 830                                 f_best = f_out;
 831                                 err_best = f_err;
 832                         }
 833                         n++;
 834                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 835                 p += p_inc;
 836         } while ((p <= p_max));
 837
 838         if (!m_best) {
 839                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 840                 return 1;
 841         }
 842         m = m_best;
 843         n = n_best;
 844         p = p_best;
 845         splitm(index, m, &m1, &m2);
 846         splitp(index, p, &p1, &p2);
 847         n1 = n - 2;
 848
 849         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 850                 "f: %d (%d), VCO: %d\n",
 851                 m, m1, m2, n, n1, p, p1, p2,
 852                 CALC_VCLOCK3(m, n, p), CALC_VCLOCK(m1, m2, n1, p1, p2),
 853                 CALC_VCLOCK3(m, n, p) * p);
 854         *retm1 = m1;
 855         *retm2 = m2;
 856         *retn = n1;
 857         *retp1 = p1;
 858         *retp2 = p2;
 859         *retclock = CALC_VCLOCK(m1, m2, n1, p1, p2);
 860
 861         return 0;
 862 }
 863
 864 static __inline__ int
 865 check_overflow(u32 value, u32 limit, const char *description)
 866 {
 867         if (value > limit) {
 868                 WRN_MSG("%s value %d exceeds limit %d\n",
 869                         description, value, limit);
 870                 return 1;
 871         }
 872         return 0;
 873 }
 874
 875 /* It is assumed that hw is filled in with the initial state information. */
 876 int
 877 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 878                      struct fb_var_screeninfo *var)
 879 {
 880         int pipe = PIPE_A;
 881         u32 *dpll, *fp0, *fp1;
 882         u32 m1, m2, n, p1, p2, clock_target, clock;
 883         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 884         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 885         u32 vsync_pol, hsync_pol;
 886         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 887
 888         DBG_MSG("intelfbhw_mode_to_hw\n");
 889
 890         /* Disable VGA */
 891         hw->vgacntrl |= VGA_DISABLE;
 892
 893         /* Check whether pipe A or pipe B is enabled. */
 894         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 895                 pipe = PIPE_A;
 896         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
 897                 pipe = PIPE_B;
 898
 899         /* Set which pipe's registers will be set. */
 900         if (pipe == PIPE_B) {
 901                 dpll = &hw->dpll_b;
 902                 fp0 = &hw->fpb0;
 903                 fp1 = &hw->fpb1;
 904                 hs = &hw->hsync_b;
 905                 hb = &hw->hblank_b;
 906                 ht = &hw->htotal_b;
 907                 vs = &hw->vsync_b;
 908                 vb = &hw->vblank_b;
 909                 vt = &hw->vtotal_b;
 910                 ss = &hw->src_size_b;
 911                 pipe_conf = &hw->pipe_b_conf;
 912         } else {
 913                 dpll = &hw->dpll_a;
 914                 fp0 = &hw->fpa0;
 915                 fp1 = &hw->fpa1;
 916                 hs = &hw->hsync_a;
 917                 hb = &hw->hblank_a;
 918                 ht = &hw->htotal_a;
 919                 vs = &hw->vsync_a;
 920                 vb = &hw->vblank_a;
 921                 vt = &hw->vtotal_a;
 922                 ss = &hw->src_size_a;
 923                 pipe_conf = &hw->pipe_a_conf;
 924         }
 925
 926         /* Use ADPA register for sync control. */
 927         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
 928
 929         /* sync polarity */
 930         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
 931                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
 932         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
 933                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
 934         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
 935                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
 936         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
 937                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
 938
 939         /* Connect correct pipe to the analog port DAC */
 940         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
 941         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
 942
 943         /* Set DPMS state to D0 (on) */
 944         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
 945         hw->adpa |= ADPA_DPMS_D0;
 946
 947         hw->adpa |= ADPA_DAC_ENABLE;
 948
 949         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
 950         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
 951         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
 952
 953         /* Desired clock in kHz */
 954         clock_target = 1000000000 / var->pixclock;
 955
 956         if (calc_pll_params(PLLS_I8xx, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
 957                 WRN_MSG("calc_pll_params failed\n");
 958                 return 1;
 959         }
 960
 961         /* Check for overflow. */
 962         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
 963                 return 1;
 964         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
 965                 return 1;
 966         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
 967                 return 1;
 968         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
 969                 return 1;
 970         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
 971                 return 1;
 972
 973         *dpll &= ~DPLL_P1_FORCE_DIV2;
 974         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
 975                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
 976         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
 977         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
 978                (m1 << FP_M1_DIVISOR_SHIFT) |
 979                (m2 << FP_M2_DIVISOR_SHIFT);
 980         *fp1 = *fp0;
 981
 982         hw->dvob &= ~PORT_ENABLE;
 983         hw->dvoc &= ~PORT_ENABLE;
 984
 985         /* Use display plane A. */
 986         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
 987         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
 988         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
 989         switch (intelfb_var_to_depth(var)) {
 990         case 8:
 991                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
 992                 break;
 993         case 15:
 994                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
 995                 break;
 996         case 16:
 997                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
 998                 break;
 999         case 24:
1000                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1001                 break;
1002         }
1003         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1004         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1005
1006         /* Set CRTC registers. */
1007         hactive = var->xres;
1008         hsync_start = hactive + var->right_margin;
1009         hsync_end = hsync_start + var->hsync_len;
1010         htotal = hsync_end + var->left_margin;
1011         hblank_start = hactive;
1012         hblank_end = htotal;
1013
1014         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1015                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1016                 hblank_end);
1017
1018         vactive = var->yres;
1019         vsync_start = vactive + var->lower_margin;
1020         vsync_end = vsync_start + var->vsync_len;
1021         vtotal = vsync_end + var->upper_margin;
1022         vblank_start = vactive;
1023         vblank_end = vtotal;
1024         vblank_end = vsync_end + 1;
1025
1026         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1027                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1028                 vblank_end);
1029
1030         /* Adjust for register values, and check for overflow. */
1031         hactive--;
1032         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1033                 return 1;
1034         hsync_start--;
1035         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1036                 return 1;
1037         hsync_end--;
1038         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1039                 return 1;
1040         htotal--;
1041         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1042                 return 1;
1043         hblank_start--;
1044         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1045                 return 1;
1046         hblank_end--;
1047         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1048                 return 1;
1049
1050         vactive--;
1051         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1052                 return 1;
1053         vsync_start--;
1054         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1055                 return 1;
1056         vsync_end--;
1057         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1058                 return 1;
1059         vtotal--;
1060         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1061                 return 1;
1062         vblank_start--;
1063         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1064                 return 1;
1065         vblank_end--;
1066         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1067                 return 1;
1068
1069         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1070         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1071               (hblank_end << HSYNCEND_SHIFT);
1072         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1073
1074         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1075         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1076               (vblank_end << VSYNCEND_SHIFT);
1077         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1078         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1079               (vactive << SRC_SIZE_VERT_SHIFT);
1080
1081         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1082         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1083
1084         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1085                           var->xoffset * var->bits_per_pixel / 8;
1086
1087         hw->disp_a_base += dinfo->fb.offset << 12;
1088
1089         /* Check stride alignment. */
1090         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1091                 WRN_MSG("display stride %d has bad alignment %d\n",
1092                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1093                 return 1;
1094         }
1095
1096         /* Set the palette to 8-bit mode. */
1097         *pipe_conf &= ~PIPECONF_GAMMA;
1098         return 0;
1099 }
1100
1101 /* Program a (non-VGA) video mode. */
1102 int
1103 intelfbhw_program_mode(struct intelfb_info *dinfo,
1104                      const struct intelfb_hwstate *hw, int blank)
1105 {
1106         int pipe = PIPE_A;
1107         u32 tmp;
1108         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1109         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1110         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1111         u32 hsync_reg, htotal_reg, hblank_reg;
1112         u32 vsync_reg, vtotal_reg, vblank_reg;
1113         u32 src_size_reg;
1114
1115         /* Assume single pipe, display plane A, analog CRT. */
1116
1117 #if VERBOSE > 0
1118         DBG_MSG("intelfbhw_program_mode\n");
1119 #endif
1120
1121         /* Disable VGA */
1122         tmp = INREG(VGACNTRL);
1123         tmp |= VGA_DISABLE;
1124         OUTREG(VGACNTRL, tmp);
1125
1126         /* Check whether pipe A or pipe B is enabled. */
1127         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1128                 pipe = PIPE_A;
1129         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1130                 pipe = PIPE_B;
1131
1132         dinfo->pipe = pipe;
1133
1134         if (pipe == PIPE_B) {
1135                 dpll = &hw->dpll_b;
1136                 fp0 = &hw->fpb0;
1137                 fp1 = &hw->fpb1;
1138                 pipe_conf = &hw->pipe_b_conf;
1139                 hs = &hw->hsync_b;
1140                 hb = &hw->hblank_b;
1141                 ht = &hw->htotal_b;
1142                 vs = &hw->vsync_b;
1143                 vb = &hw->vblank_b;
1144                 vt = &hw->vtotal_b;
1145                 ss = &hw->src_size_b;
1146                 dpll_reg = DPLL_B;
1147                 fp0_reg = FPB0;
1148                 fp1_reg = FPB1;
1149                 pipe_conf_reg = PIPEBCONF;
1150                 hsync_reg = HSYNC_B;
1151                 htotal_reg = HTOTAL_B;
1152                 hblank_reg = HBLANK_B;
1153                 vsync_reg = VSYNC_B;
1154                 vtotal_reg = VTOTAL_B;
1155                 vblank_reg = VBLANK_B;
1156                 src_size_reg = SRC_SIZE_B;
1157         } else {
1158                 dpll = &hw->dpll_a;
1159                 fp0 = &hw->fpa0;
1160                 fp1 = &hw->fpa1;
1161                 pipe_conf = &hw->pipe_a_conf;
1162                 hs = &hw->hsync_a;
1163                 hb = &hw->hblank_a;
1164                 ht = &hw->htotal_a;
1165                 vs = &hw->vsync_a;
1166                 vb = &hw->vblank_a;
1167                 vt = &hw->vtotal_a;
1168                 ss = &hw->src_size_a;
1169                 dpll_reg = DPLL_A;
1170                 fp0_reg = FPA0;
1171                 fp1_reg = FPA1;
1172                 pipe_conf_reg = PIPEACONF;
1173                 hsync_reg = HSYNC_A;
1174                 htotal_reg = HTOTAL_A;
1175                 hblank_reg = HBLANK_A;
1176                 vsync_reg = VSYNC_A;
1177                 vtotal_reg = VTOTAL_A;
1178                 vblank_reg = VBLANK_A;
1179                 src_size_reg = SRC_SIZE_A;
1180         }
1181
1182         /* Disable planes A and B. */
1183         tmp = INREG(DSPACNTR);
1184         tmp &= ~DISPPLANE_PLANE_ENABLE;
1185         OUTREG(DSPACNTR, tmp);
1186         tmp = INREG(DSPBCNTR);
1187         tmp &= ~DISPPLANE_PLANE_ENABLE;
1188         OUTREG(DSPBCNTR, tmp);
1189
1190         /* Wait for vblank.  For now, just wait for a 50Hz cycle (20ms)) */
1191         mdelay(20);
1192
1193         /* Disable Sync */
1194         tmp = INREG(ADPA);
1195         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1196         tmp |= ADPA_DPMS_D3;
1197         OUTREG(ADPA, tmp);
1198
1199         /* turn off pipe */
1200         tmp = INREG(pipe_conf_reg);
1201         tmp &= ~PIPECONF_ENABLE;
1202         OUTREG(pipe_conf_reg, tmp);
1203
1204         /* turn off PLL */
1205         tmp = INREG(dpll_reg);
1206         dpll_reg &= ~DPLL_VCO_ENABLE;
1207         OUTREG(dpll_reg, tmp);
1208
1209         /* Set PLL parameters */
1210         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1211         OUTREG(fp0_reg, *fp0);
1212         OUTREG(fp1_reg, *fp1);
1213
1214         /* Set pipe parameters */
1215         OUTREG(hsync_reg, *hs);
1216         OUTREG(hblank_reg, *hb);
1217         OUTREG(htotal_reg, *ht);
1218         OUTREG(vsync_reg, *vs);
1219         OUTREG(vblank_reg, *vb);
1220         OUTREG(vtotal_reg, *vt);
1221         OUTREG(src_size_reg, *ss);
1222
1223         /* Set DVOs B/C */
1224         OUTREG(DVOB, hw->dvob);
1225         OUTREG(DVOC, hw->dvoc);
1226
1227         /* Set ADPA */
1228         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1229
1230         /* Enable PLL */
1231         tmp = INREG(dpll_reg);
1232         tmp |= DPLL_VCO_ENABLE;
1233         OUTREG(dpll_reg, tmp);
1234
1235         /* Enable pipe */
1236         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1237
1238         /* Enable sync */
1239         tmp = INREG(ADPA);
1240         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1241         tmp |= ADPA_DPMS_D0;
1242         OUTREG(ADPA, tmp);
1243
1244         /* setup display plane */
1245         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1246                 /*
1247                  *      i830M errata: the display plane must be enabled
1248                  *      to allow writes to the other bits in the plane
1249                  *      control register.
1250                  */
1251                 tmp = INREG(DSPACNTR);
1252                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1253                         tmp |= DISPPLANE_PLANE_ENABLE;
1254                         OUTREG(DSPACNTR, tmp);
1255                         OUTREG(DSPACNTR,
1256                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1257                         mdelay(1);
1258               }
1259         }
1260
1261         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1262         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1263         OUTREG(DSPABASE, hw->disp_a_base);
1264
1265         /* Enable plane */
1266         if (!blank) {
1267                 tmp = INREG(DSPACNTR);
1268                 tmp |= DISPPLANE_PLANE_ENABLE;
1269                 OUTREG(DSPACNTR, tmp);
1270                 OUTREG(DSPABASE, hw->disp_a_base);
1271         }
1272
1273         return 0;
1274 }
1275
1276 /* forward declarations */
1277 static void refresh_ring(struct intelfb_info *dinfo);
1278 static void reset_state(struct intelfb_info *dinfo);
1279 static void do_flush(struct intelfb_info *dinfo);
1280
1281 static int
1282 wait_ring(struct intelfb_info *dinfo, int n)
1283 {
1284         int i = 0;
1285         unsigned long end;
1286         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1287
1288 #if VERBOSE > 0
1289         DBG_MSG("wait_ring: %d\n", n);
1290 #endif
1291
1292         end = jiffies + (HZ * 3);
1293         while (dinfo->ring_space < n) {
1294                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1295                                                    RING_HEAD_MASK);
1296                 if (dinfo->ring_tail + RING_MIN_FREE <
1297                     (u32 __iomem) dinfo->ring_head)
1298                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1299                                 - (dinfo->ring_tail + RING_MIN_FREE);
1300                 else
1301                         dinfo->ring_space = (dinfo->ring.size +
1302                                              (u32 __iomem) dinfo->ring_head)
1303                                 - (dinfo->ring_tail + RING_MIN_FREE);
1304                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1305                         end = jiffies + (HZ * 3);
1306                         last_head = (u32 __iomem) dinfo->ring_head;
1307                 }
1308                 i++;
1309                 if (time_before(end, jiffies)) {
1310                         if (!i) {
1311                                 /* Try again */
1312                                 reset_state(dinfo);
1313                                 refresh_ring(dinfo);
1314                                 do_flush(dinfo);
1315                                 end = jiffies + (HZ * 3);
1316                                 i = 1;
1317                         } else {
1318                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1319                                         dinfo->ring_space, n);
1320                                 WRN_MSG("lockup - turning off hardware "
1321                                         "acceleration\n");
1322                                 dinfo->ring_lockup = 1;
1323                                 break;
1324                         }
1325                 }
1326                 udelay(1);
1327         }
1328         return i;
1329 }
1330
1331 static void
1332 do_flush(struct intelfb_info *dinfo) {
1333         START_RING(2);
1334         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1335         OUT_RING(MI_NOOP);
1336         ADVANCE_RING();
1337 }
1338
1339 void
1340 intelfbhw_do_sync(struct intelfb_info *dinfo)
1341 {
1342 #if VERBOSE > 0
1343         DBG_MSG("intelfbhw_do_sync\n");
1344 #endif
1345
1346         if (!dinfo->accel)
1347                 return;
1348
1349         /*
1350          * Send a flush, then wait until the ring is empty.  This is what
1351          * the XFree86 driver does, and actually it doesn't seem a lot worse
1352          * than the recommended method (both have problems).
1353          */
1354         do_flush(dinfo);
1355         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1356         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1357 }
1358
1359 static void
1360 refresh_ring(struct intelfb_info *dinfo)
1361 {
1362 #if VERBOSE > 0
1363         DBG_MSG("refresh_ring\n");
1364 #endif
1365
1366         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1367                                            RING_HEAD_MASK);
1368         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1369         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1370                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1371                         - (dinfo->ring_tail + RING_MIN_FREE);
1372         else
1373                 dinfo->ring_space = (dinfo->ring.size +
1374                                      (u32 __iomem) dinfo->ring_head)
1375                         - (dinfo->ring_tail + RING_MIN_FREE);
1376 }
1377
1378 static void
1379 reset_state(struct intelfb_info *dinfo)
1380 {
1381         int i;
1382         u32 tmp;
1383
1384 #if VERBOSE > 0
1385         DBG_MSG("reset_state\n");
1386 #endif
1387
1388         for (i = 0; i < FENCE_NUM; i++)
1389                 OUTREG(FENCE + (i << 2), 0);
1390
1391         /* Flush the ring buffer if it's enabled. */
1392         tmp = INREG(PRI_RING_LENGTH);
1393         if (tmp & RING_ENABLE) {
1394 #if VERBOSE > 0
1395                 DBG_MSG("reset_state: ring was enabled\n");
1396 #endif
1397                 refresh_ring(dinfo);
1398                 intelfbhw_do_sync(dinfo);
1399                 DO_RING_IDLE();
1400         }
1401
1402         OUTREG(PRI_RING_LENGTH, 0);
1403         OUTREG(PRI_RING_HEAD, 0);
1404         OUTREG(PRI_RING_TAIL, 0);
1405         OUTREG(PRI_RING_START, 0);
1406 }
1407
1408 /* Stop the 2D engine, and turn off the ring buffer. */
1409 void
1410 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1411 {
1412 #if VERBOSE > 0
1413         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1414                 dinfo->ring_active);
1415 #endif
1416
1417         if (!dinfo->accel)
1418                 return;
1419
1420         dinfo->ring_active = 0;
1421         reset_state(dinfo);
1422 }
1423
1424 /*
1425  * Enable the ring buffer, and initialise the 2D engine.
1426  * It is assumed that the graphics engine has been stopped by previously
1427  * calling intelfb_2d_stop().
1428  */
1429 void
1430 intelfbhw_2d_start(struct intelfb_info *dinfo)
1431 {
1432 #if VERBOSE > 0
1433         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1434                 dinfo->accel, dinfo->ring_active);
1435 #endif
1436
1437         if (!dinfo->accel)
1438                 return;
1439
1440         /* Initialise the primary ring buffer. */
1441         OUTREG(PRI_RING_LENGTH, 0);
1442         OUTREG(PRI_RING_TAIL, 0);
1443         OUTREG(PRI_RING_HEAD, 0);
1444
1445         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1446         OUTREG(PRI_RING_LENGTH,
1447                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1448                 RING_NO_REPORT | RING_ENABLE);
1449         refresh_ring(dinfo);
1450         dinfo->ring_active = 1;
1451 }
1452
1453 /* 2D fillrect (solid fill or invert) */
1454 void
1455 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1456                       u32 color, u32 pitch, u32 bpp, u32 rop)
1457 {
1458         u32 br00, br09, br13, br14, br16;
1459
1460 #if VERBOSE > 0
1461         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1462                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1463 #endif
1464
1465         br00 = COLOR_BLT_CMD;
1466         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1467         br13 = (rop << ROP_SHIFT) | pitch;
1468         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1469         br16 = color;
1470
1471         switch (bpp) {
1472         case 8:
1473                 br13 |= COLOR_DEPTH_8;
1474                 break;
1475         case 16:
1476                 br13 |= COLOR_DEPTH_16;
1477                 break;
1478         case 32:
1479                 br13 |= COLOR_DEPTH_32;
1480                 br00 |= WRITE_ALPHA | WRITE_RGB;
1481                 break;
1482         }
1483
1484         START_RING(6);
1485         OUT_RING(br00);
1486         OUT_RING(br13);
1487         OUT_RING(br14);
1488         OUT_RING(br09);
1489         OUT_RING(br16);
1490         OUT_RING(MI_NOOP);
1491         ADVANCE_RING();
1492
1493 #if VERBOSE > 0
1494         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1495                 dinfo->ring_tail, dinfo->ring_space);
1496 #endif
1497 }
1498
1499 void
1500 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1501                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1502 {
1503         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1504
1505 #if VERBOSE > 0
1506         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1507                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1508 #endif
1509
1510         br00 = XY_SRC_COPY_BLT_CMD;
1511         br09 = dinfo->fb_start;
1512         br11 = (pitch << PITCH_SHIFT);
1513         br12 = dinfo->fb_start;
1514         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1515         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1516         br23 = ((dstx + w) << WIDTH_SHIFT) |
1517                ((dsty + h) << HEIGHT_SHIFT);
1518         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1519
1520         switch (bpp) {
1521         case 8:
1522                 br13 |= COLOR_DEPTH_8;
1523                 break;
1524         case 16:
1525                 br13 |= COLOR_DEPTH_16;
1526                 break;
1527         case 32:
1528                 br13 |= COLOR_DEPTH_32;
1529                 br00 |= WRITE_ALPHA | WRITE_RGB;
1530                 break;
1531         }
1532
1533         START_RING(8);
1534         OUT_RING(br00);
1535         OUT_RING(br13);
1536         OUT_RING(br22);
1537         OUT_RING(br23);
1538         OUT_RING(br09);
1539         OUT_RING(br26);
1540         OUT_RING(br11);
1541         OUT_RING(br12);
1542         ADVANCE_RING();
1543 }
1544
1545 int
1546 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1547                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1548 {
1549         int nbytes, ndwords, pad, tmp;
1550         u32 br00, br09, br13, br18, br19, br22, br23;
1551         int dat, ix, iy, iw;
1552         int i, j;
1553
1554 #if VERBOSE > 0
1555         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1556 #endif
1557
1558         /* size in bytes of a padded scanline */
1559         nbytes = ROUND_UP_TO(w, 16) / 8;
1560
1561         /* Total bytes of padded scanline data to write out. */
1562         nbytes = nbytes * h;
1563
1564         /*
1565          * Check if the glyph data exceeds the immediate mode limit.
1566          * It would take a large font (1K pixels) to hit this limit.
1567          */
1568         if (nbytes > MAX_MONO_IMM_SIZE)
1569                 return 0;
1570
1571         /* Src data is packaged a dword (32-bit) at a time. */
1572         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1573
1574         /*
1575          * Ring has to be padded to a quad word. But because the command starts
1576            with 7 bytes, pad only if there is an even number of ndwords
1577          */
1578         pad = !(ndwords % 2);
1579
1580         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1581         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1582         br09 = dinfo->fb_start;
1583         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1584         br18 = bg;
1585         br19 = fg;
1586         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1587         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1588
1589         switch (bpp) {
1590         case 8:
1591                 br13 |= COLOR_DEPTH_8;
1592                 break;
1593         case 16:
1594                 br13 |= COLOR_DEPTH_16;
1595                 break;
1596         case 32:
1597                 br13 |= COLOR_DEPTH_32;
1598                 br00 |= WRITE_ALPHA | WRITE_RGB;
1599                 break;
1600         }
1601
1602         START_RING(8 + ndwords);
1603         OUT_RING(br00);
1604         OUT_RING(br13);
1605         OUT_RING(br22);
1606         OUT_RING(br23);
1607         OUT_RING(br09);
1608         OUT_RING(br18);
1609         OUT_RING(br19);
1610         ix = iy = 0;
1611         iw = ROUND_UP_TO(w, 8) / 8;
1612         while (ndwords--) {
1613                 dat = 0;
1614                 for (j = 0; j < 2; ++j) {
1615                         for (i = 0; i < 2; ++i) {
1616                                 if (ix != iw || i == 0)
1617                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1618                         }
1619                         if (ix == iw && iy != (h-1)) {
1620                                 ix = 0;
1621                                 ++iy;
1622                         }
1623                 }
1624                 OUT_RING(dat);
1625         }
1626         if (pad)
1627                 OUT_RING(MI_NOOP);
1628         ADVANCE_RING();
1629
1630         return 1;
1631 }
1632
1633 /* HW cursor functions. */
1634 void
1635 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1636 {
1637         u32 tmp;
1638
1639 #if VERBOSE > 0
1640         DBG_MSG("intelfbhw_cursor_init\n");
1641 #endif
1642
1643         if (dinfo->mobile) {
1644                 if (!dinfo->cursor.physical)
1645                         return;
1646                 tmp = INREG(CURSOR_A_CONTROL);
1647                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1648                          CURSOR_MEM_TYPE_LOCAL |
1649                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1650                 tmp |= CURSOR_MODE_DISABLE;
1651                 OUTREG(CURSOR_A_CONTROL, tmp);
1652                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1653         } else {
1654                 tmp = INREG(CURSOR_CONTROL);
1655                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1656                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1657                 tmp = CURSOR_FORMAT_3C;
1658                 OUTREG(CURSOR_CONTROL, tmp);
1659                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1660                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1661                       (64 << CURSOR_SIZE_V_SHIFT);
1662                 OUTREG(CURSOR_SIZE, tmp);
1663         }
1664 }
1665
1666 void
1667 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1668 {
1669         u32 tmp;
1670
1671 #if VERBOSE > 0
1672         DBG_MSG("intelfbhw_cursor_hide\n");
1673 #endif
1674
1675         dinfo->cursor_on = 0;
1676         if (dinfo->mobile) {
1677                 if (!dinfo->cursor.physical)
1678                         return;
1679                 tmp = INREG(CURSOR_A_CONTROL);
1680                 tmp &= ~CURSOR_MODE_MASK;
1681                 tmp |= CURSOR_MODE_DISABLE;
1682                 OUTREG(CURSOR_A_CONTROL, tmp);
1683                 /* Flush changes */
1684                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1685         } else {
1686                 tmp = INREG(CURSOR_CONTROL);
1687                 tmp &= ~CURSOR_ENABLE;
1688                 OUTREG(CURSOR_CONTROL, tmp);
1689         }
1690 }
1691
1692 void
1693 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1694 {
1695         u32 tmp;
1696
1697 #if VERBOSE > 0
1698         DBG_MSG("intelfbhw_cursor_show\n");
1699 #endif
1700
1701         dinfo->cursor_on = 1;
1702
1703         if (dinfo->cursor_blanked)
1704                 return;
1705
1706         if (dinfo->mobile) {
1707                 if (!dinfo->cursor.physical)
1708                         return;
1709                 tmp = INREG(CURSOR_A_CONTROL);
1710                 tmp &= ~CURSOR_MODE_MASK;
1711                 tmp |= CURSOR_MODE_64_4C_AX;
1712                 OUTREG(CURSOR_A_CONTROL, tmp);
1713                 /* Flush changes */
1714                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1715         } else {
1716                 tmp = INREG(CURSOR_CONTROL);
1717                 tmp |= CURSOR_ENABLE;
1718                 OUTREG(CURSOR_CONTROL, tmp);
1719         }
1720 }
1721
1722 void
1723 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1724 {
1725         u32 tmp;
1726
1727 #if VERBOSE > 0
1728         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1729 #endif
1730
1731         /*
1732          * Sets the position.  The coordinates are assumed to already
1733          * have any offset adjusted.  Assume that the cursor is never
1734          * completely off-screen, and that x, y are always >= 0.
1735          */
1736
1737         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1738               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1739         OUTREG(CURSOR_A_POSITION, tmp);
1740 }
1741
1742 void
1743 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1744 {
1745 #if VERBOSE > 0
1746         DBG_MSG("intelfbhw_cursor_setcolor\n");
1747 #endif
1748
1749         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1750         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1751         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1752         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1753 }
1754
1755 void
1756 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1757                       u8 *data)
1758 {
1759         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1760         int i, j, w = width / 8;
1761         int mod = width % 8, t_mask, d_mask;
1762
1763 #if VERBOSE > 0
1764         DBG_MSG("intelfbhw_cursor_load\n");
1765 #endif
1766
1767         if (!dinfo->cursor.virtual)
1768                 return;
1769
1770         t_mask = 0xff >> mod;
1771         d_mask = ~(0xff >> mod);
1772         for (i = height; i--; ) {
1773                 for (j = 0; j < w; j++) {
1774                         writeb(0x00, addr + j);
1775                         writeb(*(data++), addr + j+8);
1776                 }
1777                 if (mod) {
1778                         writeb(t_mask, addr + j);
1779                         writeb(*(data++) & d_mask, addr + j+8);
1780                 }
1781                 addr += 16;
1782         }
1783 }
1784
1785 void
1786 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1787         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1788         int i, j;
1789
1790 #if VERBOSE > 0
1791         DBG_MSG("intelfbhw_cursor_reset\n");
1792 #endif
1793
1794         if (!dinfo->cursor.virtual)
1795                 return;
1796
1797         for (i = 64; i--; ) {
1798                 for (j = 0; j < 8; j++) {
1799                         writeb(0xff, addr + j+0);
1800                         writeb(0x00, addr + j+8);
1801                 }
1802                 addr += 16;
1803         }
1804 }