4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
41 #include "intelfbhw.h"
50 int min_vco_freq, max_vco_freq;
51 int p_transition_clock;
52 int p_inc_lo, p_inc_hi;
59 struct pll_min_max plls[PLLS_MAX] = {
60 { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
61 { 75, 120, 10, 20, 5, 9, 4, 7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 } //I9xx
65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
71 switch (pdev->device) {
72 case PCI_DEVICE_ID_INTEL_830M:
73 dinfo->name = "Intel(R) 830M";
74 dinfo->chipset = INTEL_830M;
76 dinfo->pll_index = PLLS_I8xx;
78 case PCI_DEVICE_ID_INTEL_845G:
79 dinfo->name = "Intel(R) 845G";
80 dinfo->chipset = INTEL_845G;
82 dinfo->pll_index = PLLS_I8xx;
84 case PCI_DEVICE_ID_INTEL_85XGM:
87 dinfo->pll_index = PLLS_I8xx;
88 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
89 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
90 INTEL_85X_VARIANT_MASK) {
91 case INTEL_VAR_855GME:
92 dinfo->name = "Intel(R) 855GME";
93 dinfo->chipset = INTEL_855GME;
96 dinfo->name = "Intel(R) 855GM";
97 dinfo->chipset = INTEL_855GM;
99 case INTEL_VAR_852GME:
100 dinfo->name = "Intel(R) 852GME";
101 dinfo->chipset = INTEL_852GME;
103 case INTEL_VAR_852GM:
104 dinfo->name = "Intel(R) 852GM";
105 dinfo->chipset = INTEL_852GM;
108 dinfo->name = "Intel(R) 852GM/855GM";
109 dinfo->chipset = INTEL_85XGM;
113 case PCI_DEVICE_ID_INTEL_865G:
114 dinfo->name = "Intel(R) 865G";
115 dinfo->chipset = INTEL_865G;
117 dinfo->pll_index = PLLS_I8xx;
119 case PCI_DEVICE_ID_INTEL_915G:
120 dinfo->name = "Intel(R) 915G";
121 dinfo->chipset = INTEL_915G;
123 dinfo->pll_index = PLLS_I9xx;
125 case PCI_DEVICE_ID_INTEL_915GM:
126 dinfo->name = "Intel(R) 915GM";
127 dinfo->chipset = INTEL_915GM;
129 dinfo->pll_index = PLLS_I9xx;
137 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
140 struct pci_dev *bridge_dev;
143 if (!pdev || !aperture_size || !stolen_size)
146 /* Find the bridge device. It is always 0:0.0 */
147 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
148 ERR_MSG("cannot find bridge device\n");
152 /* Get the fb aperture size and "stolen" memory amount. */
154 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
155 switch (pdev->device) {
156 case PCI_DEVICE_ID_INTEL_830M:
157 case PCI_DEVICE_ID_INTEL_845G:
158 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
159 *aperture_size = MB(64);
161 *aperture_size = MB(128);
162 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
163 case INTEL_830_GMCH_GMS_STOLEN_512:
164 *stolen_size = KB(512) - KB(132);
166 case INTEL_830_GMCH_GMS_STOLEN_1024:
167 *stolen_size = MB(1) - KB(132);
169 case INTEL_830_GMCH_GMS_STOLEN_8192:
170 *stolen_size = MB(8) - KB(132);
172 case INTEL_830_GMCH_GMS_LOCAL:
173 ERR_MSG("only local memory found\n");
175 case INTEL_830_GMCH_GMS_DISABLED:
176 ERR_MSG("video memory is disabled\n");
179 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
180 tmp & INTEL_830_GMCH_GMS_MASK);
185 *aperture_size = MB(128);
186 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
187 case INTEL_855_GMCH_GMS_STOLEN_1M:
188 *stolen_size = MB(1) - KB(132);
190 case INTEL_855_GMCH_GMS_STOLEN_4M:
191 *stolen_size = MB(4) - KB(132);
193 case INTEL_855_GMCH_GMS_STOLEN_8M:
194 *stolen_size = MB(8) - KB(132);
196 case INTEL_855_GMCH_GMS_STOLEN_16M:
197 *stolen_size = MB(16) - KB(132);
199 case INTEL_855_GMCH_GMS_STOLEN_32M:
200 *stolen_size = MB(32) - KB(132);
202 case INTEL_915G_GMCH_GMS_STOLEN_48M:
203 *stolen_size = MB(48) - KB(132);
205 case INTEL_915G_GMCH_GMS_STOLEN_64M:
206 *stolen_size = MB(64) - KB(132);
208 case INTEL_855_GMCH_GMS_DISABLED:
209 ERR_MSG("video memory is disabled\n");
212 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
213 tmp & INTEL_855_GMCH_GMS_MASK);
220 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
224 if (INREG(LVDS) & PORT_ENABLE)
226 if (INREG(DVOA) & PORT_ENABLE)
228 if (INREG(DVOB) & PORT_ENABLE)
230 if (INREG(DVOC) & PORT_ENABLE)
237 intelfbhw_dvo_to_string(int dvo)
241 else if (dvo & DVOB_PORT)
243 else if (dvo & DVOC_PORT)
245 else if (dvo & LVDS_PORT)
253 intelfbhw_validate_mode(struct intelfb_info *dinfo,
254 struct fb_var_screeninfo *var)
260 DBG_MSG("intelfbhw_validate_mode\n");
263 bytes_per_pixel = var->bits_per_pixel / 8;
264 if (bytes_per_pixel == 3)
267 /* Check if enough video memory. */
268 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
269 if (tmp > dinfo->fb.size) {
270 WRN_MSG("Not enough video ram for mode "
271 "(%d KByte vs %d KByte).\n",
272 BtoKB(tmp), BtoKB(dinfo->fb.size));
276 /* Check if x/y limits are OK. */
277 if (var->xres - 1 > HACTIVE_MASK) {
278 WRN_MSG("X resolution too large (%d vs %d).\n",
279 var->xres, HACTIVE_MASK + 1);
282 if (var->yres - 1 > VACTIVE_MASK) {
283 WRN_MSG("Y resolution too large (%d vs %d).\n",
284 var->yres, VACTIVE_MASK + 1);
288 /* Check for interlaced/doublescan modes. */
289 if (var->vmode & FB_VMODE_INTERLACED) {
290 WRN_MSG("Mode is interlaced.\n");
293 if (var->vmode & FB_VMODE_DOUBLE) {
294 WRN_MSG("Mode is double-scan.\n");
298 /* Check if clock is OK. */
299 tmp = 1000000000 / var->pixclock;
300 if (tmp < MIN_CLOCK) {
301 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
302 (tmp + 500) / 1000, MIN_CLOCK / 1000);
305 if (tmp > MAX_CLOCK) {
306 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
307 (tmp + 500) / 1000, MAX_CLOCK / 1000);
315 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
317 struct intelfb_info *dinfo = GET_DINFO(info);
318 u32 offset, xoffset, yoffset;
321 DBG_MSG("intelfbhw_pan_display\n");
324 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
325 yoffset = var->yoffset;
327 if ((xoffset + var->xres > var->xres_virtual) ||
328 (yoffset + var->yres > var->yres_virtual))
331 offset = (yoffset * dinfo->pitch) +
332 (xoffset * var->bits_per_pixel) / 8;
334 offset += dinfo->fb.offset << 12;
336 OUTREG(DSPABASE, offset);
341 /* Blank the screen. */
343 intelfbhw_do_blank(int blank, struct fb_info *info)
345 struct intelfb_info *dinfo = GET_DINFO(info);
349 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
352 /* Turn plane A on or off */
353 tmp = INREG(DSPACNTR);
355 tmp &= ~DISPPLANE_PLANE_ENABLE;
357 tmp |= DISPPLANE_PLANE_ENABLE;
358 OUTREG(DSPACNTR, tmp);
360 tmp = INREG(DSPABASE);
361 OUTREG(DSPABASE, tmp);
363 /* Turn off/on the HW cursor */
365 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
367 if (dinfo->cursor_on) {
369 intelfbhw_cursor_hide(dinfo);
371 intelfbhw_cursor_show(dinfo);
373 dinfo->cursor_on = 1;
375 dinfo->cursor_blanked = blank;
378 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
380 case FB_BLANK_UNBLANK:
381 case FB_BLANK_NORMAL:
384 case FB_BLANK_VSYNC_SUSPEND:
387 case FB_BLANK_HSYNC_SUSPEND:
390 case FB_BLANK_POWERDOWN:
401 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
402 unsigned red, unsigned green, unsigned blue,
406 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
407 regno, red, green, blue);
410 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
411 PALETTE_A : PALETTE_B;
413 OUTREG(palette_reg + (regno << 2),
414 (red << PALETTE_8_RED_SHIFT) |
415 (green << PALETTE_8_GREEN_SHIFT) |
416 (blue << PALETTE_8_BLUE_SHIFT));
421 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
427 DBG_MSG("intelfbhw_read_hw_state\n");
433 /* Read in as much of the HW state as possible. */
434 hw->vga0_divisor = INREG(VGA0_DIVISOR);
435 hw->vga1_divisor = INREG(VGA1_DIVISOR);
436 hw->vga_pd = INREG(VGAPD);
437 hw->dpll_a = INREG(DPLL_A);
438 hw->dpll_b = INREG(DPLL_B);
439 hw->fpa0 = INREG(FPA0);
440 hw->fpa1 = INREG(FPA1);
441 hw->fpb0 = INREG(FPB0);
442 hw->fpb1 = INREG(FPB1);
448 /* This seems to be a problem with the 852GM/855GM */
449 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
450 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
451 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
458 hw->htotal_a = INREG(HTOTAL_A);
459 hw->hblank_a = INREG(HBLANK_A);
460 hw->hsync_a = INREG(HSYNC_A);
461 hw->vtotal_a = INREG(VTOTAL_A);
462 hw->vblank_a = INREG(VBLANK_A);
463 hw->vsync_a = INREG(VSYNC_A);
464 hw->src_size_a = INREG(SRC_SIZE_A);
465 hw->bclrpat_a = INREG(BCLRPAT_A);
466 hw->htotal_b = INREG(HTOTAL_B);
467 hw->hblank_b = INREG(HBLANK_B);
468 hw->hsync_b = INREG(HSYNC_B);
469 hw->vtotal_b = INREG(VTOTAL_B);
470 hw->vblank_b = INREG(VBLANK_B);
471 hw->vsync_b = INREG(VSYNC_B);
472 hw->src_size_b = INREG(SRC_SIZE_B);
473 hw->bclrpat_b = INREG(BCLRPAT_B);
478 hw->adpa = INREG(ADPA);
479 hw->dvoa = INREG(DVOA);
480 hw->dvob = INREG(DVOB);
481 hw->dvoc = INREG(DVOC);
482 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
483 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
484 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
485 hw->lvds = INREG(LVDS);
490 hw->pipe_a_conf = INREG(PIPEACONF);
491 hw->pipe_b_conf = INREG(PIPEBCONF);
492 hw->disp_arb = INREG(DISPARB);
497 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
498 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
499 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
500 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
505 for (i = 0; i < 4; i++) {
506 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
507 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
513 hw->cursor_size = INREG(CURSOR_SIZE);
518 hw->disp_a_ctrl = INREG(DSPACNTR);
519 hw->disp_b_ctrl = INREG(DSPBCNTR);
520 hw->disp_a_base = INREG(DSPABASE);
521 hw->disp_b_base = INREG(DSPBBASE);
522 hw->disp_a_stride = INREG(DSPASTRIDE);
523 hw->disp_b_stride = INREG(DSPBSTRIDE);
528 hw->vgacntrl = INREG(VGACNTRL);
533 hw->add_id = INREG(ADD_ID);
538 for (i = 0; i < 7; i++) {
539 hw->swf0x[i] = INREG(SWF00 + (i << 2));
540 hw->swf1x[i] = INREG(SWF10 + (i << 2));
542 hw->swf3x[i] = INREG(SWF30 + (i << 2));
545 for (i = 0; i < 8; i++)
546 hw->fence[i] = INREG(FENCE + (i << 2));
548 hw->instpm = INREG(INSTPM);
549 hw->mem_mode = INREG(MEM_MODE);
550 hw->fw_blc_0 = INREG(FW_BLC_0);
551 hw->fw_blc_1 = INREG(FW_BLC_1);
557 static int calc_vclock3(int index, int m, int n, int p)
559 return PLL_REFCLK * m / n / p;
562 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
567 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
568 ((p1)) * (p2 ? 10 : 5)));
571 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
572 ((p1+2) * (1 << (p2 + 1)))));
577 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
580 int i, m1, m2, n, p1, p2;
581 int index = dinfo->pll_index;
582 DBG_MSG("intelfbhw_print_hw_state\n");
586 /* Read in as much of the HW state as possible. */
587 printk("hw state dump start\n");
588 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
589 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
590 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
591 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
592 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
593 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
594 if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
597 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
598 p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
599 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
601 printk(" VGA0: clock is %d\n",
602 calc_vclock(index, m1, m2, n, p1, p2));
604 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
605 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
606 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
607 if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
610 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
611 p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
612 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
614 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
616 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
617 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
618 printk(" FPA0: 0x%08x\n", hw->fpa0);
619 printk(" FPA1: 0x%08x\n", hw->fpa1);
620 printk(" FPB0: 0x%08x\n", hw->fpb0);
621 printk(" FPB1: 0x%08x\n", hw->fpb1);
623 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
624 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
625 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
626 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
629 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
630 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
631 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
633 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
635 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
636 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
637 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
638 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
641 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
642 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
643 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
645 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
648 printk(" PALETTE_A:\n");
649 for (i = 0; i < PALETTE_8_ENTRIES)
650 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
651 printk(" PALETTE_B:\n");
652 for (i = 0; i < PALETTE_8_ENTRIES)
653 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
656 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
657 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
658 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
659 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
660 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
661 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
662 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
663 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
664 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
665 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
666 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
667 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
668 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
669 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
670 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
671 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
673 printk(" ADPA: 0x%08x\n", hw->adpa);
674 printk(" DVOA: 0x%08x\n", hw->dvoa);
675 printk(" DVOB: 0x%08x\n", hw->dvob);
676 printk(" DVOC: 0x%08x\n", hw->dvoc);
677 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
678 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
679 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
680 printk(" LVDS: 0x%08x\n", hw->lvds);
682 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
683 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
684 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
686 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
687 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
688 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
689 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
691 printk(" CURSOR_A_PALETTE: ");
692 for (i = 0; i < 4; i++) {
693 printk("0x%08x", hw->cursor_a_palette[i]);
698 printk(" CURSOR_B_PALETTE: ");
699 for (i = 0; i < 4; i++) {
700 printk("0x%08x", hw->cursor_b_palette[i]);
706 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
708 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
709 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
710 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
711 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
712 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
713 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
715 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
716 printk(" ADD_ID: 0x%08x\n", hw->add_id);
718 for (i = 0; i < 7; i++) {
719 printk(" SWF0%d 0x%08x\n", i,
722 for (i = 0; i < 7; i++) {
723 printk(" SWF1%d 0x%08x\n", i,
726 for (i = 0; i < 3; i++) {
727 printk(" SWF3%d 0x%08x\n", i,
730 for (i = 0; i < 8; i++)
731 printk(" FENCE%d 0x%08x\n", i,
734 printk(" INSTPM 0x%08x\n", hw->instpm);
735 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
736 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
737 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
739 printk("hw state dump end\n");
745 /* Split the M parameter into M1 and M2. */
747 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
751 /* no point optimising too much - brute force m */
752 for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++)
754 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++)
756 testm = ( 5 * ( m1 + 2 )) + (m2 + 2);
759 *retm1 = (unsigned int)m1;
760 *retm2 = (unsigned int)m2;
768 /* Split the P parameter into P1 and P2. */
770 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
774 if (index == PLLS_I9xx)
779 *retp1 = (unsigned int)p1;
780 *retp2 = (unsigned int)p2;
784 if (index == PLLS_I8xx)
790 p1 = (p / (1 << (p2 + 1))) - 2;
791 if (p % 4 == 0 && p1 < plls[index].min_p1) {
793 p1 = (p / (1 << (p2 + 1))) - 2;
795 if (p1 < plls[index].min_p1 || p1 > plls[index].max_p1 || (p1 + 2) * (1 << (p2 + 1)) != p) {
798 *retp1 = (unsigned int)p1;
799 *retp2 = (unsigned int)p2;
807 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
808 u32 *retp2, u32 *retclock)
810 u32 m1, m2, n, p1, p2, n1;
811 u32 f_vco, p, p_best = 0, m, f_out;
812 u32 err_max, err_target, err_best = 10000000;
813 u32 n_best = 0, m_best = 0, f_best, f_err;
814 u32 p_min, p_max, p_inc, div_min, div_max;
816 /* Accept 0.5% difference, but aim for 0.1% */
817 err_max = 5 * clock / 1000;
818 err_target = clock / 1000;
820 DBG_MSG("Clock is %d\n", clock);
822 div_max = plls[index].max_vco_freq / clock;
823 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
825 if (clock <= plls[index].p_transition_clock)
826 p_inc = plls[index].p_inc_lo;
828 p_inc = plls[index].p_inc_hi;
829 p_min = ROUND_UP_TO(div_min, p_inc);
830 p_max = ROUND_DOWN_TO(div_max, p_inc);
831 if (p_min < plls[index].min_p)
832 p_min = plls[index].min_p;
833 if (p_max > plls[index].max_p)
834 p_max = plls[index].max_p;
836 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
840 if (splitp(index, p, &p1, &p2)) {
841 WRN_MSG("cannot split p = %d\n", p);
845 n = plls[index].min_n;
849 m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
850 if (m < plls[index].min_m)
851 m = plls[index].min_m;
852 if (m > plls[index].max_m)
853 m = plls[index].max_m;
854 f_out = calc_vclock3(index, m, n, p);
855 if (splitm(index, m, &m1, &m2)) {
856 WRN_MSG("cannot split m = %d\n", m);
861 f_err = clock - f_out;
863 f_err = f_out - clock;
865 if (f_err < err_best) {
873 } while ((n <= plls[index].max_n) && (f_out >= clock));
875 } while ((p <= p_max));
878 WRN_MSG("cannot find parameters for clock %d\n", clock);
884 splitm(index, m, &m1, &m2);
885 splitp(index, p, &p1, &p2);
888 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
889 "f: %d (%d), VCO: %d\n",
890 m, m1, m2, n, n1, p, p1, p2,
891 calc_vclock3(index, m, n, p),
892 calc_vclock(index, m1, m2, n1, p1, p2),
893 calc_vclock3(index, m, n, p) * p);
899 *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
904 static __inline__ int
905 check_overflow(u32 value, u32 limit, const char *description)
908 WRN_MSG("%s value %d exceeds limit %d\n",
909 description, value, limit);
915 /* It is assumed that hw is filled in with the initial state information. */
917 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
918 struct fb_var_screeninfo *var)
921 u32 *dpll, *fp0, *fp1;
922 u32 m1, m2, n, p1, p2, clock_target, clock;
923 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
924 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
925 u32 vsync_pol, hsync_pol;
926 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
928 DBG_MSG("intelfbhw_mode_to_hw\n");
931 hw->vgacntrl |= VGA_DISABLE;
933 /* Check whether pipe A or pipe B is enabled. */
934 if (hw->pipe_a_conf & PIPECONF_ENABLE)
936 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
939 /* Set which pipe's registers will be set. */
940 if (pipe == PIPE_B) {
950 ss = &hw->src_size_b;
951 pipe_conf = &hw->pipe_b_conf;
962 ss = &hw->src_size_a;
963 pipe_conf = &hw->pipe_a_conf;
966 /* Use ADPA register for sync control. */
967 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
970 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
971 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
972 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
973 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
974 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
975 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
976 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
977 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
979 /* Connect correct pipe to the analog port DAC */
980 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
981 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
983 /* Set DPMS state to D0 (on) */
984 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
985 hw->adpa |= ADPA_DPMS_D0;
987 hw->adpa |= ADPA_DAC_ENABLE;
989 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
990 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
991 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
993 /* Desired clock in kHz */
994 clock_target = 1000000000 / var->pixclock;
996 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2, &n, &p1, &p2, &clock)) {
997 WRN_MSG("calc_pll_params failed\n");
1001 /* Check for overflow. */
1002 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1004 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1006 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1008 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1010 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1013 *dpll &= ~DPLL_P1_FORCE_DIV2;
1014 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1015 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1016 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1017 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1018 (m1 << FP_M1_DIVISOR_SHIFT) |
1019 (m2 << FP_M2_DIVISOR_SHIFT);
1022 hw->dvob &= ~PORT_ENABLE;
1023 hw->dvoc &= ~PORT_ENABLE;
1025 /* Use display plane A. */
1026 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1027 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1028 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1029 switch (intelfb_var_to_depth(var)) {
1031 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1034 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1037 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1040 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1043 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1044 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1046 /* Set CRTC registers. */
1047 hactive = var->xres;
1048 hsync_start = hactive + var->right_margin;
1049 hsync_end = hsync_start + var->hsync_len;
1050 htotal = hsync_end + var->left_margin;
1051 hblank_start = hactive;
1052 hblank_end = htotal;
1054 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1055 hactive, hsync_start, hsync_end, htotal, hblank_start,
1058 vactive = var->yres;
1059 vsync_start = vactive + var->lower_margin;
1060 vsync_end = vsync_start + var->vsync_len;
1061 vtotal = vsync_end + var->upper_margin;
1062 vblank_start = vactive;
1063 vblank_end = vtotal;
1064 vblank_end = vsync_end + 1;
1066 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1067 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1070 /* Adjust for register values, and check for overflow. */
1072 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1075 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1078 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1081 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1084 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1087 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1091 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1094 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1097 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1100 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1103 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1106 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1109 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1110 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1111 (hblank_end << HSYNCEND_SHIFT);
1112 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1114 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1115 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1116 (vblank_end << VSYNCEND_SHIFT);
1117 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1118 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1119 (vactive << SRC_SIZE_VERT_SHIFT);
1121 hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1122 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1124 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1125 var->xoffset * var->bits_per_pixel / 8;
1127 hw->disp_a_base += dinfo->fb.offset << 12;
1129 /* Check stride alignment. */
1130 if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1131 WRN_MSG("display stride %d has bad alignment %d\n",
1132 hw->disp_a_stride, STRIDE_ALIGNMENT);
1136 /* Set the palette to 8-bit mode. */
1137 *pipe_conf &= ~PIPECONF_GAMMA;
1141 /* Program a (non-VGA) video mode. */
1143 intelfbhw_program_mode(struct intelfb_info *dinfo,
1144 const struct intelfb_hwstate *hw, int blank)
1148 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1149 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1150 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1151 u32 hsync_reg, htotal_reg, hblank_reg;
1152 u32 vsync_reg, vtotal_reg, vblank_reg;
1155 /* Assume single pipe, display plane A, analog CRT. */
1158 DBG_MSG("intelfbhw_program_mode\n");
1162 tmp = INREG(VGACNTRL);
1164 OUTREG(VGACNTRL, tmp);
1166 /* Check whether pipe A or pipe B is enabled. */
1167 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1169 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1174 if (pipe == PIPE_B) {
1178 pipe_conf = &hw->pipe_b_conf;
1185 ss = &hw->src_size_b;
1189 pipe_conf_reg = PIPEBCONF;
1190 hsync_reg = HSYNC_B;
1191 htotal_reg = HTOTAL_B;
1192 hblank_reg = HBLANK_B;
1193 vsync_reg = VSYNC_B;
1194 vtotal_reg = VTOTAL_B;
1195 vblank_reg = VBLANK_B;
1196 src_size_reg = SRC_SIZE_B;
1201 pipe_conf = &hw->pipe_a_conf;
1208 ss = &hw->src_size_a;
1212 pipe_conf_reg = PIPEACONF;
1213 hsync_reg = HSYNC_A;
1214 htotal_reg = HTOTAL_A;
1215 hblank_reg = HBLANK_A;
1216 vsync_reg = VSYNC_A;
1217 vtotal_reg = VTOTAL_A;
1218 vblank_reg = VBLANK_A;
1219 src_size_reg = SRC_SIZE_A;
1222 /* Disable planes A and B. */
1223 tmp = INREG(DSPACNTR);
1224 tmp &= ~DISPPLANE_PLANE_ENABLE;
1225 OUTREG(DSPACNTR, tmp);
1226 tmp = INREG(DSPBCNTR);
1227 tmp &= ~DISPPLANE_PLANE_ENABLE;
1228 OUTREG(DSPBCNTR, tmp);
1230 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1235 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1236 tmp |= ADPA_DPMS_D3;
1240 tmp = INREG(pipe_conf_reg);
1241 tmp &= ~PIPECONF_ENABLE;
1242 OUTREG(pipe_conf_reg, tmp);
1245 tmp = INREG(dpll_reg);
1246 dpll_reg &= ~DPLL_VCO_ENABLE;
1247 OUTREG(dpll_reg, tmp);
1249 /* Set PLL parameters */
1250 OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1251 OUTREG(fp0_reg, *fp0);
1252 OUTREG(fp1_reg, *fp1);
1254 /* Set pipe parameters */
1255 OUTREG(hsync_reg, *hs);
1256 OUTREG(hblank_reg, *hb);
1257 OUTREG(htotal_reg, *ht);
1258 OUTREG(vsync_reg, *vs);
1259 OUTREG(vblank_reg, *vb);
1260 OUTREG(vtotal_reg, *vt);
1261 OUTREG(src_size_reg, *ss);
1264 OUTREG(DVOB, hw->dvob);
1265 OUTREG(DVOC, hw->dvoc);
1268 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1271 tmp = INREG(dpll_reg);
1272 tmp |= DPLL_VCO_ENABLE;
1273 OUTREG(dpll_reg, tmp);
1276 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1280 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1281 tmp |= ADPA_DPMS_D0;
1284 /* setup display plane */
1285 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1287 * i830M errata: the display plane must be enabled
1288 * to allow writes to the other bits in the plane
1291 tmp = INREG(DSPACNTR);
1292 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1293 tmp |= DISPPLANE_PLANE_ENABLE;
1294 OUTREG(DSPACNTR, tmp);
1296 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1301 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1302 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1303 OUTREG(DSPABASE, hw->disp_a_base);
1307 tmp = INREG(DSPACNTR);
1308 tmp |= DISPPLANE_PLANE_ENABLE;
1309 OUTREG(DSPACNTR, tmp);
1310 OUTREG(DSPABASE, hw->disp_a_base);
1316 /* forward declarations */
1317 static void refresh_ring(struct intelfb_info *dinfo);
1318 static void reset_state(struct intelfb_info *dinfo);
1319 static void do_flush(struct intelfb_info *dinfo);
1322 wait_ring(struct intelfb_info *dinfo, int n)
1326 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1329 DBG_MSG("wait_ring: %d\n", n);
1332 end = jiffies + (HZ * 3);
1333 while (dinfo->ring_space < n) {
1334 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1336 if (dinfo->ring_tail + RING_MIN_FREE <
1337 (u32 __iomem) dinfo->ring_head)
1338 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1339 - (dinfo->ring_tail + RING_MIN_FREE);
1341 dinfo->ring_space = (dinfo->ring.size +
1342 (u32 __iomem) dinfo->ring_head)
1343 - (dinfo->ring_tail + RING_MIN_FREE);
1344 if ((u32 __iomem) dinfo->ring_head != last_head) {
1345 end = jiffies + (HZ * 3);
1346 last_head = (u32 __iomem) dinfo->ring_head;
1349 if (time_before(end, jiffies)) {
1353 refresh_ring(dinfo);
1355 end = jiffies + (HZ * 3);
1358 WRN_MSG("ring buffer : space: %d wanted %d\n",
1359 dinfo->ring_space, n);
1360 WRN_MSG("lockup - turning off hardware "
1362 dinfo->ring_lockup = 1;
1372 do_flush(struct intelfb_info *dinfo) {
1374 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1380 intelfbhw_do_sync(struct intelfb_info *dinfo)
1383 DBG_MSG("intelfbhw_do_sync\n");
1390 * Send a flush, then wait until the ring is empty. This is what
1391 * the XFree86 driver does, and actually it doesn't seem a lot worse
1392 * than the recommended method (both have problems).
1395 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1396 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1400 refresh_ring(struct intelfb_info *dinfo)
1403 DBG_MSG("refresh_ring\n");
1406 dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1408 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1409 if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1410 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1411 - (dinfo->ring_tail + RING_MIN_FREE);
1413 dinfo->ring_space = (dinfo->ring.size +
1414 (u32 __iomem) dinfo->ring_head)
1415 - (dinfo->ring_tail + RING_MIN_FREE);
1419 reset_state(struct intelfb_info *dinfo)
1425 DBG_MSG("reset_state\n");
1428 for (i = 0; i < FENCE_NUM; i++)
1429 OUTREG(FENCE + (i << 2), 0);
1431 /* Flush the ring buffer if it's enabled. */
1432 tmp = INREG(PRI_RING_LENGTH);
1433 if (tmp & RING_ENABLE) {
1435 DBG_MSG("reset_state: ring was enabled\n");
1437 refresh_ring(dinfo);
1438 intelfbhw_do_sync(dinfo);
1442 OUTREG(PRI_RING_LENGTH, 0);
1443 OUTREG(PRI_RING_HEAD, 0);
1444 OUTREG(PRI_RING_TAIL, 0);
1445 OUTREG(PRI_RING_START, 0);
1448 /* Stop the 2D engine, and turn off the ring buffer. */
1450 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1453 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1454 dinfo->ring_active);
1460 dinfo->ring_active = 0;
1465 * Enable the ring buffer, and initialise the 2D engine.
1466 * It is assumed that the graphics engine has been stopped by previously
1467 * calling intelfb_2d_stop().
1470 intelfbhw_2d_start(struct intelfb_info *dinfo)
1473 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1474 dinfo->accel, dinfo->ring_active);
1480 /* Initialise the primary ring buffer. */
1481 OUTREG(PRI_RING_LENGTH, 0);
1482 OUTREG(PRI_RING_TAIL, 0);
1483 OUTREG(PRI_RING_HEAD, 0);
1485 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1486 OUTREG(PRI_RING_LENGTH,
1487 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1488 RING_NO_REPORT | RING_ENABLE);
1489 refresh_ring(dinfo);
1490 dinfo->ring_active = 1;
1493 /* 2D fillrect (solid fill or invert) */
1495 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1496 u32 color, u32 pitch, u32 bpp, u32 rop)
1498 u32 br00, br09, br13, br14, br16;
1501 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1502 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1505 br00 = COLOR_BLT_CMD;
1506 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1507 br13 = (rop << ROP_SHIFT) | pitch;
1508 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1513 br13 |= COLOR_DEPTH_8;
1516 br13 |= COLOR_DEPTH_16;
1519 br13 |= COLOR_DEPTH_32;
1520 br00 |= WRITE_ALPHA | WRITE_RGB;
1534 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1535 dinfo->ring_tail, dinfo->ring_space);
1540 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1541 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1543 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1546 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1547 curx, cury, dstx, dsty, w, h, pitch, bpp);
1550 br00 = XY_SRC_COPY_BLT_CMD;
1551 br09 = dinfo->fb_start;
1552 br11 = (pitch << PITCH_SHIFT);
1553 br12 = dinfo->fb_start;
1554 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1555 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1556 br23 = ((dstx + w) << WIDTH_SHIFT) |
1557 ((dsty + h) << HEIGHT_SHIFT);
1558 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1562 br13 |= COLOR_DEPTH_8;
1565 br13 |= COLOR_DEPTH_16;
1568 br13 |= COLOR_DEPTH_32;
1569 br00 |= WRITE_ALPHA | WRITE_RGB;
1586 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1587 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1589 int nbytes, ndwords, pad, tmp;
1590 u32 br00, br09, br13, br18, br19, br22, br23;
1591 int dat, ix, iy, iw;
1595 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1598 /* size in bytes of a padded scanline */
1599 nbytes = ROUND_UP_TO(w, 16) / 8;
1601 /* Total bytes of padded scanline data to write out. */
1602 nbytes = nbytes * h;
1605 * Check if the glyph data exceeds the immediate mode limit.
1606 * It would take a large font (1K pixels) to hit this limit.
1608 if (nbytes > MAX_MONO_IMM_SIZE)
1611 /* Src data is packaged a dword (32-bit) at a time. */
1612 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1615 * Ring has to be padded to a quad word. But because the command starts
1616 with 7 bytes, pad only if there is an even number of ndwords
1618 pad = !(ndwords % 2);
1620 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1621 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1622 br09 = dinfo->fb_start;
1623 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1626 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1627 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1631 br13 |= COLOR_DEPTH_8;
1634 br13 |= COLOR_DEPTH_16;
1637 br13 |= COLOR_DEPTH_32;
1638 br00 |= WRITE_ALPHA | WRITE_RGB;
1642 START_RING(8 + ndwords);
1651 iw = ROUND_UP_TO(w, 8) / 8;
1654 for (j = 0; j < 2; ++j) {
1655 for (i = 0; i < 2; ++i) {
1656 if (ix != iw || i == 0)
1657 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1659 if (ix == iw && iy != (h-1)) {
1673 /* HW cursor functions. */
1675 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1680 DBG_MSG("intelfbhw_cursor_init\n");
1683 if (dinfo->mobile) {
1684 if (!dinfo->cursor.physical)
1686 tmp = INREG(CURSOR_A_CONTROL);
1687 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1688 CURSOR_MEM_TYPE_LOCAL |
1689 (1 << CURSOR_PIPE_SELECT_SHIFT));
1690 tmp |= CURSOR_MODE_DISABLE;
1691 OUTREG(CURSOR_A_CONTROL, tmp);
1692 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1694 tmp = INREG(CURSOR_CONTROL);
1695 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1696 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1697 tmp = CURSOR_FORMAT_3C;
1698 OUTREG(CURSOR_CONTROL, tmp);
1699 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1700 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1701 (64 << CURSOR_SIZE_V_SHIFT);
1702 OUTREG(CURSOR_SIZE, tmp);
1707 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1712 DBG_MSG("intelfbhw_cursor_hide\n");
1715 dinfo->cursor_on = 0;
1716 if (dinfo->mobile) {
1717 if (!dinfo->cursor.physical)
1719 tmp = INREG(CURSOR_A_CONTROL);
1720 tmp &= ~CURSOR_MODE_MASK;
1721 tmp |= CURSOR_MODE_DISABLE;
1722 OUTREG(CURSOR_A_CONTROL, tmp);
1724 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1726 tmp = INREG(CURSOR_CONTROL);
1727 tmp &= ~CURSOR_ENABLE;
1728 OUTREG(CURSOR_CONTROL, tmp);
1733 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1738 DBG_MSG("intelfbhw_cursor_show\n");
1741 dinfo->cursor_on = 1;
1743 if (dinfo->cursor_blanked)
1746 if (dinfo->mobile) {
1747 if (!dinfo->cursor.physical)
1749 tmp = INREG(CURSOR_A_CONTROL);
1750 tmp &= ~CURSOR_MODE_MASK;
1751 tmp |= CURSOR_MODE_64_4C_AX;
1752 OUTREG(CURSOR_A_CONTROL, tmp);
1754 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1756 tmp = INREG(CURSOR_CONTROL);
1757 tmp |= CURSOR_ENABLE;
1758 OUTREG(CURSOR_CONTROL, tmp);
1763 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1768 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1772 * Sets the position. The coordinates are assumed to already
1773 * have any offset adjusted. Assume that the cursor is never
1774 * completely off-screen, and that x, y are always >= 0.
1777 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1778 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1779 OUTREG(CURSOR_A_POSITION, tmp);
1783 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1786 DBG_MSG("intelfbhw_cursor_setcolor\n");
1789 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1790 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1791 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1792 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1796 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1799 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1800 int i, j, w = width / 8;
1801 int mod = width % 8, t_mask, d_mask;
1804 DBG_MSG("intelfbhw_cursor_load\n");
1807 if (!dinfo->cursor.virtual)
1810 t_mask = 0xff >> mod;
1811 d_mask = ~(0xff >> mod);
1812 for (i = height; i--; ) {
1813 for (j = 0; j < w; j++) {
1814 writeb(0x00, addr + j);
1815 writeb(*(data++), addr + j+8);
1818 writeb(t_mask, addr + j);
1819 writeb(*(data++) & d_mask, addr + j+8);
1826 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1827 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1831 DBG_MSG("intelfbhw_cursor_reset\n");
1834 if (!dinfo->cursor.virtual)
1837 for (i = 64; i--; ) {
1838 for (j = 0; j < 8; j++) {
1839 writeb(0xff, addr + j+0);
1840 writeb(0x00, addr + j+8);