SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco, max_vco;
  51         int p_transition_clk, ref_clk;
  52         int p_inc_lo, p_inc_hi;
  53 };
  54
  55 #define PLLS_I8xx 0
  56 #define PLLS_I9xx 1
  57 #define PLLS_MAX 2
  58
  59 static struct pll_min_max plls[PLLS_MAX] = {
  60   { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 48000, 4, 22 }, //I8xx
  61   {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000, 96000, 10, 5 }  //I9xx
  62 };
  63
  64 int
  65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  66 {
  67         u32 tmp;
  68         if (!pdev || !dinfo)
  69                 return 1;
  70
  71         switch (pdev->device) {
  72         case PCI_DEVICE_ID_INTEL_830M:
  73                 dinfo->name = "Intel(R) 830M";
  74                 dinfo->chipset = INTEL_830M;
  75                 dinfo->mobile = 1;
  76                 dinfo->pll_index = PLLS_I8xx;
  77                 return 0;
  78         case PCI_DEVICE_ID_INTEL_845G:
  79                 dinfo->name = "Intel(R) 845G";
  80                 dinfo->chipset = INTEL_845G;
  81                 dinfo->mobile = 0;
  82                 dinfo->pll_index = PLLS_I8xx;
  83                 return 0;
  84         case PCI_DEVICE_ID_INTEL_85XGM:
  85                 tmp = 0;
  86                 dinfo->mobile = 1;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  89                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  90                         INTEL_85X_VARIANT_MASK) {
  91                 case INTEL_VAR_855GME:
  92                         dinfo->name = "Intel(R) 855GME";
  93                         dinfo->chipset = INTEL_855GME;
  94                         return 0;
  95                 case INTEL_VAR_855GM:
  96                         dinfo->name = "Intel(R) 855GM";
  97                         dinfo->chipset = INTEL_855GM;
  98                         return 0;
  99                 case INTEL_VAR_852GME:
 100                         dinfo->name = "Intel(R) 852GME";
 101                         dinfo->chipset = INTEL_852GME;
 102                         return 0;
 103                 case INTEL_VAR_852GM:
 104                         dinfo->name = "Intel(R) 852GM";
 105                         dinfo->chipset = INTEL_852GM;
 106                         return 0;
 107                 default:
 108                         dinfo->name = "Intel(R) 852GM/855GM";
 109                         dinfo->chipset = INTEL_85XGM;
 110                         return 0;
 111                 }
 112                 break;
 113         case PCI_DEVICE_ID_INTEL_865G:
 114                 dinfo->name = "Intel(R) 865G";
 115                 dinfo->chipset = INTEL_865G;
 116                 dinfo->mobile = 0;
 117                 dinfo->pll_index = PLLS_I8xx;
 118                 return 0;
 119         case PCI_DEVICE_ID_INTEL_915G:
 120                 dinfo->name = "Intel(R) 915G";
 121                 dinfo->chipset = INTEL_915G;
 122                 dinfo->mobile = 0;
 123                 dinfo->pll_index = PLLS_I9xx;
 124                 return 0;
 125         case PCI_DEVICE_ID_INTEL_915GM:
 126                 dinfo->name = "Intel(R) 915GM";
 127                 dinfo->chipset = INTEL_915GM;
 128                 dinfo->mobile = 1;
 129                 dinfo->pll_index = PLLS_I9xx;
 130                 return 0;
 131         case PCI_DEVICE_ID_INTEL_945G:
 132                 dinfo->name = "Intel(R) 945G";
 133                 dinfo->chipset = INTEL_945G;
 134                 dinfo->mobile = 0;
 135                 dinfo->pll_index = PLLS_I9xx;
 136                 return 0;
 137         case PCI_DEVICE_ID_INTEL_945GM:
 138                 dinfo->name = "Intel(R) 945GM";
 139                 dinfo->chipset = INTEL_945GM;
 140                 dinfo->mobile = 1;
 141                 dinfo->pll_index = PLLS_I9xx;
 142                 return 0;
 143         default:
 144                 return 1;
 145         }
 146 }
 147
 148 int
 149 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 150                      int *stolen_size)
 151 {
 152         struct pci_dev *bridge_dev;
 153         u16 tmp;
 154
 155         if (!pdev || !aperture_size || !stolen_size)
 156                 return 1;
 157
 158         /* Find the bridge device.  It is always 0:0.0 */
 159         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 160                 ERR_MSG("cannot find bridge device\n");
 161                 return 1;
 162         }
 163
 164         /* Get the fb aperture size and "stolen" memory amount. */
 165         tmp = 0;
 166         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 167         switch (pdev->device) {
 168         case PCI_DEVICE_ID_INTEL_830M:
 169         case PCI_DEVICE_ID_INTEL_845G:
 170                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 171                         *aperture_size = MB(64);
 172                 else
 173                         *aperture_size = MB(128);
 174                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 175                 case INTEL_830_GMCH_GMS_STOLEN_512:
 176                         *stolen_size = KB(512) - KB(132);
 177                         return 0;
 178                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 179                         *stolen_size = MB(1) - KB(132);
 180                         return 0;
 181                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 182                         *stolen_size = MB(8) - KB(132);
 183                         return 0;
 184                 case INTEL_830_GMCH_GMS_LOCAL:
 185                         ERR_MSG("only local memory found\n");
 186                         return 1;
 187                 case INTEL_830_GMCH_GMS_DISABLED:
 188                         ERR_MSG("video memory is disabled\n");
 189                         return 1;
 190                 default:
 191                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 192                                 tmp & INTEL_830_GMCH_GMS_MASK);
 193                         return 1;
 194                 }
 195                 break;
 196         default:
 197                 *aperture_size = MB(128);
 198                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 199                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 200                         *stolen_size = MB(1) - KB(132);
 201                         return 0;
 202                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 203                         *stolen_size = MB(4) - KB(132);
 204                         return 0;
 205                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 206                         *stolen_size = MB(8) - KB(132);
 207                         return 0;
 208                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 209                         *stolen_size = MB(16) - KB(132);
 210                         return 0;
 211                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 212                         *stolen_size = MB(32) - KB(132);
 213                         return 0;
 214                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 215                         *stolen_size = MB(48) - KB(132);
 216                         return 0;
 217                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 218                         *stolen_size = MB(64) - KB(132);
 219                         return 0;
 220                 case INTEL_855_GMCH_GMS_DISABLED:
 221                         ERR_MSG("video memory is disabled\n");
 222                         return 0;
 223                 default:
 224                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 225                                 tmp & INTEL_855_GMCH_GMS_MASK);
 226                         return 1;
 227                 }
 228         }
 229 }
 230
 231 int
 232 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 233 {
 234         int dvo = 0;
 235
 236         if (INREG(LVDS) & PORT_ENABLE)
 237                 dvo |= LVDS_PORT;
 238         if (INREG(DVOA) & PORT_ENABLE)
 239                 dvo |= DVOA_PORT;
 240         if (INREG(DVOB) & PORT_ENABLE)
 241                 dvo |= DVOB_PORT;
 242         if (INREG(DVOC) & PORT_ENABLE)
 243                 dvo |= DVOC_PORT;
 244
 245         return dvo;
 246 }
 247
 248 const char *
 249 intelfbhw_dvo_to_string(int dvo)
 250 {
 251         if (dvo & DVOA_PORT)
 252                 return "DVO port A";
 253         else if (dvo & DVOB_PORT)
 254                 return "DVO port B";
 255         else if (dvo & DVOC_PORT)
 256                 return "DVO port C";
 257         else if (dvo & LVDS_PORT)
 258                 return "LVDS port";
 259         else
 260                 return NULL;
 261 }
 262
 263
 264 int
 265 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 266                         struct fb_var_screeninfo *var)
 267 {
 268         int bytes_per_pixel;
 269         int tmp;
 270
 271 #if VERBOSE > 0
 272         DBG_MSG("intelfbhw_validate_mode\n");
 273 #endif
 274
 275         bytes_per_pixel = var->bits_per_pixel / 8;
 276         if (bytes_per_pixel == 3)
 277                 bytes_per_pixel = 4;
 278
 279         /* Check if enough video memory. */
 280         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 281         if (tmp > dinfo->fb.size) {
 282                 WRN_MSG("Not enough video ram for mode "
 283                         "(%d KByte vs %d KByte).\n",
 284                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 285                 return 1;
 286         }
 287
 288         /* Check if x/y limits are OK. */
 289         if (var->xres - 1 > HACTIVE_MASK) {
 290                 WRN_MSG("X resolution too large (%d vs %d).\n",
 291                         var->xres, HACTIVE_MASK + 1);
 292                 return 1;
 293         }
 294         if (var->yres - 1 > VACTIVE_MASK) {
 295                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 296                         var->yres, VACTIVE_MASK + 1);
 297                 return 1;
 298         }
 299
 300         /* Check for interlaced/doublescan modes. */
 301         if (var->vmode & FB_VMODE_INTERLACED) {
 302                 WRN_MSG("Mode is interlaced.\n");
 303                 return 1;
 304         }
 305         if (var->vmode & FB_VMODE_DOUBLE) {
 306                 WRN_MSG("Mode is double-scan.\n");
 307                 return 1;
 308         }
 309
 310         /* Check if clock is OK. */
 311         tmp = 1000000000 / var->pixclock;
 312         if (tmp < MIN_CLOCK) {
 313                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 314                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 315                 return 1;
 316         }
 317         if (tmp > MAX_CLOCK) {
 318                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 319                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 320                 return 1;
 321         }
 322
 323         return 0;
 324 }
 325
 326 int
 327 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 328 {
 329         struct intelfb_info *dinfo = GET_DINFO(info);
 330         u32 offset, xoffset, yoffset;
 331
 332 #if VERBOSE > 0
 333         DBG_MSG("intelfbhw_pan_display\n");
 334 #endif
 335
 336         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 337         yoffset = var->yoffset;
 338
 339         if ((xoffset + var->xres > var->xres_virtual) ||
 340             (yoffset + var->yres > var->yres_virtual))
 341                 return -EINVAL;
 342
 343         offset = (yoffset * dinfo->pitch) +
 344                  (xoffset * var->bits_per_pixel) / 8;
 345
 346         offset += dinfo->fb.offset << 12;
 347
 348         OUTREG(DSPABASE, offset);
 349
 350         return 0;
 351 }
 352
 353 /* Blank the screen. */
 354 void
 355 intelfbhw_do_blank(int blank, struct fb_info *info)
 356 {
 357         struct intelfb_info *dinfo = GET_DINFO(info);
 358         u32 tmp;
 359
 360 #if VERBOSE > 0
 361         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 362 #endif
 363
 364         /* Turn plane A on or off */
 365         tmp = INREG(DSPACNTR);
 366         if (blank)
 367                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 368         else
 369                 tmp |= DISPPLANE_PLANE_ENABLE;
 370         OUTREG(DSPACNTR, tmp);
 371         /* Flush */
 372         tmp = INREG(DSPABASE);
 373         OUTREG(DSPABASE, tmp);
 374
 375         /* Turn off/on the HW cursor */
 376 #if VERBOSE > 0
 377         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 378 #endif
 379         if (dinfo->cursor_on) {
 380                 if (blank) {
 381                         intelfbhw_cursor_hide(dinfo);
 382                 } else {
 383                         intelfbhw_cursor_show(dinfo);
 384                 }
 385                 dinfo->cursor_on = 1;
 386         }
 387         dinfo->cursor_blanked = blank;
 388
 389         /* Set DPMS level */
 390         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 391         switch (blank) {
 392         case FB_BLANK_UNBLANK:
 393         case FB_BLANK_NORMAL:
 394                 tmp |= ADPA_DPMS_D0;
 395                 break;
 396         case FB_BLANK_VSYNC_SUSPEND:
 397                 tmp |= ADPA_DPMS_D1;
 398                 break;
 399         case FB_BLANK_HSYNC_SUSPEND:
 400                 tmp |= ADPA_DPMS_D2;
 401                 break;
 402         case FB_BLANK_POWERDOWN:
 403                 tmp |= ADPA_DPMS_D3;
 404                 break;
 405         }
 406         OUTREG(ADPA, tmp);
 407
 408         return;
 409 }
 410
 411
 412 void
 413 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 414                     unsigned red, unsigned green, unsigned blue,
 415                     unsigned transp)
 416 {
 417 #if VERBOSE > 0
 418         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 419                 regno, red, green, blue);
 420 #endif
 421
 422         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 423                           PALETTE_A : PALETTE_B;
 424
 425         OUTREG(palette_reg + (regno << 2),
 426                (red << PALETTE_8_RED_SHIFT) |
 427                (green << PALETTE_8_GREEN_SHIFT) |
 428                (blue << PALETTE_8_BLUE_SHIFT));
 429 }
 430
 431
 432 int
 433 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 434                         int flag)
 435 {
 436         int i;
 437
 438 #if VERBOSE > 0
 439         DBG_MSG("intelfbhw_read_hw_state\n");
 440 #endif
 441
 442         if (!hw || !dinfo)
 443                 return -1;
 444
 445         /* Read in as much of the HW state as possible. */
 446         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 447         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 448         hw->vga_pd = INREG(VGAPD);
 449         hw->dpll_a = INREG(DPLL_A);
 450         hw->dpll_b = INREG(DPLL_B);
 451         hw->fpa0 = INREG(FPA0);
 452         hw->fpa1 = INREG(FPA1);
 453         hw->fpb0 = INREG(FPB0);
 454         hw->fpb1 = INREG(FPB1);
 455
 456         if (flag == 1)
 457                 return flag;
 458
 459 #if 0
 460         /* This seems to be a problem with the 852GM/855GM */
 461         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 462                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 463                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 464         }
 465 #endif
 466
 467         if (flag == 2)
 468                 return flag;
 469
 470         hw->htotal_a = INREG(HTOTAL_A);
 471         hw->hblank_a = INREG(HBLANK_A);
 472         hw->hsync_a = INREG(HSYNC_A);
 473         hw->vtotal_a = INREG(VTOTAL_A);
 474         hw->vblank_a = INREG(VBLANK_A);
 475         hw->vsync_a = INREG(VSYNC_A);
 476         hw->src_size_a = INREG(SRC_SIZE_A);
 477         hw->bclrpat_a = INREG(BCLRPAT_A);
 478         hw->htotal_b = INREG(HTOTAL_B);
 479         hw->hblank_b = INREG(HBLANK_B);
 480         hw->hsync_b = INREG(HSYNC_B);
 481         hw->vtotal_b = INREG(VTOTAL_B);
 482         hw->vblank_b = INREG(VBLANK_B);
 483         hw->vsync_b = INREG(VSYNC_B);
 484         hw->src_size_b = INREG(SRC_SIZE_B);
 485         hw->bclrpat_b = INREG(BCLRPAT_B);
 486
 487         if (flag == 3)
 488                 return flag;
 489
 490         hw->adpa = INREG(ADPA);
 491         hw->dvoa = INREG(DVOA);
 492         hw->dvob = INREG(DVOB);
 493         hw->dvoc = INREG(DVOC);
 494         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 495         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 496         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 497         hw->lvds = INREG(LVDS);
 498
 499         if (flag == 4)
 500                 return flag;
 501
 502         hw->pipe_a_conf = INREG(PIPEACONF);
 503         hw->pipe_b_conf = INREG(PIPEBCONF);
 504         hw->disp_arb = INREG(DISPARB);
 505
 506         if (flag == 5)
 507                 return flag;
 508
 509         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 510         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 511         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 512         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 513
 514         if (flag == 6)
 515                 return flag;
 516
 517         for (i = 0; i < 4; i++) {
 518                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 519                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 520         }
 521
 522         if (flag == 7)
 523                 return flag;
 524
 525         hw->cursor_size = INREG(CURSOR_SIZE);
 526
 527         if (flag == 8)
 528                 return flag;
 529
 530         hw->disp_a_ctrl = INREG(DSPACNTR);
 531         hw->disp_b_ctrl = INREG(DSPBCNTR);
 532         hw->disp_a_base = INREG(DSPABASE);
 533         hw->disp_b_base = INREG(DSPBBASE);
 534         hw->disp_a_stride = INREG(DSPASTRIDE);
 535         hw->disp_b_stride = INREG(DSPBSTRIDE);
 536
 537         if (flag == 9)
 538                 return flag;
 539
 540         hw->vgacntrl = INREG(VGACNTRL);
 541
 542         if (flag == 10)
 543                 return flag;
 544
 545         hw->add_id = INREG(ADD_ID);
 546
 547         if (flag == 11)
 548                 return flag;
 549
 550         for (i = 0; i < 7; i++) {
 551                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 552                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 553                 if (i < 3)
 554                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 555         }
 556
 557         for (i = 0; i < 8; i++)
 558                 hw->fence[i] = INREG(FENCE + (i << 2));
 559
 560         hw->instpm = INREG(INSTPM);
 561         hw->mem_mode = INREG(MEM_MODE);
 562         hw->fw_blc_0 = INREG(FW_BLC_0);
 563         hw->fw_blc_1 = INREG(FW_BLC_1);
 564
 565         return 0;
 566 }
 567
 568
 569 static int calc_vclock3(int index, int m, int n, int p)
 570 {
 571         if (p == 0 || n == 0)
 572                 return 0;
 573         return plls[index].ref_clk * m / n / p;
 574 }
 575
 576 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 577 {
 578         int p2_val;
 579         switch(index)
 580         {
 581         case PLLS_I9xx:
 582                 if (p1 == 0)
 583                         return 0;
 584                 if (lvds)
 585                         p2_val = p2 ? 7 : 14;
 586                 else
 587                         p2_val = p2 ? 5 : 10;
 588                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 589                          ((p1)) * (p2_val)));
 590         case PLLS_I8xx:
 591         default:
 592                 return ((plls[index].ref_clk * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 593                          ((p1+2) * (1 << (p2 + 1)))));
 594         }
 595 }
 596
 597 void
 598 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 599 {
 600 #if REGDUMP
 601         int i, m1, m2, n, p1, p2;
 602         int index = dinfo->pll_index;
 603         DBG_MSG("intelfbhw_print_hw_state\n");
 604
 605         if (!hw || !dinfo)
 606                 return;
 607         /* Read in as much of the HW state as possible. */
 608         printk("hw state dump start\n");
 609         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 610         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 611         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 612         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 613         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 614         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 615         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 616                 p1 = 0;
 617         else
 618                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 619
 620         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 621
 622         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 623                m1, m2, n, p1, p2);
 624         printk("        VGA0: clock is %d\n",
 625                calc_vclock(index, m1, m2, n, p1, p2, 0));
 626
 627         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 628         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 629         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 630         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 631                 p1 = 0;
 632         else
 633                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 634         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 635         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 636                m1, m2, n, p1, p2);
 637         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 638
 639         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 640         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 641         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 642         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 643         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 644         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 645
 646         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 647         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 648         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 649
 650         if (IS_I9XX(dinfo)) {
 651                 int tmpp1;
 652
 653                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 654                         p1 = 0;
 655                 else
 656                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 657
 658                 tmpp1 = p1;
 659
 660                 switch (tmpp1)
 661                 {
 662                 case 0x1: p1 = 1; break;
 663                 case 0x2: p1 = 2; break;
 664                 case 0x4: p1 = 3; break;
 665                 case 0x8: p1 = 4; break;
 666                 case 0x10: p1 = 5; break;
 667                 case 0x20: p1 = 6; break;
 668                 case 0x40: p1 = 7; break;
 669                 case 0x80: p1 = 8; break;
 670                 default: break;
 671                 }
 672
 673                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 674
 675         } else {
 676                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 677                         p1 = 0;
 678                 else
 679                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 680                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 681         }
 682
 683         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 684                m1, m2, n, p1, p2);
 685         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 686
 687         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 688         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 689         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 690
 691         if (IS_I9XX(dinfo)) {
 692                 int tmpp1;
 693
 694                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 695                         p1 = 0;
 696                 else
 697                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & 0xff;
 698
 699                 tmpp1 = p1;
 700
 701                 switch (tmpp1)
 702                 {
 703                 case 0x1: p1 = 1; break;
 704                 case 0x2: p1 = 2; break;
 705                 case 0x4: p1 = 3; break;
 706                 case 0x8: p1 = 4; break;
 707                 case 0x10: p1 = 5; break;
 708                 case 0x20: p1 = 6; break;
 709                 case 0x40: p1 = 7; break;
 710                 case 0x80: p1 = 8; break;
 711                 default: break;
 712                 }
 713
 714                 p2 = (hw->dpll_a >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 715
 716         } else {
 717                 if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 718                         p1 = 0;
 719                 else
 720                         p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 721                 p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 722         }
 723         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 724                m1, m2, n, p1, p2);
 725         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 726
 727 #if 0
 728         printk("        PALETTE_A:\n");
 729         for (i = 0; i < PALETTE_8_ENTRIES)
 730                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 731         printk("        PALETTE_B:\n");
 732         for (i = 0; i < PALETTE_8_ENTRIES)
 733                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 734 #endif
 735
 736         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 737         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 738         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 739         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 740         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 741         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 742         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 743         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 744         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 745         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 746         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 747         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 748         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 749         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 750         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 751         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 752
 753         printk("        ADPA:                   0x%08x\n", hw->adpa);
 754         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 755         printk("        DVOB:                   0x%08x\n", hw->dvob);
 756         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 757         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 758         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 759         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 760         printk("        LVDS:                   0x%08x\n", hw->lvds);
 761
 762         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 763         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 764         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 765
 766         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 767         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 768         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 769         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 770
 771         printk("        CURSOR_A_PALETTE:       ");
 772         for (i = 0; i < 4; i++) {
 773                 printk("0x%08x", hw->cursor_a_palette[i]);
 774                 if (i < 3)
 775                         printk(", ");
 776         }
 777         printk("\n");
 778         printk("        CURSOR_B_PALETTE:       ");
 779         for (i = 0; i < 4; i++) {
 780                 printk("0x%08x", hw->cursor_b_palette[i]);
 781                 if (i < 3)
 782                         printk(", ");
 783         }
 784         printk("\n");
 785
 786         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 787
 788         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 789         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 790         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 791         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 792         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 793         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 794
 795         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 796         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 797
 798         for (i = 0; i < 7; i++) {
 799                 printk("        SWF0%d                  0x%08x\n", i,
 800                         hw->swf0x[i]);
 801         }
 802         for (i = 0; i < 7; i++) {
 803                 printk("        SWF1%d                  0x%08x\n", i,
 804                         hw->swf1x[i]);
 805         }
 806         for (i = 0; i < 3; i++) {
 807                 printk("        SWF3%d                  0x%08x\n", i,
 808                        hw->swf3x[i]);
 809         }
 810         for (i = 0; i < 8; i++)
 811                 printk("        FENCE%d                 0x%08x\n", i,
 812                        hw->fence[i]);
 813
 814         printk("        INSTPM                  0x%08x\n", hw->instpm);
 815         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 816         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 817         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 818
 819         printk("hw state dump end\n");
 820 #endif
 821 }
 822
 823
 824
 825 /* Split the M parameter into M1 and M2. */
 826 static int
 827 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 828 {
 829         int m1, m2;
 830         int testm;
 831         /* no point optimising too much - brute force m */
 832         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 833                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 834                         testm = (5 * (m1 + 2)) + (m2 + 2);
 835                         if (testm == m) {
 836                                 *retm1 = (unsigned int)m1;
 837                                 *retm2 = (unsigned int)m2;
 838                                 return 0;
 839                         }
 840                 }
 841         }
 842         return 1;
 843 }
 844
 845 /* Split the P parameter into P1 and P2. */
 846 static int
 847 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 848 {
 849         int p1, p2;
 850
 851         if (index == PLLS_I9xx) {
 852
 853                 p2 = 0; // for now
 854
 855                 p1 = p / (p2 ? 5 : 10);
 856
 857                 *retp1 = (unsigned int)p1;
 858                 *retp2 = (unsigned int)p2;
 859                 return 0;
 860         }
 861
 862         if (index == PLLS_I8xx) {
 863                 if (p % 4 == 0)
 864                         p2 = 1;
 865                 else
 866                         p2 = 0;
 867                 p1 = (p / (1 << (p2 + 1))) - 2;
 868                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 869                         p2 = 0;
 870                         p1 = (p / (1 << (p2 + 1))) - 2;
 871                 }
 872                 if (p1 < plls[index].min_p1 ||
 873                     p1 > plls[index].max_p1 ||
 874                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 875                         return 1;
 876                 } else {
 877                         *retp1 = (unsigned int)p1;
 878                         *retp2 = (unsigned int)p2;
 879                         return 0;
 880                 }
 881         }
 882         return 1;
 883 }
 884
 885 static int
 886 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 887                 u32 *retp2, u32 *retclock)
 888 {
 889         u32 m1, m2, n, p1, p2, n1, testm;
 890         u32 f_vco, p, p_best = 0, m, f_out = 0;
 891         u32 err_max, err_target, err_best = 10000000;
 892         u32 n_best = 0, m_best = 0, f_best, f_err;
 893         u32 p_min, p_max, p_inc, div_min, div_max;
 894
 895         /* Accept 0.5% difference, but aim for 0.1% */
 896         err_max = 5 * clock / 1000;
 897         err_target = clock / 1000;
 898
 899         DBG_MSG("Clock is %d\n", clock);
 900
 901         div_max = plls[index].max_vco / clock;
 902         if (index == PLLS_I9xx)
 903                 div_min = 5;
 904         else
 905                 div_min = ROUND_UP_TO(plls[index].min_vco, clock) / clock;
 906
 907         if (clock <= plls[index].p_transition_clk)
 908                 p_inc = plls[index].p_inc_lo;
 909         else
 910                 p_inc = plls[index].p_inc_hi;
 911         p_min = ROUND_UP_TO(div_min, p_inc);
 912         p_max = ROUND_DOWN_TO(div_max, p_inc);
 913         if (p_min < plls[index].min_p)
 914                 p_min = plls[index].min_p;
 915         if (p_max > plls[index].max_p)
 916                 p_max = plls[index].max_p;
 917
 918         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 919
 920         p = p_min;
 921         do {
 922                 if (splitp(index, p, &p1, &p2)) {
 923                         WRN_MSG("cannot split p = %d\n", p);
 924                         p += p_inc;
 925                         continue;
 926                 }
 927                 n = plls[index].min_n;
 928                 f_vco = clock * p;
 929
 930                 do {
 931                         m = ROUND_UP_TO(f_vco * n, plls[index].ref_clk) / plls[index].ref_clk;
 932                         if (m < plls[index].min_m)
 933                                 m = plls[index].min_m + 1;
 934                         if (m > plls[index].max_m)
 935                                 m = plls[index].max_m - 1;
 936                         for (testm = m - 1; testm <= m; testm++) {
 937                                 f_out = calc_vclock3(index, m, n, p);
 938                                 if (splitm(index, m, &m1, &m2)) {
 939                                         WRN_MSG("cannot split m = %d\n", m);
 940                                         n++;
 941                                         continue;
 942                                 }
 943                                 if (clock > f_out)
 944                                         f_err = clock - f_out;
 945                                 else/* slightly bias the error for bigger clocks */
 946                                         f_err = f_out - clock + 1;
 947
 948                                 if (f_err < err_best) {
 949                                         m_best = m;
 950                                         n_best = n;
 951                                         p_best = p;
 952                                         f_best = f_out;
 953                                         err_best = f_err;
 954                                 }
 955                         }
 956                         n++;
 957                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 958                 p += p_inc;
 959         } while ((p <= p_max));
 960
 961         if (!m_best) {
 962                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 963                 return 1;
 964         }
 965         m = m_best;
 966         n = n_best;
 967         p = p_best;
 968         splitm(index, m, &m1, &m2);
 969         splitp(index, p, &p1, &p2);
 970         n1 = n - 2;
 971
 972         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 973                 "f: %d (%d), VCO: %d\n",
 974                 m, m1, m2, n, n1, p, p1, p2,
 975                 calc_vclock3(index, m, n, p),
 976                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 977                 calc_vclock3(index, m, n, p) * p);
 978         *retm1 = m1;
 979         *retm2 = m2;
 980         *retn = n1;
 981         *retp1 = p1;
 982         *retp2 = p2;
 983         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 984
 985         return 0;
 986 }
 987
 988 static __inline__ int
 989 check_overflow(u32 value, u32 limit, const char *description)
 990 {
 991         if (value > limit) {
 992                 WRN_MSG("%s value %d exceeds limit %d\n",
 993                         description, value, limit);
 994                 return 1;
 995         }
 996         return 0;
 997 }
 998
 999 /* It is assumed that hw is filled in with the initial state information. */
1000 int
1001 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
1002                      struct fb_var_screeninfo *var)
1003 {
1004         int pipe = PIPE_A;
1005         u32 *dpll, *fp0, *fp1;
1006         u32 m1, m2, n, p1, p2, clock_target, clock;
1007         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
1008         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
1009         u32 vsync_pol, hsync_pol;
1010         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
1011
1012         DBG_MSG("intelfbhw_mode_to_hw\n");
1013
1014         /* Disable VGA */
1015         hw->vgacntrl |= VGA_DISABLE;
1016
1017         /* Check whether pipe A or pipe B is enabled. */
1018         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1019                 pipe = PIPE_A;
1020         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1021                 pipe = PIPE_B;
1022
1023         /* Set which pipe's registers will be set. */
1024         if (pipe == PIPE_B) {
1025                 dpll = &hw->dpll_b;
1026                 fp0 = &hw->fpb0;
1027                 fp1 = &hw->fpb1;
1028                 hs = &hw->hsync_b;
1029                 hb = &hw->hblank_b;
1030                 ht = &hw->htotal_b;
1031                 vs = &hw->vsync_b;
1032                 vb = &hw->vblank_b;
1033                 vt = &hw->vtotal_b;
1034                 ss = &hw->src_size_b;
1035                 pipe_conf = &hw->pipe_b_conf;
1036         } else {
1037                 dpll = &hw->dpll_a;
1038                 fp0 = &hw->fpa0;
1039                 fp1 = &hw->fpa1;
1040                 hs = &hw->hsync_a;
1041                 hb = &hw->hblank_a;
1042                 ht = &hw->htotal_a;
1043                 vs = &hw->vsync_a;
1044                 vb = &hw->vblank_a;
1045                 vt = &hw->vtotal_a;
1046                 ss = &hw->src_size_a;
1047                 pipe_conf = &hw->pipe_a_conf;
1048         }
1049
1050         /* Use ADPA register for sync control. */
1051         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1052
1053         /* sync polarity */
1054         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1055                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1056         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1057                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1058         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1059                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1060         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1061                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1062
1063         /* Connect correct pipe to the analog port DAC */
1064         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1065         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1066
1067         /* Set DPMS state to D0 (on) */
1068         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1069         hw->adpa |= ADPA_DPMS_D0;
1070
1071         hw->adpa |= ADPA_DAC_ENABLE;
1072
1073         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1074         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1075         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1076
1077         /* Desired clock in kHz */
1078         clock_target = 1000000000 / var->pixclock;
1079
1080         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1081                             &n, &p1, &p2, &clock)) {
1082                 WRN_MSG("calc_pll_params failed\n");
1083                 return 1;
1084         }
1085
1086         /* Check for overflow. */
1087         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1088                 return 1;
1089         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1090                 return 1;
1091         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1092                 return 1;
1093         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1094                 return 1;
1095         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1096                 return 1;
1097
1098         *dpll &= ~DPLL_P1_FORCE_DIV2;
1099         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1100                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1101
1102         if (IS_I9XX(dinfo)) {
1103                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1104                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1105         } else {
1106                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1107         }
1108
1109         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1110                (m1 << FP_M1_DIVISOR_SHIFT) |
1111                (m2 << FP_M2_DIVISOR_SHIFT);
1112         *fp1 = *fp0;
1113
1114         hw->dvob &= ~PORT_ENABLE;
1115         hw->dvoc &= ~PORT_ENABLE;
1116
1117         /* Use display plane A. */
1118         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1119         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1120         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1121         switch (intelfb_var_to_depth(var)) {
1122         case 8:
1123                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1124                 break;
1125         case 15:
1126                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1127                 break;
1128         case 16:
1129                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1130                 break;
1131         case 24:
1132                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1133                 break;
1134         }
1135         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1136         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1137
1138         /* Set CRTC registers. */
1139         hactive = var->xres;
1140         hsync_start = hactive + var->right_margin;
1141         hsync_end = hsync_start + var->hsync_len;
1142         htotal = hsync_end + var->left_margin;
1143         hblank_start = hactive;
1144         hblank_end = htotal;
1145
1146         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1147                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1148                 hblank_end);
1149
1150         vactive = var->yres;
1151         vsync_start = vactive + var->lower_margin;
1152         vsync_end = vsync_start + var->vsync_len;
1153         vtotal = vsync_end + var->upper_margin;
1154         vblank_start = vactive;
1155         vblank_end = vtotal;
1156         vblank_end = vsync_end + 1;
1157
1158         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1159                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1160                 vblank_end);
1161
1162         /* Adjust for register values, and check for overflow. */
1163         hactive--;
1164         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1165                 return 1;
1166         hsync_start--;
1167         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1168                 return 1;
1169         hsync_end--;
1170         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1171                 return 1;
1172         htotal--;
1173         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1174                 return 1;
1175         hblank_start--;
1176         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1177                 return 1;
1178         hblank_end--;
1179         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1180                 return 1;
1181
1182         vactive--;
1183         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1184                 return 1;
1185         vsync_start--;
1186         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1187                 return 1;
1188         vsync_end--;
1189         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1190                 return 1;
1191         vtotal--;
1192         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1193                 return 1;
1194         vblank_start--;
1195         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1196                 return 1;
1197         vblank_end--;
1198         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1199                 return 1;
1200
1201         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1202         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1203               (hblank_end << HSYNCEND_SHIFT);
1204         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1205
1206         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1207         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1208               (vblank_end << VSYNCEND_SHIFT);
1209         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1210         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1211               (vactive << SRC_SIZE_VERT_SHIFT);
1212
1213         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1214         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1215
1216         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1217                           var->xoffset * var->bits_per_pixel / 8;
1218
1219         hw->disp_a_base += dinfo->fb.offset << 12;
1220
1221         /* Check stride alignment. */
1222         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1223                 WRN_MSG("display stride %d has bad alignment %d\n",
1224                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1225                 return 1;
1226         }
1227
1228         /* Set the palette to 8-bit mode. */
1229         *pipe_conf &= ~PIPECONF_GAMMA;
1230         return 0;
1231 }
1232
1233 /* Program a (non-VGA) video mode. */
1234 int
1235 intelfbhw_program_mode(struct intelfb_info *dinfo,
1236                      const struct intelfb_hwstate *hw, int blank)
1237 {
1238         int pipe = PIPE_A;
1239         u32 tmp;
1240         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1241         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1242         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1243         u32 hsync_reg, htotal_reg, hblank_reg;
1244         u32 vsync_reg, vtotal_reg, vblank_reg;
1245         u32 src_size_reg;
1246         u32 count, tmp_val[3];
1247
1248         /* Assume single pipe, display plane A, analog CRT. */
1249
1250 #if VERBOSE > 0
1251         DBG_MSG("intelfbhw_program_mode\n");
1252 #endif
1253
1254         /* Disable VGA */
1255         tmp = INREG(VGACNTRL);
1256         tmp |= VGA_DISABLE;
1257         OUTREG(VGACNTRL, tmp);
1258
1259         /* Check whether pipe A or pipe B is enabled. */
1260         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1261                 pipe = PIPE_A;
1262         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1263                 pipe = PIPE_B;
1264
1265         dinfo->pipe = pipe;
1266
1267         if (pipe == PIPE_B) {
1268                 dpll = &hw->dpll_b;
1269                 fp0 = &hw->fpb0;
1270                 fp1 = &hw->fpb1;
1271                 pipe_conf = &hw->pipe_b_conf;
1272                 hs = &hw->hsync_b;
1273                 hb = &hw->hblank_b;
1274                 ht = &hw->htotal_b;
1275                 vs = &hw->vsync_b;
1276                 vb = &hw->vblank_b;
1277                 vt = &hw->vtotal_b;
1278                 ss = &hw->src_size_b;
1279                 dpll_reg = DPLL_B;
1280                 fp0_reg = FPB0;
1281                 fp1_reg = FPB1;
1282                 pipe_conf_reg = PIPEBCONF;
1283                 hsync_reg = HSYNC_B;
1284                 htotal_reg = HTOTAL_B;
1285                 hblank_reg = HBLANK_B;
1286                 vsync_reg = VSYNC_B;
1287                 vtotal_reg = VTOTAL_B;
1288                 vblank_reg = VBLANK_B;
1289                 src_size_reg = SRC_SIZE_B;
1290         } else {
1291                 dpll = &hw->dpll_a;
1292                 fp0 = &hw->fpa0;
1293                 fp1 = &hw->fpa1;
1294                 pipe_conf = &hw->pipe_a_conf;
1295                 hs = &hw->hsync_a;
1296                 hb = &hw->hblank_a;
1297                 ht = &hw->htotal_a;
1298                 vs = &hw->vsync_a;
1299                 vb = &hw->vblank_a;
1300                 vt = &hw->vtotal_a;
1301                 ss = &hw->src_size_a;
1302                 dpll_reg = DPLL_A;
1303                 fp0_reg = FPA0;
1304                 fp1_reg = FPA1;
1305                 pipe_conf_reg = PIPEACONF;
1306                 hsync_reg = HSYNC_A;
1307                 htotal_reg = HTOTAL_A;
1308                 hblank_reg = HBLANK_A;
1309                 vsync_reg = VSYNC_A;
1310                 vtotal_reg = VTOTAL_A;
1311                 vblank_reg = VBLANK_A;
1312                 src_size_reg = SRC_SIZE_A;
1313         }
1314
1315         /* turn off pipe */
1316         tmp = INREG(pipe_conf_reg);
1317         tmp &= ~PIPECONF_ENABLE;
1318         OUTREG(pipe_conf_reg, tmp);
1319
1320         count = 0;
1321         do {
1322                 tmp_val[count%3] = INREG(0x70000);
1323                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1324                         break;
1325                 count++;
1326                 udelay(1);
1327                 if (count % 200 == 0) {
1328                         tmp = INREG(pipe_conf_reg);
1329                         tmp &= ~PIPECONF_ENABLE;
1330                         OUTREG(pipe_conf_reg, tmp);
1331                 }
1332         } while(count < 2000);
1333
1334         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1335
1336         /* Disable planes A and B. */
1337         tmp = INREG(DSPACNTR);
1338         tmp &= ~DISPPLANE_PLANE_ENABLE;
1339         OUTREG(DSPACNTR, tmp);
1340         tmp = INREG(DSPBCNTR);
1341         tmp &= ~DISPPLANE_PLANE_ENABLE;
1342         OUTREG(DSPBCNTR, tmp);
1343
1344         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1345         mdelay(20);
1346
1347         /* Disable Sync */
1348         tmp = INREG(ADPA);
1349         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1350         tmp |= ADPA_DPMS_D3;
1351         OUTREG(ADPA, tmp);
1352
1353         /* do some funky magic - xyzzy */
1354         OUTREG(0x61204, 0xabcd0000);
1355
1356         /* turn off PLL */
1357         tmp = INREG(dpll_reg);
1358         dpll_reg &= ~DPLL_VCO_ENABLE;
1359         OUTREG(dpll_reg, tmp);
1360
1361         /* Set PLL parameters */
1362         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1363         OUTREG(fp0_reg, *fp0);
1364         OUTREG(fp1_reg, *fp1);
1365
1366         /* Enable PLL */
1367         tmp = INREG(dpll_reg);
1368         tmp |= DPLL_VCO_ENABLE;
1369         OUTREG(dpll_reg, tmp);
1370
1371         /* Set DVOs B/C */
1372         OUTREG(DVOB, hw->dvob);
1373         OUTREG(DVOC, hw->dvoc);
1374
1375         /* undo funky magic */
1376         OUTREG(0x61204, 0x00000000);
1377
1378         /* Set ADPA */
1379         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1380         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1381
1382         /* Set pipe parameters */
1383         OUTREG(hsync_reg, *hs);
1384         OUTREG(hblank_reg, *hb);
1385         OUTREG(htotal_reg, *ht);
1386         OUTREG(vsync_reg, *vs);
1387         OUTREG(vblank_reg, *vb);
1388         OUTREG(vtotal_reg, *vt);
1389         OUTREG(src_size_reg, *ss);
1390
1391         /* Enable pipe */
1392         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1393
1394         /* Enable sync */
1395         tmp = INREG(ADPA);
1396         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1397         tmp |= ADPA_DPMS_D0;
1398         OUTREG(ADPA, tmp);
1399
1400         /* setup display plane */
1401         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1402                 /*
1403                  *      i830M errata: the display plane must be enabled
1404                  *      to allow writes to the other bits in the plane
1405                  *      control register.
1406                  */
1407                 tmp = INREG(DSPACNTR);
1408                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1409                         tmp |= DISPPLANE_PLANE_ENABLE;
1410                         OUTREG(DSPACNTR, tmp);
1411                         OUTREG(DSPACNTR,
1412                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1413                         mdelay(1);
1414                 }
1415         }
1416
1417         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1418         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1419         OUTREG(DSPABASE, hw->disp_a_base);
1420
1421         /* Enable plane */
1422         if (!blank) {
1423                 tmp = INREG(DSPACNTR);
1424                 tmp |= DISPPLANE_PLANE_ENABLE;
1425                 OUTREG(DSPACNTR, tmp);
1426                 OUTREG(DSPABASE, hw->disp_a_base);
1427         }
1428
1429         return 0;
1430 }
1431
1432 /* forward declarations */
1433 static void refresh_ring(struct intelfb_info *dinfo);
1434 static void reset_state(struct intelfb_info *dinfo);
1435 static void do_flush(struct intelfb_info *dinfo);
1436
1437 static int
1438 wait_ring(struct intelfb_info *dinfo, int n)
1439 {
1440         int i = 0;
1441         unsigned long end;
1442         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1443
1444 #if VERBOSE > 0
1445         DBG_MSG("wait_ring: %d\n", n);
1446 #endif
1447
1448         end = jiffies + (HZ * 3);
1449         while (dinfo->ring_space < n) {
1450                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1451                                                    RING_HEAD_MASK);
1452                 if (dinfo->ring_tail + RING_MIN_FREE <
1453                     (u32 __iomem) dinfo->ring_head)
1454                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1455                                 - (dinfo->ring_tail + RING_MIN_FREE);
1456                 else
1457                         dinfo->ring_space = (dinfo->ring.size +
1458                                              (u32 __iomem) dinfo->ring_head)
1459                                 - (dinfo->ring_tail + RING_MIN_FREE);
1460                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1461                         end = jiffies + (HZ * 3);
1462                         last_head = (u32 __iomem) dinfo->ring_head;
1463                 }
1464                 i++;
1465                 if (time_before(end, jiffies)) {
1466                         if (!i) {
1467                                 /* Try again */
1468                                 reset_state(dinfo);
1469                                 refresh_ring(dinfo);
1470                                 do_flush(dinfo);
1471                                 end = jiffies + (HZ * 3);
1472                                 i = 1;
1473                         } else {
1474                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1475                                         dinfo->ring_space, n);
1476                                 WRN_MSG("lockup - turning off hardware "
1477                                         "acceleration\n");
1478                                 dinfo->ring_lockup = 1;
1479                                 break;
1480                         }
1481                 }
1482                 udelay(1);
1483         }
1484         return i;
1485 }
1486
1487 static void
1488 do_flush(struct intelfb_info *dinfo) {
1489         START_RING(2);
1490         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1491         OUT_RING(MI_NOOP);
1492         ADVANCE_RING();
1493 }
1494
1495 void
1496 intelfbhw_do_sync(struct intelfb_info *dinfo)
1497 {
1498 #if VERBOSE > 0
1499         DBG_MSG("intelfbhw_do_sync\n");
1500 #endif
1501
1502         if (!dinfo->accel)
1503                 return;
1504
1505         /*
1506          * Send a flush, then wait until the ring is empty.  This is what
1507          * the XFree86 driver does, and actually it doesn't seem a lot worse
1508          * than the recommended method (both have problems).
1509          */
1510         do_flush(dinfo);
1511         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1512         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1513 }
1514
1515 static void
1516 refresh_ring(struct intelfb_info *dinfo)
1517 {
1518 #if VERBOSE > 0
1519         DBG_MSG("refresh_ring\n");
1520 #endif
1521
1522         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1523                                            RING_HEAD_MASK);
1524         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1525         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1526                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1527                         - (dinfo->ring_tail + RING_MIN_FREE);
1528         else
1529                 dinfo->ring_space = (dinfo->ring.size +
1530                                      (u32 __iomem) dinfo->ring_head)
1531                         - (dinfo->ring_tail + RING_MIN_FREE);
1532 }
1533
1534 static void
1535 reset_state(struct intelfb_info *dinfo)
1536 {
1537         int i;
1538         u32 tmp;
1539
1540 #if VERBOSE > 0
1541         DBG_MSG("reset_state\n");
1542 #endif
1543
1544         for (i = 0; i < FENCE_NUM; i++)
1545                 OUTREG(FENCE + (i << 2), 0);
1546
1547         /* Flush the ring buffer if it's enabled. */
1548         tmp = INREG(PRI_RING_LENGTH);
1549         if (tmp & RING_ENABLE) {
1550 #if VERBOSE > 0
1551                 DBG_MSG("reset_state: ring was enabled\n");
1552 #endif
1553                 refresh_ring(dinfo);
1554                 intelfbhw_do_sync(dinfo);
1555                 DO_RING_IDLE();
1556         }
1557
1558         OUTREG(PRI_RING_LENGTH, 0);
1559         OUTREG(PRI_RING_HEAD, 0);
1560         OUTREG(PRI_RING_TAIL, 0);
1561         OUTREG(PRI_RING_START, 0);
1562 }
1563
1564 /* Stop the 2D engine, and turn off the ring buffer. */
1565 void
1566 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1567 {
1568 #if VERBOSE > 0
1569         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1570                 dinfo->ring_active);
1571 #endif
1572
1573         if (!dinfo->accel)
1574                 return;
1575
1576         dinfo->ring_active = 0;
1577         reset_state(dinfo);
1578 }
1579
1580 /*
1581  * Enable the ring buffer, and initialise the 2D engine.
1582  * It is assumed that the graphics engine has been stopped by previously
1583  * calling intelfb_2d_stop().
1584  */
1585 void
1586 intelfbhw_2d_start(struct intelfb_info *dinfo)
1587 {
1588 #if VERBOSE > 0
1589         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1590                 dinfo->accel, dinfo->ring_active);
1591 #endif
1592
1593         if (!dinfo->accel)
1594                 return;
1595
1596         /* Initialise the primary ring buffer. */
1597         OUTREG(PRI_RING_LENGTH, 0);
1598         OUTREG(PRI_RING_TAIL, 0);
1599         OUTREG(PRI_RING_HEAD, 0);
1600
1601         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1602         OUTREG(PRI_RING_LENGTH,
1603                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1604                 RING_NO_REPORT | RING_ENABLE);
1605         refresh_ring(dinfo);
1606         dinfo->ring_active = 1;
1607 }
1608
1609 /* 2D fillrect (solid fill or invert) */
1610 void
1611 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1612                       u32 color, u32 pitch, u32 bpp, u32 rop)
1613 {
1614         u32 br00, br09, br13, br14, br16;
1615
1616 #if VERBOSE > 0
1617         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1618                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1619 #endif
1620
1621         br00 = COLOR_BLT_CMD;
1622         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1623         br13 = (rop << ROP_SHIFT) | pitch;
1624         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1625         br16 = color;
1626
1627         switch (bpp) {
1628         case 8:
1629                 br13 |= COLOR_DEPTH_8;
1630                 break;
1631         case 16:
1632                 br13 |= COLOR_DEPTH_16;
1633                 break;
1634         case 32:
1635                 br13 |= COLOR_DEPTH_32;
1636                 br00 |= WRITE_ALPHA | WRITE_RGB;
1637                 break;
1638         }
1639
1640         START_RING(6);
1641         OUT_RING(br00);
1642         OUT_RING(br13);
1643         OUT_RING(br14);
1644         OUT_RING(br09);
1645         OUT_RING(br16);
1646         OUT_RING(MI_NOOP);
1647         ADVANCE_RING();
1648
1649 #if VERBOSE > 0
1650         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1651                 dinfo->ring_tail, dinfo->ring_space);
1652 #endif
1653 }
1654
1655 void
1656 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1657                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1658 {
1659         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1660
1661 #if VERBOSE > 0
1662         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1663                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1664 #endif
1665
1666         br00 = XY_SRC_COPY_BLT_CMD;
1667         br09 = dinfo->fb_start;
1668         br11 = (pitch << PITCH_SHIFT);
1669         br12 = dinfo->fb_start;
1670         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1671         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1672         br23 = ((dstx + w) << WIDTH_SHIFT) |
1673                ((dsty + h) << HEIGHT_SHIFT);
1674         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1675
1676         switch (bpp) {
1677         case 8:
1678                 br13 |= COLOR_DEPTH_8;
1679                 break;
1680         case 16:
1681                 br13 |= COLOR_DEPTH_16;
1682                 break;
1683         case 32:
1684                 br13 |= COLOR_DEPTH_32;
1685                 br00 |= WRITE_ALPHA | WRITE_RGB;
1686                 break;
1687         }
1688
1689         START_RING(8);
1690         OUT_RING(br00);
1691         OUT_RING(br13);
1692         OUT_RING(br22);
1693         OUT_RING(br23);
1694         OUT_RING(br09);
1695         OUT_RING(br26);
1696         OUT_RING(br11);
1697         OUT_RING(br12);
1698         ADVANCE_RING();
1699 }
1700
1701 int
1702 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1703                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1704 {
1705         int nbytes, ndwords, pad, tmp;
1706         u32 br00, br09, br13, br18, br19, br22, br23;
1707         int dat, ix, iy, iw;
1708         int i, j;
1709
1710 #if VERBOSE > 0
1711         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1712 #endif
1713
1714         /* size in bytes of a padded scanline */
1715         nbytes = ROUND_UP_TO(w, 16) / 8;
1716
1717         /* Total bytes of padded scanline data to write out. */
1718         nbytes = nbytes * h;
1719
1720         /*
1721          * Check if the glyph data exceeds the immediate mode limit.
1722          * It would take a large font (1K pixels) to hit this limit.
1723          */
1724         if (nbytes > MAX_MONO_IMM_SIZE)
1725                 return 0;
1726
1727         /* Src data is packaged a dword (32-bit) at a time. */
1728         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1729
1730         /*
1731          * Ring has to be padded to a quad word. But because the command starts
1732            with 7 bytes, pad only if there is an even number of ndwords
1733          */
1734         pad = !(ndwords % 2);
1735
1736         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1737         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1738         br09 = dinfo->fb_start;
1739         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1740         br18 = bg;
1741         br19 = fg;
1742         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1743         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1744
1745         switch (bpp) {
1746         case 8:
1747                 br13 |= COLOR_DEPTH_8;
1748                 break;
1749         case 16:
1750                 br13 |= COLOR_DEPTH_16;
1751                 break;
1752         case 32:
1753                 br13 |= COLOR_DEPTH_32;
1754                 br00 |= WRITE_ALPHA | WRITE_RGB;
1755                 break;
1756         }
1757
1758         START_RING(8 + ndwords);
1759         OUT_RING(br00);
1760         OUT_RING(br13);
1761         OUT_RING(br22);
1762         OUT_RING(br23);
1763         OUT_RING(br09);
1764         OUT_RING(br18);
1765         OUT_RING(br19);
1766         ix = iy = 0;
1767         iw = ROUND_UP_TO(w, 8) / 8;
1768         while (ndwords--) {
1769                 dat = 0;
1770                 for (j = 0; j < 2; ++j) {
1771                         for (i = 0; i < 2; ++i) {
1772                                 if (ix != iw || i == 0)
1773                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1774                         }
1775                         if (ix == iw && iy != (h-1)) {
1776                                 ix = 0;
1777                                 ++iy;
1778                         }
1779                 }
1780                 OUT_RING(dat);
1781         }
1782         if (pad)
1783                 OUT_RING(MI_NOOP);
1784         ADVANCE_RING();
1785
1786         return 1;
1787 }
1788
1789 /* HW cursor functions. */
1790 void
1791 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1792 {
1793         u32 tmp;
1794
1795 #if VERBOSE > 0
1796         DBG_MSG("intelfbhw_cursor_init\n");
1797 #endif
1798
1799         if (dinfo->mobile || IS_I9XX(dinfo)) {
1800                 if (!dinfo->cursor.physical)
1801                         return;
1802                 tmp = INREG(CURSOR_A_CONTROL);
1803                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1804                          CURSOR_MEM_TYPE_LOCAL |
1805                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1806                 tmp |= CURSOR_MODE_DISABLE;
1807                 OUTREG(CURSOR_A_CONTROL, tmp);
1808                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1809         } else {
1810                 tmp = INREG(CURSOR_CONTROL);
1811                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1812                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1813                 tmp = CURSOR_FORMAT_3C;
1814                 OUTREG(CURSOR_CONTROL, tmp);
1815                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1816                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1817                       (64 << CURSOR_SIZE_V_SHIFT);
1818                 OUTREG(CURSOR_SIZE, tmp);
1819         }
1820 }
1821
1822 void
1823 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1824 {
1825         u32 tmp;
1826
1827 #if VERBOSE > 0
1828         DBG_MSG("intelfbhw_cursor_hide\n");
1829 #endif
1830
1831         dinfo->cursor_on = 0;
1832         if (dinfo->mobile || IS_I9XX(dinfo)) {
1833                 if (!dinfo->cursor.physical)
1834                         return;
1835                 tmp = INREG(CURSOR_A_CONTROL);
1836                 tmp &= ~CURSOR_MODE_MASK;
1837                 tmp |= CURSOR_MODE_DISABLE;
1838                 OUTREG(CURSOR_A_CONTROL, tmp);
1839                 /* Flush changes */
1840                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1841         } else {
1842                 tmp = INREG(CURSOR_CONTROL);
1843                 tmp &= ~CURSOR_ENABLE;
1844                 OUTREG(CURSOR_CONTROL, tmp);
1845         }
1846 }
1847
1848 void
1849 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1850 {
1851         u32 tmp;
1852
1853 #if VERBOSE > 0
1854         DBG_MSG("intelfbhw_cursor_show\n");
1855 #endif
1856
1857         dinfo->cursor_on = 1;
1858
1859         if (dinfo->cursor_blanked)
1860                 return;
1861
1862         if (dinfo->mobile || IS_I9XX(dinfo)) {
1863                 if (!dinfo->cursor.physical)
1864                         return;
1865                 tmp = INREG(CURSOR_A_CONTROL);
1866                 tmp &= ~CURSOR_MODE_MASK;
1867                 tmp |= CURSOR_MODE_64_4C_AX;
1868                 OUTREG(CURSOR_A_CONTROL, tmp);
1869                 /* Flush changes */
1870                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1871         } else {
1872                 tmp = INREG(CURSOR_CONTROL);
1873                 tmp |= CURSOR_ENABLE;
1874                 OUTREG(CURSOR_CONTROL, tmp);
1875         }
1876 }
1877
1878 void
1879 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1880 {
1881         u32 tmp;
1882
1883 #if VERBOSE > 0
1884         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1885 #endif
1886
1887         /*
1888          * Sets the position. The coordinates are assumed to already
1889          * have any offset adjusted. Assume that the cursor is never
1890          * completely off-screen, and that x, y are always >= 0.
1891          */
1892
1893         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1894               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1895         OUTREG(CURSOR_A_POSITION, tmp);
1896
1897         if (IS_I9XX(dinfo)) {
1898                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1899         }
1900 }
1901
1902 void
1903 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1904 {
1905 #if VERBOSE > 0
1906         DBG_MSG("intelfbhw_cursor_setcolor\n");
1907 #endif
1908
1909         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1910         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1911         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1912         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1913 }
1914
1915 void
1916 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1917                       u8 *data)
1918 {
1919         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1920         int i, j, w = width / 8;
1921         int mod = width % 8, t_mask, d_mask;
1922
1923 #if VERBOSE > 0
1924         DBG_MSG("intelfbhw_cursor_load\n");
1925 #endif
1926
1927         if (!dinfo->cursor.virtual)
1928                 return;
1929
1930         t_mask = 0xff >> mod;
1931         d_mask = ~(0xff >> mod);
1932         for (i = height; i--; ) {
1933                 for (j = 0; j < w; j++) {
1934                         writeb(0x00, addr + j);
1935                         writeb(*(data++), addr + j+8);
1936                 }
1937                 if (mod) {
1938                         writeb(t_mask, addr + j);
1939                         writeb(*(data++) & d_mask, addr + j+8);
1940                 }
1941                 addr += 16;
1942         }
1943 }
1944
1945 void
1946 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1947         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1948         int i, j;
1949
1950 #if VERBOSE > 0
1951         DBG_MSG("intelfbhw_cursor_reset\n");
1952 #endif
1953
1954         if (!dinfo->cursor.virtual)
1955                 return;
1956
1957         for (i = 64; i--; ) {
1958                 for (j = 0; j < 8; j++) {
1959                         writeb(0xff, addr + j+0);
1960                         writeb(0x00, addr + j+8);
1961                 }
1962                 addr += 16;
1963         }
1964 }