SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/errno.h>
  25 #include <linux/string.h>
  26 #include <linux/mm.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/ioport.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/pagemap.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38
  39 #include "intelfb.h"
  40 #include "intelfbhw.h"
  41
  42 struct pll_min_max {
  43         int min_m, max_m, min_m1, max_m1;
  44         int min_m2, max_m2, min_n, max_n;
  45         int min_p, max_p, min_p1, max_p1;
  46         int min_vco, max_vco, p_transition_clk, ref_clk;
  47         int p_inc_lo, p_inc_hi;
  48 };
  49
  50 #define PLLS_I8xx 0
  51 #define PLLS_I9xx 1
  52 #define PLLS_MAX 2
  53
  54 static struct pll_min_max plls[PLLS_MAX] = {
  55         { 108, 140, 18, 26,
  56           6, 16, 3, 16,
  57           4, 128, 0, 31,
  58           930000, 1400000, 165000, 48000,
  59           4, 2 },               /* I8xx */
  60
  61         { 75, 120, 10, 20,
  62           5, 9, 4, 7,
  63           5, 80, 1, 8,
  64           1400000, 2800000, 200000, 96000,
  65           10, 5 }               /* I9xx */
  66 };
  67
  68 int intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  69 {
  70         u32 tmp;
  71         if (!pdev || !dinfo)
  72                 return 1;
  73
  74         switch (pdev->device) {
  75         case PCI_DEVICE_ID_INTEL_830M:
  76                 dinfo->name = "Intel(R) 830M";
  77                 dinfo->chipset = INTEL_830M;
  78                 dinfo->mobile = 1;
  79                 dinfo->pll_index = PLLS_I8xx;
  80                 return 0;
  81         case PCI_DEVICE_ID_INTEL_845G:
  82                 dinfo->name = "Intel(R) 845G";
  83                 dinfo->chipset = INTEL_845G;
  84                 dinfo->mobile = 0;
  85                 dinfo->pll_index = PLLS_I8xx;
  86                 return 0;
  87         case PCI_DEVICE_ID_INTEL_85XGM:
  88                 tmp = 0;
  89                 dinfo->mobile = 1;
  90                 dinfo->pll_index = PLLS_I8xx;
  91                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  92                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  93                         INTEL_85X_VARIANT_MASK) {
  94                 case INTEL_VAR_855GME:
  95                         dinfo->name = "Intel(R) 855GME";
  96                         dinfo->chipset = INTEL_855GME;
  97                         return 0;
  98                 case INTEL_VAR_855GM:
  99                         dinfo->name = "Intel(R) 855GM";
 100                         dinfo->chipset = INTEL_855GM;
 101                         return 0;
 102                 case INTEL_VAR_852GME:
 103                         dinfo->name = "Intel(R) 852GME";
 104                         dinfo->chipset = INTEL_852GME;
 105                         return 0;
 106                 case INTEL_VAR_852GM:
 107                         dinfo->name = "Intel(R) 852GM";
 108                         dinfo->chipset = INTEL_852GM;
 109                         return 0;
 110                 default:
 111                         dinfo->name = "Intel(R) 852GM/855GM";
 112                         dinfo->chipset = INTEL_85XGM;
 113                         return 0;
 114                 }
 115                 break;
 116         case PCI_DEVICE_ID_INTEL_865G:
 117                 dinfo->name = "Intel(R) 865G";
 118                 dinfo->chipset = INTEL_865G;
 119                 dinfo->mobile = 0;
 120                 dinfo->pll_index = PLLS_I8xx;
 121                 return 0;
 122         case PCI_DEVICE_ID_INTEL_915G:
 123                 dinfo->name = "Intel(R) 915G";
 124                 dinfo->chipset = INTEL_915G;
 125                 dinfo->mobile = 0;
 126                 dinfo->pll_index = PLLS_I9xx;
 127                 return 0;
 128         case PCI_DEVICE_ID_INTEL_915GM:
 129                 dinfo->name = "Intel(R) 915GM";
 130                 dinfo->chipset = INTEL_915GM;
 131                 dinfo->mobile = 1;
 132                 dinfo->pll_index = PLLS_I9xx;
 133                 return 0;
 134         case PCI_DEVICE_ID_INTEL_945G:
 135                 dinfo->name = "Intel(R) 945G";
 136                 dinfo->chipset = INTEL_945G;
 137                 dinfo->mobile = 0;
 138                 dinfo->pll_index = PLLS_I9xx;
 139                 return 0;
 140         case PCI_DEVICE_ID_INTEL_945GM:
 141                 dinfo->name = "Intel(R) 945GM";
 142                 dinfo->chipset = INTEL_945GM;
 143                 dinfo->mobile = 1;
 144                 dinfo->pll_index = PLLS_I9xx;
 145                 return 0;
 146         default:
 147                 return 1;
 148         }
 149 }
 150
 151 int intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 152                          int *stolen_size)
 153 {
 154         struct pci_dev *bridge_dev;
 155         u16 tmp;
 156         int stolen_overhead;
 157
 158         if (!pdev || !aperture_size || !stolen_size)
 159                 return 1;
 160
 161         /* Find the bridge device.  It is always 0:0.0 */
 162         if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
 163                 ERR_MSG("cannot find bridge device\n");
 164                 return 1;
 165         }
 166
 167         /* Get the fb aperture size and "stolen" memory amount. */
 168         tmp = 0;
 169         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 170         pci_dev_put(bridge_dev);
 171
 172         switch (pdev->device) {
 173         case PCI_DEVICE_ID_INTEL_915G:
 174         case PCI_DEVICE_ID_INTEL_915GM:
 175         case PCI_DEVICE_ID_INTEL_945G:
 176         case PCI_DEVICE_ID_INTEL_945GM:
 177                 /* 915 and 945 chipsets support a 256MB aperture.
 178                    Aperture size is determined by inspected the
 179                    base address of the aperture. */
 180                 if (pci_resource_start(pdev, 2) & 0x08000000)
 181                         *aperture_size = MB(128);
 182                 else
 183                         *aperture_size = MB(256);
 184                 break;
 185         default:
 186                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 187                         *aperture_size = MB(64);
 188                 else
 189                         *aperture_size = MB(128);
 190                 break;
 191         }
 192
 193         /* Stolen memory size is reduced by the GTT and the popup.
 194            GTT is 1K per MB of aperture size, and popup is 4K. */
 195         stolen_overhead = (*aperture_size / MB(1)) + 4;
 196         switch(pdev->device) {
 197         case PCI_DEVICE_ID_INTEL_830M:
 198         case PCI_DEVICE_ID_INTEL_845G:
 199                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 200                 case INTEL_830_GMCH_GMS_STOLEN_512:
 201                         *stolen_size = KB(512) - KB(stolen_overhead);
 202                         return 0;
 203                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 204                         *stolen_size = MB(1) - KB(stolen_overhead);
 205                         return 0;
 206                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 207                         *stolen_size = MB(8) - KB(stolen_overhead);
 208                         return 0;
 209                 case INTEL_830_GMCH_GMS_LOCAL:
 210                         ERR_MSG("only local memory found\n");
 211                         return 1;
 212                 case INTEL_830_GMCH_GMS_DISABLED:
 213                         ERR_MSG("video memory is disabled\n");
 214                         return 1;
 215                 default:
 216                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 217                                 tmp & INTEL_830_GMCH_GMS_MASK);
 218                         return 1;
 219                 }
 220                 break;
 221         default:
 222                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 223                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 224                         *stolen_size = MB(1) - KB(stolen_overhead);
 225                         return 0;
 226                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 227                         *stolen_size = MB(4) - KB(stolen_overhead);
 228                         return 0;
 229                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 230                         *stolen_size = MB(8) - KB(stolen_overhead);
 231                         return 0;
 232                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 233                         *stolen_size = MB(16) - KB(stolen_overhead);
 234                         return 0;
 235                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 236                         *stolen_size = MB(32) - KB(stolen_overhead);
 237                         return 0;
 238                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 239                         *stolen_size = MB(48) - KB(stolen_overhead);
 240                         return 0;
 241                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 242                         *stolen_size = MB(64) - KB(stolen_overhead);
 243                         return 0;
 244                 case INTEL_855_GMCH_GMS_DISABLED:
 245                         ERR_MSG("video memory is disabled\n");
 246                         return 0;
 247                 default:
 248                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 249                                 tmp & INTEL_855_GMCH_GMS_MASK);
 250                         return 1;
 251                 }
 252         }
 253 }
 254
 255 int intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 256 {
 257         int dvo = 0;
 258
 259         if (INREG(LVDS) & PORT_ENABLE)
 260                 dvo |= LVDS_PORT;
 261         if (INREG(DVOA) & PORT_ENABLE)
 262                 dvo |= DVOA_PORT;
 263         if (INREG(DVOB) & PORT_ENABLE)
 264                 dvo |= DVOB_PORT;
 265         if (INREG(DVOC) & PORT_ENABLE)
 266                 dvo |= DVOC_PORT;
 267
 268         return dvo;
 269 }
 270
 271 const char * intelfbhw_dvo_to_string(int dvo)
 272 {
 273         if (dvo & DVOA_PORT)
 274                 return "DVO port A";
 275         else if (dvo & DVOB_PORT)
 276                 return "DVO port B";
 277         else if (dvo & DVOC_PORT)
 278                 return "DVO port C";
 279         else if (dvo & LVDS_PORT)
 280                 return "LVDS port";
 281         else
 282                 return NULL;
 283 }
 284
 285
 286 int intelfbhw_validate_mode(struct intelfb_info *dinfo,
 287                             struct fb_var_screeninfo *var)
 288 {
 289         int bytes_per_pixel;
 290         int tmp;
 291
 292 #if VERBOSE > 0
 293         DBG_MSG("intelfbhw_validate_mode\n");
 294 #endif
 295
 296         bytes_per_pixel = var->bits_per_pixel / 8;
 297         if (bytes_per_pixel == 3)
 298                 bytes_per_pixel = 4;
 299
 300         /* Check if enough video memory. */
 301         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 302         if (tmp > dinfo->fb.size) {
 303                 WRN_MSG("Not enough video ram for mode "
 304                         "(%d KByte vs %d KByte).\n",
 305                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 306                 return 1;
 307         }
 308
 309         /* Check if x/y limits are OK. */
 310         if (var->xres - 1 > HACTIVE_MASK) {
 311                 WRN_MSG("X resolution too large (%d vs %d).\n",
 312                         var->xres, HACTIVE_MASK + 1);
 313                 return 1;
 314         }
 315         if (var->yres - 1 > VACTIVE_MASK) {
 316                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 317                         var->yres, VACTIVE_MASK + 1);
 318                 return 1;
 319         }
 320
 321         /* Check for doublescan modes. */
 322         if (var->vmode & FB_VMODE_DOUBLE) {
 323                 WRN_MSG("Mode is double-scan.\n");
 324                 return 1;
 325         }
 326
 327         /* Check if clock is OK. */
 328         tmp = 1000000000 / var->pixclock;
 329         if (tmp < MIN_CLOCK) {
 330                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 331                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 332                 return 1;
 333         }
 334         if (tmp > MAX_CLOCK) {
 335                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 336                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 337                 return 1;
 338         }
 339
 340         return 0;
 341 }
 342
 343 int intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 344 {
 345         struct intelfb_info *dinfo = GET_DINFO(info);
 346         u32 offset, xoffset, yoffset;
 347
 348 #if VERBOSE > 0
 349         DBG_MSG("intelfbhw_pan_display\n");
 350 #endif
 351
 352         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 353         yoffset = var->yoffset;
 354
 355         if ((xoffset + var->xres > var->xres_virtual) ||
 356             (yoffset + var->yres > var->yres_virtual))
 357                 return -EINVAL;
 358
 359         offset = (yoffset * dinfo->pitch) +
 360                  (xoffset * var->bits_per_pixel) / 8;
 361
 362         offset += dinfo->fb.offset << 12;
 363
 364         dinfo->vsync.pan_offset = offset;
 365         if ((var->activate & FB_ACTIVATE_VBL) &&
 366             !intelfbhw_enable_irq(dinfo, 0))
 367                 dinfo->vsync.pan_display = 1;
 368         else {
 369                 dinfo->vsync.pan_display = 0;
 370                 OUTREG(DSPABASE, offset);
 371         }
 372
 373         return 0;
 374 }
 375
 376 /* Blank the screen. */
 377 void intelfbhw_do_blank(int blank, struct fb_info *info)
 378 {
 379         struct intelfb_info *dinfo = GET_DINFO(info);
 380         u32 tmp;
 381
 382 #if VERBOSE > 0
 383         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 384 #endif
 385
 386         /* Turn plane A on or off */
 387         tmp = INREG(DSPACNTR);
 388         if (blank)
 389                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 390         else
 391                 tmp |= DISPPLANE_PLANE_ENABLE;
 392         OUTREG(DSPACNTR, tmp);
 393         /* Flush */
 394         tmp = INREG(DSPABASE);
 395         OUTREG(DSPABASE, tmp);
 396
 397         /* Turn off/on the HW cursor */
 398 #if VERBOSE > 0
 399         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 400 #endif
 401         if (dinfo->cursor_on) {
 402                 if (blank)
 403                         intelfbhw_cursor_hide(dinfo);
 404                 else
 405                         intelfbhw_cursor_show(dinfo);
 406                 dinfo->cursor_on = 1;
 407         }
 408         dinfo->cursor_blanked = blank;
 409
 410         /* Set DPMS level */
 411         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 412         switch (blank) {
 413         case FB_BLANK_UNBLANK:
 414         case FB_BLANK_NORMAL:
 415                 tmp |= ADPA_DPMS_D0;
 416                 break;
 417         case FB_BLANK_VSYNC_SUSPEND:
 418                 tmp |= ADPA_DPMS_D1;
 419                 break;
 420         case FB_BLANK_HSYNC_SUSPEND:
 421                 tmp |= ADPA_DPMS_D2;
 422                 break;
 423         case FB_BLANK_POWERDOWN:
 424                 tmp |= ADPA_DPMS_D3;
 425                 break;
 426         }
 427         OUTREG(ADPA, tmp);
 428
 429         return;
 430 }
 431
 432
 433 void intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 434                          unsigned red, unsigned green, unsigned blue,
 435                          unsigned transp)
 436 {
 437         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 438                           PALETTE_A : PALETTE_B;
 439
 440 #if VERBOSE > 0
 441         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 442                 regno, red, green, blue);
 443 #endif
 444
 445         OUTREG(palette_reg + (regno << 2),
 446                (red << PALETTE_8_RED_SHIFT) |
 447                (green << PALETTE_8_GREEN_SHIFT) |
 448                (blue << PALETTE_8_BLUE_SHIFT));
 449 }
 450
 451
 452 int intelfbhw_read_hw_state(struct intelfb_info *dinfo,
 453                             struct intelfb_hwstate *hw, int flag)
 454 {
 455         int i;
 456
 457 #if VERBOSE > 0
 458         DBG_MSG("intelfbhw_read_hw_state\n");
 459 #endif
 460
 461         if (!hw || !dinfo)
 462                 return -1;
 463
 464         /* Read in as much of the HW state as possible. */
 465         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 466         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 467         hw->vga_pd = INREG(VGAPD);
 468         hw->dpll_a = INREG(DPLL_A);
 469         hw->dpll_b = INREG(DPLL_B);
 470         hw->fpa0 = INREG(FPA0);
 471         hw->fpa1 = INREG(FPA1);
 472         hw->fpb0 = INREG(FPB0);
 473         hw->fpb1 = INREG(FPB1);
 474
 475         if (flag == 1)
 476                 return flag;
 477
 478 #if 0
 479         /* This seems to be a problem with the 852GM/855GM */
 480         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 481                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 482                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 483         }
 484 #endif
 485
 486         if (flag == 2)
 487                 return flag;
 488
 489         hw->htotal_a = INREG(HTOTAL_A);
 490         hw->hblank_a = INREG(HBLANK_A);
 491         hw->hsync_a = INREG(HSYNC_A);
 492         hw->vtotal_a = INREG(VTOTAL_A);
 493         hw->vblank_a = INREG(VBLANK_A);
 494         hw->vsync_a = INREG(VSYNC_A);
 495         hw->src_size_a = INREG(SRC_SIZE_A);
 496         hw->bclrpat_a = INREG(BCLRPAT_A);
 497         hw->htotal_b = INREG(HTOTAL_B);
 498         hw->hblank_b = INREG(HBLANK_B);
 499         hw->hsync_b = INREG(HSYNC_B);
 500         hw->vtotal_b = INREG(VTOTAL_B);
 501         hw->vblank_b = INREG(VBLANK_B);
 502         hw->vsync_b = INREG(VSYNC_B);
 503         hw->src_size_b = INREG(SRC_SIZE_B);
 504         hw->bclrpat_b = INREG(BCLRPAT_B);
 505
 506         if (flag == 3)
 507                 return flag;
 508
 509         hw->adpa = INREG(ADPA);
 510         hw->dvoa = INREG(DVOA);
 511         hw->dvob = INREG(DVOB);
 512         hw->dvoc = INREG(DVOC);
 513         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 514         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 515         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 516         hw->lvds = INREG(LVDS);
 517
 518         if (flag == 4)
 519                 return flag;
 520
 521         hw->pipe_a_conf = INREG(PIPEACONF);
 522         hw->pipe_b_conf = INREG(PIPEBCONF);
 523         hw->disp_arb = INREG(DISPARB);
 524
 525         if (flag == 5)
 526                 return flag;
 527
 528         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 529         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 530         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 531         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 532
 533         if (flag == 6)
 534                 return flag;
 535
 536         for (i = 0; i < 4; i++) {
 537                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 538                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 539         }
 540
 541         if (flag == 7)
 542                 return flag;
 543
 544         hw->cursor_size = INREG(CURSOR_SIZE);
 545
 546         if (flag == 8)
 547                 return flag;
 548
 549         hw->disp_a_ctrl = INREG(DSPACNTR);
 550         hw->disp_b_ctrl = INREG(DSPBCNTR);
 551         hw->disp_a_base = INREG(DSPABASE);
 552         hw->disp_b_base = INREG(DSPBBASE);
 553         hw->disp_a_stride = INREG(DSPASTRIDE);
 554         hw->disp_b_stride = INREG(DSPBSTRIDE);
 555
 556         if (flag == 9)
 557                 return flag;
 558
 559         hw->vgacntrl = INREG(VGACNTRL);
 560
 561         if (flag == 10)
 562                 return flag;
 563
 564         hw->add_id = INREG(ADD_ID);
 565
 566         if (flag == 11)
 567                 return flag;
 568
 569         for (i = 0; i < 7; i++) {
 570                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 571                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 572                 if (i < 3)
 573                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 574         }
 575
 576         for (i = 0; i < 8; i++)
 577                 hw->fence[i] = INREG(FENCE + (i << 2));
 578
 579         hw->instpm = INREG(INSTPM);
 580         hw->mem_mode = INREG(MEM_MODE);
 581         hw->fw_blc_0 = INREG(FW_BLC_0);
 582         hw->fw_blc_1 = INREG(FW_BLC_1);
 583
 584         hw->hwstam = INREG16(HWSTAM);
 585         hw->ier = INREG16(IER);
 586         hw->iir = INREG16(IIR);
 587         hw->imr = INREG16(IMR);
 588
 589         return 0;
 590 }
 591
 592
 593 static int calc_vclock3(int index, int m, int n, int p)
 594 {
 595         if (p == 0 || n == 0)
 596                 return 0;
 597         return plls[index].ref_clk * m / n / p;
 598 }
 599
 600 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2,
 601                        int lvds)
 602 {
 603         struct pll_min_max *pll = &plls[index];
 604         u32 m, vco, p;
 605
 606         m = (5 * (m1 + 2)) + (m2 + 2);
 607         n += 2;
 608         vco = pll->ref_clk * m / n;
 609
 610         if (index == PLLS_I8xx)
 611                 p = ((p1 + 2) * (1 << (p2 + 1)));
 612         else
 613                 p = ((p1) * (p2 ? 5 : 10));
 614         return vco / p;
 615 }
 616
 617 #if REGDUMP
 618 static void intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll,
 619                                int *o_p1, int *o_p2)
 620 {
 621         int p1, p2;
 622
 623         if (IS_I9XX(dinfo)) {
 624                 if (dpll & DPLL_P1_FORCE_DIV2)
 625                         p1 = 1;
 626                 else
 627                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 628
 629                 p1 = ffs(p1);
 630
 631                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 632         } else {
 633                 if (dpll & DPLL_P1_FORCE_DIV2)
 634                         p1 = 0;
 635                 else
 636                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 637                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 638         }
 639
 640         *o_p1 = p1;
 641         *o_p2 = p2;
 642 }
 643 #endif
 644
 645
 646 void intelfbhw_print_hw_state(struct intelfb_info *dinfo,
 647                               struct intelfb_hwstate *hw)
 648 {
 649 #if REGDUMP
 650         int i, m1, m2, n, p1, p2;
 651         int index = dinfo->pll_index;
 652         DBG_MSG("intelfbhw_print_hw_state\n");
 653
 654         if (!hw)
 655                 return;
 656         /* Read in as much of the HW state as possible. */
 657         printk("hw state dump start\n");
 658         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 659         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 660         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 661         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 662         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 663         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 664
 665         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 666
 667         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 668                m1, m2, n, p1, p2);
 669         printk("        VGA0: clock is %d\n",
 670                calc_vclock(index, m1, m2, n, p1, p2, 0));
 671
 672         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 673         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 674         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 675
 676         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 677         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 678                m1, m2, n, p1, p2);
 679         printk("        VGA1: clock is %d\n",
 680                calc_vclock(index, m1, m2, n, p1, p2, 0));
 681
 682         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 683         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 684         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 685         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 686         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 687         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 688
 689         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 690         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 691         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 692
 693         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 694
 695         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 696                m1, m2, n, p1, p2);
 697         printk("        PLLA0: clock is %d\n",
 698                calc_vclock(index, m1, m2, n, p1, p2, 0));
 699
 700         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 701         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 702         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 703
 704         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 705
 706         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 707                m1, m2, n, p1, p2);
 708         printk("        PLLA1: clock is %d\n",
 709                calc_vclock(index, m1, m2, n, p1, p2, 0));
 710
 711 #if 0
 712         printk("        PALETTE_A:\n");
 713         for (i = 0; i < PALETTE_8_ENTRIES)
 714                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 715         printk("        PALETTE_B:\n");
 716         for (i = 0; i < PALETTE_8_ENTRIES)
 717                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 718 #endif
 719
 720         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 721         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 722         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 723         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 724         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 725         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 726         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 727         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 728         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 729         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 730         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 731         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 732         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 733         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 734         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 735         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 736
 737         printk("        ADPA:                   0x%08x\n", hw->adpa);
 738         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 739         printk("        DVOB:                   0x%08x\n", hw->dvob);
 740         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 741         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 742         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 743         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 744         printk("        LVDS:                   0x%08x\n", hw->lvds);
 745
 746         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 747         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 748         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 749
 750         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 751         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 752         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 753         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 754
 755         printk("        CURSOR_A_PALETTE:       ");
 756         for (i = 0; i < 4; i++) {
 757                 printk("0x%08x", hw->cursor_a_palette[i]);
 758                 if (i < 3)
 759                         printk(", ");
 760         }
 761         printk("\n");
 762         printk("        CURSOR_B_PALETTE:       ");
 763         for (i = 0; i < 4; i++) {
 764                 printk("0x%08x", hw->cursor_b_palette[i]);
 765                 if (i < 3)
 766                         printk(", ");
 767         }
 768         printk("\n");
 769
 770         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 771
 772         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 773         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 774         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 775         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 776         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 777         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 778
 779         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 780         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 781
 782         for (i = 0; i < 7; i++) {
 783                 printk("        SWF0%d                  0x%08x\n", i,
 784                         hw->swf0x[i]);
 785         }
 786         for (i = 0; i < 7; i++) {
 787                 printk("        SWF1%d                  0x%08x\n", i,
 788                         hw->swf1x[i]);
 789         }
 790         for (i = 0; i < 3; i++) {
 791                 printk("        SWF3%d                  0x%08x\n", i,
 792                        hw->swf3x[i]);
 793         }
 794         for (i = 0; i < 8; i++)
 795                 printk("        FENCE%d                 0x%08x\n", i,
 796                        hw->fence[i]);
 797
 798         printk("        INSTPM                  0x%08x\n", hw->instpm);
 799         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 800         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 801         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 802
 803         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 804         printk("        IER                     0x%04x\n", hw->ier);
 805         printk("        IIR                     0x%04x\n", hw->iir);
 806         printk("        IMR                     0x%04x\n", hw->imr);
 807         printk("hw state dump end\n");
 808 #endif
 809 }
 810
 811
 812
 813 /* Split the M parameter into M1 and M2. */
 814 static int splitm(int index, unsigned int m, unsigned int *retm1,
 815                   unsigned int *retm2)
 816 {
 817         int m1, m2;
 818         int testm;
 819         struct pll_min_max *pll = &plls[index];
 820
 821         /* no point optimising too much - brute force m */
 822         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 823                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 824                         testm = (5 * (m1 + 2)) + (m2 + 2);
 825                         if (testm == m) {
 826                                 *retm1 = (unsigned int)m1;
 827                                 *retm2 = (unsigned int)m2;
 828                                 return 0;
 829                         }
 830                 }
 831         }
 832         return 1;
 833 }
 834
 835 /* Split the P parameter into P1 and P2. */
 836 static int splitp(int index, unsigned int p, unsigned int *retp1,
 837                   unsigned int *retp2)
 838 {
 839         int p1, p2;
 840         struct pll_min_max *pll = &plls[index];
 841
 842         if (index == PLLS_I9xx) {
 843                 p2 = (p % 10) ? 1 : 0;
 844
 845                 p1 = p / (p2 ? 5 : 10);
 846
 847                 *retp1 = (unsigned int)p1;
 848                 *retp2 = (unsigned int)p2;
 849                 return 0;
 850         }
 851
 852         if (p % 4 == 0)
 853                 p2 = 1;
 854         else
 855                 p2 = 0;
 856         p1 = (p / (1 << (p2 + 1))) - 2;
 857         if (p % 4 == 0 && p1 < pll->min_p1) {
 858                 p2 = 0;
 859                 p1 = (p / (1 << (p2 + 1))) - 2;
 860         }
 861         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 862             (p1 + 2) * (1 << (p2 + 1)) != p) {
 863                 return 1;
 864         } else {
 865                 *retp1 = (unsigned int)p1;
 866                 *retp2 = (unsigned int)p2;
 867                 return 0;
 868         }
 869 }
 870
 871 static int calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2,
 872                            u32 *retn, u32 *retp1, u32 *retp2, u32 *retclock)
 873 {
 874         u32 m1, m2, n, p1, p2, n1, testm;
 875         u32 f_vco, p, p_best = 0, m, f_out = 0;
 876         u32 err_max, err_target, err_best = 10000000;
 877         u32 n_best = 0, m_best = 0, f_best, f_err;
 878         u32 p_min, p_max, p_inc, div_max;
 879         struct pll_min_max *pll = &plls[index];
 880
 881         /* Accept 0.5% difference, but aim for 0.1% */
 882         err_max = 5 * clock / 1000;
 883         err_target = clock / 1000;
 884
 885         DBG_MSG("Clock is %d\n", clock);
 886
 887         div_max = pll->max_vco / clock;
 888
 889         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 890         p_min = p_inc;
 891         p_max = ROUND_DOWN_TO(div_max, p_inc);
 892         if (p_min < pll->min_p)
 893                 p_min = pll->min_p;
 894         if (p_max > pll->max_p)
 895                 p_max = pll->max_p;
 896
 897         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 898
 899         p = p_min;
 900         do {
 901                 if (splitp(index, p, &p1, &p2)) {
 902                         WRN_MSG("cannot split p = %d\n", p);
 903                         p += p_inc;
 904                         continue;
 905                 }
 906                 n = pll->min_n;
 907                 f_vco = clock * p;
 908
 909                 do {
 910                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 911                         if (m < pll->min_m)
 912                                 m = pll->min_m + 1;
 913                         if (m > pll->max_m)
 914                                 m = pll->max_m - 1;
 915                         for (testm = m - 1; testm <= m; testm++) {
 916                                 f_out = calc_vclock3(index, testm, n, p);
 917                                 if (splitm(index, testm, &m1, &m2)) {
 918                                         WRN_MSG("cannot split m = %d\n",
 919                                                 testm);
 920                                         continue;
 921                                 }
 922                                 if (clock > f_out)
 923                                         f_err = clock - f_out;
 924                                 else/* slightly bias the error for bigger clocks */
 925                                         f_err = f_out - clock + 1;
 926
 927                                 if (f_err < err_best) {
 928                                         m_best = testm;
 929                                         n_best = n;
 930                                         p_best = p;
 931                                         f_best = f_out;
 932                                         err_best = f_err;
 933                                 }
 934                         }
 935                         n++;
 936                 } while ((n <= pll->max_n) && (f_out >= clock));
 937                 p += p_inc;
 938         } while ((p <= p_max));
 939
 940         if (!m_best) {
 941                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 942                 return 1;
 943         }
 944         m = m_best;
 945         n = n_best;
 946         p = p_best;
 947         splitm(index, m, &m1, &m2);
 948         splitp(index, p, &p1, &p2);
 949         n1 = n - 2;
 950
 951         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 952                 "f: %d (%d), VCO: %d\n",
 953                 m, m1, m2, n, n1, p, p1, p2,
 954                 calc_vclock3(index, m, n, p),
 955                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 956                 calc_vclock3(index, m, n, p) * p);
 957         *retm1 = m1;
 958         *retm2 = m2;
 959         *retn = n1;
 960         *retp1 = p1;
 961         *retp2 = p2;
 962         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 963
 964         return 0;
 965 }
 966
 967 static __inline__ int check_overflow(u32 value, u32 limit,
 968                                      const char *description)
 969 {
 970         if (value > limit) {
 971                 WRN_MSG("%s value %d exceeds limit %d\n",
 972                         description, value, limit);
 973                 return 1;
 974         }
 975         return 0;
 976 }
 977
 978 /* It is assumed that hw is filled in with the initial state information. */
 979 int intelfbhw_mode_to_hw(struct intelfb_info *dinfo,
 980                          struct intelfb_hwstate *hw,
 981                          struct fb_var_screeninfo *var)
 982 {
 983         int pipe = PIPE_A;
 984         u32 *dpll, *fp0, *fp1;
 985         u32 m1, m2, n, p1, p2, clock_target, clock;
 986         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 987         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 988         u32 vsync_pol, hsync_pol;
 989         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 990         u32 stride_alignment;
 991
 992         DBG_MSG("intelfbhw_mode_to_hw\n");
 993
 994         /* Disable VGA */
 995         hw->vgacntrl |= VGA_DISABLE;
 996
 997         /* Check whether pipe A or pipe B is enabled. */
 998         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 999                 pipe = PIPE_A;
1000         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1001                 pipe = PIPE_B;
1002
1003         /* Set which pipe's registers will be set. */
1004         if (pipe == PIPE_B) {
1005                 dpll = &hw->dpll_b;
1006                 fp0 = &hw->fpb0;
1007                 fp1 = &hw->fpb1;
1008                 hs = &hw->hsync_b;
1009                 hb = &hw->hblank_b;
1010                 ht = &hw->htotal_b;
1011                 vs = &hw->vsync_b;
1012                 vb = &hw->vblank_b;
1013                 vt = &hw->vtotal_b;
1014                 ss = &hw->src_size_b;
1015                 pipe_conf = &hw->pipe_b_conf;
1016         } else {
1017                 dpll = &hw->dpll_a;
1018                 fp0 = &hw->fpa0;
1019                 fp1 = &hw->fpa1;
1020                 hs = &hw->hsync_a;
1021                 hb = &hw->hblank_a;
1022                 ht = &hw->htotal_a;
1023                 vs = &hw->vsync_a;
1024                 vb = &hw->vblank_a;
1025                 vt = &hw->vtotal_a;
1026                 ss = &hw->src_size_a;
1027                 pipe_conf = &hw->pipe_a_conf;
1028         }
1029
1030         /* Use ADPA register for sync control. */
1031         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1032
1033         /* sync polarity */
1034         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1035                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1036         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1037                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1038         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1039                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1040         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1041                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1042
1043         /* Connect correct pipe to the analog port DAC */
1044         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1045         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1046
1047         /* Set DPMS state to D0 (on) */
1048         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1049         hw->adpa |= ADPA_DPMS_D0;
1050
1051         hw->adpa |= ADPA_DAC_ENABLE;
1052
1053         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1054         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1055         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1056
1057         /* Desired clock in kHz */
1058         clock_target = 1000000000 / var->pixclock;
1059
1060         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1061                             &n, &p1, &p2, &clock)) {
1062                 WRN_MSG("calc_pll_params failed\n");
1063                 return 1;
1064         }
1065
1066         /* Check for overflow. */
1067         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1068                 return 1;
1069         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1070                 return 1;
1071         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1072                 return 1;
1073         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1074                 return 1;
1075         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1076                 return 1;
1077
1078         *dpll &= ~DPLL_P1_FORCE_DIV2;
1079         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1080                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1081
1082         if (IS_I9XX(dinfo)) {
1083                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1084                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1085         } else
1086                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1087
1088         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1089                (m1 << FP_M1_DIVISOR_SHIFT) |
1090                (m2 << FP_M2_DIVISOR_SHIFT);
1091         *fp1 = *fp0;
1092
1093         hw->dvob &= ~PORT_ENABLE;
1094         hw->dvoc &= ~PORT_ENABLE;
1095
1096         /* Use display plane A. */
1097         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1098         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1099         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1100         switch (intelfb_var_to_depth(var)) {
1101         case 8:
1102                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1103                 break;
1104         case 15:
1105                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1106                 break;
1107         case 16:
1108                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1109                 break;
1110         case 24:
1111                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1112                 break;
1113         }
1114         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1115         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1116
1117         /* Set CRTC registers. */
1118         hactive = var->xres;
1119         hsync_start = hactive + var->right_margin;
1120         hsync_end = hsync_start + var->hsync_len;
1121         htotal = hsync_end + var->left_margin;
1122         hblank_start = hactive;
1123         hblank_end = htotal;
1124
1125         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1126                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1127                 hblank_end);
1128
1129         vactive = var->yres;
1130         vsync_start = vactive + var->lower_margin;
1131         vsync_end = vsync_start + var->vsync_len;
1132         vtotal = vsync_end + var->upper_margin;
1133         vblank_start = vactive;
1134         vblank_end = vtotal;
1135         vblank_end = vsync_end + 1;
1136
1137         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1138                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1139                 vblank_end);
1140
1141         /* Adjust for register values, and check for overflow. */
1142         hactive--;
1143         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1144                 return 1;
1145         hsync_start--;
1146         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1147                 return 1;
1148         hsync_end--;
1149         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1150                 return 1;
1151         htotal--;
1152         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1153                 return 1;
1154         hblank_start--;
1155         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1156                 return 1;
1157         hblank_end--;
1158         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1159                 return 1;
1160
1161         vactive--;
1162         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1163                 return 1;
1164         vsync_start--;
1165         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1166                 return 1;
1167         vsync_end--;
1168         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1169                 return 1;
1170         vtotal--;
1171         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1172                 return 1;
1173         vblank_start--;
1174         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1175                 return 1;
1176         vblank_end--;
1177         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1178                 return 1;
1179
1180         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1181         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1182               (hblank_end << HSYNCEND_SHIFT);
1183         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1184
1185         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1186         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1187               (vblank_end << VSYNCEND_SHIFT);
1188         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1189         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1190               (vactive << SRC_SIZE_VERT_SHIFT);
1191
1192         hw->disp_a_stride = dinfo->pitch;
1193         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1194
1195         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1196                           var->xoffset * var->bits_per_pixel / 8;
1197
1198         hw->disp_a_base += dinfo->fb.offset << 12;
1199
1200         /* Check stride alignment. */
1201         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1202                                             STRIDE_ALIGNMENT;
1203         if (hw->disp_a_stride % stride_alignment != 0) {
1204                 WRN_MSG("display stride %d has bad alignment %d\n",
1205                         hw->disp_a_stride, stride_alignment);
1206                 return 1;
1207         }
1208
1209         /* Set the palette to 8-bit mode. */
1210         *pipe_conf &= ~PIPECONF_GAMMA;
1211
1212         if (var->vmode & FB_VMODE_INTERLACED)
1213                 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1214         else
1215                 *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1216
1217         return 0;
1218 }
1219
1220 /* Program a (non-VGA) video mode. */
1221 int intelfbhw_program_mode(struct intelfb_info *dinfo,
1222                            const struct intelfb_hwstate *hw, int blank)
1223 {
1224         int pipe = PIPE_A;
1225         u32 tmp;
1226         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1227         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1228         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1229         u32 hsync_reg, htotal_reg, hblank_reg;
1230         u32 vsync_reg, vtotal_reg, vblank_reg;
1231         u32 src_size_reg;
1232         u32 count, tmp_val[3];
1233
1234         /* Assume single pipe, display plane A, analog CRT. */
1235
1236 #if VERBOSE > 0
1237         DBG_MSG("intelfbhw_program_mode\n");
1238 #endif
1239
1240         /* Disable VGA */
1241         tmp = INREG(VGACNTRL);
1242         tmp |= VGA_DISABLE;
1243         OUTREG(VGACNTRL, tmp);
1244
1245         /* Check whether pipe A or pipe B is enabled. */
1246         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1247                 pipe = PIPE_A;
1248         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1249                 pipe = PIPE_B;
1250
1251         dinfo->pipe = pipe;
1252
1253         if (pipe == PIPE_B) {
1254                 dpll = &hw->dpll_b;
1255                 fp0 = &hw->fpb0;
1256                 fp1 = &hw->fpb1;
1257                 pipe_conf = &hw->pipe_b_conf;
1258                 hs = &hw->hsync_b;
1259                 hb = &hw->hblank_b;
1260                 ht = &hw->htotal_b;
1261                 vs = &hw->vsync_b;
1262                 vb = &hw->vblank_b;
1263                 vt = &hw->vtotal_b;
1264                 ss = &hw->src_size_b;
1265                 dpll_reg = DPLL_B;
1266                 fp0_reg = FPB0;
1267                 fp1_reg = FPB1;
1268                 pipe_conf_reg = PIPEBCONF;
1269                 hsync_reg = HSYNC_B;
1270                 htotal_reg = HTOTAL_B;
1271                 hblank_reg = HBLANK_B;
1272                 vsync_reg = VSYNC_B;
1273                 vtotal_reg = VTOTAL_B;
1274                 vblank_reg = VBLANK_B;
1275                 src_size_reg = SRC_SIZE_B;
1276         } else {
1277                 dpll = &hw->dpll_a;
1278                 fp0 = &hw->fpa0;
1279                 fp1 = &hw->fpa1;
1280                 pipe_conf = &hw->pipe_a_conf;
1281                 hs = &hw->hsync_a;
1282                 hb = &hw->hblank_a;
1283                 ht = &hw->htotal_a;
1284                 vs = &hw->vsync_a;
1285                 vb = &hw->vblank_a;
1286                 vt = &hw->vtotal_a;
1287                 ss = &hw->src_size_a;
1288                 dpll_reg = DPLL_A;
1289                 fp0_reg = FPA0;
1290                 fp1_reg = FPA1;
1291                 pipe_conf_reg = PIPEACONF;
1292                 hsync_reg = HSYNC_A;
1293                 htotal_reg = HTOTAL_A;
1294                 hblank_reg = HBLANK_A;
1295                 vsync_reg = VSYNC_A;
1296                 vtotal_reg = VTOTAL_A;
1297                 vblank_reg = VBLANK_A;
1298                 src_size_reg = SRC_SIZE_A;
1299         }
1300
1301         /* turn off pipe */
1302         tmp = INREG(pipe_conf_reg);
1303         tmp &= ~PIPECONF_ENABLE;
1304         OUTREG(pipe_conf_reg, tmp);
1305
1306         count = 0;
1307         do {
1308                 tmp_val[count % 3] = INREG(PIPEA_DSL);
1309                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1] == tmp_val[2]))
1310                         break;
1311                 count++;
1312                 udelay(1);
1313                 if (count % 200 == 0) {
1314                         tmp = INREG(pipe_conf_reg);
1315                         tmp &= ~PIPECONF_ENABLE;
1316                         OUTREG(pipe_conf_reg, tmp);
1317                 }
1318         } while (count < 2000);
1319
1320         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1321
1322         /* Disable planes A and B. */
1323         tmp = INREG(DSPACNTR);
1324         tmp &= ~DISPPLANE_PLANE_ENABLE;
1325         OUTREG(DSPACNTR, tmp);
1326         tmp = INREG(DSPBCNTR);
1327         tmp &= ~DISPPLANE_PLANE_ENABLE;
1328         OUTREG(DSPBCNTR, tmp);
1329
1330         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1331         mdelay(20);
1332
1333         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1334         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1335         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1336
1337         /* Disable Sync */
1338         tmp = INREG(ADPA);
1339         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1340         tmp |= ADPA_DPMS_D3;
1341         OUTREG(ADPA, tmp);
1342
1343         /* do some funky magic - xyzzy */
1344         OUTREG(0x61204, 0xabcd0000);
1345
1346         /* turn off PLL */
1347         tmp = INREG(dpll_reg);
1348         tmp &= ~DPLL_VCO_ENABLE;
1349         OUTREG(dpll_reg, tmp);
1350
1351         /* Set PLL parameters */
1352         OUTREG(fp0_reg, *fp0);
1353         OUTREG(fp1_reg, *fp1);
1354
1355         /* Enable PLL */
1356         OUTREG(dpll_reg, *dpll);
1357
1358         /* Set DVOs B/C */
1359         OUTREG(DVOB, hw->dvob);
1360         OUTREG(DVOC, hw->dvoc);
1361
1362         /* undo funky magic */
1363         OUTREG(0x61204, 0x00000000);
1364
1365         /* Set ADPA */
1366         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1367         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1368
1369         /* Set pipe parameters */
1370         OUTREG(hsync_reg, *hs);
1371         OUTREG(hblank_reg, *hb);
1372         OUTREG(htotal_reg, *ht);
1373         OUTREG(vsync_reg, *vs);
1374         OUTREG(vblank_reg, *vb);
1375         OUTREG(vtotal_reg, *vt);
1376         OUTREG(src_size_reg, *ss);
1377
1378         /* Enable pipe */
1379         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1380
1381         /* Enable sync */
1382         tmp = INREG(ADPA);
1383         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1384         tmp |= ADPA_DPMS_D0;
1385         OUTREG(ADPA, tmp);
1386
1387         /* setup display plane */
1388         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1389                 /*
1390                  *      i830M errata: the display plane must be enabled
1391                  *      to allow writes to the other bits in the plane
1392                  *      control register.
1393                  */
1394                 tmp = INREG(DSPACNTR);
1395                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1396                         tmp |= DISPPLANE_PLANE_ENABLE;
1397                         OUTREG(DSPACNTR, tmp);
1398                         OUTREG(DSPACNTR,
1399                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1400                         mdelay(1);
1401                 }
1402         }
1403
1404         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1405         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1406         OUTREG(DSPABASE, hw->disp_a_base);
1407
1408         /* Enable plane */
1409         if (!blank) {
1410                 tmp = INREG(DSPACNTR);
1411                 tmp |= DISPPLANE_PLANE_ENABLE;
1412                 OUTREG(DSPACNTR, tmp);
1413                 OUTREG(DSPABASE, hw->disp_a_base);
1414         }
1415
1416         return 0;
1417 }
1418
1419 /* forward declarations */
1420 static void refresh_ring(struct intelfb_info *dinfo);
1421 static void reset_state(struct intelfb_info *dinfo);
1422 static void do_flush(struct intelfb_info *dinfo);
1423
1424 static  u32 get_ring_space(struct intelfb_info *dinfo)
1425 {
1426         u32 ring_space;
1427
1428         if (dinfo->ring_tail >= dinfo->ring_head)
1429                 ring_space = dinfo->ring.size -
1430                         (dinfo->ring_tail - dinfo->ring_head);
1431         else
1432                 ring_space = dinfo->ring_head - dinfo->ring_tail;
1433
1434         if (ring_space > RING_MIN_FREE)
1435                 ring_space -= RING_MIN_FREE;
1436         else
1437                 ring_space = 0;
1438
1439         return ring_space;
1440 }
1441
1442 static int wait_ring(struct intelfb_info *dinfo, int n)
1443 {
1444         int i = 0;
1445         unsigned long end;
1446         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1447
1448 #if VERBOSE > 0
1449         DBG_MSG("wait_ring: %d\n", n);
1450 #endif
1451
1452         end = jiffies + (HZ * 3);
1453         while (dinfo->ring_space < n) {
1454                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1455                 dinfo->ring_space = get_ring_space(dinfo);
1456
1457                 if (dinfo->ring_head != last_head) {
1458                         end = jiffies + (HZ * 3);
1459                         last_head = dinfo->ring_head;
1460                 }
1461                 i++;
1462                 if (time_before(end, jiffies)) {
1463                         if (!i) {
1464                                 /* Try again */
1465                                 reset_state(dinfo);
1466                                 refresh_ring(dinfo);
1467                                 do_flush(dinfo);
1468                                 end = jiffies + (HZ * 3);
1469                                 i = 1;
1470                         } else {
1471                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1472                                         dinfo->ring_space, n);
1473                                 WRN_MSG("lockup - turning off hardware "
1474                                         "acceleration\n");
1475                                 dinfo->ring_lockup = 1;
1476                                 break;
1477                         }
1478                 }
1479                 udelay(1);
1480         }
1481         return i;
1482 }
1483
1484 static void do_flush(struct intelfb_info *dinfo)
1485 {
1486         START_RING(2);
1487         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1488         OUT_RING(MI_NOOP);
1489         ADVANCE_RING();
1490 }
1491
1492 void intelfbhw_do_sync(struct intelfb_info *dinfo)
1493 {
1494 #if VERBOSE > 0
1495         DBG_MSG("intelfbhw_do_sync\n");
1496 #endif
1497
1498         if (!dinfo->accel)
1499                 return;
1500
1501         /*
1502          * Send a flush, then wait until the ring is empty.  This is what
1503          * the XFree86 driver does, and actually it doesn't seem a lot worse
1504          * than the recommended method (both have problems).
1505          */
1506         do_flush(dinfo);
1507         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1508         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1509 }
1510
1511 static void refresh_ring(struct intelfb_info *dinfo)
1512 {
1513 #if VERBOSE > 0
1514         DBG_MSG("refresh_ring\n");
1515 #endif
1516
1517         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1518         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1519         dinfo->ring_space = get_ring_space(dinfo);
1520 }
1521
1522 static void reset_state(struct intelfb_info *dinfo)
1523 {
1524         int i;
1525         u32 tmp;
1526
1527 #if VERBOSE > 0
1528         DBG_MSG("reset_state\n");
1529 #endif
1530
1531         for (i = 0; i < FENCE_NUM; i++)
1532                 OUTREG(FENCE + (i << 2), 0);
1533
1534         /* Flush the ring buffer if it's enabled. */
1535         tmp = INREG(PRI_RING_LENGTH);
1536         if (tmp & RING_ENABLE) {
1537 #if VERBOSE > 0
1538                 DBG_MSG("reset_state: ring was enabled\n");
1539 #endif
1540                 refresh_ring(dinfo);
1541                 intelfbhw_do_sync(dinfo);
1542                 DO_RING_IDLE();
1543         }
1544
1545         OUTREG(PRI_RING_LENGTH, 0);
1546         OUTREG(PRI_RING_HEAD, 0);
1547         OUTREG(PRI_RING_TAIL, 0);
1548         OUTREG(PRI_RING_START, 0);
1549 }
1550
1551 /* Stop the 2D engine, and turn off the ring buffer. */
1552 void intelfbhw_2d_stop(struct intelfb_info *dinfo)
1553 {
1554 #if VERBOSE > 0
1555         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n",
1556                 dinfo->accel, dinfo->ring_active);
1557 #endif
1558
1559         if (!dinfo->accel)
1560                 return;
1561
1562         dinfo->ring_active = 0;
1563         reset_state(dinfo);
1564 }
1565
1566 /*
1567  * Enable the ring buffer, and initialise the 2D engine.
1568  * It is assumed that the graphics engine has been stopped by previously
1569  * calling intelfb_2d_stop().
1570  */
1571 void intelfbhw_2d_start(struct intelfb_info *dinfo)
1572 {
1573 #if VERBOSE > 0
1574         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1575                 dinfo->accel, dinfo->ring_active);
1576 #endif
1577
1578         if (!dinfo->accel)
1579                 return;
1580
1581         /* Initialise the primary ring buffer. */
1582         OUTREG(PRI_RING_LENGTH, 0);
1583         OUTREG(PRI_RING_TAIL, 0);
1584         OUTREG(PRI_RING_HEAD, 0);
1585
1586         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1587         OUTREG(PRI_RING_LENGTH,
1588                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1589                 RING_NO_REPORT | RING_ENABLE);
1590         refresh_ring(dinfo);
1591         dinfo->ring_active = 1;
1592 }
1593
1594 /* 2D fillrect (solid fill or invert) */
1595 void intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w,
1596                            u32 h, u32 color, u32 pitch, u32 bpp, u32 rop)
1597 {
1598         u32 br00, br09, br13, br14, br16;
1599
1600 #if VERBOSE > 0
1601         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1602                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1603 #endif
1604
1605         br00 = COLOR_BLT_CMD;
1606         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1607         br13 = (rop << ROP_SHIFT) | pitch;
1608         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1609         br16 = color;
1610
1611         switch (bpp) {
1612         case 8:
1613                 br13 |= COLOR_DEPTH_8;
1614                 break;
1615         case 16:
1616                 br13 |= COLOR_DEPTH_16;
1617                 break;
1618         case 32:
1619                 br13 |= COLOR_DEPTH_32;
1620                 br00 |= WRITE_ALPHA | WRITE_RGB;
1621                 break;
1622         }
1623
1624         START_RING(6);
1625         OUT_RING(br00);
1626         OUT_RING(br13);
1627         OUT_RING(br14);
1628         OUT_RING(br09);
1629         OUT_RING(br16);
1630         OUT_RING(MI_NOOP);
1631         ADVANCE_RING();
1632
1633 #if VERBOSE > 0
1634         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1635                 dinfo->ring_tail, dinfo->ring_space);
1636 #endif
1637 }
1638
1639 void
1640 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1641                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1642 {
1643         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1644
1645 #if VERBOSE > 0
1646         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1647                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1648 #endif
1649
1650         br00 = XY_SRC_COPY_BLT_CMD;
1651         br09 = dinfo->fb_start;
1652         br11 = (pitch << PITCH_SHIFT);
1653         br12 = dinfo->fb_start;
1654         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1655         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1656         br23 = ((dstx + w) << WIDTH_SHIFT) |
1657                ((dsty + h) << HEIGHT_SHIFT);
1658         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1659
1660         switch (bpp) {
1661         case 8:
1662                 br13 |= COLOR_DEPTH_8;
1663                 break;
1664         case 16:
1665                 br13 |= COLOR_DEPTH_16;
1666                 break;
1667         case 32:
1668                 br13 |= COLOR_DEPTH_32;
1669                 br00 |= WRITE_ALPHA | WRITE_RGB;
1670                 break;
1671         }
1672
1673         START_RING(8);
1674         OUT_RING(br00);
1675         OUT_RING(br13);
1676         OUT_RING(br22);
1677         OUT_RING(br23);
1678         OUT_RING(br09);
1679         OUT_RING(br26);
1680         OUT_RING(br11);
1681         OUT_RING(br12);
1682         ADVANCE_RING();
1683 }
1684
1685 int intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1686                            u32 h, const u8* cdat, u32 x, u32 y, u32 pitch,
1687                            u32 bpp)
1688 {
1689         int nbytes, ndwords, pad, tmp;
1690         u32 br00, br09, br13, br18, br19, br22, br23;
1691         int dat, ix, iy, iw;
1692         int i, j;
1693
1694 #if VERBOSE > 0
1695         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1696 #endif
1697
1698         /* size in bytes of a padded scanline */
1699         nbytes = ROUND_UP_TO(w, 16) / 8;
1700
1701         /* Total bytes of padded scanline data to write out. */
1702         nbytes = nbytes * h;
1703
1704         /*
1705          * Check if the glyph data exceeds the immediate mode limit.
1706          * It would take a large font (1K pixels) to hit this limit.
1707          */
1708         if (nbytes > MAX_MONO_IMM_SIZE)
1709                 return 0;
1710
1711         /* Src data is packaged a dword (32-bit) at a time. */
1712         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1713
1714         /*
1715          * Ring has to be padded to a quad word. But because the command starts
1716            with 7 bytes, pad only if there is an even number of ndwords
1717          */
1718         pad = !(ndwords % 2);
1719
1720         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1721         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1722         br09 = dinfo->fb_start;
1723         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1724         br18 = bg;
1725         br19 = fg;
1726         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1727         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1728
1729         switch (bpp) {
1730         case 8:
1731                 br13 |= COLOR_DEPTH_8;
1732                 break;
1733         case 16:
1734                 br13 |= COLOR_DEPTH_16;
1735                 break;
1736         case 32:
1737                 br13 |= COLOR_DEPTH_32;
1738                 br00 |= WRITE_ALPHA | WRITE_RGB;
1739                 break;
1740         }
1741
1742         START_RING(8 + ndwords);
1743         OUT_RING(br00);
1744         OUT_RING(br13);
1745         OUT_RING(br22);
1746         OUT_RING(br23);
1747         OUT_RING(br09);
1748         OUT_RING(br18);
1749         OUT_RING(br19);
1750         ix = iy = 0;
1751         iw = ROUND_UP_TO(w, 8) / 8;
1752         while (ndwords--) {
1753                 dat = 0;
1754                 for (j = 0; j < 2; ++j) {
1755                         for (i = 0; i < 2; ++i) {
1756                                 if (ix != iw || i == 0)
1757                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1758                         }
1759                         if (ix == iw && iy != (h-1)) {
1760                                 ix = 0;
1761                                 ++iy;
1762                         }
1763                 }
1764                 OUT_RING(dat);
1765         }
1766         if (pad)
1767                 OUT_RING(MI_NOOP);
1768         ADVANCE_RING();
1769
1770         return 1;
1771 }
1772
1773 /* HW cursor functions. */
1774 void intelfbhw_cursor_init(struct intelfb_info *dinfo)
1775 {
1776         u32 tmp;
1777
1778 #if VERBOSE > 0
1779         DBG_MSG("intelfbhw_cursor_init\n");
1780 #endif
1781
1782         if (dinfo->mobile || IS_I9XX(dinfo)) {
1783                 if (!dinfo->cursor.physical)
1784                         return;
1785                 tmp = INREG(CURSOR_A_CONTROL);
1786                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1787                          CURSOR_MEM_TYPE_LOCAL |
1788                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1789                 tmp |= CURSOR_MODE_DISABLE;
1790                 OUTREG(CURSOR_A_CONTROL, tmp);
1791                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1792         } else {
1793                 tmp = INREG(CURSOR_CONTROL);
1794                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1795                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1796                 tmp = CURSOR_FORMAT_3C;
1797                 OUTREG(CURSOR_CONTROL, tmp);
1798                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1799                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1800                       (64 << CURSOR_SIZE_V_SHIFT);
1801                 OUTREG(CURSOR_SIZE, tmp);
1802         }
1803 }
1804
1805 void intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1806 {
1807         u32 tmp;
1808
1809 #if VERBOSE > 0
1810         DBG_MSG("intelfbhw_cursor_hide\n");
1811 #endif
1812
1813         dinfo->cursor_on = 0;
1814         if (dinfo->mobile || IS_I9XX(dinfo)) {
1815                 if (!dinfo->cursor.physical)
1816                         return;
1817                 tmp = INREG(CURSOR_A_CONTROL);
1818                 tmp &= ~CURSOR_MODE_MASK;
1819                 tmp |= CURSOR_MODE_DISABLE;
1820                 OUTREG(CURSOR_A_CONTROL, tmp);
1821                 /* Flush changes */
1822                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1823         } else {
1824                 tmp = INREG(CURSOR_CONTROL);
1825                 tmp &= ~CURSOR_ENABLE;
1826                 OUTREG(CURSOR_CONTROL, tmp);
1827         }
1828 }
1829
1830 void intelfbhw_cursor_show(struct intelfb_info *dinfo)
1831 {
1832         u32 tmp;
1833
1834 #if VERBOSE > 0
1835         DBG_MSG("intelfbhw_cursor_show\n");
1836 #endif
1837
1838         dinfo->cursor_on = 1;
1839
1840         if (dinfo->cursor_blanked)
1841                 return;
1842
1843         if (dinfo->mobile || IS_I9XX(dinfo)) {
1844                 if (!dinfo->cursor.physical)
1845                         return;
1846                 tmp = INREG(CURSOR_A_CONTROL);
1847                 tmp &= ~CURSOR_MODE_MASK;
1848                 tmp |= CURSOR_MODE_64_4C_AX;
1849                 OUTREG(CURSOR_A_CONTROL, tmp);
1850                 /* Flush changes */
1851                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1852         } else {
1853                 tmp = INREG(CURSOR_CONTROL);
1854                 tmp |= CURSOR_ENABLE;
1855                 OUTREG(CURSOR_CONTROL, tmp);
1856         }
1857 }
1858
1859 void intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1860 {
1861         u32 tmp;
1862
1863 #if VERBOSE > 0
1864         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1865 #endif
1866
1867         /*
1868          * Sets the position. The coordinates are assumed to already
1869          * have any offset adjusted. Assume that the cursor is never
1870          * completely off-screen, and that x, y are always >= 0.
1871          */
1872
1873         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1874               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1875         OUTREG(CURSOR_A_POSITION, tmp);
1876
1877         if (IS_I9XX(dinfo))
1878                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1879 }
1880
1881 void intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1882 {
1883 #if VERBOSE > 0
1884         DBG_MSG("intelfbhw_cursor_setcolor\n");
1885 #endif
1886
1887         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1888         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1889         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1890         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1891 }
1892
1893 void intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1894                            u8 *data)
1895 {
1896         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1897         int i, j, w = width / 8;
1898         int mod = width % 8, t_mask, d_mask;
1899
1900 #if VERBOSE > 0
1901         DBG_MSG("intelfbhw_cursor_load\n");
1902 #endif
1903
1904         if (!dinfo->cursor.virtual)
1905                 return;
1906
1907         t_mask = 0xff >> mod;
1908         d_mask = ~(0xff >> mod);
1909         for (i = height; i--; ) {
1910                 for (j = 0; j < w; j++) {
1911                         writeb(0x00, addr + j);
1912                         writeb(*(data++), addr + j+8);
1913                 }
1914                 if (mod) {
1915                         writeb(t_mask, addr + j);
1916                         writeb(*(data++) & d_mask, addr + j+8);
1917                 }
1918                 addr += 16;
1919         }
1920 }
1921
1922 void intelfbhw_cursor_reset(struct intelfb_info *dinfo)
1923 {
1924         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1925         int i, j;
1926
1927 #if VERBOSE > 0
1928         DBG_MSG("intelfbhw_cursor_reset\n");
1929 #endif
1930
1931         if (!dinfo->cursor.virtual)
1932                 return;
1933
1934         for (i = 64; i--; ) {
1935                 for (j = 0; j < 8; j++) {
1936                         writeb(0xff, addr + j+0);
1937                         writeb(0x00, addr + j+8);
1938                 }
1939                 addr += 16;
1940         }
1941 }
1942
1943 static irqreturn_t
1944 intelfbhw_irq(int irq, void *dev_id) {
1945         int handled = 0;
1946         u16 tmp;
1947         struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1948
1949         spin_lock(&dinfo->int_lock);
1950
1951         tmp = INREG16(IIR);
1952         tmp &= VSYNC_PIPE_A_INTERRUPT;
1953
1954         if (tmp == 0) {
1955                 spin_unlock(&dinfo->int_lock);
1956                 return IRQ_RETVAL(handled);
1957         }
1958
1959         OUTREG16(IIR, tmp);
1960
1961         if (tmp & VSYNC_PIPE_A_INTERRUPT) {
1962                 dinfo->vsync.count++;
1963                 if (dinfo->vsync.pan_display) {
1964                         dinfo->vsync.pan_display = 0;
1965                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1966                 }
1967                 wake_up_interruptible(&dinfo->vsync.wait);
1968                 handled = 1;
1969         }
1970
1971         spin_unlock(&dinfo->int_lock);
1972
1973         return IRQ_RETVAL(handled);
1974 }
1975
1976 int
1977 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
1978
1979         if (!test_and_set_bit(0, &dinfo->irq_flags)) {
1980                 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
1981                      "intelfb", dinfo)) {
1982                         clear_bit(0, &dinfo->irq_flags);
1983                         return -EINVAL;
1984                 }
1985
1986                 spin_lock_irq(&dinfo->int_lock);
1987                 OUTREG16(HWSTAM, 0xfffe);
1988                 OUTREG16(IMR, 0x0);
1989                 OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
1990                 spin_unlock_irq(&dinfo->int_lock);
1991         } else if (reenable) {
1992                 u16 ier;
1993
1994                 spin_lock_irq(&dinfo->int_lock);
1995                 ier = INREG16(IER);
1996                 if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
1997                         DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
1998                         OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
1999                 }
2000                 spin_unlock_irq(&dinfo->int_lock);
2001         }
2002         return 0;
2003 }
2004
2005 void
2006 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2007
2008         if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2009                 if (dinfo->vsync.pan_display) {
2010                         dinfo->vsync.pan_display = 0;
2011                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2012                 }
2013                 spin_lock_irq(&dinfo->int_lock);
2014                 OUTREG16(HWSTAM, 0xffff);
2015                 OUTREG16(IMR, 0xffff);
2016                 OUTREG16(IER, 0x0);
2017
2018                 OUTREG16(IIR, INREG16(IIR)); /* clear IRQ requests */
2019                 spin_unlock_irq(&dinfo->int_lock);
2020
2021                 free_irq(dinfo->pdev->irq, dinfo);
2022         }
2023 }
2024
2025 int intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe)
2026 {
2027         struct intelfb_vsync *vsync;
2028         unsigned int count;
2029         int ret;
2030
2031         switch (pipe) {
2032                 case 0:
2033                         vsync = &dinfo->vsync;
2034                         break;
2035                 default:
2036                         return -ENODEV;
2037         }
2038
2039         ret = intelfbhw_enable_irq(dinfo, 0);
2040         if (ret)
2041                 return ret;
2042
2043         count = vsync->count;
2044         ret = wait_event_interruptible_timeout(vsync->wait,
2045                                                count != vsync->count, HZ / 10);
2046         if (ret < 0)
2047                 return ret;
2048         if (ret == 0) {
2049                 intelfbhw_enable_irq(dinfo, 1);
2050                 DBG_MSG("wait_for_vsync timed out!\n");
2051                 return -ETIMEDOUT;
2052         }
2053
2054         return 0;
2055 }