4 * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
6 * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
9 * This driver consists of two parts. The first part (intelfbdrv.c) provides
10 * the basic fbdev interfaces, is derived in part from the radeonfb and
11 * vesafb drivers, and is covered by the GPL. The second part (intelfbhw.c)
12 * provides the code to program the hardware. Most of it is derived from
13 * the i810/i830 XFree86 driver. The HW-specific code is covered here
14 * under a dual license (GPL and MIT/XFree86 license).
20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
22 #include <linux/config.h>
23 #include <linux/module.h>
24 #include <linux/kernel.h>
25 #include <linux/errno.h>
26 #include <linux/string.h>
28 #include <linux/tty.h>
29 #include <linux/slab.h>
30 #include <linux/delay.h>
32 #include <linux/ioport.h>
33 #include <linux/init.h>
34 #include <linux/pci.h>
35 #include <linux/vmalloc.h>
36 #include <linux/pagemap.h>
37 #include <linux/interrupt.h>
42 #include "intelfbhw.h"
45 int min_m, max_m, min_m1, max_m1;
46 int min_m2, max_m2, min_n, max_n;
47 int min_p, max_p, min_p1, max_p1;
48 int min_vco, max_vco, p_transition_clk, ref_clk;
49 int p_inc_lo, p_inc_hi;
56 static struct pll_min_max plls[PLLS_MAX] = {
60 930000, 1400000, 165000, 48000,
66 1400000, 2800000, 200000, 96000,
71 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
77 switch (pdev->device) {
78 case PCI_DEVICE_ID_INTEL_830M:
79 dinfo->name = "Intel(R) 830M";
80 dinfo->chipset = INTEL_830M;
82 dinfo->pll_index = PLLS_I8xx;
84 case PCI_DEVICE_ID_INTEL_845G:
85 dinfo->name = "Intel(R) 845G";
86 dinfo->chipset = INTEL_845G;
88 dinfo->pll_index = PLLS_I8xx;
90 case PCI_DEVICE_ID_INTEL_85XGM:
93 dinfo->pll_index = PLLS_I8xx;
94 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
95 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
96 INTEL_85X_VARIANT_MASK) {
97 case INTEL_VAR_855GME:
98 dinfo->name = "Intel(R) 855GME";
99 dinfo->chipset = INTEL_855GME;
101 case INTEL_VAR_855GM:
102 dinfo->name = "Intel(R) 855GM";
103 dinfo->chipset = INTEL_855GM;
105 case INTEL_VAR_852GME:
106 dinfo->name = "Intel(R) 852GME";
107 dinfo->chipset = INTEL_852GME;
109 case INTEL_VAR_852GM:
110 dinfo->name = "Intel(R) 852GM";
111 dinfo->chipset = INTEL_852GM;
114 dinfo->name = "Intel(R) 852GM/855GM";
115 dinfo->chipset = INTEL_85XGM;
119 case PCI_DEVICE_ID_INTEL_865G:
120 dinfo->name = "Intel(R) 865G";
121 dinfo->chipset = INTEL_865G;
123 dinfo->pll_index = PLLS_I8xx;
125 case PCI_DEVICE_ID_INTEL_915G:
126 dinfo->name = "Intel(R) 915G";
127 dinfo->chipset = INTEL_915G;
129 dinfo->pll_index = PLLS_I9xx;
131 case PCI_DEVICE_ID_INTEL_915GM:
132 dinfo->name = "Intel(R) 915GM";
133 dinfo->chipset = INTEL_915GM;
135 dinfo->pll_index = PLLS_I9xx;
137 case PCI_DEVICE_ID_INTEL_945G:
138 dinfo->name = "Intel(R) 945G";
139 dinfo->chipset = INTEL_945G;
141 dinfo->pll_index = PLLS_I9xx;
143 case PCI_DEVICE_ID_INTEL_945GM:
144 dinfo->name = "Intel(R) 945GM";
145 dinfo->chipset = INTEL_945GM;
147 dinfo->pll_index = PLLS_I9xx;
155 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
158 struct pci_dev *bridge_dev;
162 if (!pdev || !aperture_size || !stolen_size)
165 /* Find the bridge device. It is always 0:0.0 */
166 if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
167 ERR_MSG("cannot find bridge device\n");
171 /* Get the fb aperture size and "stolen" memory amount. */
173 pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
174 switch (pdev->device) {
175 case PCI_DEVICE_ID_INTEL_915G:
176 case PCI_DEVICE_ID_INTEL_915GM:
177 case PCI_DEVICE_ID_INTEL_945G:
178 case PCI_DEVICE_ID_INTEL_945GM:
179 /* 915 and 945 chipsets support a 256MB aperture.
180 Aperture size is determined by inspected the
181 base address of the aperture. */
182 if (pci_resource_start(pdev, 2) & 0x08000000)
183 *aperture_size = MB(128);
185 *aperture_size = MB(256);
188 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
189 *aperture_size = MB(64);
191 *aperture_size = MB(128);
195 /* Stolen memory size is reduced by the GTT and the popup.
196 GTT is 1K per MB of aperture size, and popup is 4K. */
197 stolen_overhead = (*aperture_size / MB(1)) + 4;
198 switch(pdev->device) {
199 case PCI_DEVICE_ID_INTEL_830M:
200 case PCI_DEVICE_ID_INTEL_845G:
201 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
202 case INTEL_830_GMCH_GMS_STOLEN_512:
203 *stolen_size = KB(512) - KB(stolen_overhead);
205 case INTEL_830_GMCH_GMS_STOLEN_1024:
206 *stolen_size = MB(1) - KB(stolen_overhead);
208 case INTEL_830_GMCH_GMS_STOLEN_8192:
209 *stolen_size = MB(8) - KB(stolen_overhead);
211 case INTEL_830_GMCH_GMS_LOCAL:
212 ERR_MSG("only local memory found\n");
214 case INTEL_830_GMCH_GMS_DISABLED:
215 ERR_MSG("video memory is disabled\n");
218 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
219 tmp & INTEL_830_GMCH_GMS_MASK);
224 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
225 case INTEL_855_GMCH_GMS_STOLEN_1M:
226 *stolen_size = MB(1) - KB(stolen_overhead);
228 case INTEL_855_GMCH_GMS_STOLEN_4M:
229 *stolen_size = MB(4) - KB(stolen_overhead);
231 case INTEL_855_GMCH_GMS_STOLEN_8M:
232 *stolen_size = MB(8) - KB(stolen_overhead);
234 case INTEL_855_GMCH_GMS_STOLEN_16M:
235 *stolen_size = MB(16) - KB(stolen_overhead);
237 case INTEL_855_GMCH_GMS_STOLEN_32M:
238 *stolen_size = MB(32) - KB(stolen_overhead);
240 case INTEL_915G_GMCH_GMS_STOLEN_48M:
241 *stolen_size = MB(48) - KB(stolen_overhead);
243 case INTEL_915G_GMCH_GMS_STOLEN_64M:
244 *stolen_size = MB(64) - KB(stolen_overhead);
246 case INTEL_855_GMCH_GMS_DISABLED:
247 ERR_MSG("video memory is disabled\n");
250 ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
251 tmp & INTEL_855_GMCH_GMS_MASK);
258 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
262 if (INREG(LVDS) & PORT_ENABLE)
264 if (INREG(DVOA) & PORT_ENABLE)
266 if (INREG(DVOB) & PORT_ENABLE)
268 if (INREG(DVOC) & PORT_ENABLE)
275 intelfbhw_dvo_to_string(int dvo)
279 else if (dvo & DVOB_PORT)
281 else if (dvo & DVOC_PORT)
283 else if (dvo & LVDS_PORT)
291 intelfbhw_validate_mode(struct intelfb_info *dinfo,
292 struct fb_var_screeninfo *var)
298 DBG_MSG("intelfbhw_validate_mode\n");
301 bytes_per_pixel = var->bits_per_pixel / 8;
302 if (bytes_per_pixel == 3)
305 /* Check if enough video memory. */
306 tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
307 if (tmp > dinfo->fb.size) {
308 WRN_MSG("Not enough video ram for mode "
309 "(%d KByte vs %d KByte).\n",
310 BtoKB(tmp), BtoKB(dinfo->fb.size));
314 /* Check if x/y limits are OK. */
315 if (var->xres - 1 > HACTIVE_MASK) {
316 WRN_MSG("X resolution too large (%d vs %d).\n",
317 var->xres, HACTIVE_MASK + 1);
320 if (var->yres - 1 > VACTIVE_MASK) {
321 WRN_MSG("Y resolution too large (%d vs %d).\n",
322 var->yres, VACTIVE_MASK + 1);
326 /* Check for interlaced/doublescan modes. */
327 if (var->vmode & FB_VMODE_INTERLACED) {
328 WRN_MSG("Mode is interlaced.\n");
331 if (var->vmode & FB_VMODE_DOUBLE) {
332 WRN_MSG("Mode is double-scan.\n");
336 /* Check if clock is OK. */
337 tmp = 1000000000 / var->pixclock;
338 if (tmp < MIN_CLOCK) {
339 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
340 (tmp + 500) / 1000, MIN_CLOCK / 1000);
343 if (tmp > MAX_CLOCK) {
344 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
345 (tmp + 500) / 1000, MAX_CLOCK / 1000);
353 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
355 struct intelfb_info *dinfo = GET_DINFO(info);
356 u32 offset, xoffset, yoffset;
359 DBG_MSG("intelfbhw_pan_display\n");
362 xoffset = ROUND_DOWN_TO(var->xoffset, 8);
363 yoffset = var->yoffset;
365 if ((xoffset + var->xres > var->xres_virtual) ||
366 (yoffset + var->yres > var->yres_virtual))
369 offset = (yoffset * dinfo->pitch) +
370 (xoffset * var->bits_per_pixel) / 8;
372 offset += dinfo->fb.offset << 12;
374 OUTREG(DSPABASE, offset);
379 /* Blank the screen. */
381 intelfbhw_do_blank(int blank, struct fb_info *info)
383 struct intelfb_info *dinfo = GET_DINFO(info);
387 DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
390 /* Turn plane A on or off */
391 tmp = INREG(DSPACNTR);
393 tmp &= ~DISPPLANE_PLANE_ENABLE;
395 tmp |= DISPPLANE_PLANE_ENABLE;
396 OUTREG(DSPACNTR, tmp);
398 tmp = INREG(DSPABASE);
399 OUTREG(DSPABASE, tmp);
401 /* Turn off/on the HW cursor */
403 DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
405 if (dinfo->cursor_on) {
407 intelfbhw_cursor_hide(dinfo);
409 intelfbhw_cursor_show(dinfo);
411 dinfo->cursor_on = 1;
413 dinfo->cursor_blanked = blank;
416 tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
418 case FB_BLANK_UNBLANK:
419 case FB_BLANK_NORMAL:
422 case FB_BLANK_VSYNC_SUSPEND:
425 case FB_BLANK_HSYNC_SUSPEND:
428 case FB_BLANK_POWERDOWN:
439 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
440 unsigned red, unsigned green, unsigned blue,
444 DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
445 regno, red, green, blue);
448 u32 palette_reg = (dinfo->pipe == PIPE_A) ?
449 PALETTE_A : PALETTE_B;
451 OUTREG(palette_reg + (regno << 2),
452 (red << PALETTE_8_RED_SHIFT) |
453 (green << PALETTE_8_GREEN_SHIFT) |
454 (blue << PALETTE_8_BLUE_SHIFT));
459 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
465 DBG_MSG("intelfbhw_read_hw_state\n");
471 /* Read in as much of the HW state as possible. */
472 hw->vga0_divisor = INREG(VGA0_DIVISOR);
473 hw->vga1_divisor = INREG(VGA1_DIVISOR);
474 hw->vga_pd = INREG(VGAPD);
475 hw->dpll_a = INREG(DPLL_A);
476 hw->dpll_b = INREG(DPLL_B);
477 hw->fpa0 = INREG(FPA0);
478 hw->fpa1 = INREG(FPA1);
479 hw->fpb0 = INREG(FPB0);
480 hw->fpb1 = INREG(FPB1);
486 /* This seems to be a problem with the 852GM/855GM */
487 for (i = 0; i < PALETTE_8_ENTRIES; i++) {
488 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
489 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
496 hw->htotal_a = INREG(HTOTAL_A);
497 hw->hblank_a = INREG(HBLANK_A);
498 hw->hsync_a = INREG(HSYNC_A);
499 hw->vtotal_a = INREG(VTOTAL_A);
500 hw->vblank_a = INREG(VBLANK_A);
501 hw->vsync_a = INREG(VSYNC_A);
502 hw->src_size_a = INREG(SRC_SIZE_A);
503 hw->bclrpat_a = INREG(BCLRPAT_A);
504 hw->htotal_b = INREG(HTOTAL_B);
505 hw->hblank_b = INREG(HBLANK_B);
506 hw->hsync_b = INREG(HSYNC_B);
507 hw->vtotal_b = INREG(VTOTAL_B);
508 hw->vblank_b = INREG(VBLANK_B);
509 hw->vsync_b = INREG(VSYNC_B);
510 hw->src_size_b = INREG(SRC_SIZE_B);
511 hw->bclrpat_b = INREG(BCLRPAT_B);
516 hw->adpa = INREG(ADPA);
517 hw->dvoa = INREG(DVOA);
518 hw->dvob = INREG(DVOB);
519 hw->dvoc = INREG(DVOC);
520 hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
521 hw->dvob_srcdim = INREG(DVOB_SRCDIM);
522 hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
523 hw->lvds = INREG(LVDS);
528 hw->pipe_a_conf = INREG(PIPEACONF);
529 hw->pipe_b_conf = INREG(PIPEBCONF);
530 hw->disp_arb = INREG(DISPARB);
535 hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
536 hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
537 hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
538 hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
543 for (i = 0; i < 4; i++) {
544 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
545 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
551 hw->cursor_size = INREG(CURSOR_SIZE);
556 hw->disp_a_ctrl = INREG(DSPACNTR);
557 hw->disp_b_ctrl = INREG(DSPBCNTR);
558 hw->disp_a_base = INREG(DSPABASE);
559 hw->disp_b_base = INREG(DSPBBASE);
560 hw->disp_a_stride = INREG(DSPASTRIDE);
561 hw->disp_b_stride = INREG(DSPBSTRIDE);
566 hw->vgacntrl = INREG(VGACNTRL);
571 hw->add_id = INREG(ADD_ID);
576 for (i = 0; i < 7; i++) {
577 hw->swf0x[i] = INREG(SWF00 + (i << 2));
578 hw->swf1x[i] = INREG(SWF10 + (i << 2));
580 hw->swf3x[i] = INREG(SWF30 + (i << 2));
583 for (i = 0; i < 8; i++)
584 hw->fence[i] = INREG(FENCE + (i << 2));
586 hw->instpm = INREG(INSTPM);
587 hw->mem_mode = INREG(MEM_MODE);
588 hw->fw_blc_0 = INREG(FW_BLC_0);
589 hw->fw_blc_1 = INREG(FW_BLC_1);
591 hw->hwstam = INREG16(HWSTAM);
592 hw->ier = INREG16(IER);
593 hw->iir = INREG16(IIR);
594 hw->imr = INREG16(IMR);
600 static int calc_vclock3(int index, int m, int n, int p)
602 if (p == 0 || n == 0)
604 return plls[index].ref_clk * m / n / p;
607 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
609 struct pll_min_max *pll = &plls[index];
612 m = (5 * (m1 + 2)) + (m2 + 2);
614 vco = pll->ref_clk * m / n;
616 if (index == PLLS_I8xx) {
617 p = ((p1 + 2) * (1 << (p2 + 1)));
619 p = ((p1) * (p2 ? 5 : 10));
625 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
629 if (IS_I9XX(dinfo)) {
630 if (dpll & DPLL_P1_FORCE_DIV2)
633 p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
637 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
639 if (dpll & DPLL_P1_FORCE_DIV2)
642 p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
643 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
652 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
655 int i, m1, m2, n, p1, p2;
656 int index = dinfo->pll_index;
657 DBG_MSG("intelfbhw_print_hw_state\n");
661 /* Read in as much of the HW state as possible. */
662 printk("hw state dump start\n");
663 printk(" VGA0_DIVISOR: 0x%08x\n", hw->vga0_divisor);
664 printk(" VGA1_DIVISOR: 0x%08x\n", hw->vga1_divisor);
665 printk(" VGAPD: 0x%08x\n", hw->vga_pd);
666 n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
667 m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
668 m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
670 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
672 printk(" VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
674 printk(" VGA0: clock is %d\n",
675 calc_vclock(index, m1, m2, n, p1, p2, 0));
677 n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
678 m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
679 m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
681 intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
682 printk(" VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
684 printk(" VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
686 printk(" DPLL_A: 0x%08x\n", hw->dpll_a);
687 printk(" DPLL_B: 0x%08x\n", hw->dpll_b);
688 printk(" FPA0: 0x%08x\n", hw->fpa0);
689 printk(" FPA1: 0x%08x\n", hw->fpa1);
690 printk(" FPB0: 0x%08x\n", hw->fpb0);
691 printk(" FPB1: 0x%08x\n", hw->fpb1);
693 n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
694 m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
695 m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
697 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
699 printk(" PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
701 printk(" PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
703 n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
704 m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
705 m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
707 intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
709 printk(" PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
711 printk(" PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
714 printk(" PALETTE_A:\n");
715 for (i = 0; i < PALETTE_8_ENTRIES)
716 printk(" %3d: 0x%08x\n", i, hw->palette_a[i]);
717 printk(" PALETTE_B:\n");
718 for (i = 0; i < PALETTE_8_ENTRIES)
719 printk(" %3d: 0x%08x\n", i, hw->palette_b[i]);
722 printk(" HTOTAL_A: 0x%08x\n", hw->htotal_a);
723 printk(" HBLANK_A: 0x%08x\n", hw->hblank_a);
724 printk(" HSYNC_A: 0x%08x\n", hw->hsync_a);
725 printk(" VTOTAL_A: 0x%08x\n", hw->vtotal_a);
726 printk(" VBLANK_A: 0x%08x\n", hw->vblank_a);
727 printk(" VSYNC_A: 0x%08x\n", hw->vsync_a);
728 printk(" SRC_SIZE_A: 0x%08x\n", hw->src_size_a);
729 printk(" BCLRPAT_A: 0x%08x\n", hw->bclrpat_a);
730 printk(" HTOTAL_B: 0x%08x\n", hw->htotal_b);
731 printk(" HBLANK_B: 0x%08x\n", hw->hblank_b);
732 printk(" HSYNC_B: 0x%08x\n", hw->hsync_b);
733 printk(" VTOTAL_B: 0x%08x\n", hw->vtotal_b);
734 printk(" VBLANK_B: 0x%08x\n", hw->vblank_b);
735 printk(" VSYNC_B: 0x%08x\n", hw->vsync_b);
736 printk(" SRC_SIZE_B: 0x%08x\n", hw->src_size_b);
737 printk(" BCLRPAT_B: 0x%08x\n", hw->bclrpat_b);
739 printk(" ADPA: 0x%08x\n", hw->adpa);
740 printk(" DVOA: 0x%08x\n", hw->dvoa);
741 printk(" DVOB: 0x%08x\n", hw->dvob);
742 printk(" DVOC: 0x%08x\n", hw->dvoc);
743 printk(" DVOA_SRCDIM: 0x%08x\n", hw->dvoa_srcdim);
744 printk(" DVOB_SRCDIM: 0x%08x\n", hw->dvob_srcdim);
745 printk(" DVOC_SRCDIM: 0x%08x\n", hw->dvoc_srcdim);
746 printk(" LVDS: 0x%08x\n", hw->lvds);
748 printk(" PIPEACONF: 0x%08x\n", hw->pipe_a_conf);
749 printk(" PIPEBCONF: 0x%08x\n", hw->pipe_b_conf);
750 printk(" DISPARB: 0x%08x\n", hw->disp_arb);
752 printk(" CURSOR_A_CONTROL: 0x%08x\n", hw->cursor_a_control);
753 printk(" CURSOR_B_CONTROL: 0x%08x\n", hw->cursor_b_control);
754 printk(" CURSOR_A_BASEADDR: 0x%08x\n", hw->cursor_a_base);
755 printk(" CURSOR_B_BASEADDR: 0x%08x\n", hw->cursor_b_base);
757 printk(" CURSOR_A_PALETTE: ");
758 for (i = 0; i < 4; i++) {
759 printk("0x%08x", hw->cursor_a_palette[i]);
764 printk(" CURSOR_B_PALETTE: ");
765 for (i = 0; i < 4; i++) {
766 printk("0x%08x", hw->cursor_b_palette[i]);
772 printk(" CURSOR_SIZE: 0x%08x\n", hw->cursor_size);
774 printk(" DSPACNTR: 0x%08x\n", hw->disp_a_ctrl);
775 printk(" DSPBCNTR: 0x%08x\n", hw->disp_b_ctrl);
776 printk(" DSPABASE: 0x%08x\n", hw->disp_a_base);
777 printk(" DSPBBASE: 0x%08x\n", hw->disp_b_base);
778 printk(" DSPASTRIDE: 0x%08x\n", hw->disp_a_stride);
779 printk(" DSPBSTRIDE: 0x%08x\n", hw->disp_b_stride);
781 printk(" VGACNTRL: 0x%08x\n", hw->vgacntrl);
782 printk(" ADD_ID: 0x%08x\n", hw->add_id);
784 for (i = 0; i < 7; i++) {
785 printk(" SWF0%d 0x%08x\n", i,
788 for (i = 0; i < 7; i++) {
789 printk(" SWF1%d 0x%08x\n", i,
792 for (i = 0; i < 3; i++) {
793 printk(" SWF3%d 0x%08x\n", i,
796 for (i = 0; i < 8; i++)
797 printk(" FENCE%d 0x%08x\n", i,
800 printk(" INSTPM 0x%08x\n", hw->instpm);
801 printk(" MEM_MODE 0x%08x\n", hw->mem_mode);
802 printk(" FW_BLC_0 0x%08x\n", hw->fw_blc_0);
803 printk(" FW_BLC_1 0x%08x\n", hw->fw_blc_1);
805 printk(" HWSTAM 0x%04x\n", hw->hwstam);
806 printk(" IER 0x%04x\n", hw->ier);
807 printk(" IIR 0x%04x\n", hw->iir);
808 printk(" IMR 0x%04x\n", hw->imr);
809 printk("hw state dump end\n");
815 /* Split the M parameter into M1 and M2. */
817 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
821 struct pll_min_max *pll = &plls[index];
823 /* no point optimising too much - brute force m */
824 for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
825 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
826 testm = (5 * (m1 + 2)) + (m2 + 2);
828 *retm1 = (unsigned int)m1;
829 *retm2 = (unsigned int)m2;
837 /* Split the P parameter into P1 and P2. */
839 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
842 struct pll_min_max *pll = &plls[index];
844 if (index == PLLS_I9xx) {
845 p2 = (p % 10) ? 1 : 0;
847 p1 = p / (p2 ? 5 : 10);
849 *retp1 = (unsigned int)p1;
850 *retp2 = (unsigned int)p2;
858 p1 = (p / (1 << (p2 + 1))) - 2;
859 if (p % 4 == 0 && p1 < pll->min_p1) {
861 p1 = (p / (1 << (p2 + 1))) - 2;
863 if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
864 (p1 + 2) * (1 << (p2 + 1)) != p) {
867 *retp1 = (unsigned int)p1;
868 *retp2 = (unsigned int)p2;
874 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
875 u32 *retp2, u32 *retclock)
877 u32 m1, m2, n, p1, p2, n1, testm;
878 u32 f_vco, p, p_best = 0, m, f_out = 0;
879 u32 err_max, err_target, err_best = 10000000;
880 u32 n_best = 0, m_best = 0, f_best, f_err;
881 u32 p_min, p_max, p_inc, div_max;
882 struct pll_min_max *pll = &plls[index];
884 /* Accept 0.5% difference, but aim for 0.1% */
885 err_max = 5 * clock / 1000;
886 err_target = clock / 1000;
888 DBG_MSG("Clock is %d\n", clock);
890 div_max = pll->max_vco / clock;
892 p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
894 p_max = ROUND_DOWN_TO(div_max, p_inc);
895 if (p_min < pll->min_p)
897 if (p_max > pll->max_p)
900 DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
904 if (splitp(index, p, &p1, &p2)) {
905 WRN_MSG("cannot split p = %d\n", p);
913 m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
918 for (testm = m - 1; testm <= m; testm++) {
919 f_out = calc_vclock3(index, m, n, p);
920 if (splitm(index, testm, &m1, &m2)) {
921 WRN_MSG("cannot split m = %d\n", m);
926 f_err = clock - f_out;
927 else/* slightly bias the error for bigger clocks */
928 f_err = f_out - clock + 1;
930 if (f_err < err_best) {
939 } while ((n <= pll->max_n) && (f_out >= clock));
941 } while ((p <= p_max));
944 WRN_MSG("cannot find parameters for clock %d\n", clock);
950 splitm(index, m, &m1, &m2);
951 splitp(index, p, &p1, &p2);
954 DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
955 "f: %d (%d), VCO: %d\n",
956 m, m1, m2, n, n1, p, p1, p2,
957 calc_vclock3(index, m, n, p),
958 calc_vclock(index, m1, m2, n1, p1, p2, 0),
959 calc_vclock3(index, m, n, p) * p);
965 *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
970 static __inline__ int
971 check_overflow(u32 value, u32 limit, const char *description)
974 WRN_MSG("%s value %d exceeds limit %d\n",
975 description, value, limit);
981 /* It is assumed that hw is filled in with the initial state information. */
983 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
984 struct fb_var_screeninfo *var)
987 u32 *dpll, *fp0, *fp1;
988 u32 m1, m2, n, p1, p2, clock_target, clock;
989 u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
990 u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
991 u32 vsync_pol, hsync_pol;
992 u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
993 u32 stride_alignment;
995 DBG_MSG("intelfbhw_mode_to_hw\n");
998 hw->vgacntrl |= VGA_DISABLE;
1000 /* Check whether pipe A or pipe B is enabled. */
1001 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1003 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1006 /* Set which pipe's registers will be set. */
1007 if (pipe == PIPE_B) {
1017 ss = &hw->src_size_b;
1018 pipe_conf = &hw->pipe_b_conf;
1029 ss = &hw->src_size_a;
1030 pipe_conf = &hw->pipe_a_conf;
1033 /* Use ADPA register for sync control. */
1034 hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1037 hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1038 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1039 vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1040 ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1041 hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1042 (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1043 hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1044 (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1046 /* Connect correct pipe to the analog port DAC */
1047 hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1048 hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1050 /* Set DPMS state to D0 (on) */
1051 hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1052 hw->adpa |= ADPA_DPMS_D0;
1054 hw->adpa |= ADPA_DAC_ENABLE;
1056 *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1057 *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1058 *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1060 /* Desired clock in kHz */
1061 clock_target = 1000000000 / var->pixclock;
1063 if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1064 &n, &p1, &p2, &clock)) {
1065 WRN_MSG("calc_pll_params failed\n");
1069 /* Check for overflow. */
1070 if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1072 if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1074 if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1076 if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1078 if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1081 *dpll &= ~DPLL_P1_FORCE_DIV2;
1082 *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1083 (DPLL_P1_MASK << DPLL_P1_SHIFT));
1085 if (IS_I9XX(dinfo)) {
1086 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1087 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1089 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1092 *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1093 (m1 << FP_M1_DIVISOR_SHIFT) |
1094 (m2 << FP_M2_DIVISOR_SHIFT);
1097 hw->dvob &= ~PORT_ENABLE;
1098 hw->dvoc &= ~PORT_ENABLE;
1100 /* Use display plane A. */
1101 hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1102 hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1103 hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1104 switch (intelfb_var_to_depth(var)) {
1106 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1109 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1112 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1115 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1118 hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1119 hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1121 /* Set CRTC registers. */
1122 hactive = var->xres;
1123 hsync_start = hactive + var->right_margin;
1124 hsync_end = hsync_start + var->hsync_len;
1125 htotal = hsync_end + var->left_margin;
1126 hblank_start = hactive;
1127 hblank_end = htotal;
1129 DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1130 hactive, hsync_start, hsync_end, htotal, hblank_start,
1133 vactive = var->yres;
1134 vsync_start = vactive + var->lower_margin;
1135 vsync_end = vsync_start + var->vsync_len;
1136 vtotal = vsync_end + var->upper_margin;
1137 vblank_start = vactive;
1138 vblank_end = vtotal;
1139 vblank_end = vsync_end + 1;
1141 DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1142 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1145 /* Adjust for register values, and check for overflow. */
1147 if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1150 if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1153 if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1156 if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1159 if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1162 if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1166 if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1169 if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1172 if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1175 if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1178 if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1181 if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1184 *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1185 *hb = (hblank_start << HBLANKSTART_SHIFT) |
1186 (hblank_end << HSYNCEND_SHIFT);
1187 *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1189 *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1190 *vb = (vblank_start << VBLANKSTART_SHIFT) |
1191 (vblank_end << VSYNCEND_SHIFT);
1192 *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1193 *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1194 (vactive << SRC_SIZE_VERT_SHIFT);
1196 hw->disp_a_stride = dinfo->pitch;
1197 DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1199 hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1200 var->xoffset * var->bits_per_pixel / 8;
1202 hw->disp_a_base += dinfo->fb.offset << 12;
1204 /* Check stride alignment. */
1205 stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1207 if (hw->disp_a_stride % stride_alignment != 0) {
1208 WRN_MSG("display stride %d has bad alignment %d\n",
1209 hw->disp_a_stride, stride_alignment);
1213 /* Set the palette to 8-bit mode. */
1214 *pipe_conf &= ~PIPECONF_GAMMA;
1218 /* Program a (non-VGA) video mode. */
1220 intelfbhw_program_mode(struct intelfb_info *dinfo,
1221 const struct intelfb_hwstate *hw, int blank)
1225 const u32 *dpll, *fp0, *fp1, *pipe_conf;
1226 const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1227 u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1228 u32 hsync_reg, htotal_reg, hblank_reg;
1229 u32 vsync_reg, vtotal_reg, vblank_reg;
1231 u32 count, tmp_val[3];
1233 /* Assume single pipe, display plane A, analog CRT. */
1236 DBG_MSG("intelfbhw_program_mode\n");
1240 tmp = INREG(VGACNTRL);
1242 OUTREG(VGACNTRL, tmp);
1244 /* Check whether pipe A or pipe B is enabled. */
1245 if (hw->pipe_a_conf & PIPECONF_ENABLE)
1247 else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1252 if (pipe == PIPE_B) {
1256 pipe_conf = &hw->pipe_b_conf;
1263 ss = &hw->src_size_b;
1267 pipe_conf_reg = PIPEBCONF;
1268 hsync_reg = HSYNC_B;
1269 htotal_reg = HTOTAL_B;
1270 hblank_reg = HBLANK_B;
1271 vsync_reg = VSYNC_B;
1272 vtotal_reg = VTOTAL_B;
1273 vblank_reg = VBLANK_B;
1274 src_size_reg = SRC_SIZE_B;
1279 pipe_conf = &hw->pipe_a_conf;
1286 ss = &hw->src_size_a;
1290 pipe_conf_reg = PIPEACONF;
1291 hsync_reg = HSYNC_A;
1292 htotal_reg = HTOTAL_A;
1293 hblank_reg = HBLANK_A;
1294 vsync_reg = VSYNC_A;
1295 vtotal_reg = VTOTAL_A;
1296 vblank_reg = VBLANK_A;
1297 src_size_reg = SRC_SIZE_A;
1301 tmp = INREG(pipe_conf_reg);
1302 tmp &= ~PIPECONF_ENABLE;
1303 OUTREG(pipe_conf_reg, tmp);
1307 tmp_val[count%3] = INREG(0x70000);
1308 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1312 if (count % 200 == 0) {
1313 tmp = INREG(pipe_conf_reg);
1314 tmp &= ~PIPECONF_ENABLE;
1315 OUTREG(pipe_conf_reg, tmp);
1317 } while(count < 2000);
1319 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1321 /* Disable planes A and B. */
1322 tmp = INREG(DSPACNTR);
1323 tmp &= ~DISPPLANE_PLANE_ENABLE;
1324 OUTREG(DSPACNTR, tmp);
1325 tmp = INREG(DSPBCNTR);
1326 tmp &= ~DISPPLANE_PLANE_ENABLE;
1327 OUTREG(DSPBCNTR, tmp);
1329 /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1332 OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1333 OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1334 OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1338 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1339 tmp |= ADPA_DPMS_D3;
1342 /* do some funky magic - xyzzy */
1343 OUTREG(0x61204, 0xabcd0000);
1346 tmp = INREG(dpll_reg);
1347 dpll_reg &= ~DPLL_VCO_ENABLE;
1348 OUTREG(dpll_reg, tmp);
1350 /* Set PLL parameters */
1351 OUTREG(fp0_reg, *fp0);
1352 OUTREG(fp1_reg, *fp1);
1355 OUTREG(dpll_reg, *dpll);
1358 OUTREG(DVOB, hw->dvob);
1359 OUTREG(DVOC, hw->dvoc);
1361 /* undo funky magic */
1362 OUTREG(0x61204, 0x00000000);
1365 OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1366 OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1368 /* Set pipe parameters */
1369 OUTREG(hsync_reg, *hs);
1370 OUTREG(hblank_reg, *hb);
1371 OUTREG(htotal_reg, *ht);
1372 OUTREG(vsync_reg, *vs);
1373 OUTREG(vblank_reg, *vb);
1374 OUTREG(vtotal_reg, *vt);
1375 OUTREG(src_size_reg, *ss);
1378 OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1382 tmp &= ~ADPA_DPMS_CONTROL_MASK;
1383 tmp |= ADPA_DPMS_D0;
1386 /* setup display plane */
1387 if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1389 * i830M errata: the display plane must be enabled
1390 * to allow writes to the other bits in the plane
1393 tmp = INREG(DSPACNTR);
1394 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1395 tmp |= DISPPLANE_PLANE_ENABLE;
1396 OUTREG(DSPACNTR, tmp);
1398 hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1403 OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1404 OUTREG(DSPASTRIDE, hw->disp_a_stride);
1405 OUTREG(DSPABASE, hw->disp_a_base);
1409 tmp = INREG(DSPACNTR);
1410 tmp |= DISPPLANE_PLANE_ENABLE;
1411 OUTREG(DSPACNTR, tmp);
1412 OUTREG(DSPABASE, hw->disp_a_base);
1418 /* forward declarations */
1419 static void refresh_ring(struct intelfb_info *dinfo);
1420 static void reset_state(struct intelfb_info *dinfo);
1421 static void do_flush(struct intelfb_info *dinfo);
1424 wait_ring(struct intelfb_info *dinfo, int n)
1428 u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1431 DBG_MSG("wait_ring: %d\n", n);
1434 end = jiffies + (HZ * 3);
1435 while (dinfo->ring_space < n) {
1436 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1437 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1438 dinfo->ring_space = dinfo->ring_head
1439 - (dinfo->ring_tail + RING_MIN_FREE);
1441 dinfo->ring_space = (dinfo->ring.size +
1443 - (dinfo->ring_tail + RING_MIN_FREE);
1444 if (dinfo->ring_head != last_head) {
1445 end = jiffies + (HZ * 3);
1446 last_head = dinfo->ring_head;
1449 if (time_before(end, jiffies)) {
1453 refresh_ring(dinfo);
1455 end = jiffies + (HZ * 3);
1458 WRN_MSG("ring buffer : space: %d wanted %d\n",
1459 dinfo->ring_space, n);
1460 WRN_MSG("lockup - turning off hardware "
1462 dinfo->ring_lockup = 1;
1472 do_flush(struct intelfb_info *dinfo) {
1474 OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1480 intelfbhw_do_sync(struct intelfb_info *dinfo)
1483 DBG_MSG("intelfbhw_do_sync\n");
1490 * Send a flush, then wait until the ring is empty. This is what
1491 * the XFree86 driver does, and actually it doesn't seem a lot worse
1492 * than the recommended method (both have problems).
1495 wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1496 dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1500 refresh_ring(struct intelfb_info *dinfo)
1503 DBG_MSG("refresh_ring\n");
1506 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1507 dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1508 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1509 dinfo->ring_space = dinfo->ring_head
1510 - (dinfo->ring_tail + RING_MIN_FREE);
1512 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1513 - (dinfo->ring_tail + RING_MIN_FREE);
1517 reset_state(struct intelfb_info *dinfo)
1523 DBG_MSG("reset_state\n");
1526 for (i = 0; i < FENCE_NUM; i++)
1527 OUTREG(FENCE + (i << 2), 0);
1529 /* Flush the ring buffer if it's enabled. */
1530 tmp = INREG(PRI_RING_LENGTH);
1531 if (tmp & RING_ENABLE) {
1533 DBG_MSG("reset_state: ring was enabled\n");
1535 refresh_ring(dinfo);
1536 intelfbhw_do_sync(dinfo);
1540 OUTREG(PRI_RING_LENGTH, 0);
1541 OUTREG(PRI_RING_HEAD, 0);
1542 OUTREG(PRI_RING_TAIL, 0);
1543 OUTREG(PRI_RING_START, 0);
1546 /* Stop the 2D engine, and turn off the ring buffer. */
1548 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1551 DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1552 dinfo->ring_active);
1558 dinfo->ring_active = 0;
1563 * Enable the ring buffer, and initialise the 2D engine.
1564 * It is assumed that the graphics engine has been stopped by previously
1565 * calling intelfb_2d_stop().
1568 intelfbhw_2d_start(struct intelfb_info *dinfo)
1571 DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1572 dinfo->accel, dinfo->ring_active);
1578 /* Initialise the primary ring buffer. */
1579 OUTREG(PRI_RING_LENGTH, 0);
1580 OUTREG(PRI_RING_TAIL, 0);
1581 OUTREG(PRI_RING_HEAD, 0);
1583 OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1584 OUTREG(PRI_RING_LENGTH,
1585 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1586 RING_NO_REPORT | RING_ENABLE);
1587 refresh_ring(dinfo);
1588 dinfo->ring_active = 1;
1591 /* 2D fillrect (solid fill or invert) */
1593 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1594 u32 color, u32 pitch, u32 bpp, u32 rop)
1596 u32 br00, br09, br13, br14, br16;
1599 DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1600 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1603 br00 = COLOR_BLT_CMD;
1604 br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1605 br13 = (rop << ROP_SHIFT) | pitch;
1606 br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1611 br13 |= COLOR_DEPTH_8;
1614 br13 |= COLOR_DEPTH_16;
1617 br13 |= COLOR_DEPTH_32;
1618 br00 |= WRITE_ALPHA | WRITE_RGB;
1632 DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1633 dinfo->ring_tail, dinfo->ring_space);
1638 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1639 u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1641 u32 br00, br09, br11, br12, br13, br22, br23, br26;
1644 DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1645 curx, cury, dstx, dsty, w, h, pitch, bpp);
1648 br00 = XY_SRC_COPY_BLT_CMD;
1649 br09 = dinfo->fb_start;
1650 br11 = (pitch << PITCH_SHIFT);
1651 br12 = dinfo->fb_start;
1652 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1653 br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1654 br23 = ((dstx + w) << WIDTH_SHIFT) |
1655 ((dsty + h) << HEIGHT_SHIFT);
1656 br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1660 br13 |= COLOR_DEPTH_8;
1663 br13 |= COLOR_DEPTH_16;
1666 br13 |= COLOR_DEPTH_32;
1667 br00 |= WRITE_ALPHA | WRITE_RGB;
1684 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1685 u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1687 int nbytes, ndwords, pad, tmp;
1688 u32 br00, br09, br13, br18, br19, br22, br23;
1689 int dat, ix, iy, iw;
1693 DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1696 /* size in bytes of a padded scanline */
1697 nbytes = ROUND_UP_TO(w, 16) / 8;
1699 /* Total bytes of padded scanline data to write out. */
1700 nbytes = nbytes * h;
1703 * Check if the glyph data exceeds the immediate mode limit.
1704 * It would take a large font (1K pixels) to hit this limit.
1706 if (nbytes > MAX_MONO_IMM_SIZE)
1709 /* Src data is packaged a dword (32-bit) at a time. */
1710 ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1713 * Ring has to be padded to a quad word. But because the command starts
1714 with 7 bytes, pad only if there is an even number of ndwords
1716 pad = !(ndwords % 2);
1718 tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1719 br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1720 br09 = dinfo->fb_start;
1721 br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1724 br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1725 br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1729 br13 |= COLOR_DEPTH_8;
1732 br13 |= COLOR_DEPTH_16;
1735 br13 |= COLOR_DEPTH_32;
1736 br00 |= WRITE_ALPHA | WRITE_RGB;
1740 START_RING(8 + ndwords);
1749 iw = ROUND_UP_TO(w, 8) / 8;
1752 for (j = 0; j < 2; ++j) {
1753 for (i = 0; i < 2; ++i) {
1754 if (ix != iw || i == 0)
1755 dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1757 if (ix == iw && iy != (h-1)) {
1771 /* HW cursor functions. */
1773 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1778 DBG_MSG("intelfbhw_cursor_init\n");
1781 if (dinfo->mobile || IS_I9XX(dinfo)) {
1782 if (!dinfo->cursor.physical)
1784 tmp = INREG(CURSOR_A_CONTROL);
1785 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1786 CURSOR_MEM_TYPE_LOCAL |
1787 (1 << CURSOR_PIPE_SELECT_SHIFT));
1788 tmp |= CURSOR_MODE_DISABLE;
1789 OUTREG(CURSOR_A_CONTROL, tmp);
1790 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1792 tmp = INREG(CURSOR_CONTROL);
1793 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1794 CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1795 tmp = CURSOR_FORMAT_3C;
1796 OUTREG(CURSOR_CONTROL, tmp);
1797 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1798 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1799 (64 << CURSOR_SIZE_V_SHIFT);
1800 OUTREG(CURSOR_SIZE, tmp);
1805 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1810 DBG_MSG("intelfbhw_cursor_hide\n");
1813 dinfo->cursor_on = 0;
1814 if (dinfo->mobile || IS_I9XX(dinfo)) {
1815 if (!dinfo->cursor.physical)
1817 tmp = INREG(CURSOR_A_CONTROL);
1818 tmp &= ~CURSOR_MODE_MASK;
1819 tmp |= CURSOR_MODE_DISABLE;
1820 OUTREG(CURSOR_A_CONTROL, tmp);
1822 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1824 tmp = INREG(CURSOR_CONTROL);
1825 tmp &= ~CURSOR_ENABLE;
1826 OUTREG(CURSOR_CONTROL, tmp);
1831 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1836 DBG_MSG("intelfbhw_cursor_show\n");
1839 dinfo->cursor_on = 1;
1841 if (dinfo->cursor_blanked)
1844 if (dinfo->mobile || IS_I9XX(dinfo)) {
1845 if (!dinfo->cursor.physical)
1847 tmp = INREG(CURSOR_A_CONTROL);
1848 tmp &= ~CURSOR_MODE_MASK;
1849 tmp |= CURSOR_MODE_64_4C_AX;
1850 OUTREG(CURSOR_A_CONTROL, tmp);
1852 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1854 tmp = INREG(CURSOR_CONTROL);
1855 tmp |= CURSOR_ENABLE;
1856 OUTREG(CURSOR_CONTROL, tmp);
1861 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1866 DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1870 * Sets the position. The coordinates are assumed to already
1871 * have any offset adjusted. Assume that the cursor is never
1872 * completely off-screen, and that x, y are always >= 0.
1875 tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1876 ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1877 OUTREG(CURSOR_A_POSITION, tmp);
1879 if (IS_I9XX(dinfo)) {
1880 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1885 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1888 DBG_MSG("intelfbhw_cursor_setcolor\n");
1891 OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1892 OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1893 OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1894 OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1898 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1901 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1902 int i, j, w = width / 8;
1903 int mod = width % 8, t_mask, d_mask;
1906 DBG_MSG("intelfbhw_cursor_load\n");
1909 if (!dinfo->cursor.virtual)
1912 t_mask = 0xff >> mod;
1913 d_mask = ~(0xff >> mod);
1914 for (i = height; i--; ) {
1915 for (j = 0; j < w; j++) {
1916 writeb(0x00, addr + j);
1917 writeb(*(data++), addr + j+8);
1920 writeb(t_mask, addr + j);
1921 writeb(*(data++) & d_mask, addr + j+8);
1928 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1929 u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1933 DBG_MSG("intelfbhw_cursor_reset\n");
1936 if (!dinfo->cursor.virtual)
1939 for (i = 64; i--; ) {
1940 for (j = 0; j < 8; j++) {
1941 writeb(0xff, addr + j+0);
1942 writeb(0x00, addr + j+8);
1949 intelfbhw_irq(int irq, void *dev_id, struct pt_regs *fp) {
1952 struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1954 spin_lock(&dinfo->int_lock);
1957 tmp &= VSYNC_PIPE_A_INTERRUPT;
1960 spin_unlock(&dinfo->int_lock);
1961 return IRQ_RETVAL(handled);
1966 if (tmp & VSYNC_PIPE_A_INTERRUPT) {
1967 dinfo->vsync.count++;
1968 wake_up_interruptible(&dinfo->vsync.wait);
1972 spin_unlock(&dinfo->int_lock);
1974 return IRQ_RETVAL(handled);
1978 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
1980 if (!test_and_set_bit(0, &dinfo->irq_flags)) {
1981 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, SA_SHIRQ, "intelfb", dinfo)) {
1982 clear_bit(0, &dinfo->irq_flags);
1986 spin_lock_irq(&dinfo->int_lock);
1987 OUTREG16(HWSTAM, 0xfffe);
1989 OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
1990 spin_unlock_irq(&dinfo->int_lock);
1991 } else if (reenable) {
1994 spin_lock_irq(&dinfo->int_lock);
1996 if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
1997 DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
1998 OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
2000 spin_unlock_irq(&dinfo->int_lock);
2006 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2009 if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2010 spin_lock_irq(&dinfo->int_lock);
2011 OUTREG16(HWSTAM, 0xffff);
2012 OUTREG16(IMR, 0xffff);
2017 spin_unlock_irq(&dinfo->int_lock);
2019 free_irq(dinfo->pdev->irq, dinfo);