SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m;
  45         int min_m1, max_m1;
  46         int min_m2, max_m2;
  47         int min_n, max_n;
  48         int min_p, max_p;
  49         int min_p1, max_p1;
  50         int min_vco_freq, max_vco_freq;
  51         int p_transition_clock;
  52         int p_inc_lo, p_inc_hi;
  53 };
  54
  55 #define PLLS_I8xx 0
  56 #define PLLS_I9xx 1
  57 #define PLLS_MAX 2
  58
  59 static struct pll_min_max plls[PLLS_MAX] = {
  60         { 108, 140, 18, 26, 6, 16, 3, 16, 4, 128, 0, 31, 930000, 1400000, 165000, 4, 22 }, //I8xx
  61         {  75, 120, 10, 20, 5, 9, 4,  7, 5, 80, 1, 8, 930000, 2800000, 200000, 10, 5 }  //I9xx
  62 };
  63
  64 int
  65 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  66 {
  67         u32 tmp;
  68         if (!pdev || !dinfo)
  69                 return 1;
  70
  71         switch (pdev->device) {
  72         case PCI_DEVICE_ID_INTEL_830M:
  73                 dinfo->name = "Intel(R) 830M";
  74                 dinfo->chipset = INTEL_830M;
  75                 dinfo->mobile = 1;
  76                 dinfo->pll_index = PLLS_I8xx;
  77                 return 0;
  78         case PCI_DEVICE_ID_INTEL_845G:
  79                 dinfo->name = "Intel(R) 845G";
  80                 dinfo->chipset = INTEL_845G;
  81                 dinfo->mobile = 0;
  82                 dinfo->pll_index = PLLS_I8xx;
  83                 return 0;
  84         case PCI_DEVICE_ID_INTEL_85XGM:
  85                 tmp = 0;
  86                 dinfo->mobile = 1;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  89                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  90                         INTEL_85X_VARIANT_MASK) {
  91                 case INTEL_VAR_855GME:
  92                         dinfo->name = "Intel(R) 855GME";
  93                         dinfo->chipset = INTEL_855GME;
  94                         return 0;
  95                 case INTEL_VAR_855GM:
  96                         dinfo->name = "Intel(R) 855GM";
  97                         dinfo->chipset = INTEL_855GM;
  98                         return 0;
  99                 case INTEL_VAR_852GME:
 100                         dinfo->name = "Intel(R) 852GME";
 101                         dinfo->chipset = INTEL_852GME;
 102                         return 0;
 103                 case INTEL_VAR_852GM:
 104                         dinfo->name = "Intel(R) 852GM";
 105                         dinfo->chipset = INTEL_852GM;
 106                         return 0;
 107                 default:
 108                         dinfo->name = "Intel(R) 852GM/855GM";
 109                         dinfo->chipset = INTEL_85XGM;
 110                         return 0;
 111                 }
 112                 break;
 113         case PCI_DEVICE_ID_INTEL_865G:
 114                 dinfo->name = "Intel(R) 865G";
 115                 dinfo->chipset = INTEL_865G;
 116                 dinfo->mobile = 0;
 117                 dinfo->pll_index = PLLS_I8xx;
 118                 return 0;
 119         case PCI_DEVICE_ID_INTEL_915G:
 120                 dinfo->name = "Intel(R) 915G";
 121                 dinfo->chipset = INTEL_915G;
 122                 dinfo->mobile = 0;
 123                 dinfo->pll_index = PLLS_I9xx;
 124                 return 0;
 125         case PCI_DEVICE_ID_INTEL_915GM:
 126                 dinfo->name = "Intel(R) 915GM";
 127                 dinfo->chipset = INTEL_915GM;
 128                 dinfo->mobile = 1;
 129                 dinfo->pll_index = PLLS_I9xx;
 130                 return 0;
 131         case PCI_DEVICE_ID_INTEL_945G:
 132                 dinfo->name = "Intel(R) 945G";
 133                 dinfo->chipset = INTEL_945G;
 134                 dinfo->mobile = 0;
 135                 dinfo->pll_index = PLLS_I9xx;
 136                 return 0;
 137         case PCI_DEVICE_ID_INTEL_945GM:
 138                 dinfo->name = "Intel(R) 945GM";
 139                 dinfo->chipset = INTEL_945GM;
 140                 dinfo->mobile = 1;
 141                 dinfo->pll_index = PLLS_I9xx;
 142                 return 0;
 143         default:
 144                 return 1;
 145         }
 146 }
 147
 148 int
 149 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 150                      int *stolen_size)
 151 {
 152         struct pci_dev *bridge_dev;
 153         u16 tmp;
 154
 155         if (!pdev || !aperture_size || !stolen_size)
 156                 return 1;
 157
 158         /* Find the bridge device.  It is always 0:0.0 */
 159         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 160                 ERR_MSG("cannot find bridge device\n");
 161                 return 1;
 162         }
 163
 164         /* Get the fb aperture size and "stolen" memory amount. */
 165         tmp = 0;
 166         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 167         switch (pdev->device) {
 168         case PCI_DEVICE_ID_INTEL_830M:
 169         case PCI_DEVICE_ID_INTEL_845G:
 170                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 171                         *aperture_size = MB(64);
 172                 else
 173                         *aperture_size = MB(128);
 174                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 175                 case INTEL_830_GMCH_GMS_STOLEN_512:
 176                         *stolen_size = KB(512) - KB(132);
 177                         return 0;
 178                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 179                         *stolen_size = MB(1) - KB(132);
 180                         return 0;
 181                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 182                         *stolen_size = MB(8) - KB(132);
 183                         return 0;
 184                 case INTEL_830_GMCH_GMS_LOCAL:
 185                         ERR_MSG("only local memory found\n");
 186                         return 1;
 187                 case INTEL_830_GMCH_GMS_DISABLED:
 188                         ERR_MSG("video memory is disabled\n");
 189                         return 1;
 190                 default:
 191                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 192                                 tmp & INTEL_830_GMCH_GMS_MASK);
 193                         return 1;
 194                 }
 195                 break;
 196         default:
 197                 *aperture_size = MB(128);
 198                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 199                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 200                         *stolen_size = MB(1) - KB(132);
 201                         return 0;
 202                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 203                         *stolen_size = MB(4) - KB(132);
 204                         return 0;
 205                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 206                         *stolen_size = MB(8) - KB(132);
 207                         return 0;
 208                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 209                         *stolen_size = MB(16) - KB(132);
 210                         return 0;
 211                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 212                         *stolen_size = MB(32) - KB(132);
 213                         return 0;
 214                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 215                         *stolen_size = MB(48) - KB(132);
 216                         return 0;
 217                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 218                         *stolen_size = MB(64) - KB(132);
 219                         return 0;
 220                 case INTEL_855_GMCH_GMS_DISABLED:
 221                         ERR_MSG("video memory is disabled\n");
 222                         return 0;
 223                 default:
 224                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 225                                 tmp & INTEL_855_GMCH_GMS_MASK);
 226                         return 1;
 227                 }
 228         }
 229 }
 230
 231 int
 232 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 233 {
 234         int dvo = 0;
 235
 236         if (INREG(LVDS) & PORT_ENABLE)
 237                 dvo |= LVDS_PORT;
 238         if (INREG(DVOA) & PORT_ENABLE)
 239                 dvo |= DVOA_PORT;
 240         if (INREG(DVOB) & PORT_ENABLE)
 241                 dvo |= DVOB_PORT;
 242         if (INREG(DVOC) & PORT_ENABLE)
 243                 dvo |= DVOC_PORT;
 244
 245         return dvo;
 246 }
 247
 248 const char *
 249 intelfbhw_dvo_to_string(int dvo)
 250 {
 251         if (dvo & DVOA_PORT)
 252                 return "DVO port A";
 253         else if (dvo & DVOB_PORT)
 254                 return "DVO port B";
 255         else if (dvo & DVOC_PORT)
 256                 return "DVO port C";
 257         else if (dvo & LVDS_PORT)
 258                 return "LVDS port";
 259         else
 260                 return NULL;
 261 }
 262
 263
 264 int
 265 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 266                         struct fb_var_screeninfo *var)
 267 {
 268         int bytes_per_pixel;
 269         int tmp;
 270
 271 #if VERBOSE > 0
 272         DBG_MSG("intelfbhw_validate_mode\n");
 273 #endif
 274
 275         bytes_per_pixel = var->bits_per_pixel / 8;
 276         if (bytes_per_pixel == 3)
 277                 bytes_per_pixel = 4;
 278
 279         /* Check if enough video memory. */
 280         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 281         if (tmp > dinfo->fb.size) {
 282                 WRN_MSG("Not enough video ram for mode "
 283                         "(%d KByte vs %d KByte).\n",
 284                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 285                 return 1;
 286         }
 287
 288         /* Check if x/y limits are OK. */
 289         if (var->xres - 1 > HACTIVE_MASK) {
 290                 WRN_MSG("X resolution too large (%d vs %d).\n",
 291                         var->xres, HACTIVE_MASK + 1);
 292                 return 1;
 293         }
 294         if (var->yres - 1 > VACTIVE_MASK) {
 295                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 296                         var->yres, VACTIVE_MASK + 1);
 297                 return 1;
 298         }
 299
 300         /* Check for interlaced/doublescan modes. */
 301         if (var->vmode & FB_VMODE_INTERLACED) {
 302                 WRN_MSG("Mode is interlaced.\n");
 303                 return 1;
 304         }
 305         if (var->vmode & FB_VMODE_DOUBLE) {
 306                 WRN_MSG("Mode is double-scan.\n");
 307                 return 1;
 308         }
 309
 310         /* Check if clock is OK. */
 311         tmp = 1000000000 / var->pixclock;
 312         if (tmp < MIN_CLOCK) {
 313                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 314                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 315                 return 1;
 316         }
 317         if (tmp > MAX_CLOCK) {
 318                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 319                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 320                 return 1;
 321         }
 322
 323         return 0;
 324 }
 325
 326 int
 327 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 328 {
 329         struct intelfb_info *dinfo = GET_DINFO(info);
 330         u32 offset, xoffset, yoffset;
 331
 332 #if VERBOSE > 0
 333         DBG_MSG("intelfbhw_pan_display\n");
 334 #endif
 335
 336         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 337         yoffset = var->yoffset;
 338
 339         if ((xoffset + var->xres > var->xres_virtual) ||
 340             (yoffset + var->yres > var->yres_virtual))
 341                 return -EINVAL;
 342
 343         offset = (yoffset * dinfo->pitch) +
 344                  (xoffset * var->bits_per_pixel) / 8;
 345
 346         offset += dinfo->fb.offset << 12;
 347
 348         OUTREG(DSPABASE, offset);
 349
 350         return 0;
 351 }
 352
 353 /* Blank the screen. */
 354 void
 355 intelfbhw_do_blank(int blank, struct fb_info *info)
 356 {
 357         struct intelfb_info *dinfo = GET_DINFO(info);
 358         u32 tmp;
 359
 360 #if VERBOSE > 0
 361         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 362 #endif
 363
 364         /* Turn plane A on or off */
 365         tmp = INREG(DSPACNTR);
 366         if (blank)
 367                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 368         else
 369                 tmp |= DISPPLANE_PLANE_ENABLE;
 370         OUTREG(DSPACNTR, tmp);
 371         /* Flush */
 372         tmp = INREG(DSPABASE);
 373         OUTREG(DSPABASE, tmp);
 374
 375         /* Turn off/on the HW cursor */
 376 #if VERBOSE > 0
 377         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 378 #endif
 379         if (dinfo->cursor_on) {
 380                 if (blank) {
 381                         intelfbhw_cursor_hide(dinfo);
 382                 } else {
 383                         intelfbhw_cursor_show(dinfo);
 384                 }
 385                 dinfo->cursor_on = 1;
 386         }
 387         dinfo->cursor_blanked = blank;
 388
 389         /* Set DPMS level */
 390         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 391         switch (blank) {
 392         case FB_BLANK_UNBLANK:
 393         case FB_BLANK_NORMAL:
 394                 tmp |= ADPA_DPMS_D0;
 395                 break;
 396         case FB_BLANK_VSYNC_SUSPEND:
 397                 tmp |= ADPA_DPMS_D1;
 398                 break;
 399         case FB_BLANK_HSYNC_SUSPEND:
 400                 tmp |= ADPA_DPMS_D2;
 401                 break;
 402         case FB_BLANK_POWERDOWN:
 403                 tmp |= ADPA_DPMS_D3;
 404                 break;
 405         }
 406         OUTREG(ADPA, tmp);
 407
 408         return;
 409 }
 410
 411
 412 void
 413 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 414                     unsigned red, unsigned green, unsigned blue,
 415                     unsigned transp)
 416 {
 417 #if VERBOSE > 0
 418         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 419                 regno, red, green, blue);
 420 #endif
 421
 422         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 423                           PALETTE_A : PALETTE_B;
 424
 425         OUTREG(palette_reg + (regno << 2),
 426                (red << PALETTE_8_RED_SHIFT) |
 427                (green << PALETTE_8_GREEN_SHIFT) |
 428                (blue << PALETTE_8_BLUE_SHIFT));
 429 }
 430
 431
 432 int
 433 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 434                         int flag)
 435 {
 436         int i;
 437
 438 #if VERBOSE > 0
 439         DBG_MSG("intelfbhw_read_hw_state\n");
 440 #endif
 441
 442         if (!hw || !dinfo)
 443                 return -1;
 444
 445         /* Read in as much of the HW state as possible. */
 446         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 447         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 448         hw->vga_pd = INREG(VGAPD);
 449         hw->dpll_a = INREG(DPLL_A);
 450         hw->dpll_b = INREG(DPLL_B);
 451         hw->fpa0 = INREG(FPA0);
 452         hw->fpa1 = INREG(FPA1);
 453         hw->fpb0 = INREG(FPB0);
 454         hw->fpb1 = INREG(FPB1);
 455
 456         if (flag == 1)
 457                 return flag;
 458
 459 #if 0
 460         /* This seems to be a problem with the 852GM/855GM */
 461         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 462                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 463                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 464         }
 465 #endif
 466
 467         if (flag == 2)
 468                 return flag;
 469
 470         hw->htotal_a = INREG(HTOTAL_A);
 471         hw->hblank_a = INREG(HBLANK_A);
 472         hw->hsync_a = INREG(HSYNC_A);
 473         hw->vtotal_a = INREG(VTOTAL_A);
 474         hw->vblank_a = INREG(VBLANK_A);
 475         hw->vsync_a = INREG(VSYNC_A);
 476         hw->src_size_a = INREG(SRC_SIZE_A);
 477         hw->bclrpat_a = INREG(BCLRPAT_A);
 478         hw->htotal_b = INREG(HTOTAL_B);
 479         hw->hblank_b = INREG(HBLANK_B);
 480         hw->hsync_b = INREG(HSYNC_B);
 481         hw->vtotal_b = INREG(VTOTAL_B);
 482         hw->vblank_b = INREG(VBLANK_B);
 483         hw->vsync_b = INREG(VSYNC_B);
 484         hw->src_size_b = INREG(SRC_SIZE_B);
 485         hw->bclrpat_b = INREG(BCLRPAT_B);
 486
 487         if (flag == 3)
 488                 return flag;
 489
 490         hw->adpa = INREG(ADPA);
 491         hw->dvoa = INREG(DVOA);
 492         hw->dvob = INREG(DVOB);
 493         hw->dvoc = INREG(DVOC);
 494         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 495         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 496         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 497         hw->lvds = INREG(LVDS);
 498
 499         if (flag == 4)
 500                 return flag;
 501
 502         hw->pipe_a_conf = INREG(PIPEACONF);
 503         hw->pipe_b_conf = INREG(PIPEBCONF);
 504         hw->disp_arb = INREG(DISPARB);
 505
 506         if (flag == 5)
 507                 return flag;
 508
 509         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 510         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 511         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 512         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 513
 514         if (flag == 6)
 515                 return flag;
 516
 517         for (i = 0; i < 4; i++) {
 518                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 519                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 520         }
 521
 522         if (flag == 7)
 523                 return flag;
 524
 525         hw->cursor_size = INREG(CURSOR_SIZE);
 526
 527         if (flag == 8)
 528                 return flag;
 529
 530         hw->disp_a_ctrl = INREG(DSPACNTR);
 531         hw->disp_b_ctrl = INREG(DSPBCNTR);
 532         hw->disp_a_base = INREG(DSPABASE);
 533         hw->disp_b_base = INREG(DSPBBASE);
 534         hw->disp_a_stride = INREG(DSPASTRIDE);
 535         hw->disp_b_stride = INREG(DSPBSTRIDE);
 536
 537         if (flag == 9)
 538                 return flag;
 539
 540         hw->vgacntrl = INREG(VGACNTRL);
 541
 542         if (flag == 10)
 543                 return flag;
 544
 545         hw->add_id = INREG(ADD_ID);
 546
 547         if (flag == 11)
 548                 return flag;
 549
 550         for (i = 0; i < 7; i++) {
 551                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 552                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 553                 if (i < 3)
 554                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 555         }
 556
 557         for (i = 0; i < 8; i++)
 558                 hw->fence[i] = INREG(FENCE + (i << 2));
 559
 560         hw->instpm = INREG(INSTPM);
 561         hw->mem_mode = INREG(MEM_MODE);
 562         hw->fw_blc_0 = INREG(FW_BLC_0);
 563         hw->fw_blc_1 = INREG(FW_BLC_1);
 564
 565         return 0;
 566 }
 567
 568
 569 static int calc_vclock3(int index, int m, int n, int p)
 570 {
 571         if (p == 0 || n == 0)
 572                 return 0;
 573         return PLL_REFCLK * m / n / p;
 574 }
 575
 576 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2)
 577 {
 578         switch(index)
 579         {
 580         case PLLS_I9xx:
 581                 if (p1 == 0)
 582                         return 0;
 583                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 584                          ((p1)) * (p2 ? 10 : 5)));
 585         case PLLS_I8xx:
 586         default:
 587                 return ((PLL_REFCLK * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) /
 588                          ((p1+2) * (1 << (p2 + 1)))));
 589         }
 590 }
 591
 592 void
 593 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 594 {
 595 #if REGDUMP
 596         int i, m1, m2, n, p1, p2;
 597         int index = dinfo->pll_index;
 598         DBG_MSG("intelfbhw_print_hw_state\n");
 599
 600         if (!hw || !dinfo)
 601                 return;
 602         /* Read in as much of the HW state as possible. */
 603         printk("hw state dump start\n");
 604         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 605         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 606         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 607         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 608         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 609         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 610         if (hw->vga_pd & VGAPD_0_P1_FORCE_DIV2)
 611                 p1 = 0;
 612         else
 613                 p1 = (hw->vga_pd >> VGAPD_0_P1_SHIFT) & DPLL_P1_MASK;
 614         p2 = (hw->vga_pd >> VGAPD_0_P2_SHIFT) & DPLL_P2_MASK;
 615         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 616                m1, m2, n, p1, p2);
 617         printk("        VGA0: clock is %d\n",
 618                calc_vclock(index, m1, m2, n, p1, p2));
 619
 620         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 621         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 622         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 623         if (hw->vga_pd & VGAPD_1_P1_FORCE_DIV2)
 624                 p1 = 0;
 625         else
 626                 p1 = (hw->vga_pd >> VGAPD_1_P1_SHIFT) & DPLL_P1_MASK;
 627         p2 = (hw->vga_pd >> VGAPD_1_P2_SHIFT) & DPLL_P2_MASK;
 628         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 629                m1, m2, n, p1, p2);
 630         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 631
 632         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 633         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 634         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 635         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 636         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 637         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 638
 639         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 640         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 641         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 642         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 643                 p1 = 0;
 644         else
 645                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 646         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 647         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 648                m1, m2, n, p1, p2);
 649         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 650
 651         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 652         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 653         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 654         if (hw->dpll_a & DPLL_P1_FORCE_DIV2)
 655                 p1 = 0;
 656         else
 657                 p1 = (hw->dpll_a >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 658         p2 = (hw->dpll_a >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 659         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 660                m1, m2, n, p1, p2);
 661         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2));
 662
 663 #if 0
 664         printk("        PALETTE_A:\n");
 665         for (i = 0; i < PALETTE_8_ENTRIES)
 666                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 667         printk("        PALETTE_B:\n");
 668         for (i = 0; i < PALETTE_8_ENTRIES)
 669                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 670 #endif
 671
 672         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 673         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 674         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 675         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 676         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 677         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 678         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 679         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 680         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 681         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 682         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 683         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 684         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 685         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 686         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 687         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 688
 689         printk("        ADPA:                   0x%08x\n", hw->adpa);
 690         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 691         printk("        DVOB:                   0x%08x\n", hw->dvob);
 692         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 693         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 694         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 695         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 696         printk("        LVDS:                   0x%08x\n", hw->lvds);
 697
 698         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 699         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 700         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 701
 702         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 703         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 704         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 705         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 706
 707         printk("        CURSOR_A_PALETTE:       ");
 708         for (i = 0; i < 4; i++) {
 709                 printk("0x%08x", hw->cursor_a_palette[i]);
 710                 if (i < 3)
 711                         printk(", ");
 712         }
 713         printk("\n");
 714         printk("        CURSOR_B_PALETTE:       ");
 715         for (i = 0; i < 4; i++) {
 716                 printk("0x%08x", hw->cursor_b_palette[i]);
 717                 if (i < 3)
 718                         printk(", ");
 719         }
 720         printk("\n");
 721
 722         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 723
 724         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 725         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 726         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 727         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 728         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 729         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 730
 731         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 732         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 733
 734         for (i = 0; i < 7; i++) {
 735                 printk("        SWF0%d                  0x%08x\n", i,
 736                         hw->swf0x[i]);
 737         }
 738         for (i = 0; i < 7; i++) {
 739                 printk("        SWF1%d                  0x%08x\n", i,
 740                         hw->swf1x[i]);
 741         }
 742         for (i = 0; i < 3; i++) {
 743                 printk("        SWF3%d                  0x%08x\n", i,
 744                        hw->swf3x[i]);
 745         }
 746         for (i = 0; i < 8; i++)
 747                 printk("        FENCE%d                 0x%08x\n", i,
 748                        hw->fence[i]);
 749
 750         printk("        INSTPM                  0x%08x\n", hw->instpm);
 751         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 752         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 753         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 754
 755         printk("hw state dump end\n");
 756 #endif
 757 }
 758
 759
 760
 761 /* Split the M parameter into M1 and M2. */
 762 static int
 763 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 764 {
 765         int m1, m2;
 766         int testm;
 767         /* no point optimising too much - brute force m */
 768         for (m1 = plls[index].min_m1; m1 < plls[index].max_m1+1; m1++) {
 769                 for (m2 = plls[index].min_m2; m2 < plls[index].max_m2+1; m2++) {
 770                         testm  = ( 5 * ( m1 + 2 )) + (m2 + 2);
 771                         if (testm == m) {
 772                                 *retm1 = (unsigned int)m1;
 773                                 *retm2 = (unsigned int)m2;
 774                                 return 0;
 775                         }
 776                 }
 777         }
 778         return 1;
 779 }
 780
 781 /* Split the P parameter into P1 and P2. */
 782 static int
 783 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 784 {
 785         int p1, p2;
 786
 787         if (index == PLLS_I9xx) {
 788                 switch (p) {
 789                 case 10:
 790                         p1 = 2;
 791                         p2 = 0;
 792                         break;
 793                 case 20:
 794                         p1 = 1;
 795                         p2 = 0;
 796                         break;
 797                 default:
 798                         p1 = (p / 10) + 1;
 799                         p2 = 0;
 800                         break;
 801                 }
 802
 803                 *retp1 = (unsigned int)p1;
 804                 *retp2 = (unsigned int)p2;
 805                 return 0;
 806         }
 807
 808         if (index == PLLS_I8xx) {
 809                 if (p % 4 == 0)
 810                         p2 = 1;
 811                 else
 812                         p2 = 0;
 813                 p1 = (p / (1 << (p2 + 1))) - 2;
 814                 if (p % 4 == 0 && p1 < plls[index].min_p1) {
 815                         p2 = 0;
 816                         p1 = (p / (1 << (p2 + 1))) - 2;
 817                 }
 818                 if (p1 < plls[index].min_p1 ||
 819                     p1 > plls[index].max_p1 ||
 820                     (p1 + 2) * (1 << (p2 + 1)) != p) {
 821                         return 1;
 822                 } else {
 823                         *retp1 = (unsigned int)p1;
 824                         *retp2 = (unsigned int)p2;
 825                         return 0;
 826                 }
 827         }
 828         return 1;
 829 }
 830
 831 static int
 832 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 833                 u32 *retp2, u32 *retclock)
 834 {
 835         u32 m1, m2, n, p1, p2, n1, testm;
 836         u32 f_vco, p, p_best = 0, m, f_out = 0;
 837         u32 err_max, err_target, err_best = 10000000;
 838         u32 n_best = 0, m_best = 0, f_best, f_err;
 839         u32 p_min, p_max, p_inc, div_min, div_max;
 840
 841         /* Accept 0.5% difference, but aim for 0.1% */
 842         err_max = 5 * clock / 1000;
 843         err_target = clock / 1000;
 844
 845         DBG_MSG("Clock is %d\n", clock);
 846
 847         div_max = plls[index].max_vco_freq / clock;
 848         if (index == PLLS_I9xx)
 849                 div_min = 5;
 850         else
 851                 div_min = ROUND_UP_TO(plls[index].min_vco_freq, clock) / clock;
 852
 853         if (clock <= plls[index].p_transition_clock)
 854                 p_inc = plls[index].p_inc_lo;
 855         else
 856                 p_inc = plls[index].p_inc_hi;
 857         p_min = ROUND_UP_TO(div_min, p_inc);
 858         p_max = ROUND_DOWN_TO(div_max, p_inc);
 859         if (p_min < plls[index].min_p)
 860                 p_min = plls[index].min_p;
 861         if (p_max > plls[index].max_p)
 862                 p_max = plls[index].max_p;
 863
 864         if (clock < PLL_REFCLK && index == PLLS_I9xx) {
 865                 p_min = 10;
 866                 p_max = 20;
 867                 /* this makes 640x480 work it really shouldn't
 868                    - SOMEONE WITHOUT DOCS WOZ HERE */
 869                 if (clock < 30000)
 870                         clock *= 4;
 871         }
 872
 873         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 874
 875         p = p_min;
 876         do {
 877                 if (splitp(index, p, &p1, &p2)) {
 878                         WRN_MSG("cannot split p = %d\n", p);
 879                         p += p_inc;
 880                         continue;
 881                 }
 882                 n = plls[index].min_n;
 883                 f_vco = clock * p;
 884
 885                 do {
 886                         m = ROUND_UP_TO(f_vco * n, PLL_REFCLK) / PLL_REFCLK;
 887                         if (m < plls[index].min_m)
 888                                 m = plls[index].min_m + 1;
 889                         if (m > plls[index].max_m)
 890                                 m = plls[index].max_m - 1;
 891                         for (testm = m - 1; testm <= m; testm++) {
 892                                 f_out = calc_vclock3(index, m, n, p);
 893                                 if (splitm(index, m, &m1, &m2)) {
 894                                         WRN_MSG("cannot split m = %d\n", m);
 895                                         n++;
 896                                         continue;
 897                                 }
 898                                 if (clock > f_out)
 899                                         f_err = clock - f_out;
 900                                 else/* slightly bias the error for bigger clocks */
 901                                         f_err = f_out - clock + 1;
 902
 903                                 if (f_err < err_best) {
 904                                         m_best = m;
 905                                         n_best = n;
 906                                         p_best = p;
 907                                         f_best = f_out;
 908                                         err_best = f_err;
 909                                 }
 910                         }
 911                         n++;
 912                 } while ((n <= plls[index].max_n) && (f_out >= clock));
 913                 p += p_inc;
 914         } while ((p <= p_max));
 915
 916         if (!m_best) {
 917                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 918                 return 1;
 919         }
 920         m = m_best;
 921         n = n_best;
 922         p = p_best;
 923         splitm(index, m, &m1, &m2);
 924         splitp(index, p, &p1, &p2);
 925         n1 = n - 2;
 926
 927         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 928                 "f: %d (%d), VCO: %d\n",
 929                 m, m1, m2, n, n1, p, p1, p2,
 930                 calc_vclock3(index, m, n, p),
 931                 calc_vclock(index, m1, m2, n1, p1, p2),
 932                 calc_vclock3(index, m, n, p) * p);
 933         *retm1 = m1;
 934         *retm2 = m2;
 935         *retn = n1;
 936         *retp1 = p1;
 937         *retp2 = p2;
 938         *retclock = calc_vclock(index, m1, m2, n1, p1, p2);
 939
 940         return 0;
 941 }
 942
 943 static __inline__ int
 944 check_overflow(u32 value, u32 limit, const char *description)
 945 {
 946         if (value > limit) {
 947                 WRN_MSG("%s value %d exceeds limit %d\n",
 948                         description, value, limit);
 949                 return 1;
 950         }
 951         return 0;
 952 }
 953
 954 /* It is assumed that hw is filled in with the initial state information. */
 955 int
 956 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 957                      struct fb_var_screeninfo *var)
 958 {
 959         int pipe = PIPE_A;
 960         u32 *dpll, *fp0, *fp1;
 961         u32 m1, m2, n, p1, p2, clock_target, clock;
 962         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 963         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 964         u32 vsync_pol, hsync_pol;
 965         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 966
 967         DBG_MSG("intelfbhw_mode_to_hw\n");
 968
 969         /* Disable VGA */
 970         hw->vgacntrl |= VGA_DISABLE;
 971
 972         /* Check whether pipe A or pipe B is enabled. */
 973         if (hw->pipe_a_conf & PIPECONF_ENABLE)
 974                 pipe = PIPE_A;
 975         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
 976                 pipe = PIPE_B;
 977
 978         /* Set which pipe's registers will be set. */
 979         if (pipe == PIPE_B) {
 980                 dpll = &hw->dpll_b;
 981                 fp0 = &hw->fpb0;
 982                 fp1 = &hw->fpb1;
 983                 hs = &hw->hsync_b;
 984                 hb = &hw->hblank_b;
 985                 ht = &hw->htotal_b;
 986                 vs = &hw->vsync_b;
 987                 vb = &hw->vblank_b;
 988                 vt = &hw->vtotal_b;
 989                 ss = &hw->src_size_b;
 990                 pipe_conf = &hw->pipe_b_conf;
 991         } else {
 992                 dpll = &hw->dpll_a;
 993                 fp0 = &hw->fpa0;
 994                 fp1 = &hw->fpa1;
 995                 hs = &hw->hsync_a;
 996                 hb = &hw->hblank_a;
 997                 ht = &hw->htotal_a;
 998                 vs = &hw->vsync_a;
 999                 vb = &hw->vblank_a;
1000                 vt = &hw->vtotal_a;
1001                 ss = &hw->src_size_a;
1002                 pipe_conf = &hw->pipe_a_conf;
1003         }
1004
1005         /* Use ADPA register for sync control. */
1006         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1007
1008         /* sync polarity */
1009         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1010                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1011         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1012                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1013         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1014                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1015         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1016                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1017
1018         /* Connect correct pipe to the analog port DAC */
1019         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1020         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1021
1022         /* Set DPMS state to D0 (on) */
1023         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1024         hw->adpa |= ADPA_DPMS_D0;
1025
1026         hw->adpa |= ADPA_DAC_ENABLE;
1027
1028         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1029         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1030         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1031
1032         /* Desired clock in kHz */
1033         clock_target = 1000000000 / var->pixclock;
1034
1035         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1036                             &n, &p1, &p2, &clock)) {
1037                 WRN_MSG("calc_pll_params failed\n");
1038                 return 1;
1039         }
1040
1041         /* Check for overflow. */
1042         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1043                 return 1;
1044         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1045                 return 1;
1046         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1047                 return 1;
1048         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1049                 return 1;
1050         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1051                 return 1;
1052
1053         *dpll &= ~DPLL_P1_FORCE_DIV2;
1054         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1055                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1056         *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1057         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1058                (m1 << FP_M1_DIVISOR_SHIFT) |
1059                (m2 << FP_M2_DIVISOR_SHIFT);
1060         *fp1 = *fp0;
1061
1062         hw->dvob &= ~PORT_ENABLE;
1063         hw->dvoc &= ~PORT_ENABLE;
1064
1065         /* Use display plane A. */
1066         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1067         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1068         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1069         switch (intelfb_var_to_depth(var)) {
1070         case 8:
1071                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1072                 break;
1073         case 15:
1074                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1075                 break;
1076         case 16:
1077                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1078                 break;
1079         case 24:
1080                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1081                 break;
1082         }
1083         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1084         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1085
1086         /* Set CRTC registers. */
1087         hactive = var->xres;
1088         hsync_start = hactive + var->right_margin;
1089         hsync_end = hsync_start + var->hsync_len;
1090         htotal = hsync_end + var->left_margin;
1091         hblank_start = hactive;
1092         hblank_end = htotal;
1093
1094         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1095                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1096                 hblank_end);
1097
1098         vactive = var->yres;
1099         vsync_start = vactive + var->lower_margin;
1100         vsync_end = vsync_start + var->vsync_len;
1101         vtotal = vsync_end + var->upper_margin;
1102         vblank_start = vactive;
1103         vblank_end = vtotal;
1104         vblank_end = vsync_end + 1;
1105
1106         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1107                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1108                 vblank_end);
1109
1110         /* Adjust for register values, and check for overflow. */
1111         hactive--;
1112         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1113                 return 1;
1114         hsync_start--;
1115         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1116                 return 1;
1117         hsync_end--;
1118         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1119                 return 1;
1120         htotal--;
1121         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1122                 return 1;
1123         hblank_start--;
1124         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1125                 return 1;
1126         hblank_end--;
1127         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1128                 return 1;
1129
1130         vactive--;
1131         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1132                 return 1;
1133         vsync_start--;
1134         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1135                 return 1;
1136         vsync_end--;
1137         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1138                 return 1;
1139         vtotal--;
1140         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1141                 return 1;
1142         vblank_start--;
1143         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1144                 return 1;
1145         vblank_end--;
1146         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1147                 return 1;
1148
1149         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1150         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1151               (hblank_end << HSYNCEND_SHIFT);
1152         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1153
1154         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1155         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1156               (vblank_end << VSYNCEND_SHIFT);
1157         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1158         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1159               (vactive << SRC_SIZE_VERT_SHIFT);
1160
1161         hw->disp_a_stride = var->xres_virtual * var->bits_per_pixel / 8;
1162         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1163
1164         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1165                           var->xoffset * var->bits_per_pixel / 8;
1166
1167         hw->disp_a_base += dinfo->fb.offset << 12;
1168
1169         /* Check stride alignment. */
1170         if (hw->disp_a_stride % STRIDE_ALIGNMENT != 0) {
1171                 WRN_MSG("display stride %d has bad alignment %d\n",
1172                         hw->disp_a_stride, STRIDE_ALIGNMENT);
1173                 return 1;
1174         }
1175
1176         /* Set the palette to 8-bit mode. */
1177         *pipe_conf &= ~PIPECONF_GAMMA;
1178         return 0;
1179 }
1180
1181 /* Program a (non-VGA) video mode. */
1182 int
1183 intelfbhw_program_mode(struct intelfb_info *dinfo,
1184                      const struct intelfb_hwstate *hw, int blank)
1185 {
1186         int pipe = PIPE_A;
1187         u32 tmp;
1188         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1189         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1190         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1191         u32 hsync_reg, htotal_reg, hblank_reg;
1192         u32 vsync_reg, vtotal_reg, vblank_reg;
1193         u32 src_size_reg;
1194         u32 count, tmp_val[3];
1195
1196         /* Assume single pipe, display plane A, analog CRT. */
1197
1198 #if VERBOSE > 0
1199         DBG_MSG("intelfbhw_program_mode\n");
1200 #endif
1201
1202         /* Disable VGA */
1203         tmp = INREG(VGACNTRL);
1204         tmp |= VGA_DISABLE;
1205         OUTREG(VGACNTRL, tmp);
1206
1207         /* Check whether pipe A or pipe B is enabled. */
1208         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1209                 pipe = PIPE_A;
1210         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1211                 pipe = PIPE_B;
1212
1213         dinfo->pipe = pipe;
1214
1215         if (pipe == PIPE_B) {
1216                 dpll = &hw->dpll_b;
1217                 fp0 = &hw->fpb0;
1218                 fp1 = &hw->fpb1;
1219                 pipe_conf = &hw->pipe_b_conf;
1220                 hs = &hw->hsync_b;
1221                 hb = &hw->hblank_b;
1222                 ht = &hw->htotal_b;
1223                 vs = &hw->vsync_b;
1224                 vb = &hw->vblank_b;
1225                 vt = &hw->vtotal_b;
1226                 ss = &hw->src_size_b;
1227                 dpll_reg = DPLL_B;
1228                 fp0_reg = FPB0;
1229                 fp1_reg = FPB1;
1230                 pipe_conf_reg = PIPEBCONF;
1231                 hsync_reg = HSYNC_B;
1232                 htotal_reg = HTOTAL_B;
1233                 hblank_reg = HBLANK_B;
1234                 vsync_reg = VSYNC_B;
1235                 vtotal_reg = VTOTAL_B;
1236                 vblank_reg = VBLANK_B;
1237                 src_size_reg = SRC_SIZE_B;
1238         } else {
1239                 dpll = &hw->dpll_a;
1240                 fp0 = &hw->fpa0;
1241                 fp1 = &hw->fpa1;
1242                 pipe_conf = &hw->pipe_a_conf;
1243                 hs = &hw->hsync_a;
1244                 hb = &hw->hblank_a;
1245                 ht = &hw->htotal_a;
1246                 vs = &hw->vsync_a;
1247                 vb = &hw->vblank_a;
1248                 vt = &hw->vtotal_a;
1249                 ss = &hw->src_size_a;
1250                 dpll_reg = DPLL_A;
1251                 fp0_reg = FPA0;
1252                 fp1_reg = FPA1;
1253                 pipe_conf_reg = PIPEACONF;
1254                 hsync_reg = HSYNC_A;
1255                 htotal_reg = HTOTAL_A;
1256                 hblank_reg = HBLANK_A;
1257                 vsync_reg = VSYNC_A;
1258                 vtotal_reg = VTOTAL_A;
1259                 vblank_reg = VBLANK_A;
1260                 src_size_reg = SRC_SIZE_A;
1261         }
1262
1263         /* turn off pipe */
1264         tmp = INREG(pipe_conf_reg);
1265         tmp &= ~PIPECONF_ENABLE;
1266         OUTREG(pipe_conf_reg, tmp);
1267
1268         count = 0;
1269         do {
1270           tmp_val[count%3] = INREG(0x70000);
1271           if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1272             break;
1273           count++;
1274           udelay(1);
1275           if (count % 200 == 0) {
1276             tmp = INREG(pipe_conf_reg);
1277             tmp &= ~PIPECONF_ENABLE;
1278             OUTREG(pipe_conf_reg, tmp);
1279           }
1280         } while(count < 2000);
1281
1282         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1283
1284         /* Disable planes A and B. */
1285         tmp = INREG(DSPACNTR);
1286         tmp &= ~DISPPLANE_PLANE_ENABLE;
1287         OUTREG(DSPACNTR, tmp);
1288         tmp = INREG(DSPBCNTR);
1289         tmp &= ~DISPPLANE_PLANE_ENABLE;
1290         OUTREG(DSPBCNTR, tmp);
1291
1292         /* Wait for vblank.  For now, just wait for a 50Hz cycle (20ms)) */
1293         mdelay(20);
1294
1295         /* Disable Sync */
1296         tmp = INREG(ADPA);
1297         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1298         tmp |= ADPA_DPMS_D3;
1299         OUTREG(ADPA, tmp);
1300
1301         /* do some funky magic - xyzzy */
1302         OUTREG(0x61204, 0xabcd0000);
1303
1304         /* turn off PLL */
1305         tmp = INREG(dpll_reg);
1306         dpll_reg &= ~DPLL_VCO_ENABLE;
1307         OUTREG(dpll_reg, tmp);
1308
1309         /* Set PLL parameters */
1310         OUTREG(dpll_reg, *dpll & ~DPLL_VCO_ENABLE);
1311         OUTREG(fp0_reg, *fp0);
1312         OUTREG(fp1_reg, *fp1);
1313
1314         /* Enable PLL */
1315         tmp = INREG(dpll_reg);
1316         tmp |= DPLL_VCO_ENABLE;
1317         OUTREG(dpll_reg, tmp);
1318
1319         /* Set DVOs B/C */
1320         OUTREG(DVOB, hw->dvob);
1321         OUTREG(DVOC, hw->dvoc);
1322
1323         /* undo funky magic */
1324         OUTREG(0x61204, 0x00000000);
1325
1326         /* Set ADPA */
1327         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1328         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1329
1330         /* Set pipe parameters */
1331         OUTREG(hsync_reg, *hs);
1332         OUTREG(hblank_reg, *hb);
1333         OUTREG(htotal_reg, *ht);
1334         OUTREG(vsync_reg, *vs);
1335         OUTREG(vblank_reg, *vb);
1336         OUTREG(vtotal_reg, *vt);
1337         OUTREG(src_size_reg, *ss);
1338
1339         /* Enable pipe */
1340         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1341
1342         /* Enable sync */
1343         tmp = INREG(ADPA);
1344         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1345         tmp |= ADPA_DPMS_D0;
1346         OUTREG(ADPA, tmp);
1347
1348         /* setup display plane */
1349         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1350                 /*
1351                  *      i830M errata: the display plane must be enabled
1352                  *      to allow writes to the other bits in the plane
1353                  *      control register.
1354                  */
1355                 tmp = INREG(DSPACNTR);
1356                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1357                         tmp |= DISPPLANE_PLANE_ENABLE;
1358                         OUTREG(DSPACNTR, tmp);
1359                         OUTREG(DSPACNTR,
1360                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1361                         mdelay(1);
1362               }
1363         }
1364
1365         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1366         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1367         OUTREG(DSPABASE, hw->disp_a_base);
1368
1369         /* Enable plane */
1370         if (!blank) {
1371                 tmp = INREG(DSPACNTR);
1372                 tmp |= DISPPLANE_PLANE_ENABLE;
1373                 OUTREG(DSPACNTR, tmp);
1374                 OUTREG(DSPABASE, hw->disp_a_base);
1375         }
1376
1377         return 0;
1378 }
1379
1380 /* forward declarations */
1381 static void refresh_ring(struct intelfb_info *dinfo);
1382 static void reset_state(struct intelfb_info *dinfo);
1383 static void do_flush(struct intelfb_info *dinfo);
1384
1385 static int
1386 wait_ring(struct intelfb_info *dinfo, int n)
1387 {
1388         int i = 0;
1389         unsigned long end;
1390         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1391
1392 #if VERBOSE > 0
1393         DBG_MSG("wait_ring: %d\n", n);
1394 #endif
1395
1396         end = jiffies + (HZ * 3);
1397         while (dinfo->ring_space < n) {
1398                 dinfo->ring_head = (u8 __iomem *)(INREG(PRI_RING_HEAD) &
1399                                                    RING_HEAD_MASK);
1400                 if (dinfo->ring_tail + RING_MIN_FREE <
1401                     (u32 __iomem) dinfo->ring_head)
1402                         dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1403                                 - (dinfo->ring_tail + RING_MIN_FREE);
1404                 else
1405                         dinfo->ring_space = (dinfo->ring.size +
1406                                              (u32 __iomem) dinfo->ring_head)
1407                                 - (dinfo->ring_tail + RING_MIN_FREE);
1408                 if ((u32 __iomem) dinfo->ring_head != last_head) {
1409                         end = jiffies + (HZ * 3);
1410                         last_head = (u32 __iomem) dinfo->ring_head;
1411                 }
1412                 i++;
1413                 if (time_before(end, jiffies)) {
1414                         if (!i) {
1415                                 /* Try again */
1416                                 reset_state(dinfo);
1417                                 refresh_ring(dinfo);
1418                                 do_flush(dinfo);
1419                                 end = jiffies + (HZ * 3);
1420                                 i = 1;
1421                         } else {
1422                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1423                                         dinfo->ring_space, n);
1424                                 WRN_MSG("lockup - turning off hardware "
1425                                         "acceleration\n");
1426                                 dinfo->ring_lockup = 1;
1427                                 break;
1428                         }
1429                 }
1430                 udelay(1);
1431         }
1432         return i;
1433 }
1434
1435 static void
1436 do_flush(struct intelfb_info *dinfo) {
1437         START_RING(2);
1438         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1439         OUT_RING(MI_NOOP);
1440         ADVANCE_RING();
1441 }
1442
1443 void
1444 intelfbhw_do_sync(struct intelfb_info *dinfo)
1445 {
1446 #if VERBOSE > 0
1447         DBG_MSG("intelfbhw_do_sync\n");
1448 #endif
1449
1450         if (!dinfo->accel)
1451                 return;
1452
1453         /*
1454          * Send a flush, then wait until the ring is empty.  This is what
1455          * the XFree86 driver does, and actually it doesn't seem a lot worse
1456          * than the recommended method (both have problems).
1457          */
1458         do_flush(dinfo);
1459         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1460         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1461 }
1462
1463 static void
1464 refresh_ring(struct intelfb_info *dinfo)
1465 {
1466 #if VERBOSE > 0
1467         DBG_MSG("refresh_ring\n");
1468 #endif
1469
1470         dinfo->ring_head = (u8 __iomem *) (INREG(PRI_RING_HEAD) &
1471                                            RING_HEAD_MASK);
1472         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1473         if (dinfo->ring_tail + RING_MIN_FREE < (u32 __iomem)dinfo->ring_head)
1474                 dinfo->ring_space = (u32 __iomem) dinfo->ring_head
1475                         - (dinfo->ring_tail + RING_MIN_FREE);
1476         else
1477                 dinfo->ring_space = (dinfo->ring.size +
1478                                      (u32 __iomem) dinfo->ring_head)
1479                         - (dinfo->ring_tail + RING_MIN_FREE);
1480 }
1481
1482 static void
1483 reset_state(struct intelfb_info *dinfo)
1484 {
1485         int i;
1486         u32 tmp;
1487
1488 #if VERBOSE > 0
1489         DBG_MSG("reset_state\n");
1490 #endif
1491
1492         for (i = 0; i < FENCE_NUM; i++)
1493                 OUTREG(FENCE + (i << 2), 0);
1494
1495         /* Flush the ring buffer if it's enabled. */
1496         tmp = INREG(PRI_RING_LENGTH);
1497         if (tmp & RING_ENABLE) {
1498 #if VERBOSE > 0
1499                 DBG_MSG("reset_state: ring was enabled\n");
1500 #endif
1501                 refresh_ring(dinfo);
1502                 intelfbhw_do_sync(dinfo);
1503                 DO_RING_IDLE();
1504         }
1505
1506         OUTREG(PRI_RING_LENGTH, 0);
1507         OUTREG(PRI_RING_HEAD, 0);
1508         OUTREG(PRI_RING_TAIL, 0);
1509         OUTREG(PRI_RING_START, 0);
1510 }
1511
1512 /* Stop the 2D engine, and turn off the ring buffer. */
1513 void
1514 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1515 {
1516 #if VERBOSE > 0
1517         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1518                 dinfo->ring_active);
1519 #endif
1520
1521         if (!dinfo->accel)
1522                 return;
1523
1524         dinfo->ring_active = 0;
1525         reset_state(dinfo);
1526 }
1527
1528 /*
1529  * Enable the ring buffer, and initialise the 2D engine.
1530  * It is assumed that the graphics engine has been stopped by previously
1531  * calling intelfb_2d_stop().
1532  */
1533 void
1534 intelfbhw_2d_start(struct intelfb_info *dinfo)
1535 {
1536 #if VERBOSE > 0
1537         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1538                 dinfo->accel, dinfo->ring_active);
1539 #endif
1540
1541         if (!dinfo->accel)
1542                 return;
1543
1544         /* Initialise the primary ring buffer. */
1545         OUTREG(PRI_RING_LENGTH, 0);
1546         OUTREG(PRI_RING_TAIL, 0);
1547         OUTREG(PRI_RING_HEAD, 0);
1548
1549         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1550         OUTREG(PRI_RING_LENGTH,
1551                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1552                 RING_NO_REPORT | RING_ENABLE);
1553         refresh_ring(dinfo);
1554         dinfo->ring_active = 1;
1555 }
1556
1557 /* 2D fillrect (solid fill or invert) */
1558 void
1559 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1560                       u32 color, u32 pitch, u32 bpp, u32 rop)
1561 {
1562         u32 br00, br09, br13, br14, br16;
1563
1564 #if VERBOSE > 0
1565         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1566                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1567 #endif
1568
1569         br00 = COLOR_BLT_CMD;
1570         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1571         br13 = (rop << ROP_SHIFT) | pitch;
1572         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1573         br16 = color;
1574
1575         switch (bpp) {
1576         case 8:
1577                 br13 |= COLOR_DEPTH_8;
1578                 break;
1579         case 16:
1580                 br13 |= COLOR_DEPTH_16;
1581                 break;
1582         case 32:
1583                 br13 |= COLOR_DEPTH_32;
1584                 br00 |= WRITE_ALPHA | WRITE_RGB;
1585                 break;
1586         }
1587
1588         START_RING(6);
1589         OUT_RING(br00);
1590         OUT_RING(br13);
1591         OUT_RING(br14);
1592         OUT_RING(br09);
1593         OUT_RING(br16);
1594         OUT_RING(MI_NOOP);
1595         ADVANCE_RING();
1596
1597 #if VERBOSE > 0
1598         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1599                 dinfo->ring_tail, dinfo->ring_space);
1600 #endif
1601 }
1602
1603 void
1604 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1605                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1606 {
1607         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1608
1609 #if VERBOSE > 0
1610         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1611                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1612 #endif
1613
1614         br00 = XY_SRC_COPY_BLT_CMD;
1615         br09 = dinfo->fb_start;
1616         br11 = (pitch << PITCH_SHIFT);
1617         br12 = dinfo->fb_start;
1618         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1619         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1620         br23 = ((dstx + w) << WIDTH_SHIFT) |
1621                ((dsty + h) << HEIGHT_SHIFT);
1622         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1623
1624         switch (bpp) {
1625         case 8:
1626                 br13 |= COLOR_DEPTH_8;
1627                 break;
1628         case 16:
1629                 br13 |= COLOR_DEPTH_16;
1630                 break;
1631         case 32:
1632                 br13 |= COLOR_DEPTH_32;
1633                 br00 |= WRITE_ALPHA | WRITE_RGB;
1634                 break;
1635         }
1636
1637         START_RING(8);
1638         OUT_RING(br00);
1639         OUT_RING(br13);
1640         OUT_RING(br22);
1641         OUT_RING(br23);
1642         OUT_RING(br09);
1643         OUT_RING(br26);
1644         OUT_RING(br11);
1645         OUT_RING(br12);
1646         ADVANCE_RING();
1647 }
1648
1649 int
1650 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1651                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1652 {
1653         int nbytes, ndwords, pad, tmp;
1654         u32 br00, br09, br13, br18, br19, br22, br23;
1655         int dat, ix, iy, iw;
1656         int i, j;
1657
1658 #if VERBOSE > 0
1659         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1660 #endif
1661
1662         /* size in bytes of a padded scanline */
1663         nbytes = ROUND_UP_TO(w, 16) / 8;
1664
1665         /* Total bytes of padded scanline data to write out. */
1666         nbytes = nbytes * h;
1667
1668         /*
1669          * Check if the glyph data exceeds the immediate mode limit.
1670          * It would take a large font (1K pixels) to hit this limit.
1671          */
1672         if (nbytes > MAX_MONO_IMM_SIZE)
1673                 return 0;
1674
1675         /* Src data is packaged a dword (32-bit) at a time. */
1676         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1677
1678         /*
1679          * Ring has to be padded to a quad word. But because the command starts
1680            with 7 bytes, pad only if there is an even number of ndwords
1681          */
1682         pad = !(ndwords % 2);
1683
1684         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1685         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1686         br09 = dinfo->fb_start;
1687         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1688         br18 = bg;
1689         br19 = fg;
1690         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1691         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1692
1693         switch (bpp) {
1694         case 8:
1695                 br13 |= COLOR_DEPTH_8;
1696                 break;
1697         case 16:
1698                 br13 |= COLOR_DEPTH_16;
1699                 break;
1700         case 32:
1701                 br13 |= COLOR_DEPTH_32;
1702                 br00 |= WRITE_ALPHA | WRITE_RGB;
1703                 break;
1704         }
1705
1706         START_RING(8 + ndwords);
1707         OUT_RING(br00);
1708         OUT_RING(br13);
1709         OUT_RING(br22);
1710         OUT_RING(br23);
1711         OUT_RING(br09);
1712         OUT_RING(br18);
1713         OUT_RING(br19);
1714         ix = iy = 0;
1715         iw = ROUND_UP_TO(w, 8) / 8;
1716         while (ndwords--) {
1717                 dat = 0;
1718                 for (j = 0; j < 2; ++j) {
1719                         for (i = 0; i < 2; ++i) {
1720                                 if (ix != iw || i == 0)
1721                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1722                         }
1723                         if (ix == iw && iy != (h-1)) {
1724                                 ix = 0;
1725                                 ++iy;
1726                         }
1727                 }
1728                 OUT_RING(dat);
1729         }
1730         if (pad)
1731                 OUT_RING(MI_NOOP);
1732         ADVANCE_RING();
1733
1734         return 1;
1735 }
1736
1737 /* HW cursor functions. */
1738 void
1739 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1740 {
1741         u32 tmp;
1742
1743 #if VERBOSE > 0
1744         DBG_MSG("intelfbhw_cursor_init\n");
1745 #endif
1746
1747         if (dinfo->mobile || IS_I9xx(dinfo)) {
1748                 if (!dinfo->cursor.physical)
1749                         return;
1750                 tmp = INREG(CURSOR_A_CONTROL);
1751                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1752                          CURSOR_MEM_TYPE_LOCAL |
1753                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1754                 tmp |= CURSOR_MODE_DISABLE;
1755                 OUTREG(CURSOR_A_CONTROL, tmp);
1756                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1757         } else {
1758                 tmp = INREG(CURSOR_CONTROL);
1759                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1760                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1761                 tmp = CURSOR_FORMAT_3C;
1762                 OUTREG(CURSOR_CONTROL, tmp);
1763                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1764                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1765                       (64 << CURSOR_SIZE_V_SHIFT);
1766                 OUTREG(CURSOR_SIZE, tmp);
1767         }
1768 }
1769
1770 void
1771 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1772 {
1773         u32 tmp;
1774
1775 #if VERBOSE > 0
1776         DBG_MSG("intelfbhw_cursor_hide\n");
1777 #endif
1778
1779         dinfo->cursor_on = 0;
1780         if (dinfo->mobile || IS_I9xx(dinfo)) {
1781                 if (!dinfo->cursor.physical)
1782                         return;
1783                 tmp = INREG(CURSOR_A_CONTROL);
1784                 tmp &= ~CURSOR_MODE_MASK;
1785                 tmp |= CURSOR_MODE_DISABLE;
1786                 OUTREG(CURSOR_A_CONTROL, tmp);
1787                 /* Flush changes */
1788                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1789         } else {
1790                 tmp = INREG(CURSOR_CONTROL);
1791                 tmp &= ~CURSOR_ENABLE;
1792                 OUTREG(CURSOR_CONTROL, tmp);
1793         }
1794 }
1795
1796 void
1797 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1798 {
1799         u32 tmp;
1800
1801 #if VERBOSE > 0
1802         DBG_MSG("intelfbhw_cursor_show\n");
1803 #endif
1804
1805         dinfo->cursor_on = 1;
1806
1807         if (dinfo->cursor_blanked)
1808                 return;
1809
1810         if (dinfo->mobile || IS_I9xx(dinfo)) {
1811                 if (!dinfo->cursor.physical)
1812                         return;
1813                 tmp = INREG(CURSOR_A_CONTROL);
1814                 tmp &= ~CURSOR_MODE_MASK;
1815                 tmp |= CURSOR_MODE_64_4C_AX;
1816                 OUTREG(CURSOR_A_CONTROL, tmp);
1817                 /* Flush changes */
1818                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1819         } else {
1820                 tmp = INREG(CURSOR_CONTROL);
1821                 tmp |= CURSOR_ENABLE;
1822                 OUTREG(CURSOR_CONTROL, tmp);
1823         }
1824 }
1825
1826 void
1827 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1828 {
1829         u32 tmp;
1830
1831 #if VERBOSE > 0
1832         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1833 #endif
1834
1835         /*
1836          * Sets the position.  The coordinates are assumed to already
1837          * have any offset adjusted.  Assume that the cursor is never
1838          * completely off-screen, and that x, y are always >= 0.
1839          */
1840
1841         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1842               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1843         OUTREG(CURSOR_A_POSITION, tmp);
1844
1845         if (IS_I9xx(dinfo)) {
1846                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1847         }
1848 }
1849
1850 void
1851 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1852 {
1853 #if VERBOSE > 0
1854         DBG_MSG("intelfbhw_cursor_setcolor\n");
1855 #endif
1856
1857         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1858         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1859         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1860         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1861 }
1862
1863 void
1864 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1865                       u8 *data)
1866 {
1867         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1868         int i, j, w = width / 8;
1869         int mod = width % 8, t_mask, d_mask;
1870
1871 #if VERBOSE > 0
1872         DBG_MSG("intelfbhw_cursor_load\n");
1873 #endif
1874
1875         if (!dinfo->cursor.virtual)
1876                 return;
1877
1878         t_mask = 0xff >> mod;
1879         d_mask = ~(0xff >> mod);
1880         for (i = height; i--; ) {
1881                 for (j = 0; j < w; j++) {
1882                         writeb(0x00, addr + j);
1883                         writeb(*(data++), addr + j+8);
1884                 }
1885                 if (mod) {
1886                         writeb(t_mask, addr + j);
1887                         writeb(*(data++) & d_mask, addr + j+8);
1888                 }
1889                 addr += 16;
1890         }
1891 }
1892
1893 void
1894 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1895         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1896         int i, j;
1897
1898 #if VERBOSE > 0
1899         DBG_MSG("intelfbhw_cursor_reset\n");
1900 #endif
1901
1902         if (!dinfo->cursor.virtual)
1903                 return;
1904
1905         for (i = 64; i--; ) {
1906                 for (j = 0; j < 8; j++) {
1907                         writeb(0xff, addr + j+0);
1908                         writeb(0x00, addr + j+8);
1909                 }
1910                 addr += 16;
1911         }
1912 }