SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/config.h>
  23 #include <linux/module.h>
  24 #include <linux/kernel.h>
  25 #include <linux/errno.h>
  26 #include <linux/string.h>
  27 #include <linux/mm.h>
  28 #include <linux/tty.h>
  29 #include <linux/slab.h>
  30 #include <linux/delay.h>
  31 #include <linux/fb.h>
  32 #include <linux/ioport.h>
  33 #include <linux/init.h>
  34 #include <linux/pci.h>
  35 #include <linux/vmalloc.h>
  36 #include <linux/pagemap.h>
  37
  38 #include <asm/io.h>
  39
  40 #include "intelfb.h"
  41 #include "intelfbhw.h"
  42
  43 struct pll_min_max {
  44         int min_m, max_m, min_m1, max_m1;
  45         int min_m2, max_m2, min_n, max_n;
  46         int min_p, max_p, min_p1, max_p1;
  47         int min_vco, max_vco, p_transition_clk, ref_clk;
  48         int p_inc_lo, p_inc_hi;
  49 };
  50
  51 #define PLLS_I8xx 0
  52 #define PLLS_I9xx 1
  53 #define PLLS_MAX 2
  54
  55 static struct pll_min_max plls[PLLS_MAX] = {
  56         { 108, 140, 18, 26,
  57           6, 16, 3, 16,
  58           4, 128, 0, 31,
  59           930000, 1400000, 165000, 48000,
  60           4, 2 }, //I8xx
  61
  62         { 75, 120, 10, 20,
  63           5, 9, 4, 7,
  64           5, 80, 1, 8,
  65           1400000, 2800000, 200000, 96000,
  66           10, 5 }  //I9xx
  67 };
  68
  69 int
  70 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  71 {
  72         u32 tmp;
  73         if (!pdev || !dinfo)
  74                 return 1;
  75
  76         switch (pdev->device) {
  77         case PCI_DEVICE_ID_INTEL_830M:
  78                 dinfo->name = "Intel(R) 830M";
  79                 dinfo->chipset = INTEL_830M;
  80                 dinfo->mobile = 1;
  81                 dinfo->pll_index = PLLS_I8xx;
  82                 return 0;
  83         case PCI_DEVICE_ID_INTEL_845G:
  84                 dinfo->name = "Intel(R) 845G";
  85                 dinfo->chipset = INTEL_845G;
  86                 dinfo->mobile = 0;
  87                 dinfo->pll_index = PLLS_I8xx;
  88                 return 0;
  89         case PCI_DEVICE_ID_INTEL_85XGM:
  90                 tmp = 0;
  91                 dinfo->mobile = 1;
  92                 dinfo->pll_index = PLLS_I8xx;
  93                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  94                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  95                         INTEL_85X_VARIANT_MASK) {
  96                 case INTEL_VAR_855GME:
  97                         dinfo->name = "Intel(R) 855GME";
  98                         dinfo->chipset = INTEL_855GME;
  99                         return 0;
 100                 case INTEL_VAR_855GM:
 101                         dinfo->name = "Intel(R) 855GM";
 102                         dinfo->chipset = INTEL_855GM;
 103                         return 0;
 104                 case INTEL_VAR_852GME:
 105                         dinfo->name = "Intel(R) 852GME";
 106                         dinfo->chipset = INTEL_852GME;
 107                         return 0;
 108                 case INTEL_VAR_852GM:
 109                         dinfo->name = "Intel(R) 852GM";
 110                         dinfo->chipset = INTEL_852GM;
 111                         return 0;
 112                 default:
 113                         dinfo->name = "Intel(R) 852GM/855GM";
 114                         dinfo->chipset = INTEL_85XGM;
 115                         return 0;
 116                 }
 117                 break;
 118         case PCI_DEVICE_ID_INTEL_865G:
 119                 dinfo->name = "Intel(R) 865G";
 120                 dinfo->chipset = INTEL_865G;
 121                 dinfo->mobile = 0;
 122                 dinfo->pll_index = PLLS_I8xx;
 123                 return 0;
 124         case PCI_DEVICE_ID_INTEL_915G:
 125                 dinfo->name = "Intel(R) 915G";
 126                 dinfo->chipset = INTEL_915G;
 127                 dinfo->mobile = 0;
 128                 dinfo->pll_index = PLLS_I9xx;
 129                 return 0;
 130         case PCI_DEVICE_ID_INTEL_915GM:
 131                 dinfo->name = "Intel(R) 915GM";
 132                 dinfo->chipset = INTEL_915GM;
 133                 dinfo->mobile = 1;
 134                 dinfo->pll_index = PLLS_I9xx;
 135                 return 0;
 136         case PCI_DEVICE_ID_INTEL_945G:
 137                 dinfo->name = "Intel(R) 945G";
 138                 dinfo->chipset = INTEL_945G;
 139                 dinfo->mobile = 0;
 140                 dinfo->pll_index = PLLS_I9xx;
 141                 return 0;
 142         case PCI_DEVICE_ID_INTEL_945GM:
 143                 dinfo->name = "Intel(R) 945GM";
 144                 dinfo->chipset = INTEL_945GM;
 145                 dinfo->mobile = 1;
 146                 dinfo->pll_index = PLLS_I9xx;
 147                 return 0;
 148         default:
 149                 return 1;
 150         }
 151 }
 152
 153 int
 154 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 155                      int *stolen_size)
 156 {
 157         struct pci_dev *bridge_dev;
 158         u16 tmp;
 159         int stolen_overhead;
 160
 161         if (!pdev || !aperture_size || !stolen_size)
 162                 return 1;
 163
 164         /* Find the bridge device.  It is always 0:0.0 */
 165         if (!(bridge_dev = pci_find_slot(0, PCI_DEVFN(0, 0)))) {
 166                 ERR_MSG("cannot find bridge device\n");
 167                 return 1;
 168         }
 169
 170         /* Get the fb aperture size and "stolen" memory amount. */
 171         tmp = 0;
 172         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 173         switch (pdev->device) {
 174         case PCI_DEVICE_ID_INTEL_915G:
 175         case PCI_DEVICE_ID_INTEL_915GM:
 176         case PCI_DEVICE_ID_INTEL_945G:
 177         case PCI_DEVICE_ID_INTEL_945GM:
 178                 /* 915 and 945 chipsets support a 256MB aperture.
 179                    Aperture size is determined by inspected the
 180                    base address of the aperture. */
 181                 if (pci_resource_start(pdev, 2) & 0x08000000)
 182                         *aperture_size = MB(128);
 183                 else
 184                         *aperture_size = MB(256);
 185                 break;
 186         default:
 187                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 188                         *aperture_size = MB(64);
 189                 else
 190                         *aperture_size = MB(128);
 191                 break;
 192         }
 193
 194         /* Stolen memory size is reduced by the GTT and the popup.
 195            GTT is 1K per MB of aperture size, and popup is 4K. */
 196         stolen_overhead = (*aperture_size / MB(1)) + 4;
 197         switch(pdev->device) {
 198         case PCI_DEVICE_ID_INTEL_830M:
 199         case PCI_DEVICE_ID_INTEL_845G:
 200                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 201                 case INTEL_830_GMCH_GMS_STOLEN_512:
 202                         *stolen_size = KB(512) - KB(stolen_overhead);
 203                         return 0;
 204                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 205                         *stolen_size = MB(1) - KB(stolen_overhead);
 206                         return 0;
 207                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 208                         *stolen_size = MB(8) - KB(stolen_overhead);
 209                         return 0;
 210                 case INTEL_830_GMCH_GMS_LOCAL:
 211                         ERR_MSG("only local memory found\n");
 212                         return 1;
 213                 case INTEL_830_GMCH_GMS_DISABLED:
 214                         ERR_MSG("video memory is disabled\n");
 215                         return 1;
 216                 default:
 217                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 218                                 tmp & INTEL_830_GMCH_GMS_MASK);
 219                         return 1;
 220                 }
 221                 break;
 222         default:
 223                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 224                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 225                         *stolen_size = MB(1) - KB(stolen_overhead);
 226                         return 0;
 227                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 228                         *stolen_size = MB(4) - KB(stolen_overhead);
 229                         return 0;
 230                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 231                         *stolen_size = MB(8) - KB(stolen_overhead);
 232                         return 0;
 233                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 234                         *stolen_size = MB(16) - KB(stolen_overhead);
 235                         return 0;
 236                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 237                         *stolen_size = MB(32) - KB(stolen_overhead);
 238                         return 0;
 239                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 240                         *stolen_size = MB(48) - KB(stolen_overhead);
 241                         return 0;
 242                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 243                         *stolen_size = MB(64) - KB(stolen_overhead);
 244                         return 0;
 245                 case INTEL_855_GMCH_GMS_DISABLED:
 246                         ERR_MSG("video memory is disabled\n");
 247                         return 0;
 248                 default:
 249                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 250                                 tmp & INTEL_855_GMCH_GMS_MASK);
 251                         return 1;
 252                 }
 253         }
 254 }
 255
 256 int
 257 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 258 {
 259         int dvo = 0;
 260
 261         if (INREG(LVDS) & PORT_ENABLE)
 262                 dvo |= LVDS_PORT;
 263         if (INREG(DVOA) & PORT_ENABLE)
 264                 dvo |= DVOA_PORT;
 265         if (INREG(DVOB) & PORT_ENABLE)
 266                 dvo |= DVOB_PORT;
 267         if (INREG(DVOC) & PORT_ENABLE)
 268                 dvo |= DVOC_PORT;
 269
 270         return dvo;
 271 }
 272
 273 const char *
 274 intelfbhw_dvo_to_string(int dvo)
 275 {
 276         if (dvo & DVOA_PORT)
 277                 return "DVO port A";
 278         else if (dvo & DVOB_PORT)
 279                 return "DVO port B";
 280         else if (dvo & DVOC_PORT)
 281                 return "DVO port C";
 282         else if (dvo & LVDS_PORT)
 283                 return "LVDS port";
 284         else
 285                 return NULL;
 286 }
 287
 288
 289 int
 290 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 291                         struct fb_var_screeninfo *var)
 292 {
 293         int bytes_per_pixel;
 294         int tmp;
 295
 296 #if VERBOSE > 0
 297         DBG_MSG("intelfbhw_validate_mode\n");
 298 #endif
 299
 300         bytes_per_pixel = var->bits_per_pixel / 8;
 301         if (bytes_per_pixel == 3)
 302                 bytes_per_pixel = 4;
 303
 304         /* Check if enough video memory. */
 305         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 306         if (tmp > dinfo->fb.size) {
 307                 WRN_MSG("Not enough video ram for mode "
 308                         "(%d KByte vs %d KByte).\n",
 309                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 310                 return 1;
 311         }
 312
 313         /* Check if x/y limits are OK. */
 314         if (var->xres - 1 > HACTIVE_MASK) {
 315                 WRN_MSG("X resolution too large (%d vs %d).\n",
 316                         var->xres, HACTIVE_MASK + 1);
 317                 return 1;
 318         }
 319         if (var->yres - 1 > VACTIVE_MASK) {
 320                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 321                         var->yres, VACTIVE_MASK + 1);
 322                 return 1;
 323         }
 324
 325         /* Check for interlaced/doublescan modes. */
 326         if (var->vmode & FB_VMODE_INTERLACED) {
 327                 WRN_MSG("Mode is interlaced.\n");
 328                 return 1;
 329         }
 330         if (var->vmode & FB_VMODE_DOUBLE) {
 331                 WRN_MSG("Mode is double-scan.\n");
 332                 return 1;
 333         }
 334
 335         /* Check if clock is OK. */
 336         tmp = 1000000000 / var->pixclock;
 337         if (tmp < MIN_CLOCK) {
 338                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 339                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 340                 return 1;
 341         }
 342         if (tmp > MAX_CLOCK) {
 343                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 344                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 345                 return 1;
 346         }
 347
 348         return 0;
 349 }
 350
 351 int
 352 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 353 {
 354         struct intelfb_info *dinfo = GET_DINFO(info);
 355         u32 offset, xoffset, yoffset;
 356
 357 #if VERBOSE > 0
 358         DBG_MSG("intelfbhw_pan_display\n");
 359 #endif
 360
 361         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 362         yoffset = var->yoffset;
 363
 364         if ((xoffset + var->xres > var->xres_virtual) ||
 365             (yoffset + var->yres > var->yres_virtual))
 366                 return -EINVAL;
 367
 368         offset = (yoffset * dinfo->pitch) +
 369                  (xoffset * var->bits_per_pixel) / 8;
 370
 371         offset += dinfo->fb.offset << 12;
 372
 373         OUTREG(DSPABASE, offset);
 374
 375         return 0;
 376 }
 377
 378 /* Blank the screen. */
 379 void
 380 intelfbhw_do_blank(int blank, struct fb_info *info)
 381 {
 382         struct intelfb_info *dinfo = GET_DINFO(info);
 383         u32 tmp;
 384
 385 #if VERBOSE > 0
 386         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 387 #endif
 388
 389         /* Turn plane A on or off */
 390         tmp = INREG(DSPACNTR);
 391         if (blank)
 392                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 393         else
 394                 tmp |= DISPPLANE_PLANE_ENABLE;
 395         OUTREG(DSPACNTR, tmp);
 396         /* Flush */
 397         tmp = INREG(DSPABASE);
 398         OUTREG(DSPABASE, tmp);
 399
 400         /* Turn off/on the HW cursor */
 401 #if VERBOSE > 0
 402         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 403 #endif
 404         if (dinfo->cursor_on) {
 405                 if (blank) {
 406                         intelfbhw_cursor_hide(dinfo);
 407                 } else {
 408                         intelfbhw_cursor_show(dinfo);
 409                 }
 410                 dinfo->cursor_on = 1;
 411         }
 412         dinfo->cursor_blanked = blank;
 413
 414         /* Set DPMS level */
 415         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 416         switch (blank) {
 417         case FB_BLANK_UNBLANK:
 418         case FB_BLANK_NORMAL:
 419                 tmp |= ADPA_DPMS_D0;
 420                 break;
 421         case FB_BLANK_VSYNC_SUSPEND:
 422                 tmp |= ADPA_DPMS_D1;
 423                 break;
 424         case FB_BLANK_HSYNC_SUSPEND:
 425                 tmp |= ADPA_DPMS_D2;
 426                 break;
 427         case FB_BLANK_POWERDOWN:
 428                 tmp |= ADPA_DPMS_D3;
 429                 break;
 430         }
 431         OUTREG(ADPA, tmp);
 432
 433         return;
 434 }
 435
 436
 437 void
 438 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 439                     unsigned red, unsigned green, unsigned blue,
 440                     unsigned transp)
 441 {
 442 #if VERBOSE > 0
 443         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 444                 regno, red, green, blue);
 445 #endif
 446
 447         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 448                           PALETTE_A : PALETTE_B;
 449
 450         OUTREG(palette_reg + (regno << 2),
 451                (red << PALETTE_8_RED_SHIFT) |
 452                (green << PALETTE_8_GREEN_SHIFT) |
 453                (blue << PALETTE_8_BLUE_SHIFT));
 454 }
 455
 456
 457 int
 458 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 459                         int flag)
 460 {
 461         int i;
 462
 463 #if VERBOSE > 0
 464         DBG_MSG("intelfbhw_read_hw_state\n");
 465 #endif
 466
 467         if (!hw || !dinfo)
 468                 return -1;
 469
 470         /* Read in as much of the HW state as possible. */
 471         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 472         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 473         hw->vga_pd = INREG(VGAPD);
 474         hw->dpll_a = INREG(DPLL_A);
 475         hw->dpll_b = INREG(DPLL_B);
 476         hw->fpa0 = INREG(FPA0);
 477         hw->fpa1 = INREG(FPA1);
 478         hw->fpb0 = INREG(FPB0);
 479         hw->fpb1 = INREG(FPB1);
 480
 481         if (flag == 1)
 482                 return flag;
 483
 484 #if 0
 485         /* This seems to be a problem with the 852GM/855GM */
 486         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 487                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 488                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 489         }
 490 #endif
 491
 492         if (flag == 2)
 493                 return flag;
 494
 495         hw->htotal_a = INREG(HTOTAL_A);
 496         hw->hblank_a = INREG(HBLANK_A);
 497         hw->hsync_a = INREG(HSYNC_A);
 498         hw->vtotal_a = INREG(VTOTAL_A);
 499         hw->vblank_a = INREG(VBLANK_A);
 500         hw->vsync_a = INREG(VSYNC_A);
 501         hw->src_size_a = INREG(SRC_SIZE_A);
 502         hw->bclrpat_a = INREG(BCLRPAT_A);
 503         hw->htotal_b = INREG(HTOTAL_B);
 504         hw->hblank_b = INREG(HBLANK_B);
 505         hw->hsync_b = INREG(HSYNC_B);
 506         hw->vtotal_b = INREG(VTOTAL_B);
 507         hw->vblank_b = INREG(VBLANK_B);
 508         hw->vsync_b = INREG(VSYNC_B);
 509         hw->src_size_b = INREG(SRC_SIZE_B);
 510         hw->bclrpat_b = INREG(BCLRPAT_B);
 511
 512         if (flag == 3)
 513                 return flag;
 514
 515         hw->adpa = INREG(ADPA);
 516         hw->dvoa = INREG(DVOA);
 517         hw->dvob = INREG(DVOB);
 518         hw->dvoc = INREG(DVOC);
 519         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 520         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 521         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 522         hw->lvds = INREG(LVDS);
 523
 524         if (flag == 4)
 525                 return flag;
 526
 527         hw->pipe_a_conf = INREG(PIPEACONF);
 528         hw->pipe_b_conf = INREG(PIPEBCONF);
 529         hw->disp_arb = INREG(DISPARB);
 530
 531         if (flag == 5)
 532                 return flag;
 533
 534         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 535         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 536         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 537         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 538
 539         if (flag == 6)
 540                 return flag;
 541
 542         for (i = 0; i < 4; i++) {
 543                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 544                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 545         }
 546
 547         if (flag == 7)
 548                 return flag;
 549
 550         hw->cursor_size = INREG(CURSOR_SIZE);
 551
 552         if (flag == 8)
 553                 return flag;
 554
 555         hw->disp_a_ctrl = INREG(DSPACNTR);
 556         hw->disp_b_ctrl = INREG(DSPBCNTR);
 557         hw->disp_a_base = INREG(DSPABASE);
 558         hw->disp_b_base = INREG(DSPBBASE);
 559         hw->disp_a_stride = INREG(DSPASTRIDE);
 560         hw->disp_b_stride = INREG(DSPBSTRIDE);
 561
 562         if (flag == 9)
 563                 return flag;
 564
 565         hw->vgacntrl = INREG(VGACNTRL);
 566
 567         if (flag == 10)
 568                 return flag;
 569
 570         hw->add_id = INREG(ADD_ID);
 571
 572         if (flag == 11)
 573                 return flag;
 574
 575         for (i = 0; i < 7; i++) {
 576                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 577                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 578                 if (i < 3)
 579                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 580         }
 581
 582         for (i = 0; i < 8; i++)
 583                 hw->fence[i] = INREG(FENCE + (i << 2));
 584
 585         hw->instpm = INREG(INSTPM);
 586         hw->mem_mode = INREG(MEM_MODE);
 587         hw->fw_blc_0 = INREG(FW_BLC_0);
 588         hw->fw_blc_1 = INREG(FW_BLC_1);
 589
 590         hw->hwstam = INREG16(HWSTAM);
 591         hw->ier = INREG16(IER);
 592         hw->iir = INREG16(IIR);
 593         hw->imr = INREG16(IMR);
 594
 595         return 0;
 596 }
 597
 598
 599 static int calc_vclock3(int index, int m, int n, int p)
 600 {
 601         if (p == 0 || n == 0)
 602                 return 0;
 603         return plls[index].ref_clk * m / n / p;
 604 }
 605
 606 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 607 {
 608         struct pll_min_max *pll = &plls[index];
 609         u32 m, vco, p;
 610
 611         m = (5 * (m1 + 2)) + (m2 + 2);
 612         n += 2;
 613         vco = pll->ref_clk * m / n;
 614
 615         if (index == PLLS_I8xx) {
 616                 p = ((p1 + 2) * (1 << (p2 + 1)));
 617         } else {
 618                 p = ((p1) * (p2 ? 5 : 10));
 619         }
 620         return vco / p;
 621 }
 622
 623 static void
 624 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
 625 {
 626         int p1, p2;
 627
 628         if (IS_I9XX(dinfo)) {
 629                 if (dpll & DPLL_P1_FORCE_DIV2)
 630                         p1 = 1;
 631                 else
 632                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 633
 634                 p1 = ffs(p1);
 635
 636                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 637         } else {
 638                 if (dpll & DPLL_P1_FORCE_DIV2)
 639                         p1 = 0;
 640                 else
 641                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 642                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 643         }
 644
 645         *o_p1 = p1;
 646         *o_p2 = p2;
 647 }
 648
 649
 650 void
 651 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 652 {
 653 #if REGDUMP
 654         int i, m1, m2, n, p1, p2;
 655         int index = dinfo->pll_index;
 656         DBG_MSG("intelfbhw_print_hw_state\n");
 657
 658         if (!hw || !dinfo)
 659                 return;
 660         /* Read in as much of the HW state as possible. */
 661         printk("hw state dump start\n");
 662         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 663         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 664         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 665         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 666         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 667         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 668
 669         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 670
 671         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 672                m1, m2, n, p1, p2);
 673         printk("        VGA0: clock is %d\n",
 674                calc_vclock(index, m1, m2, n, p1, p2, 0));
 675
 676         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 677         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 678         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 679
 680         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 681         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 682                m1, m2, n, p1, p2);
 683         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 684
 685         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 686         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 687         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 688         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 689         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 690         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 691
 692         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 693         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 694         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 695
 696         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 697
 698         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 699                m1, m2, n, p1, p2);
 700         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 701
 702         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 703         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 704         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 705
 706         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 707
 708         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 709                m1, m2, n, p1, p2);
 710         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 711
 712 #if 0
 713         printk("        PALETTE_A:\n");
 714         for (i = 0; i < PALETTE_8_ENTRIES)
 715                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 716         printk("        PALETTE_B:\n");
 717         for (i = 0; i < PALETTE_8_ENTRIES)
 718                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 719 #endif
 720
 721         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 722         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 723         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 724         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 725         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 726         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 727         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 728         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 729         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 730         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 731         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 732         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 733         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 734         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 735         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 736         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 737
 738         printk("        ADPA:                   0x%08x\n", hw->adpa);
 739         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 740         printk("        DVOB:                   0x%08x\n", hw->dvob);
 741         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 742         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 743         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 744         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 745         printk("        LVDS:                   0x%08x\n", hw->lvds);
 746
 747         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 748         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 749         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 750
 751         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 752         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 753         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 754         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 755
 756         printk("        CURSOR_A_PALETTE:       ");
 757         for (i = 0; i < 4; i++) {
 758                 printk("0x%08x", hw->cursor_a_palette[i]);
 759                 if (i < 3)
 760                         printk(", ");
 761         }
 762         printk("\n");
 763         printk("        CURSOR_B_PALETTE:       ");
 764         for (i = 0; i < 4; i++) {
 765                 printk("0x%08x", hw->cursor_b_palette[i]);
 766                 if (i < 3)
 767                         printk(", ");
 768         }
 769         printk("\n");
 770
 771         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 772
 773         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 774         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 775         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 776         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 777         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 778         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 779
 780         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 781         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 782
 783         for (i = 0; i < 7; i++) {
 784                 printk("        SWF0%d                  0x%08x\n", i,
 785                         hw->swf0x[i]);
 786         }
 787         for (i = 0; i < 7; i++) {
 788                 printk("        SWF1%d                  0x%08x\n", i,
 789                         hw->swf1x[i]);
 790         }
 791         for (i = 0; i < 3; i++) {
 792                 printk("        SWF3%d                  0x%08x\n", i,
 793                        hw->swf3x[i]);
 794         }
 795         for (i = 0; i < 8; i++)
 796                 printk("        FENCE%d                 0x%08x\n", i,
 797                        hw->fence[i]);
 798
 799         printk("        INSTPM                  0x%08x\n", hw->instpm);
 800         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 801         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 802         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 803
 804         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 805         printk("        IER                     0x%04x\n", hw->ier);
 806         printk("        IIR                     0x%04x\n", hw->iir);
 807         printk("        IMR                     0x%04x\n", hw->imr);
 808         printk("hw state dump end\n");
 809 #endif
 810 }
 811
 812
 813
 814 /* Split the M parameter into M1 and M2. */
 815 static int
 816 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 817 {
 818         int m1, m2;
 819         int testm;
 820         struct pll_min_max *pll = &plls[index];
 821
 822         /* no point optimising too much - brute force m */
 823         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 824                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 825                         testm = (5 * (m1 + 2)) + (m2 + 2);
 826                         if (testm == m) {
 827                                 *retm1 = (unsigned int)m1;
 828                                 *retm2 = (unsigned int)m2;
 829                                 return 0;
 830                         }
 831                 }
 832         }
 833         return 1;
 834 }
 835
 836 /* Split the P parameter into P1 and P2. */
 837 static int
 838 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 839 {
 840         int p1, p2;
 841         struct pll_min_max *pll = &plls[index];
 842
 843         if (index == PLLS_I9xx) {
 844                 p2 = (p % 10) ? 1 : 0;
 845
 846                 p1 = p / (p2 ? 5 : 10);
 847
 848                 *retp1 = (unsigned int)p1;
 849                 *retp2 = (unsigned int)p2;
 850                 return 0;
 851         }
 852
 853         if (p % 4 == 0)
 854                 p2 = 1;
 855         else
 856                 p2 = 0;
 857         p1 = (p / (1 << (p2 + 1))) - 2;
 858         if (p % 4 == 0 && p1 < pll->min_p1) {
 859                 p2 = 0;
 860                 p1 = (p / (1 << (p2 + 1))) - 2;
 861         }
 862         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 863             (p1 + 2) * (1 << (p2 + 1)) != p) {
 864                 return 1;
 865         } else {
 866                 *retp1 = (unsigned int)p1;
 867                 *retp2 = (unsigned int)p2;
 868                 return 0;
 869         }
 870 }
 871
 872 static int
 873 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 874                 u32 *retp2, u32 *retclock)
 875 {
 876         u32 m1, m2, n, p1, p2, n1, testm;
 877         u32 f_vco, p, p_best = 0, m, f_out = 0;
 878         u32 err_max, err_target, err_best = 10000000;
 879         u32 n_best = 0, m_best = 0, f_best, f_err;
 880         u32 p_min, p_max, p_inc, div_max;
 881         struct pll_min_max *pll = &plls[index];
 882
 883         /* Accept 0.5% difference, but aim for 0.1% */
 884         err_max = 5 * clock / 1000;
 885         err_target = clock / 1000;
 886
 887         DBG_MSG("Clock is %d\n", clock);
 888
 889         div_max = pll->max_vco / clock;
 890
 891         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 892         p_min = p_inc;
 893         p_max = ROUND_DOWN_TO(div_max, p_inc);
 894         if (p_min < pll->min_p)
 895                 p_min = pll->min_p;
 896         if (p_max > pll->max_p)
 897                 p_max = pll->max_p;
 898
 899         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 900
 901         p = p_min;
 902         do {
 903                 if (splitp(index, p, &p1, &p2)) {
 904                         WRN_MSG("cannot split p = %d\n", p);
 905                         p += p_inc;
 906                         continue;
 907                 }
 908                 n = pll->min_n;
 909                 f_vco = clock * p;
 910
 911                 do {
 912                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 913                         if (m < pll->min_m)
 914                                 m = pll->min_m + 1;
 915                         if (m > pll->max_m)
 916                                 m = pll->max_m - 1;
 917                         for (testm = m - 1; testm <= m; testm++) {
 918                                 f_out = calc_vclock3(index, m, n, p);
 919                                 if (splitm(index, testm, &m1, &m2)) {
 920                                         WRN_MSG("cannot split m = %d\n", m);
 921                                         n++;
 922                                         continue;
 923                                 }
 924                                 if (clock > f_out)
 925                                         f_err = clock - f_out;
 926                                 else/* slightly bias the error for bigger clocks */
 927                                         f_err = f_out - clock + 1;
 928
 929                                 if (f_err < err_best) {
 930                                         m_best = testm;
 931                                         n_best = n;
 932                                         p_best = p;
 933                                         f_best = f_out;
 934                                         err_best = f_err;
 935                                 }
 936                         }
 937                         n++;
 938                 } while ((n <= pll->max_n) && (f_out >= clock));
 939                 p += p_inc;
 940         } while ((p <= p_max));
 941
 942         if (!m_best) {
 943                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 944                 return 1;
 945         }
 946         m = m_best;
 947         n = n_best;
 948         p = p_best;
 949         splitm(index, m, &m1, &m2);
 950         splitp(index, p, &p1, &p2);
 951         n1 = n - 2;
 952
 953         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 954                 "f: %d (%d), VCO: %d\n",
 955                 m, m1, m2, n, n1, p, p1, p2,
 956                 calc_vclock3(index, m, n, p),
 957                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 958                 calc_vclock3(index, m, n, p) * p);
 959         *retm1 = m1;
 960         *retm2 = m2;
 961         *retn = n1;
 962         *retp1 = p1;
 963         *retp2 = p2;
 964         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 965
 966         return 0;
 967 }
 968
 969 static __inline__ int
 970 check_overflow(u32 value, u32 limit, const char *description)
 971 {
 972         if (value > limit) {
 973                 WRN_MSG("%s value %d exceeds limit %d\n",
 974                         description, value, limit);
 975                 return 1;
 976         }
 977         return 0;
 978 }
 979
 980 /* It is assumed that hw is filled in with the initial state information. */
 981 int
 982 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 983                      struct fb_var_screeninfo *var)
 984 {
 985         int pipe = PIPE_A;
 986         u32 *dpll, *fp0, *fp1;
 987         u32 m1, m2, n, p1, p2, clock_target, clock;
 988         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 989         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 990         u32 vsync_pol, hsync_pol;
 991         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 992         u32 stride_alignment;
 993
 994         DBG_MSG("intelfbhw_mode_to_hw\n");
 995
 996         /* Disable VGA */
 997         hw->vgacntrl |= VGA_DISABLE;
 998
 999         /* Check whether pipe A or pipe B is enabled. */
1000         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1001                 pipe = PIPE_A;
1002         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1003                 pipe = PIPE_B;
1004
1005         /* Set which pipe's registers will be set. */
1006         if (pipe == PIPE_B) {
1007                 dpll = &hw->dpll_b;
1008                 fp0 = &hw->fpb0;
1009                 fp1 = &hw->fpb1;
1010                 hs = &hw->hsync_b;
1011                 hb = &hw->hblank_b;
1012                 ht = &hw->htotal_b;
1013                 vs = &hw->vsync_b;
1014                 vb = &hw->vblank_b;
1015                 vt = &hw->vtotal_b;
1016                 ss = &hw->src_size_b;
1017                 pipe_conf = &hw->pipe_b_conf;
1018         } else {
1019                 dpll = &hw->dpll_a;
1020                 fp0 = &hw->fpa0;
1021                 fp1 = &hw->fpa1;
1022                 hs = &hw->hsync_a;
1023                 hb = &hw->hblank_a;
1024                 ht = &hw->htotal_a;
1025                 vs = &hw->vsync_a;
1026                 vb = &hw->vblank_a;
1027                 vt = &hw->vtotal_a;
1028                 ss = &hw->src_size_a;
1029                 pipe_conf = &hw->pipe_a_conf;
1030         }
1031
1032         /* Use ADPA register for sync control. */
1033         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1034
1035         /* sync polarity */
1036         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1037                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1038         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1039                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1040         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1041                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1042         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1043                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1044
1045         /* Connect correct pipe to the analog port DAC */
1046         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1047         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1048
1049         /* Set DPMS state to D0 (on) */
1050         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1051         hw->adpa |= ADPA_DPMS_D0;
1052
1053         hw->adpa |= ADPA_DAC_ENABLE;
1054
1055         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1056         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1057         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1058
1059         /* Desired clock in kHz */
1060         clock_target = 1000000000 / var->pixclock;
1061
1062         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1063                             &n, &p1, &p2, &clock)) {
1064                 WRN_MSG("calc_pll_params failed\n");
1065                 return 1;
1066         }
1067
1068         /* Check for overflow. */
1069         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1070                 return 1;
1071         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1072                 return 1;
1073         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1074                 return 1;
1075         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1076                 return 1;
1077         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1078                 return 1;
1079
1080         *dpll &= ~DPLL_P1_FORCE_DIV2;
1081         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1082                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1083
1084         if (IS_I9XX(dinfo)) {
1085                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1086                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1087         } else {
1088                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1089         }
1090
1091         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1092                (m1 << FP_M1_DIVISOR_SHIFT) |
1093                (m2 << FP_M2_DIVISOR_SHIFT);
1094         *fp1 = *fp0;
1095
1096         hw->dvob &= ~PORT_ENABLE;
1097         hw->dvoc &= ~PORT_ENABLE;
1098
1099         /* Use display plane A. */
1100         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1101         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1102         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1103         switch (intelfb_var_to_depth(var)) {
1104         case 8:
1105                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1106                 break;
1107         case 15:
1108                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1109                 break;
1110         case 16:
1111                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1112                 break;
1113         case 24:
1114                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1115                 break;
1116         }
1117         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1118         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1119
1120         /* Set CRTC registers. */
1121         hactive = var->xres;
1122         hsync_start = hactive + var->right_margin;
1123         hsync_end = hsync_start + var->hsync_len;
1124         htotal = hsync_end + var->left_margin;
1125         hblank_start = hactive;
1126         hblank_end = htotal;
1127
1128         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1129                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1130                 hblank_end);
1131
1132         vactive = var->yres;
1133         vsync_start = vactive + var->lower_margin;
1134         vsync_end = vsync_start + var->vsync_len;
1135         vtotal = vsync_end + var->upper_margin;
1136         vblank_start = vactive;
1137         vblank_end = vtotal;
1138         vblank_end = vsync_end + 1;
1139
1140         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1141                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1142                 vblank_end);
1143
1144         /* Adjust for register values, and check for overflow. */
1145         hactive--;
1146         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1147                 return 1;
1148         hsync_start--;
1149         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1150                 return 1;
1151         hsync_end--;
1152         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1153                 return 1;
1154         htotal--;
1155         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1156                 return 1;
1157         hblank_start--;
1158         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1159                 return 1;
1160         hblank_end--;
1161         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1162                 return 1;
1163
1164         vactive--;
1165         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1166                 return 1;
1167         vsync_start--;
1168         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1169                 return 1;
1170         vsync_end--;
1171         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1172                 return 1;
1173         vtotal--;
1174         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1175                 return 1;
1176         vblank_start--;
1177         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1178                 return 1;
1179         vblank_end--;
1180         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1181                 return 1;
1182
1183         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1184         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1185               (hblank_end << HSYNCEND_SHIFT);
1186         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1187
1188         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1189         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1190               (vblank_end << VSYNCEND_SHIFT);
1191         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1192         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1193               (vactive << SRC_SIZE_VERT_SHIFT);
1194
1195         hw->disp_a_stride = dinfo->pitch;
1196         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1197
1198         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1199                           var->xoffset * var->bits_per_pixel / 8;
1200
1201         hw->disp_a_base += dinfo->fb.offset << 12;
1202
1203         /* Check stride alignment. */
1204         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1205                                             STRIDE_ALIGNMENT;
1206         if (hw->disp_a_stride % stride_alignment != 0) {
1207                 WRN_MSG("display stride %d has bad alignment %d\n",
1208                         hw->disp_a_stride, stride_alignment);
1209                 return 1;
1210         }
1211
1212         /* Set the palette to 8-bit mode. */
1213         *pipe_conf &= ~PIPECONF_GAMMA;
1214         return 0;
1215 }
1216
1217 /* Program a (non-VGA) video mode. */
1218 int
1219 intelfbhw_program_mode(struct intelfb_info *dinfo,
1220                      const struct intelfb_hwstate *hw, int blank)
1221 {
1222         int pipe = PIPE_A;
1223         u32 tmp;
1224         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1225         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1226         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1227         u32 hsync_reg, htotal_reg, hblank_reg;
1228         u32 vsync_reg, vtotal_reg, vblank_reg;
1229         u32 src_size_reg;
1230         u32 count, tmp_val[3];
1231
1232         /* Assume single pipe, display plane A, analog CRT. */
1233
1234 #if VERBOSE > 0
1235         DBG_MSG("intelfbhw_program_mode\n");
1236 #endif
1237
1238         /* Disable VGA */
1239         tmp = INREG(VGACNTRL);
1240         tmp |= VGA_DISABLE;
1241         OUTREG(VGACNTRL, tmp);
1242
1243         /* Check whether pipe A or pipe B is enabled. */
1244         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1245                 pipe = PIPE_A;
1246         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1247                 pipe = PIPE_B;
1248
1249         dinfo->pipe = pipe;
1250
1251         if (pipe == PIPE_B) {
1252                 dpll = &hw->dpll_b;
1253                 fp0 = &hw->fpb0;
1254                 fp1 = &hw->fpb1;
1255                 pipe_conf = &hw->pipe_b_conf;
1256                 hs = &hw->hsync_b;
1257                 hb = &hw->hblank_b;
1258                 ht = &hw->htotal_b;
1259                 vs = &hw->vsync_b;
1260                 vb = &hw->vblank_b;
1261                 vt = &hw->vtotal_b;
1262                 ss = &hw->src_size_b;
1263                 dpll_reg = DPLL_B;
1264                 fp0_reg = FPB0;
1265                 fp1_reg = FPB1;
1266                 pipe_conf_reg = PIPEBCONF;
1267                 hsync_reg = HSYNC_B;
1268                 htotal_reg = HTOTAL_B;
1269                 hblank_reg = HBLANK_B;
1270                 vsync_reg = VSYNC_B;
1271                 vtotal_reg = VTOTAL_B;
1272                 vblank_reg = VBLANK_B;
1273                 src_size_reg = SRC_SIZE_B;
1274         } else {
1275                 dpll = &hw->dpll_a;
1276                 fp0 = &hw->fpa0;
1277                 fp1 = &hw->fpa1;
1278                 pipe_conf = &hw->pipe_a_conf;
1279                 hs = &hw->hsync_a;
1280                 hb = &hw->hblank_a;
1281                 ht = &hw->htotal_a;
1282                 vs = &hw->vsync_a;
1283                 vb = &hw->vblank_a;
1284                 vt = &hw->vtotal_a;
1285                 ss = &hw->src_size_a;
1286                 dpll_reg = DPLL_A;
1287                 fp0_reg = FPA0;
1288                 fp1_reg = FPA1;
1289                 pipe_conf_reg = PIPEACONF;
1290                 hsync_reg = HSYNC_A;
1291                 htotal_reg = HTOTAL_A;
1292                 hblank_reg = HBLANK_A;
1293                 vsync_reg = VSYNC_A;
1294                 vtotal_reg = VTOTAL_A;
1295                 vblank_reg = VBLANK_A;
1296                 src_size_reg = SRC_SIZE_A;
1297         }
1298
1299         /* turn off pipe */
1300         tmp = INREG(pipe_conf_reg);
1301         tmp &= ~PIPECONF_ENABLE;
1302         OUTREG(pipe_conf_reg, tmp);
1303
1304         count = 0;
1305         do {
1306                 tmp_val[count%3] = INREG(0x70000);
1307                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1308                         break;
1309                 count++;
1310                 udelay(1);
1311                 if (count % 200 == 0) {
1312                         tmp = INREG(pipe_conf_reg);
1313                         tmp &= ~PIPECONF_ENABLE;
1314                         OUTREG(pipe_conf_reg, tmp);
1315                 }
1316         } while(count < 2000);
1317
1318         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1319
1320         /* Disable planes A and B. */
1321         tmp = INREG(DSPACNTR);
1322         tmp &= ~DISPPLANE_PLANE_ENABLE;
1323         OUTREG(DSPACNTR, tmp);
1324         tmp = INREG(DSPBCNTR);
1325         tmp &= ~DISPPLANE_PLANE_ENABLE;
1326         OUTREG(DSPBCNTR, tmp);
1327
1328         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1329         mdelay(20);
1330
1331         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1332         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1333         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1334
1335         /* Disable Sync */
1336         tmp = INREG(ADPA);
1337         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1338         tmp |= ADPA_DPMS_D3;
1339         OUTREG(ADPA, tmp);
1340
1341         /* do some funky magic - xyzzy */
1342         OUTREG(0x61204, 0xabcd0000);
1343
1344         /* turn off PLL */
1345         tmp = INREG(dpll_reg);
1346         dpll_reg &= ~DPLL_VCO_ENABLE;
1347         OUTREG(dpll_reg, tmp);
1348
1349         /* Set PLL parameters */
1350         OUTREG(fp0_reg, *fp0);
1351         OUTREG(fp1_reg, *fp1);
1352
1353         /* Enable PLL */
1354         OUTREG(dpll_reg, *dpll);
1355
1356         /* Set DVOs B/C */
1357         OUTREG(DVOB, hw->dvob);
1358         OUTREG(DVOC, hw->dvoc);
1359
1360         /* undo funky magic */
1361         OUTREG(0x61204, 0x00000000);
1362
1363         /* Set ADPA */
1364         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1365         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1366
1367         /* Set pipe parameters */
1368         OUTREG(hsync_reg, *hs);
1369         OUTREG(hblank_reg, *hb);
1370         OUTREG(htotal_reg, *ht);
1371         OUTREG(vsync_reg, *vs);
1372         OUTREG(vblank_reg, *vb);
1373         OUTREG(vtotal_reg, *vt);
1374         OUTREG(src_size_reg, *ss);
1375
1376         /* Enable pipe */
1377         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1378
1379         /* Enable sync */
1380         tmp = INREG(ADPA);
1381         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1382         tmp |= ADPA_DPMS_D0;
1383         OUTREG(ADPA, tmp);
1384
1385         /* setup display plane */
1386         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1387                 /*
1388                  *      i830M errata: the display plane must be enabled
1389                  *      to allow writes to the other bits in the plane
1390                  *      control register.
1391                  */
1392                 tmp = INREG(DSPACNTR);
1393                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1394                         tmp |= DISPPLANE_PLANE_ENABLE;
1395                         OUTREG(DSPACNTR, tmp);
1396                         OUTREG(DSPACNTR,
1397                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1398                         mdelay(1);
1399                 }
1400         }
1401
1402         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1403         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1404         OUTREG(DSPABASE, hw->disp_a_base);
1405
1406         /* Enable plane */
1407         if (!blank) {
1408                 tmp = INREG(DSPACNTR);
1409                 tmp |= DISPPLANE_PLANE_ENABLE;
1410                 OUTREG(DSPACNTR, tmp);
1411                 OUTREG(DSPABASE, hw->disp_a_base);
1412         }
1413
1414         return 0;
1415 }
1416
1417 /* forward declarations */
1418 static void refresh_ring(struct intelfb_info *dinfo);
1419 static void reset_state(struct intelfb_info *dinfo);
1420 static void do_flush(struct intelfb_info *dinfo);
1421
1422 static int
1423 wait_ring(struct intelfb_info *dinfo, int n)
1424 {
1425         int i = 0;
1426         unsigned long end;
1427         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1428
1429 #if VERBOSE > 0
1430         DBG_MSG("wait_ring: %d\n", n);
1431 #endif
1432
1433         end = jiffies + (HZ * 3);
1434         while (dinfo->ring_space < n) {
1435                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1436                 if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1437                         dinfo->ring_space = dinfo->ring_head
1438                                 - (dinfo->ring_tail + RING_MIN_FREE);
1439                 else
1440                         dinfo->ring_space = (dinfo->ring.size +
1441                                              dinfo->ring_head)
1442                                 - (dinfo->ring_tail + RING_MIN_FREE);
1443                 if (dinfo->ring_head != last_head) {
1444                         end = jiffies + (HZ * 3);
1445                         last_head = dinfo->ring_head;
1446                 }
1447                 i++;
1448                 if (time_before(end, jiffies)) {
1449                         if (!i) {
1450                                 /* Try again */
1451                                 reset_state(dinfo);
1452                                 refresh_ring(dinfo);
1453                                 do_flush(dinfo);
1454                                 end = jiffies + (HZ * 3);
1455                                 i = 1;
1456                         } else {
1457                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1458                                         dinfo->ring_space, n);
1459                                 WRN_MSG("lockup - turning off hardware "
1460                                         "acceleration\n");
1461                                 dinfo->ring_lockup = 1;
1462                                 break;
1463                         }
1464                 }
1465                 udelay(1);
1466         }
1467         return i;
1468 }
1469
1470 static void
1471 do_flush(struct intelfb_info *dinfo) {
1472         START_RING(2);
1473         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1474         OUT_RING(MI_NOOP);
1475         ADVANCE_RING();
1476 }
1477
1478 void
1479 intelfbhw_do_sync(struct intelfb_info *dinfo)
1480 {
1481 #if VERBOSE > 0
1482         DBG_MSG("intelfbhw_do_sync\n");
1483 #endif
1484
1485         if (!dinfo->accel)
1486                 return;
1487
1488         /*
1489          * Send a flush, then wait until the ring is empty.  This is what
1490          * the XFree86 driver does, and actually it doesn't seem a lot worse
1491          * than the recommended method (both have problems).
1492          */
1493         do_flush(dinfo);
1494         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1495         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1496 }
1497
1498 static void
1499 refresh_ring(struct intelfb_info *dinfo)
1500 {
1501 #if VERBOSE > 0
1502         DBG_MSG("refresh_ring\n");
1503 #endif
1504
1505         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1506         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1507         if (dinfo->ring_tail + RING_MIN_FREE < dinfo->ring_head)
1508                 dinfo->ring_space = dinfo->ring_head
1509                         - (dinfo->ring_tail + RING_MIN_FREE);
1510         else
1511                 dinfo->ring_space = (dinfo->ring.size + dinfo->ring_head)
1512                         - (dinfo->ring_tail + RING_MIN_FREE);
1513 }
1514
1515 static void
1516 reset_state(struct intelfb_info *dinfo)
1517 {
1518         int i;
1519         u32 tmp;
1520
1521 #if VERBOSE > 0
1522         DBG_MSG("reset_state\n");
1523 #endif
1524
1525         for (i = 0; i < FENCE_NUM; i++)
1526                 OUTREG(FENCE + (i << 2), 0);
1527
1528         /* Flush the ring buffer if it's enabled. */
1529         tmp = INREG(PRI_RING_LENGTH);
1530         if (tmp & RING_ENABLE) {
1531 #if VERBOSE > 0
1532                 DBG_MSG("reset_state: ring was enabled\n");
1533 #endif
1534                 refresh_ring(dinfo);
1535                 intelfbhw_do_sync(dinfo);
1536                 DO_RING_IDLE();
1537         }
1538
1539         OUTREG(PRI_RING_LENGTH, 0);
1540         OUTREG(PRI_RING_HEAD, 0);
1541         OUTREG(PRI_RING_TAIL, 0);
1542         OUTREG(PRI_RING_START, 0);
1543 }
1544
1545 /* Stop the 2D engine, and turn off the ring buffer. */
1546 void
1547 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1548 {
1549 #if VERBOSE > 0
1550         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1551                 dinfo->ring_active);
1552 #endif
1553
1554         if (!dinfo->accel)
1555                 return;
1556
1557         dinfo->ring_active = 0;
1558         reset_state(dinfo);
1559 }
1560
1561 /*
1562  * Enable the ring buffer, and initialise the 2D engine.
1563  * It is assumed that the graphics engine has been stopped by previously
1564  * calling intelfb_2d_stop().
1565  */
1566 void
1567 intelfbhw_2d_start(struct intelfb_info *dinfo)
1568 {
1569 #if VERBOSE > 0
1570         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1571                 dinfo->accel, dinfo->ring_active);
1572 #endif
1573
1574         if (!dinfo->accel)
1575                 return;
1576
1577         /* Initialise the primary ring buffer. */
1578         OUTREG(PRI_RING_LENGTH, 0);
1579         OUTREG(PRI_RING_TAIL, 0);
1580         OUTREG(PRI_RING_HEAD, 0);
1581
1582         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1583         OUTREG(PRI_RING_LENGTH,
1584                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1585                 RING_NO_REPORT | RING_ENABLE);
1586         refresh_ring(dinfo);
1587         dinfo->ring_active = 1;
1588 }
1589
1590 /* 2D fillrect (solid fill or invert) */
1591 void
1592 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1593                       u32 color, u32 pitch, u32 bpp, u32 rop)
1594 {
1595         u32 br00, br09, br13, br14, br16;
1596
1597 #if VERBOSE > 0
1598         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1599                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1600 #endif
1601
1602         br00 = COLOR_BLT_CMD;
1603         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1604         br13 = (rop << ROP_SHIFT) | pitch;
1605         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1606         br16 = color;
1607
1608         switch (bpp) {
1609         case 8:
1610                 br13 |= COLOR_DEPTH_8;
1611                 break;
1612         case 16:
1613                 br13 |= COLOR_DEPTH_16;
1614                 break;
1615         case 32:
1616                 br13 |= COLOR_DEPTH_32;
1617                 br00 |= WRITE_ALPHA | WRITE_RGB;
1618                 break;
1619         }
1620
1621         START_RING(6);
1622         OUT_RING(br00);
1623         OUT_RING(br13);
1624         OUT_RING(br14);
1625         OUT_RING(br09);
1626         OUT_RING(br16);
1627         OUT_RING(MI_NOOP);
1628         ADVANCE_RING();
1629
1630 #if VERBOSE > 0
1631         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1632                 dinfo->ring_tail, dinfo->ring_space);
1633 #endif
1634 }
1635
1636 void
1637 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1638                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1639 {
1640         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1641
1642 #if VERBOSE > 0
1643         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1644                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1645 #endif
1646
1647         br00 = XY_SRC_COPY_BLT_CMD;
1648         br09 = dinfo->fb_start;
1649         br11 = (pitch << PITCH_SHIFT);
1650         br12 = dinfo->fb_start;
1651         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1652         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1653         br23 = ((dstx + w) << WIDTH_SHIFT) |
1654                ((dsty + h) << HEIGHT_SHIFT);
1655         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1656
1657         switch (bpp) {
1658         case 8:
1659                 br13 |= COLOR_DEPTH_8;
1660                 break;
1661         case 16:
1662                 br13 |= COLOR_DEPTH_16;
1663                 break;
1664         case 32:
1665                 br13 |= COLOR_DEPTH_32;
1666                 br00 |= WRITE_ALPHA | WRITE_RGB;
1667                 break;
1668         }
1669
1670         START_RING(8);
1671         OUT_RING(br00);
1672         OUT_RING(br13);
1673         OUT_RING(br22);
1674         OUT_RING(br23);
1675         OUT_RING(br09);
1676         OUT_RING(br26);
1677         OUT_RING(br11);
1678         OUT_RING(br12);
1679         ADVANCE_RING();
1680 }
1681
1682 int
1683 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1684                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1685 {
1686         int nbytes, ndwords, pad, tmp;
1687         u32 br00, br09, br13, br18, br19, br22, br23;
1688         int dat, ix, iy, iw;
1689         int i, j;
1690
1691 #if VERBOSE > 0
1692         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1693 #endif
1694
1695         /* size in bytes of a padded scanline */
1696         nbytes = ROUND_UP_TO(w, 16) / 8;
1697
1698         /* Total bytes of padded scanline data to write out. */
1699         nbytes = nbytes * h;
1700
1701         /*
1702          * Check if the glyph data exceeds the immediate mode limit.
1703          * It would take a large font (1K pixels) to hit this limit.
1704          */
1705         if (nbytes > MAX_MONO_IMM_SIZE)
1706                 return 0;
1707
1708         /* Src data is packaged a dword (32-bit) at a time. */
1709         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1710
1711         /*
1712          * Ring has to be padded to a quad word. But because the command starts
1713            with 7 bytes, pad only if there is an even number of ndwords
1714          */
1715         pad = !(ndwords % 2);
1716
1717         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1718         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1719         br09 = dinfo->fb_start;
1720         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1721         br18 = bg;
1722         br19 = fg;
1723         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1724         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1725
1726         switch (bpp) {
1727         case 8:
1728                 br13 |= COLOR_DEPTH_8;
1729                 break;
1730         case 16:
1731                 br13 |= COLOR_DEPTH_16;
1732                 break;
1733         case 32:
1734                 br13 |= COLOR_DEPTH_32;
1735                 br00 |= WRITE_ALPHA | WRITE_RGB;
1736                 break;
1737         }
1738
1739         START_RING(8 + ndwords);
1740         OUT_RING(br00);
1741         OUT_RING(br13);
1742         OUT_RING(br22);
1743         OUT_RING(br23);
1744         OUT_RING(br09);
1745         OUT_RING(br18);
1746         OUT_RING(br19);
1747         ix = iy = 0;
1748         iw = ROUND_UP_TO(w, 8) / 8;
1749         while (ndwords--) {
1750                 dat = 0;
1751                 for (j = 0; j < 2; ++j) {
1752                         for (i = 0; i < 2; ++i) {
1753                                 if (ix != iw || i == 0)
1754                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1755                         }
1756                         if (ix == iw && iy != (h-1)) {
1757                                 ix = 0;
1758                                 ++iy;
1759                         }
1760                 }
1761                 OUT_RING(dat);
1762         }
1763         if (pad)
1764                 OUT_RING(MI_NOOP);
1765         ADVANCE_RING();
1766
1767         return 1;
1768 }
1769
1770 /* HW cursor functions. */
1771 void
1772 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1773 {
1774         u32 tmp;
1775
1776 #if VERBOSE > 0
1777         DBG_MSG("intelfbhw_cursor_init\n");
1778 #endif
1779
1780         if (dinfo->mobile || IS_I9XX(dinfo)) {
1781                 if (!dinfo->cursor.physical)
1782                         return;
1783                 tmp = INREG(CURSOR_A_CONTROL);
1784                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1785                          CURSOR_MEM_TYPE_LOCAL |
1786                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1787                 tmp |= CURSOR_MODE_DISABLE;
1788                 OUTREG(CURSOR_A_CONTROL, tmp);
1789                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1790         } else {
1791                 tmp = INREG(CURSOR_CONTROL);
1792                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1793                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1794                 tmp = CURSOR_FORMAT_3C;
1795                 OUTREG(CURSOR_CONTROL, tmp);
1796                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1797                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1798                       (64 << CURSOR_SIZE_V_SHIFT);
1799                 OUTREG(CURSOR_SIZE, tmp);
1800         }
1801 }
1802
1803 void
1804 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1805 {
1806         u32 tmp;
1807
1808 #if VERBOSE > 0
1809         DBG_MSG("intelfbhw_cursor_hide\n");
1810 #endif
1811
1812         dinfo->cursor_on = 0;
1813         if (dinfo->mobile || IS_I9XX(dinfo)) {
1814                 if (!dinfo->cursor.physical)
1815                         return;
1816                 tmp = INREG(CURSOR_A_CONTROL);
1817                 tmp &= ~CURSOR_MODE_MASK;
1818                 tmp |= CURSOR_MODE_DISABLE;
1819                 OUTREG(CURSOR_A_CONTROL, tmp);
1820                 /* Flush changes */
1821                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1822         } else {
1823                 tmp = INREG(CURSOR_CONTROL);
1824                 tmp &= ~CURSOR_ENABLE;
1825                 OUTREG(CURSOR_CONTROL, tmp);
1826         }
1827 }
1828
1829 void
1830 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1831 {
1832         u32 tmp;
1833
1834 #if VERBOSE > 0
1835         DBG_MSG("intelfbhw_cursor_show\n");
1836 #endif
1837
1838         dinfo->cursor_on = 1;
1839
1840         if (dinfo->cursor_blanked)
1841                 return;
1842
1843         if (dinfo->mobile || IS_I9XX(dinfo)) {
1844                 if (!dinfo->cursor.physical)
1845                         return;
1846                 tmp = INREG(CURSOR_A_CONTROL);
1847                 tmp &= ~CURSOR_MODE_MASK;
1848                 tmp |= CURSOR_MODE_64_4C_AX;
1849                 OUTREG(CURSOR_A_CONTROL, tmp);
1850                 /* Flush changes */
1851                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1852         } else {
1853                 tmp = INREG(CURSOR_CONTROL);
1854                 tmp |= CURSOR_ENABLE;
1855                 OUTREG(CURSOR_CONTROL, tmp);
1856         }
1857 }
1858
1859 void
1860 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1861 {
1862         u32 tmp;
1863
1864 #if VERBOSE > 0
1865         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1866 #endif
1867
1868         /*
1869          * Sets the position. The coordinates are assumed to already
1870          * have any offset adjusted. Assume that the cursor is never
1871          * completely off-screen, and that x, y are always >= 0.
1872          */
1873
1874         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1875               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1876         OUTREG(CURSOR_A_POSITION, tmp);
1877
1878         if (IS_I9XX(dinfo)) {
1879                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1880         }
1881 }
1882
1883 void
1884 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1885 {
1886 #if VERBOSE > 0
1887         DBG_MSG("intelfbhw_cursor_setcolor\n");
1888 #endif
1889
1890         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1891         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1892         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1893         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1894 }
1895
1896 void
1897 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1898                       u8 *data)
1899 {
1900         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1901         int i, j, w = width / 8;
1902         int mod = width % 8, t_mask, d_mask;
1903
1904 #if VERBOSE > 0
1905         DBG_MSG("intelfbhw_cursor_load\n");
1906 #endif
1907
1908         if (!dinfo->cursor.virtual)
1909                 return;
1910
1911         t_mask = 0xff >> mod;
1912         d_mask = ~(0xff >> mod);
1913         for (i = height; i--; ) {
1914                 for (j = 0; j < w; j++) {
1915                         writeb(0x00, addr + j);
1916                         writeb(*(data++), addr + j+8);
1917                 }
1918                 if (mod) {
1919                         writeb(t_mask, addr + j);
1920                         writeb(*(data++) & d_mask, addr + j+8);
1921                 }
1922                 addr += 16;
1923         }
1924 }
1925
1926 void
1927 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1928         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1929         int i, j;
1930
1931 #if VERBOSE > 0
1932         DBG_MSG("intelfbhw_cursor_reset\n");
1933 #endif
1934
1935         if (!dinfo->cursor.virtual)
1936                 return;
1937
1938         for (i = 64; i--; ) {
1939                 for (j = 0; j < 8; j++) {
1940                         writeb(0xff, addr + j+0);
1941                         writeb(0x00, addr + j+8);
1942                 }
1943                 addr += 16;
1944         }
1945 }