SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/intelfb/intelfbhw.c

   1 /*
   2  * intelfb
   3  *
   4  * Linux framebuffer driver for Intel(R) 865G integrated graphics chips.
   5  *
   6  * Copyright © 2002, 2003 David Dawes <dawes@xfree86.org>
   7  *                   2004 Sylvain Meyer
   8  *
   9  * This driver consists of two parts.  The first part (intelfbdrv.c) provides
  10  * the basic fbdev interfaces, is derived in part from the radeonfb and
  11  * vesafb drivers, and is covered by the GPL.  The second part (intelfbhw.c)
  12  * provides the code to program the hardware.  Most of it is derived from
  13  * the i810/i830 XFree86 driver.  The HW-specific code is covered here
  14  * under a dual license (GPL and MIT/XFree86 license).
  15  *
  16  * Author: David Dawes
  17  *
  18  */
  19
  20 /* $DHD: intelfb/intelfbhw.c,v 1.9 2003/06/27 15:06:25 dawes Exp $ */
  21
  22 #include <linux/module.h>
  23 #include <linux/kernel.h>
  24 #include <linux/errno.h>
  25 #include <linux/string.h>
  26 #include <linux/mm.h>
  27 #include <linux/slab.h>
  28 #include <linux/delay.h>
  29 #include <linux/fb.h>
  30 #include <linux/ioport.h>
  31 #include <linux/init.h>
  32 #include <linux/pci.h>
  33 #include <linux/vmalloc.h>
  34 #include <linux/pagemap.h>
  35 #include <linux/interrupt.h>
  36
  37 #include <asm/io.h>
  38
  39 #include "intelfb.h"
  40 #include "intelfbhw.h"
  41
  42 struct pll_min_max {
  43         int min_m, max_m, min_m1, max_m1;
  44         int min_m2, max_m2, min_n, max_n;
  45         int min_p, max_p, min_p1, max_p1;
  46         int min_vco, max_vco, p_transition_clk, ref_clk;
  47         int p_inc_lo, p_inc_hi;
  48 };
  49
  50 #define PLLS_I8xx 0
  51 #define PLLS_I9xx 1
  52 #define PLLS_MAX 2
  53
  54 static struct pll_min_max plls[PLLS_MAX] = {
  55         { 108, 140, 18, 26,
  56           6, 16, 3, 16,
  57           4, 128, 0, 31,
  58           930000, 1400000, 165000, 48000,
  59           4, 2 }, //I8xx
  60
  61         { 75, 120, 10, 20,
  62           5, 9, 4, 7,
  63           5, 80, 1, 8,
  64           1400000, 2800000, 200000, 96000,
  65           10, 5 }  //I9xx
  66 };
  67
  68 int
  69 intelfbhw_get_chipset(struct pci_dev *pdev, struct intelfb_info *dinfo)
  70 {
  71         u32 tmp;
  72         if (!pdev || !dinfo)
  73                 return 1;
  74
  75         switch (pdev->device) {
  76         case PCI_DEVICE_ID_INTEL_830M:
  77                 dinfo->name = "Intel(R) 830M";
  78                 dinfo->chipset = INTEL_830M;
  79                 dinfo->mobile = 1;
  80                 dinfo->pll_index = PLLS_I8xx;
  81                 return 0;
  82         case PCI_DEVICE_ID_INTEL_845G:
  83                 dinfo->name = "Intel(R) 845G";
  84                 dinfo->chipset = INTEL_845G;
  85                 dinfo->mobile = 0;
  86                 dinfo->pll_index = PLLS_I8xx;
  87                 return 0;
  88         case PCI_DEVICE_ID_INTEL_85XGM:
  89                 tmp = 0;
  90                 dinfo->mobile = 1;
  91                 dinfo->pll_index = PLLS_I8xx;
  92                 pci_read_config_dword(pdev, INTEL_85X_CAPID, &tmp);
  93                 switch ((tmp >> INTEL_85X_VARIANT_SHIFT) &
  94                         INTEL_85X_VARIANT_MASK) {
  95                 case INTEL_VAR_855GME:
  96                         dinfo->name = "Intel(R) 855GME";
  97                         dinfo->chipset = INTEL_855GME;
  98                         return 0;
  99                 case INTEL_VAR_855GM:
 100                         dinfo->name = "Intel(R) 855GM";
 101                         dinfo->chipset = INTEL_855GM;
 102                         return 0;
 103                 case INTEL_VAR_852GME:
 104                         dinfo->name = "Intel(R) 852GME";
 105                         dinfo->chipset = INTEL_852GME;
 106                         return 0;
 107                 case INTEL_VAR_852GM:
 108                         dinfo->name = "Intel(R) 852GM";
 109                         dinfo->chipset = INTEL_852GM;
 110                         return 0;
 111                 default:
 112                         dinfo->name = "Intel(R) 852GM/855GM";
 113                         dinfo->chipset = INTEL_85XGM;
 114                         return 0;
 115                 }
 116                 break;
 117         case PCI_DEVICE_ID_INTEL_865G:
 118                 dinfo->name = "Intel(R) 865G";
 119                 dinfo->chipset = INTEL_865G;
 120                 dinfo->mobile = 0;
 121                 dinfo->pll_index = PLLS_I8xx;
 122                 return 0;
 123         case PCI_DEVICE_ID_INTEL_915G:
 124                 dinfo->name = "Intel(R) 915G";
 125                 dinfo->chipset = INTEL_915G;
 126                 dinfo->mobile = 0;
 127                 dinfo->pll_index = PLLS_I9xx;
 128                 return 0;
 129         case PCI_DEVICE_ID_INTEL_915GM:
 130                 dinfo->name = "Intel(R) 915GM";
 131                 dinfo->chipset = INTEL_915GM;
 132                 dinfo->mobile = 1;
 133                 dinfo->pll_index = PLLS_I9xx;
 134                 return 0;
 135         case PCI_DEVICE_ID_INTEL_945G:
 136                 dinfo->name = "Intel(R) 945G";
 137                 dinfo->chipset = INTEL_945G;
 138                 dinfo->mobile = 0;
 139                 dinfo->pll_index = PLLS_I9xx;
 140                 return 0;
 141         case PCI_DEVICE_ID_INTEL_945GM:
 142                 dinfo->name = "Intel(R) 945GM";
 143                 dinfo->chipset = INTEL_945GM;
 144                 dinfo->mobile = 1;
 145                 dinfo->pll_index = PLLS_I9xx;
 146                 return 0;
 147         default:
 148                 return 1;
 149         }
 150 }
 151
 152 int
 153 intelfbhw_get_memory(struct pci_dev *pdev, int *aperture_size,
 154                      int *stolen_size)
 155 {
 156         struct pci_dev *bridge_dev;
 157         u16 tmp;
 158         int stolen_overhead;
 159
 160         if (!pdev || !aperture_size || !stolen_size)
 161                 return 1;
 162
 163         /* Find the bridge device.  It is always 0:0.0 */
 164         if (!(bridge_dev = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0)))) {
 165                 ERR_MSG("cannot find bridge device\n");
 166                 return 1;
 167         }
 168
 169         /* Get the fb aperture size and "stolen" memory amount. */
 170         tmp = 0;
 171         pci_read_config_word(bridge_dev, INTEL_GMCH_CTRL, &tmp);
 172         pci_dev_put(bridge_dev);
 173
 174         switch (pdev->device) {
 175         case PCI_DEVICE_ID_INTEL_915G:
 176         case PCI_DEVICE_ID_INTEL_915GM:
 177         case PCI_DEVICE_ID_INTEL_945G:
 178         case PCI_DEVICE_ID_INTEL_945GM:
 179                 /* 915 and 945 chipsets support a 256MB aperture.
 180                    Aperture size is determined by inspected the
 181                    base address of the aperture. */
 182                 if (pci_resource_start(pdev, 2) & 0x08000000)
 183                         *aperture_size = MB(128);
 184                 else
 185                         *aperture_size = MB(256);
 186                 break;
 187         default:
 188                 if ((tmp & INTEL_GMCH_MEM_MASK) == INTEL_GMCH_MEM_64M)
 189                         *aperture_size = MB(64);
 190                 else
 191                         *aperture_size = MB(128);
 192                 break;
 193         }
 194
 195         /* Stolen memory size is reduced by the GTT and the popup.
 196            GTT is 1K per MB of aperture size, and popup is 4K. */
 197         stolen_overhead = (*aperture_size / MB(1)) + 4;
 198         switch(pdev->device) {
 199         case PCI_DEVICE_ID_INTEL_830M:
 200         case PCI_DEVICE_ID_INTEL_845G:
 201                 switch (tmp & INTEL_830_GMCH_GMS_MASK) {
 202                 case INTEL_830_GMCH_GMS_STOLEN_512:
 203                         *stolen_size = KB(512) - KB(stolen_overhead);
 204                         return 0;
 205                 case INTEL_830_GMCH_GMS_STOLEN_1024:
 206                         *stolen_size = MB(1) - KB(stolen_overhead);
 207                         return 0;
 208                 case INTEL_830_GMCH_GMS_STOLEN_8192:
 209                         *stolen_size = MB(8) - KB(stolen_overhead);
 210                         return 0;
 211                 case INTEL_830_GMCH_GMS_LOCAL:
 212                         ERR_MSG("only local memory found\n");
 213                         return 1;
 214                 case INTEL_830_GMCH_GMS_DISABLED:
 215                         ERR_MSG("video memory is disabled\n");
 216                         return 1;
 217                 default:
 218                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 219                                 tmp & INTEL_830_GMCH_GMS_MASK);
 220                         return 1;
 221                 }
 222                 break;
 223         default:
 224                 switch (tmp & INTEL_855_GMCH_GMS_MASK) {
 225                 case INTEL_855_GMCH_GMS_STOLEN_1M:
 226                         *stolen_size = MB(1) - KB(stolen_overhead);
 227                         return 0;
 228                 case INTEL_855_GMCH_GMS_STOLEN_4M:
 229                         *stolen_size = MB(4) - KB(stolen_overhead);
 230                         return 0;
 231                 case INTEL_855_GMCH_GMS_STOLEN_8M:
 232                         *stolen_size = MB(8) - KB(stolen_overhead);
 233                         return 0;
 234                 case INTEL_855_GMCH_GMS_STOLEN_16M:
 235                         *stolen_size = MB(16) - KB(stolen_overhead);
 236                         return 0;
 237                 case INTEL_855_GMCH_GMS_STOLEN_32M:
 238                         *stolen_size = MB(32) - KB(stolen_overhead);
 239                         return 0;
 240                 case INTEL_915G_GMCH_GMS_STOLEN_48M:
 241                         *stolen_size = MB(48) - KB(stolen_overhead);
 242                         return 0;
 243                 case INTEL_915G_GMCH_GMS_STOLEN_64M:
 244                         *stolen_size = MB(64) - KB(stolen_overhead);
 245                         return 0;
 246                 case INTEL_855_GMCH_GMS_DISABLED:
 247                         ERR_MSG("video memory is disabled\n");
 248                         return 0;
 249                 default:
 250                         ERR_MSG("unexpected GMCH_GMS value: 0x%02x\n",
 251                                 tmp & INTEL_855_GMCH_GMS_MASK);
 252                         return 1;
 253                 }
 254         }
 255 }
 256
 257 int
 258 intelfbhw_check_non_crt(struct intelfb_info *dinfo)
 259 {
 260         int dvo = 0;
 261
 262         if (INREG(LVDS) & PORT_ENABLE)
 263                 dvo |= LVDS_PORT;
 264         if (INREG(DVOA) & PORT_ENABLE)
 265                 dvo |= DVOA_PORT;
 266         if (INREG(DVOB) & PORT_ENABLE)
 267                 dvo |= DVOB_PORT;
 268         if (INREG(DVOC) & PORT_ENABLE)
 269                 dvo |= DVOC_PORT;
 270
 271         return dvo;
 272 }
 273
 274 const char *
 275 intelfbhw_dvo_to_string(int dvo)
 276 {
 277         if (dvo & DVOA_PORT)
 278                 return "DVO port A";
 279         else if (dvo & DVOB_PORT)
 280                 return "DVO port B";
 281         else if (dvo & DVOC_PORT)
 282                 return "DVO port C";
 283         else if (dvo & LVDS_PORT)
 284                 return "LVDS port";
 285         else
 286                 return NULL;
 287 }
 288
 289
 290 int
 291 intelfbhw_validate_mode(struct intelfb_info *dinfo,
 292                         struct fb_var_screeninfo *var)
 293 {
 294         int bytes_per_pixel;
 295         int tmp;
 296
 297 #if VERBOSE > 0
 298         DBG_MSG("intelfbhw_validate_mode\n");
 299 #endif
 300
 301         bytes_per_pixel = var->bits_per_pixel / 8;
 302         if (bytes_per_pixel == 3)
 303                 bytes_per_pixel = 4;
 304
 305         /* Check if enough video memory. */
 306         tmp = var->yres_virtual * var->xres_virtual * bytes_per_pixel;
 307         if (tmp > dinfo->fb.size) {
 308                 WRN_MSG("Not enough video ram for mode "
 309                         "(%d KByte vs %d KByte).\n",
 310                         BtoKB(tmp), BtoKB(dinfo->fb.size));
 311                 return 1;
 312         }
 313
 314         /* Check if x/y limits are OK. */
 315         if (var->xres - 1 > HACTIVE_MASK) {
 316                 WRN_MSG("X resolution too large (%d vs %d).\n",
 317                         var->xres, HACTIVE_MASK + 1);
 318                 return 1;
 319         }
 320         if (var->yres - 1 > VACTIVE_MASK) {
 321                 WRN_MSG("Y resolution too large (%d vs %d).\n",
 322                         var->yres, VACTIVE_MASK + 1);
 323                 return 1;
 324         }
 325
 326         /* Check for doublescan modes. */
 327         if (var->vmode & FB_VMODE_DOUBLE) {
 328                 WRN_MSG("Mode is double-scan.\n");
 329                 return 1;
 330         }
 331
 332         /* Check if clock is OK. */
 333         tmp = 1000000000 / var->pixclock;
 334         if (tmp < MIN_CLOCK) {
 335                 WRN_MSG("Pixel clock is too low (%d MHz vs %d MHz).\n",
 336                         (tmp + 500) / 1000, MIN_CLOCK / 1000);
 337                 return 1;
 338         }
 339         if (tmp > MAX_CLOCK) {
 340                 WRN_MSG("Pixel clock is too high (%d MHz vs %d MHz).\n",
 341                         (tmp + 500) / 1000, MAX_CLOCK / 1000);
 342                 return 1;
 343         }
 344
 345         return 0;
 346 }
 347
 348 int
 349 intelfbhw_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
 350 {
 351         struct intelfb_info *dinfo = GET_DINFO(info);
 352         u32 offset, xoffset, yoffset;
 353
 354 #if VERBOSE > 0
 355         DBG_MSG("intelfbhw_pan_display\n");
 356 #endif
 357
 358         xoffset = ROUND_DOWN_TO(var->xoffset, 8);
 359         yoffset = var->yoffset;
 360
 361         if ((xoffset + var->xres > var->xres_virtual) ||
 362             (yoffset + var->yres > var->yres_virtual))
 363                 return -EINVAL;
 364
 365         offset = (yoffset * dinfo->pitch) +
 366                  (xoffset * var->bits_per_pixel) / 8;
 367
 368         offset += dinfo->fb.offset << 12;
 369
 370         dinfo->vsync.pan_offset = offset;
 371         if ((var->activate & FB_ACTIVATE_VBL) && !intelfbhw_enable_irq(dinfo, 0)) {
 372                 dinfo->vsync.pan_display = 1;
 373         } else {
 374                 dinfo->vsync.pan_display = 0;
 375                 OUTREG(DSPABASE, offset);
 376         }
 377
 378         return 0;
 379 }
 380
 381 /* Blank the screen. */
 382 void
 383 intelfbhw_do_blank(int blank, struct fb_info *info)
 384 {
 385         struct intelfb_info *dinfo = GET_DINFO(info);
 386         u32 tmp;
 387
 388 #if VERBOSE > 0
 389         DBG_MSG("intelfbhw_do_blank: blank is %d\n", blank);
 390 #endif
 391
 392         /* Turn plane A on or off */
 393         tmp = INREG(DSPACNTR);
 394         if (blank)
 395                 tmp &= ~DISPPLANE_PLANE_ENABLE;
 396         else
 397                 tmp |= DISPPLANE_PLANE_ENABLE;
 398         OUTREG(DSPACNTR, tmp);
 399         /* Flush */
 400         tmp = INREG(DSPABASE);
 401         OUTREG(DSPABASE, tmp);
 402
 403         /* Turn off/on the HW cursor */
 404 #if VERBOSE > 0
 405         DBG_MSG("cursor_on is %d\n", dinfo->cursor_on);
 406 #endif
 407         if (dinfo->cursor_on) {
 408                 if (blank) {
 409                         intelfbhw_cursor_hide(dinfo);
 410                 } else {
 411                         intelfbhw_cursor_show(dinfo);
 412                 }
 413                 dinfo->cursor_on = 1;
 414         }
 415         dinfo->cursor_blanked = blank;
 416
 417         /* Set DPMS level */
 418         tmp = INREG(ADPA) & ~ADPA_DPMS_CONTROL_MASK;
 419         switch (blank) {
 420         case FB_BLANK_UNBLANK:
 421         case FB_BLANK_NORMAL:
 422                 tmp |= ADPA_DPMS_D0;
 423                 break;
 424         case FB_BLANK_VSYNC_SUSPEND:
 425                 tmp |= ADPA_DPMS_D1;
 426                 break;
 427         case FB_BLANK_HSYNC_SUSPEND:
 428                 tmp |= ADPA_DPMS_D2;
 429                 break;
 430         case FB_BLANK_POWERDOWN:
 431                 tmp |= ADPA_DPMS_D3;
 432                 break;
 433         }
 434         OUTREG(ADPA, tmp);
 435
 436         return;
 437 }
 438
 439
 440 void
 441 intelfbhw_setcolreg(struct intelfb_info *dinfo, unsigned regno,
 442                     unsigned red, unsigned green, unsigned blue,
 443                     unsigned transp)
 444 {
 445 #if VERBOSE > 0
 446         DBG_MSG("intelfbhw_setcolreg: %d: (%d, %d, %d)\n",
 447                 regno, red, green, blue);
 448 #endif
 449
 450         u32 palette_reg = (dinfo->pipe == PIPE_A) ?
 451                           PALETTE_A : PALETTE_B;
 452
 453         OUTREG(palette_reg + (regno << 2),
 454                (red << PALETTE_8_RED_SHIFT) |
 455                (green << PALETTE_8_GREEN_SHIFT) |
 456                (blue << PALETTE_8_BLUE_SHIFT));
 457 }
 458
 459
 460 int
 461 intelfbhw_read_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 462                         int flag)
 463 {
 464         int i;
 465
 466 #if VERBOSE > 0
 467         DBG_MSG("intelfbhw_read_hw_state\n");
 468 #endif
 469
 470         if (!hw || !dinfo)
 471                 return -1;
 472
 473         /* Read in as much of the HW state as possible. */
 474         hw->vga0_divisor = INREG(VGA0_DIVISOR);
 475         hw->vga1_divisor = INREG(VGA1_DIVISOR);
 476         hw->vga_pd = INREG(VGAPD);
 477         hw->dpll_a = INREG(DPLL_A);
 478         hw->dpll_b = INREG(DPLL_B);
 479         hw->fpa0 = INREG(FPA0);
 480         hw->fpa1 = INREG(FPA1);
 481         hw->fpb0 = INREG(FPB0);
 482         hw->fpb1 = INREG(FPB1);
 483
 484         if (flag == 1)
 485                 return flag;
 486
 487 #if 0
 488         /* This seems to be a problem with the 852GM/855GM */
 489         for (i = 0; i < PALETTE_8_ENTRIES; i++) {
 490                 hw->palette_a[i] = INREG(PALETTE_A + (i << 2));
 491                 hw->palette_b[i] = INREG(PALETTE_B + (i << 2));
 492         }
 493 #endif
 494
 495         if (flag == 2)
 496                 return flag;
 497
 498         hw->htotal_a = INREG(HTOTAL_A);
 499         hw->hblank_a = INREG(HBLANK_A);
 500         hw->hsync_a = INREG(HSYNC_A);
 501         hw->vtotal_a = INREG(VTOTAL_A);
 502         hw->vblank_a = INREG(VBLANK_A);
 503         hw->vsync_a = INREG(VSYNC_A);
 504         hw->src_size_a = INREG(SRC_SIZE_A);
 505         hw->bclrpat_a = INREG(BCLRPAT_A);
 506         hw->htotal_b = INREG(HTOTAL_B);
 507         hw->hblank_b = INREG(HBLANK_B);
 508         hw->hsync_b = INREG(HSYNC_B);
 509         hw->vtotal_b = INREG(VTOTAL_B);
 510         hw->vblank_b = INREG(VBLANK_B);
 511         hw->vsync_b = INREG(VSYNC_B);
 512         hw->src_size_b = INREG(SRC_SIZE_B);
 513         hw->bclrpat_b = INREG(BCLRPAT_B);
 514
 515         if (flag == 3)
 516                 return flag;
 517
 518         hw->adpa = INREG(ADPA);
 519         hw->dvoa = INREG(DVOA);
 520         hw->dvob = INREG(DVOB);
 521         hw->dvoc = INREG(DVOC);
 522         hw->dvoa_srcdim = INREG(DVOA_SRCDIM);
 523         hw->dvob_srcdim = INREG(DVOB_SRCDIM);
 524         hw->dvoc_srcdim = INREG(DVOC_SRCDIM);
 525         hw->lvds = INREG(LVDS);
 526
 527         if (flag == 4)
 528                 return flag;
 529
 530         hw->pipe_a_conf = INREG(PIPEACONF);
 531         hw->pipe_b_conf = INREG(PIPEBCONF);
 532         hw->disp_arb = INREG(DISPARB);
 533
 534         if (flag == 5)
 535                 return flag;
 536
 537         hw->cursor_a_control = INREG(CURSOR_A_CONTROL);
 538         hw->cursor_b_control = INREG(CURSOR_B_CONTROL);
 539         hw->cursor_a_base = INREG(CURSOR_A_BASEADDR);
 540         hw->cursor_b_base = INREG(CURSOR_B_BASEADDR);
 541
 542         if (flag == 6)
 543                 return flag;
 544
 545         for (i = 0; i < 4; i++) {
 546                 hw->cursor_a_palette[i] = INREG(CURSOR_A_PALETTE0 + (i << 2));
 547                 hw->cursor_b_palette[i] = INREG(CURSOR_B_PALETTE0 + (i << 2));
 548         }
 549
 550         if (flag == 7)
 551                 return flag;
 552
 553         hw->cursor_size = INREG(CURSOR_SIZE);
 554
 555         if (flag == 8)
 556                 return flag;
 557
 558         hw->disp_a_ctrl = INREG(DSPACNTR);
 559         hw->disp_b_ctrl = INREG(DSPBCNTR);
 560         hw->disp_a_base = INREG(DSPABASE);
 561         hw->disp_b_base = INREG(DSPBBASE);
 562         hw->disp_a_stride = INREG(DSPASTRIDE);
 563         hw->disp_b_stride = INREG(DSPBSTRIDE);
 564
 565         if (flag == 9)
 566                 return flag;
 567
 568         hw->vgacntrl = INREG(VGACNTRL);
 569
 570         if (flag == 10)
 571                 return flag;
 572
 573         hw->add_id = INREG(ADD_ID);
 574
 575         if (flag == 11)
 576                 return flag;
 577
 578         for (i = 0; i < 7; i++) {
 579                 hw->swf0x[i] = INREG(SWF00 + (i << 2));
 580                 hw->swf1x[i] = INREG(SWF10 + (i << 2));
 581                 if (i < 3)
 582                         hw->swf3x[i] = INREG(SWF30 + (i << 2));
 583         }
 584
 585         for (i = 0; i < 8; i++)
 586                 hw->fence[i] = INREG(FENCE + (i << 2));
 587
 588         hw->instpm = INREG(INSTPM);
 589         hw->mem_mode = INREG(MEM_MODE);
 590         hw->fw_blc_0 = INREG(FW_BLC_0);
 591         hw->fw_blc_1 = INREG(FW_BLC_1);
 592
 593         hw->hwstam = INREG16(HWSTAM);
 594         hw->ier = INREG16(IER);
 595         hw->iir = INREG16(IIR);
 596         hw->imr = INREG16(IMR);
 597
 598         return 0;
 599 }
 600
 601
 602 static int calc_vclock3(int index, int m, int n, int p)
 603 {
 604         if (p == 0 || n == 0)
 605                 return 0;
 606         return plls[index].ref_clk * m / n / p;
 607 }
 608
 609 static int calc_vclock(int index, int m1, int m2, int n, int p1, int p2, int lvds)
 610 {
 611         struct pll_min_max *pll = &plls[index];
 612         u32 m, vco, p;
 613
 614         m = (5 * (m1 + 2)) + (m2 + 2);
 615         n += 2;
 616         vco = pll->ref_clk * m / n;
 617
 618         if (index == PLLS_I8xx) {
 619                 p = ((p1 + 2) * (1 << (p2 + 1)));
 620         } else {
 621                 p = ((p1) * (p2 ? 5 : 10));
 622         }
 623         return vco / p;
 624 }
 625
 626 #if REGDUMP
 627 static void
 628 intelfbhw_get_p1p2(struct intelfb_info *dinfo, int dpll, int *o_p1, int *o_p2)
 629 {
 630         int p1, p2;
 631
 632         if (IS_I9XX(dinfo)) {
 633                 if (dpll & DPLL_P1_FORCE_DIV2)
 634                         p1 = 1;
 635                 else
 636                         p1 = (dpll >> DPLL_P1_SHIFT) & 0xff;
 637
 638                 p1 = ffs(p1);
 639
 640                 p2 = (dpll >> DPLL_I9XX_P2_SHIFT) & DPLL_P2_MASK;
 641         } else {
 642                 if (dpll & DPLL_P1_FORCE_DIV2)
 643                         p1 = 0;
 644                 else
 645                         p1 = (dpll >> DPLL_P1_SHIFT) & DPLL_P1_MASK;
 646                 p2 = (dpll >> DPLL_P2_SHIFT) & DPLL_P2_MASK;
 647         }
 648
 649         *o_p1 = p1;
 650         *o_p2 = p2;
 651 }
 652 #endif
 653
 654
 655 void
 656 intelfbhw_print_hw_state(struct intelfb_info *dinfo, struct intelfb_hwstate *hw)
 657 {
 658 #if REGDUMP
 659         int i, m1, m2, n, p1, p2;
 660         int index = dinfo->pll_index;
 661         DBG_MSG("intelfbhw_print_hw_state\n");
 662
 663         if (!hw)
 664                 return;
 665         /* Read in as much of the HW state as possible. */
 666         printk("hw state dump start\n");
 667         printk("        VGA0_DIVISOR:           0x%08x\n", hw->vga0_divisor);
 668         printk("        VGA1_DIVISOR:           0x%08x\n", hw->vga1_divisor);
 669         printk("        VGAPD:                  0x%08x\n", hw->vga_pd);
 670         n = (hw->vga0_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 671         m1 = (hw->vga0_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 672         m2 = (hw->vga0_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 673
 674         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 675
 676         printk("        VGA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 677                m1, m2, n, p1, p2);
 678         printk("        VGA0: clock is %d\n",
 679                calc_vclock(index, m1, m2, n, p1, p2, 0));
 680
 681         n = (hw->vga1_divisor >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 682         m1 = (hw->vga1_divisor >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 683         m2 = (hw->vga1_divisor >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 684
 685         intelfbhw_get_p1p2(dinfo, hw->vga_pd, &p1, &p2);
 686         printk("        VGA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 687                m1, m2, n, p1, p2);
 688         printk("        VGA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 689
 690         printk("        DPLL_A:                 0x%08x\n", hw->dpll_a);
 691         printk("        DPLL_B:                 0x%08x\n", hw->dpll_b);
 692         printk("        FPA0:                   0x%08x\n", hw->fpa0);
 693         printk("        FPA1:                   0x%08x\n", hw->fpa1);
 694         printk("        FPB0:                   0x%08x\n", hw->fpb0);
 695         printk("        FPB1:                   0x%08x\n", hw->fpb1);
 696
 697         n = (hw->fpa0 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 698         m1 = (hw->fpa0 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 699         m2 = (hw->fpa0 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 700
 701         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 702
 703         printk("        PLLA0: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 704                m1, m2, n, p1, p2);
 705         printk("        PLLA0: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 706
 707         n = (hw->fpa1 >> FP_N_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 708         m1 = (hw->fpa1 >> FP_M1_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 709         m2 = (hw->fpa1 >> FP_M2_DIVISOR_SHIFT) & FP_DIVISOR_MASK;
 710
 711         intelfbhw_get_p1p2(dinfo, hw->dpll_a, &p1, &p2);
 712
 713         printk("        PLLA1: (m1, m2, n, p1, p2) = (%d, %d, %d, %d, %d)\n",
 714                m1, m2, n, p1, p2);
 715         printk("        PLLA1: clock is %d\n", calc_vclock(index, m1, m2, n, p1, p2, 0));
 716
 717 #if 0
 718         printk("        PALETTE_A:\n");
 719         for (i = 0; i < PALETTE_8_ENTRIES)
 720                 printk("        %3d:    0x%08x\n", i, hw->palette_a[i]);
 721         printk("        PALETTE_B:\n");
 722         for (i = 0; i < PALETTE_8_ENTRIES)
 723                 printk("        %3d:    0x%08x\n", i, hw->palette_b[i]);
 724 #endif
 725
 726         printk("        HTOTAL_A:               0x%08x\n", hw->htotal_a);
 727         printk("        HBLANK_A:               0x%08x\n", hw->hblank_a);
 728         printk("        HSYNC_A:                0x%08x\n", hw->hsync_a);
 729         printk("        VTOTAL_A:               0x%08x\n", hw->vtotal_a);
 730         printk("        VBLANK_A:               0x%08x\n", hw->vblank_a);
 731         printk("        VSYNC_A:                0x%08x\n", hw->vsync_a);
 732         printk("        SRC_SIZE_A:             0x%08x\n", hw->src_size_a);
 733         printk("        BCLRPAT_A:              0x%08x\n", hw->bclrpat_a);
 734         printk("        HTOTAL_B:               0x%08x\n", hw->htotal_b);
 735         printk("        HBLANK_B:               0x%08x\n", hw->hblank_b);
 736         printk("        HSYNC_B:                0x%08x\n", hw->hsync_b);
 737         printk("        VTOTAL_B:               0x%08x\n", hw->vtotal_b);
 738         printk("        VBLANK_B:               0x%08x\n", hw->vblank_b);
 739         printk("        VSYNC_B:                0x%08x\n", hw->vsync_b);
 740         printk("        SRC_SIZE_B:             0x%08x\n", hw->src_size_b);
 741         printk("        BCLRPAT_B:              0x%08x\n", hw->bclrpat_b);
 742
 743         printk("        ADPA:                   0x%08x\n", hw->adpa);
 744         printk("        DVOA:                   0x%08x\n", hw->dvoa);
 745         printk("        DVOB:                   0x%08x\n", hw->dvob);
 746         printk("        DVOC:                   0x%08x\n", hw->dvoc);
 747         printk("        DVOA_SRCDIM:            0x%08x\n", hw->dvoa_srcdim);
 748         printk("        DVOB_SRCDIM:            0x%08x\n", hw->dvob_srcdim);
 749         printk("        DVOC_SRCDIM:            0x%08x\n", hw->dvoc_srcdim);
 750         printk("        LVDS:                   0x%08x\n", hw->lvds);
 751
 752         printk("        PIPEACONF:              0x%08x\n", hw->pipe_a_conf);
 753         printk("        PIPEBCONF:              0x%08x\n", hw->pipe_b_conf);
 754         printk("        DISPARB:                0x%08x\n", hw->disp_arb);
 755
 756         printk("        CURSOR_A_CONTROL:       0x%08x\n", hw->cursor_a_control);
 757         printk("        CURSOR_B_CONTROL:       0x%08x\n", hw->cursor_b_control);
 758         printk("        CURSOR_A_BASEADDR:      0x%08x\n", hw->cursor_a_base);
 759         printk("        CURSOR_B_BASEADDR:      0x%08x\n", hw->cursor_b_base);
 760
 761         printk("        CURSOR_A_PALETTE:       ");
 762         for (i = 0; i < 4; i++) {
 763                 printk("0x%08x", hw->cursor_a_palette[i]);
 764                 if (i < 3)
 765                         printk(", ");
 766         }
 767         printk("\n");
 768         printk("        CURSOR_B_PALETTE:       ");
 769         for (i = 0; i < 4; i++) {
 770                 printk("0x%08x", hw->cursor_b_palette[i]);
 771                 if (i < 3)
 772                         printk(", ");
 773         }
 774         printk("\n");
 775
 776         printk("        CURSOR_SIZE:            0x%08x\n", hw->cursor_size);
 777
 778         printk("        DSPACNTR:               0x%08x\n", hw->disp_a_ctrl);
 779         printk("        DSPBCNTR:               0x%08x\n", hw->disp_b_ctrl);
 780         printk("        DSPABASE:               0x%08x\n", hw->disp_a_base);
 781         printk("        DSPBBASE:               0x%08x\n", hw->disp_b_base);
 782         printk("        DSPASTRIDE:             0x%08x\n", hw->disp_a_stride);
 783         printk("        DSPBSTRIDE:             0x%08x\n", hw->disp_b_stride);
 784
 785         printk("        VGACNTRL:               0x%08x\n", hw->vgacntrl);
 786         printk("        ADD_ID:                 0x%08x\n", hw->add_id);
 787
 788         for (i = 0; i < 7; i++) {
 789                 printk("        SWF0%d                  0x%08x\n", i,
 790                         hw->swf0x[i]);
 791         }
 792         for (i = 0; i < 7; i++) {
 793                 printk("        SWF1%d                  0x%08x\n", i,
 794                         hw->swf1x[i]);
 795         }
 796         for (i = 0; i < 3; i++) {
 797                 printk("        SWF3%d                  0x%08x\n", i,
 798                        hw->swf3x[i]);
 799         }
 800         for (i = 0; i < 8; i++)
 801                 printk("        FENCE%d                 0x%08x\n", i,
 802                        hw->fence[i]);
 803
 804         printk("        INSTPM                  0x%08x\n", hw->instpm);
 805         printk("        MEM_MODE                0x%08x\n", hw->mem_mode);
 806         printk("        FW_BLC_0                0x%08x\n", hw->fw_blc_0);
 807         printk("        FW_BLC_1                0x%08x\n", hw->fw_blc_1);
 808
 809         printk("        HWSTAM                  0x%04x\n", hw->hwstam);
 810         printk("        IER                     0x%04x\n", hw->ier);
 811         printk("        IIR                     0x%04x\n", hw->iir);
 812         printk("        IMR                     0x%04x\n", hw->imr);
 813         printk("hw state dump end\n");
 814 #endif
 815 }
 816
 817
 818
 819 /* Split the M parameter into M1 and M2. */
 820 static int
 821 splitm(int index, unsigned int m, unsigned int *retm1, unsigned int *retm2)
 822 {
 823         int m1, m2;
 824         int testm;
 825         struct pll_min_max *pll = &plls[index];
 826
 827         /* no point optimising too much - brute force m */
 828         for (m1 = pll->min_m1; m1 < pll->max_m1 + 1; m1++) {
 829                 for (m2 = pll->min_m2; m2 < pll->max_m2 + 1; m2++) {
 830                         testm = (5 * (m1 + 2)) + (m2 + 2);
 831                         if (testm == m) {
 832                                 *retm1 = (unsigned int)m1;
 833                                 *retm2 = (unsigned int)m2;
 834                                 return 0;
 835                         }
 836                 }
 837         }
 838         return 1;
 839 }
 840
 841 /* Split the P parameter into P1 and P2. */
 842 static int
 843 splitp(int index, unsigned int p, unsigned int *retp1, unsigned int *retp2)
 844 {
 845         int p1, p2;
 846         struct pll_min_max *pll = &plls[index];
 847
 848         if (index == PLLS_I9xx) {
 849                 p2 = (p % 10) ? 1 : 0;
 850
 851                 p1 = p / (p2 ? 5 : 10);
 852
 853                 *retp1 = (unsigned int)p1;
 854                 *retp2 = (unsigned int)p2;
 855                 return 0;
 856         }
 857
 858         if (p % 4 == 0)
 859                 p2 = 1;
 860         else
 861                 p2 = 0;
 862         p1 = (p / (1 << (p2 + 1))) - 2;
 863         if (p % 4 == 0 && p1 < pll->min_p1) {
 864                 p2 = 0;
 865                 p1 = (p / (1 << (p2 + 1))) - 2;
 866         }
 867         if (p1 < pll->min_p1 || p1 > pll->max_p1 ||
 868             (p1 + 2) * (1 << (p2 + 1)) != p) {
 869                 return 1;
 870         } else {
 871                 *retp1 = (unsigned int)p1;
 872                 *retp2 = (unsigned int)p2;
 873                 return 0;
 874         }
 875 }
 876
 877 static int
 878 calc_pll_params(int index, int clock, u32 *retm1, u32 *retm2, u32 *retn, u32 *retp1,
 879                 u32 *retp2, u32 *retclock)
 880 {
 881         u32 m1, m2, n, p1, p2, n1, testm;
 882         u32 f_vco, p, p_best = 0, m, f_out = 0;
 883         u32 err_max, err_target, err_best = 10000000;
 884         u32 n_best = 0, m_best = 0, f_best, f_err;
 885         u32 p_min, p_max, p_inc, div_max;
 886         struct pll_min_max *pll = &plls[index];
 887
 888         /* Accept 0.5% difference, but aim for 0.1% */
 889         err_max = 5 * clock / 1000;
 890         err_target = clock / 1000;
 891
 892         DBG_MSG("Clock is %d\n", clock);
 893
 894         div_max = pll->max_vco / clock;
 895
 896         p_inc = (clock <= pll->p_transition_clk) ? pll->p_inc_lo : pll->p_inc_hi;
 897         p_min = p_inc;
 898         p_max = ROUND_DOWN_TO(div_max, p_inc);
 899         if (p_min < pll->min_p)
 900                 p_min = pll->min_p;
 901         if (p_max > pll->max_p)
 902                 p_max = pll->max_p;
 903
 904         DBG_MSG("p range is %d-%d (%d)\n", p_min, p_max, p_inc);
 905
 906         p = p_min;
 907         do {
 908                 if (splitp(index, p, &p1, &p2)) {
 909                         WRN_MSG("cannot split p = %d\n", p);
 910                         p += p_inc;
 911                         continue;
 912                 }
 913                 n = pll->min_n;
 914                 f_vco = clock * p;
 915
 916                 do {
 917                         m = ROUND_UP_TO(f_vco * n, pll->ref_clk) / pll->ref_clk;
 918                         if (m < pll->min_m)
 919                                 m = pll->min_m + 1;
 920                         if (m > pll->max_m)
 921                                 m = pll->max_m - 1;
 922                         for (testm = m - 1; testm <= m; testm++) {
 923                                 f_out = calc_vclock3(index, testm, n, p);
 924                                 if (splitm(index, testm, &m1, &m2)) {
 925                                         WRN_MSG("cannot split m = %d\n",
 926                                                 testm);
 927                                         continue;
 928                                 }
 929                                 if (clock > f_out)
 930                                         f_err = clock - f_out;
 931                                 else/* slightly bias the error for bigger clocks */
 932                                         f_err = f_out - clock + 1;
 933
 934                                 if (f_err < err_best) {
 935                                         m_best = testm;
 936                                         n_best = n;
 937                                         p_best = p;
 938                                         f_best = f_out;
 939                                         err_best = f_err;
 940                                 }
 941                         }
 942                         n++;
 943                 } while ((n <= pll->max_n) && (f_out >= clock));
 944                 p += p_inc;
 945         } while ((p <= p_max));
 946
 947         if (!m_best) {
 948                 WRN_MSG("cannot find parameters for clock %d\n", clock);
 949                 return 1;
 950         }
 951         m = m_best;
 952         n = n_best;
 953         p = p_best;
 954         splitm(index, m, &m1, &m2);
 955         splitp(index, p, &p1, &p2);
 956         n1 = n - 2;
 957
 958         DBG_MSG("m, n, p: %d (%d,%d), %d (%d), %d (%d,%d), "
 959                 "f: %d (%d), VCO: %d\n",
 960                 m, m1, m2, n, n1, p, p1, p2,
 961                 calc_vclock3(index, m, n, p),
 962                 calc_vclock(index, m1, m2, n1, p1, p2, 0),
 963                 calc_vclock3(index, m, n, p) * p);
 964         *retm1 = m1;
 965         *retm2 = m2;
 966         *retn = n1;
 967         *retp1 = p1;
 968         *retp2 = p2;
 969         *retclock = calc_vclock(index, m1, m2, n1, p1, p2, 0);
 970
 971         return 0;
 972 }
 973
 974 static __inline__ int
 975 check_overflow(u32 value, u32 limit, const char *description)
 976 {
 977         if (value > limit) {
 978                 WRN_MSG("%s value %d exceeds limit %d\n",
 979                         description, value, limit);
 980                 return 1;
 981         }
 982         return 0;
 983 }
 984
 985 /* It is assumed that hw is filled in with the initial state information. */
 986 int
 987 intelfbhw_mode_to_hw(struct intelfb_info *dinfo, struct intelfb_hwstate *hw,
 988                      struct fb_var_screeninfo *var)
 989 {
 990         int pipe = PIPE_A;
 991         u32 *dpll, *fp0, *fp1;
 992         u32 m1, m2, n, p1, p2, clock_target, clock;
 993         u32 hsync_start, hsync_end, hblank_start, hblank_end, htotal, hactive;
 994         u32 vsync_start, vsync_end, vblank_start, vblank_end, vtotal, vactive;
 995         u32 vsync_pol, hsync_pol;
 996         u32 *vs, *vb, *vt, *hs, *hb, *ht, *ss, *pipe_conf;
 997         u32 stride_alignment;
 998
 999         DBG_MSG("intelfbhw_mode_to_hw\n");
1000
1001         /* Disable VGA */
1002         hw->vgacntrl |= VGA_DISABLE;
1003
1004         /* Check whether pipe A or pipe B is enabled. */
1005         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1006                 pipe = PIPE_A;
1007         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1008                 pipe = PIPE_B;
1009
1010         /* Set which pipe's registers will be set. */
1011         if (pipe == PIPE_B) {
1012                 dpll = &hw->dpll_b;
1013                 fp0 = &hw->fpb0;
1014                 fp1 = &hw->fpb1;
1015                 hs = &hw->hsync_b;
1016                 hb = &hw->hblank_b;
1017                 ht = &hw->htotal_b;
1018                 vs = &hw->vsync_b;
1019                 vb = &hw->vblank_b;
1020                 vt = &hw->vtotal_b;
1021                 ss = &hw->src_size_b;
1022                 pipe_conf = &hw->pipe_b_conf;
1023         } else {
1024                 dpll = &hw->dpll_a;
1025                 fp0 = &hw->fpa0;
1026                 fp1 = &hw->fpa1;
1027                 hs = &hw->hsync_a;
1028                 hb = &hw->hblank_a;
1029                 ht = &hw->htotal_a;
1030                 vs = &hw->vsync_a;
1031                 vb = &hw->vblank_a;
1032                 vt = &hw->vtotal_a;
1033                 ss = &hw->src_size_a;
1034                 pipe_conf = &hw->pipe_a_conf;
1035         }
1036
1037         /* Use ADPA register for sync control. */
1038         hw->adpa &= ~ADPA_USE_VGA_HVPOLARITY;
1039
1040         /* sync polarity */
1041         hsync_pol = (var->sync & FB_SYNC_HOR_HIGH_ACT) ?
1042                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1043         vsync_pol = (var->sync & FB_SYNC_VERT_HIGH_ACT) ?
1044                         ADPA_SYNC_ACTIVE_HIGH : ADPA_SYNC_ACTIVE_LOW;
1045         hw->adpa &= ~((ADPA_SYNC_ACTIVE_MASK << ADPA_VSYNC_ACTIVE_SHIFT) |
1046                       (ADPA_SYNC_ACTIVE_MASK << ADPA_HSYNC_ACTIVE_SHIFT));
1047         hw->adpa |= (hsync_pol << ADPA_HSYNC_ACTIVE_SHIFT) |
1048                     (vsync_pol << ADPA_VSYNC_ACTIVE_SHIFT);
1049
1050         /* Connect correct pipe to the analog port DAC */
1051         hw->adpa &= ~(PIPE_MASK << ADPA_PIPE_SELECT_SHIFT);
1052         hw->adpa |= (pipe << ADPA_PIPE_SELECT_SHIFT);
1053
1054         /* Set DPMS state to D0 (on) */
1055         hw->adpa &= ~ADPA_DPMS_CONTROL_MASK;
1056         hw->adpa |= ADPA_DPMS_D0;
1057
1058         hw->adpa |= ADPA_DAC_ENABLE;
1059
1060         *dpll |= (DPLL_VCO_ENABLE | DPLL_VGA_MODE_DISABLE);
1061         *dpll &= ~(DPLL_RATE_SELECT_MASK | DPLL_REFERENCE_SELECT_MASK);
1062         *dpll |= (DPLL_REFERENCE_DEFAULT | DPLL_RATE_SELECT_FP0);
1063
1064         /* Desired clock in kHz */
1065         clock_target = 1000000000 / var->pixclock;
1066
1067         if (calc_pll_params(dinfo->pll_index, clock_target, &m1, &m2,
1068                             &n, &p1, &p2, &clock)) {
1069                 WRN_MSG("calc_pll_params failed\n");
1070                 return 1;
1071         }
1072
1073         /* Check for overflow. */
1074         if (check_overflow(p1, DPLL_P1_MASK, "PLL P1 parameter"))
1075                 return 1;
1076         if (check_overflow(p2, DPLL_P2_MASK, "PLL P2 parameter"))
1077                 return 1;
1078         if (check_overflow(m1, FP_DIVISOR_MASK, "PLL M1 parameter"))
1079                 return 1;
1080         if (check_overflow(m2, FP_DIVISOR_MASK, "PLL M2 parameter"))
1081                 return 1;
1082         if (check_overflow(n, FP_DIVISOR_MASK, "PLL N parameter"))
1083                 return 1;
1084
1085         *dpll &= ~DPLL_P1_FORCE_DIV2;
1086         *dpll &= ~((DPLL_P2_MASK << DPLL_P2_SHIFT) |
1087                    (DPLL_P1_MASK << DPLL_P1_SHIFT));
1088
1089         if (IS_I9XX(dinfo)) {
1090                 *dpll |= (p2 << DPLL_I9XX_P2_SHIFT);
1091                 *dpll |= (1 << (p1 - 1)) << DPLL_P1_SHIFT;
1092         } else {
1093                 *dpll |= (p2 << DPLL_P2_SHIFT) | (p1 << DPLL_P1_SHIFT);
1094         }
1095
1096         *fp0 = (n << FP_N_DIVISOR_SHIFT) |
1097                (m1 << FP_M1_DIVISOR_SHIFT) |
1098                (m2 << FP_M2_DIVISOR_SHIFT);
1099         *fp1 = *fp0;
1100
1101         hw->dvob &= ~PORT_ENABLE;
1102         hw->dvoc &= ~PORT_ENABLE;
1103
1104         /* Use display plane A. */
1105         hw->disp_a_ctrl |= DISPPLANE_PLANE_ENABLE;
1106         hw->disp_a_ctrl &= ~DISPPLANE_GAMMA_ENABLE;
1107         hw->disp_a_ctrl &= ~DISPPLANE_PIXFORMAT_MASK;
1108         switch (intelfb_var_to_depth(var)) {
1109         case 8:
1110                 hw->disp_a_ctrl |= DISPPLANE_8BPP | DISPPLANE_GAMMA_ENABLE;
1111                 break;
1112         case 15:
1113                 hw->disp_a_ctrl |= DISPPLANE_15_16BPP;
1114                 break;
1115         case 16:
1116                 hw->disp_a_ctrl |= DISPPLANE_16BPP;
1117                 break;
1118         case 24:
1119                 hw->disp_a_ctrl |= DISPPLANE_32BPP_NO_ALPHA;
1120                 break;
1121         }
1122         hw->disp_a_ctrl &= ~(PIPE_MASK << DISPPLANE_SEL_PIPE_SHIFT);
1123         hw->disp_a_ctrl |= (pipe << DISPPLANE_SEL_PIPE_SHIFT);
1124
1125         /* Set CRTC registers. */
1126         hactive = var->xres;
1127         hsync_start = hactive + var->right_margin;
1128         hsync_end = hsync_start + var->hsync_len;
1129         htotal = hsync_end + var->left_margin;
1130         hblank_start = hactive;
1131         hblank_end = htotal;
1132
1133         DBG_MSG("H: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1134                 hactive, hsync_start, hsync_end, htotal, hblank_start,
1135                 hblank_end);
1136
1137         vactive = var->yres;
1138         vsync_start = vactive + var->lower_margin;
1139         vsync_end = vsync_start + var->vsync_len;
1140         vtotal = vsync_end + var->upper_margin;
1141         vblank_start = vactive;
1142         vblank_end = vtotal;
1143         vblank_end = vsync_end + 1;
1144
1145         DBG_MSG("V: act %d, ss %d, se %d, tot %d bs %d, be %d\n",
1146                 vactive, vsync_start, vsync_end, vtotal, vblank_start,
1147                 vblank_end);
1148
1149         /* Adjust for register values, and check for overflow. */
1150         hactive--;
1151         if (check_overflow(hactive, HACTIVE_MASK, "CRTC hactive"))
1152                 return 1;
1153         hsync_start--;
1154         if (check_overflow(hsync_start, HSYNCSTART_MASK, "CRTC hsync_start"))
1155                 return 1;
1156         hsync_end--;
1157         if (check_overflow(hsync_end, HSYNCEND_MASK, "CRTC hsync_end"))
1158                 return 1;
1159         htotal--;
1160         if (check_overflow(htotal, HTOTAL_MASK, "CRTC htotal"))
1161                 return 1;
1162         hblank_start--;
1163         if (check_overflow(hblank_start, HBLANKSTART_MASK, "CRTC hblank_start"))
1164                 return 1;
1165         hblank_end--;
1166         if (check_overflow(hblank_end, HBLANKEND_MASK, "CRTC hblank_end"))
1167                 return 1;
1168
1169         vactive--;
1170         if (check_overflow(vactive, VACTIVE_MASK, "CRTC vactive"))
1171                 return 1;
1172         vsync_start--;
1173         if (check_overflow(vsync_start, VSYNCSTART_MASK, "CRTC vsync_start"))
1174                 return 1;
1175         vsync_end--;
1176         if (check_overflow(vsync_end, VSYNCEND_MASK, "CRTC vsync_end"))
1177                 return 1;
1178         vtotal--;
1179         if (check_overflow(vtotal, VTOTAL_MASK, "CRTC vtotal"))
1180                 return 1;
1181         vblank_start--;
1182         if (check_overflow(vblank_start, VBLANKSTART_MASK, "CRTC vblank_start"))
1183                 return 1;
1184         vblank_end--;
1185         if (check_overflow(vblank_end, VBLANKEND_MASK, "CRTC vblank_end"))
1186                 return 1;
1187
1188         *ht = (htotal << HTOTAL_SHIFT) | (hactive << HACTIVE_SHIFT);
1189         *hb = (hblank_start << HBLANKSTART_SHIFT) |
1190               (hblank_end << HSYNCEND_SHIFT);
1191         *hs = (hsync_start << HSYNCSTART_SHIFT) | (hsync_end << HSYNCEND_SHIFT);
1192
1193         *vt = (vtotal << VTOTAL_SHIFT) | (vactive << VACTIVE_SHIFT);
1194         *vb = (vblank_start << VBLANKSTART_SHIFT) |
1195               (vblank_end << VSYNCEND_SHIFT);
1196         *vs = (vsync_start << VSYNCSTART_SHIFT) | (vsync_end << VSYNCEND_SHIFT);
1197         *ss = (hactive << SRC_SIZE_HORIZ_SHIFT) |
1198               (vactive << SRC_SIZE_VERT_SHIFT);
1199
1200         hw->disp_a_stride = dinfo->pitch;
1201         DBG_MSG("pitch is %d\n", hw->disp_a_stride);
1202
1203         hw->disp_a_base = hw->disp_a_stride * var->yoffset +
1204                           var->xoffset * var->bits_per_pixel / 8;
1205
1206         hw->disp_a_base += dinfo->fb.offset << 12;
1207
1208         /* Check stride alignment. */
1209         stride_alignment = IS_I9XX(dinfo) ? STRIDE_ALIGNMENT_I9XX :
1210                                             STRIDE_ALIGNMENT;
1211         if (hw->disp_a_stride % stride_alignment != 0) {
1212                 WRN_MSG("display stride %d has bad alignment %d\n",
1213                         hw->disp_a_stride, stride_alignment);
1214                 return 1;
1215         }
1216
1217         /* Set the palette to 8-bit mode. */
1218         *pipe_conf &= ~PIPECONF_GAMMA;
1219
1220         if (var->vmode & FB_VMODE_INTERLACED)
1221                 *pipe_conf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
1222         else
1223                 *pipe_conf &= ~PIPECONF_INTERLACE_MASK;
1224
1225         return 0;
1226 }
1227
1228 /* Program a (non-VGA) video mode. */
1229 int
1230 intelfbhw_program_mode(struct intelfb_info *dinfo,
1231                      const struct intelfb_hwstate *hw, int blank)
1232 {
1233         int pipe = PIPE_A;
1234         u32 tmp;
1235         const u32 *dpll, *fp0, *fp1, *pipe_conf;
1236         const u32 *hs, *ht, *hb, *vs, *vt, *vb, *ss;
1237         u32 dpll_reg, fp0_reg, fp1_reg, pipe_conf_reg;
1238         u32 hsync_reg, htotal_reg, hblank_reg;
1239         u32 vsync_reg, vtotal_reg, vblank_reg;
1240         u32 src_size_reg;
1241         u32 count, tmp_val[3];
1242
1243         /* Assume single pipe, display plane A, analog CRT. */
1244
1245 #if VERBOSE > 0
1246         DBG_MSG("intelfbhw_program_mode\n");
1247 #endif
1248
1249         /* Disable VGA */
1250         tmp = INREG(VGACNTRL);
1251         tmp |= VGA_DISABLE;
1252         OUTREG(VGACNTRL, tmp);
1253
1254         /* Check whether pipe A or pipe B is enabled. */
1255         if (hw->pipe_a_conf & PIPECONF_ENABLE)
1256                 pipe = PIPE_A;
1257         else if (hw->pipe_b_conf & PIPECONF_ENABLE)
1258                 pipe = PIPE_B;
1259
1260         dinfo->pipe = pipe;
1261
1262         if (pipe == PIPE_B) {
1263                 dpll = &hw->dpll_b;
1264                 fp0 = &hw->fpb0;
1265                 fp1 = &hw->fpb1;
1266                 pipe_conf = &hw->pipe_b_conf;
1267                 hs = &hw->hsync_b;
1268                 hb = &hw->hblank_b;
1269                 ht = &hw->htotal_b;
1270                 vs = &hw->vsync_b;
1271                 vb = &hw->vblank_b;
1272                 vt = &hw->vtotal_b;
1273                 ss = &hw->src_size_b;
1274                 dpll_reg = DPLL_B;
1275                 fp0_reg = FPB0;
1276                 fp1_reg = FPB1;
1277                 pipe_conf_reg = PIPEBCONF;
1278                 hsync_reg = HSYNC_B;
1279                 htotal_reg = HTOTAL_B;
1280                 hblank_reg = HBLANK_B;
1281                 vsync_reg = VSYNC_B;
1282                 vtotal_reg = VTOTAL_B;
1283                 vblank_reg = VBLANK_B;
1284                 src_size_reg = SRC_SIZE_B;
1285         } else {
1286                 dpll = &hw->dpll_a;
1287                 fp0 = &hw->fpa0;
1288                 fp1 = &hw->fpa1;
1289                 pipe_conf = &hw->pipe_a_conf;
1290                 hs = &hw->hsync_a;
1291                 hb = &hw->hblank_a;
1292                 ht = &hw->htotal_a;
1293                 vs = &hw->vsync_a;
1294                 vb = &hw->vblank_a;
1295                 vt = &hw->vtotal_a;
1296                 ss = &hw->src_size_a;
1297                 dpll_reg = DPLL_A;
1298                 fp0_reg = FPA0;
1299                 fp1_reg = FPA1;
1300                 pipe_conf_reg = PIPEACONF;
1301                 hsync_reg = HSYNC_A;
1302                 htotal_reg = HTOTAL_A;
1303                 hblank_reg = HBLANK_A;
1304                 vsync_reg = VSYNC_A;
1305                 vtotal_reg = VTOTAL_A;
1306                 vblank_reg = VBLANK_A;
1307                 src_size_reg = SRC_SIZE_A;
1308         }
1309
1310         /* turn off pipe */
1311         tmp = INREG(pipe_conf_reg);
1312         tmp &= ~PIPECONF_ENABLE;
1313         OUTREG(pipe_conf_reg, tmp);
1314
1315         count = 0;
1316         do {
1317                 tmp_val[count%3] = INREG(0x70000);
1318                 if ((tmp_val[0] == tmp_val[1]) && (tmp_val[1]==tmp_val[2]))
1319                         break;
1320                 count++;
1321                 udelay(1);
1322                 if (count % 200 == 0) {
1323                         tmp = INREG(pipe_conf_reg);
1324                         tmp &= ~PIPECONF_ENABLE;
1325                         OUTREG(pipe_conf_reg, tmp);
1326                 }
1327         } while(count < 2000);
1328
1329         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1330
1331         /* Disable planes A and B. */
1332         tmp = INREG(DSPACNTR);
1333         tmp &= ~DISPPLANE_PLANE_ENABLE;
1334         OUTREG(DSPACNTR, tmp);
1335         tmp = INREG(DSPBCNTR);
1336         tmp &= ~DISPPLANE_PLANE_ENABLE;
1337         OUTREG(DSPBCNTR, tmp);
1338
1339         /* Wait for vblank. For now, just wait for a 50Hz cycle (20ms)) */
1340         mdelay(20);
1341
1342         OUTREG(DVOB, INREG(DVOB) & ~PORT_ENABLE);
1343         OUTREG(DVOC, INREG(DVOC) & ~PORT_ENABLE);
1344         OUTREG(ADPA, INREG(ADPA) & ~ADPA_DAC_ENABLE);
1345
1346         /* Disable Sync */
1347         tmp = INREG(ADPA);
1348         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1349         tmp |= ADPA_DPMS_D3;
1350         OUTREG(ADPA, tmp);
1351
1352         /* do some funky magic - xyzzy */
1353         OUTREG(0x61204, 0xabcd0000);
1354
1355         /* turn off PLL */
1356         tmp = INREG(dpll_reg);
1357         tmp &= ~DPLL_VCO_ENABLE;
1358         OUTREG(dpll_reg, tmp);
1359
1360         /* Set PLL parameters */
1361         OUTREG(fp0_reg, *fp0);
1362         OUTREG(fp1_reg, *fp1);
1363
1364         /* Enable PLL */
1365         OUTREG(dpll_reg, *dpll);
1366
1367         /* Set DVOs B/C */
1368         OUTREG(DVOB, hw->dvob);
1369         OUTREG(DVOC, hw->dvoc);
1370
1371         /* undo funky magic */
1372         OUTREG(0x61204, 0x00000000);
1373
1374         /* Set ADPA */
1375         OUTREG(ADPA, INREG(ADPA) | ADPA_DAC_ENABLE);
1376         OUTREG(ADPA, (hw->adpa & ~(ADPA_DPMS_CONTROL_MASK)) | ADPA_DPMS_D3);
1377
1378         /* Set pipe parameters */
1379         OUTREG(hsync_reg, *hs);
1380         OUTREG(hblank_reg, *hb);
1381         OUTREG(htotal_reg, *ht);
1382         OUTREG(vsync_reg, *vs);
1383         OUTREG(vblank_reg, *vb);
1384         OUTREG(vtotal_reg, *vt);
1385         OUTREG(src_size_reg, *ss);
1386
1387         /* Enable pipe */
1388         OUTREG(pipe_conf_reg, *pipe_conf | PIPECONF_ENABLE);
1389
1390         /* Enable sync */
1391         tmp = INREG(ADPA);
1392         tmp &= ~ADPA_DPMS_CONTROL_MASK;
1393         tmp |= ADPA_DPMS_D0;
1394         OUTREG(ADPA, tmp);
1395
1396         /* setup display plane */
1397         if (dinfo->pdev->device == PCI_DEVICE_ID_INTEL_830M) {
1398                 /*
1399                  *      i830M errata: the display plane must be enabled
1400                  *      to allow writes to the other bits in the plane
1401                  *      control register.
1402                  */
1403                 tmp = INREG(DSPACNTR);
1404                 if ((tmp & DISPPLANE_PLANE_ENABLE) != DISPPLANE_PLANE_ENABLE) {
1405                         tmp |= DISPPLANE_PLANE_ENABLE;
1406                         OUTREG(DSPACNTR, tmp);
1407                         OUTREG(DSPACNTR,
1408                                hw->disp_a_ctrl|DISPPLANE_PLANE_ENABLE);
1409                         mdelay(1);
1410                 }
1411         }
1412
1413         OUTREG(DSPACNTR, hw->disp_a_ctrl & ~DISPPLANE_PLANE_ENABLE);
1414         OUTREG(DSPASTRIDE, hw->disp_a_stride);
1415         OUTREG(DSPABASE, hw->disp_a_base);
1416
1417         /* Enable plane */
1418         if (!blank) {
1419                 tmp = INREG(DSPACNTR);
1420                 tmp |= DISPPLANE_PLANE_ENABLE;
1421                 OUTREG(DSPACNTR, tmp);
1422                 OUTREG(DSPABASE, hw->disp_a_base);
1423         }
1424
1425         return 0;
1426 }
1427
1428 /* forward declarations */
1429 static void refresh_ring(struct intelfb_info *dinfo);
1430 static void reset_state(struct intelfb_info *dinfo);
1431 static void do_flush(struct intelfb_info *dinfo);
1432
1433 static  u32 get_ring_space(struct intelfb_info *dinfo)
1434 {
1435         u32 ring_space;
1436
1437         if (dinfo->ring_tail >= dinfo->ring_head)
1438                 ring_space = dinfo->ring.size -
1439                         (dinfo->ring_tail - dinfo->ring_head);
1440         else
1441                 ring_space = dinfo->ring_head - dinfo->ring_tail;
1442
1443         if (ring_space > RING_MIN_FREE)
1444                 ring_space -= RING_MIN_FREE;
1445         else
1446                 ring_space = 0;
1447
1448         return ring_space;
1449 }
1450
1451 static int
1452 wait_ring(struct intelfb_info *dinfo, int n)
1453 {
1454         int i = 0;
1455         unsigned long end;
1456         u32 last_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1457
1458 #if VERBOSE > 0
1459         DBG_MSG("wait_ring: %d\n", n);
1460 #endif
1461
1462         end = jiffies + (HZ * 3);
1463         while (dinfo->ring_space < n) {
1464                 dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1465                 dinfo->ring_space = get_ring_space(dinfo);
1466
1467                 if (dinfo->ring_head != last_head) {
1468                         end = jiffies + (HZ * 3);
1469                         last_head = dinfo->ring_head;
1470                 }
1471                 i++;
1472                 if (time_before(end, jiffies)) {
1473                         if (!i) {
1474                                 /* Try again */
1475                                 reset_state(dinfo);
1476                                 refresh_ring(dinfo);
1477                                 do_flush(dinfo);
1478                                 end = jiffies + (HZ * 3);
1479                                 i = 1;
1480                         } else {
1481                                 WRN_MSG("ring buffer : space: %d wanted %d\n",
1482                                         dinfo->ring_space, n);
1483                                 WRN_MSG("lockup - turning off hardware "
1484                                         "acceleration\n");
1485                                 dinfo->ring_lockup = 1;
1486                                 break;
1487                         }
1488                 }
1489                 udelay(1);
1490         }
1491         return i;
1492 }
1493
1494 static void
1495 do_flush(struct intelfb_info *dinfo) {
1496         START_RING(2);
1497         OUT_RING(MI_FLUSH | MI_WRITE_DIRTY_STATE | MI_INVALIDATE_MAP_CACHE);
1498         OUT_RING(MI_NOOP);
1499         ADVANCE_RING();
1500 }
1501
1502 void
1503 intelfbhw_do_sync(struct intelfb_info *dinfo)
1504 {
1505 #if VERBOSE > 0
1506         DBG_MSG("intelfbhw_do_sync\n");
1507 #endif
1508
1509         if (!dinfo->accel)
1510                 return;
1511
1512         /*
1513          * Send a flush, then wait until the ring is empty.  This is what
1514          * the XFree86 driver does, and actually it doesn't seem a lot worse
1515          * than the recommended method (both have problems).
1516          */
1517         do_flush(dinfo);
1518         wait_ring(dinfo, dinfo->ring.size - RING_MIN_FREE);
1519         dinfo->ring_space = dinfo->ring.size - RING_MIN_FREE;
1520 }
1521
1522 static void
1523 refresh_ring(struct intelfb_info *dinfo)
1524 {
1525 #if VERBOSE > 0
1526         DBG_MSG("refresh_ring\n");
1527 #endif
1528
1529         dinfo->ring_head = INREG(PRI_RING_HEAD) & RING_HEAD_MASK;
1530         dinfo->ring_tail = INREG(PRI_RING_TAIL) & RING_TAIL_MASK;
1531         dinfo->ring_space = get_ring_space(dinfo);
1532 }
1533
1534 static void
1535 reset_state(struct intelfb_info *dinfo)
1536 {
1537         int i;
1538         u32 tmp;
1539
1540 #if VERBOSE > 0
1541         DBG_MSG("reset_state\n");
1542 #endif
1543
1544         for (i = 0; i < FENCE_NUM; i++)
1545                 OUTREG(FENCE + (i << 2), 0);
1546
1547         /* Flush the ring buffer if it's enabled. */
1548         tmp = INREG(PRI_RING_LENGTH);
1549         if (tmp & RING_ENABLE) {
1550 #if VERBOSE > 0
1551                 DBG_MSG("reset_state: ring was enabled\n");
1552 #endif
1553                 refresh_ring(dinfo);
1554                 intelfbhw_do_sync(dinfo);
1555                 DO_RING_IDLE();
1556         }
1557
1558         OUTREG(PRI_RING_LENGTH, 0);
1559         OUTREG(PRI_RING_HEAD, 0);
1560         OUTREG(PRI_RING_TAIL, 0);
1561         OUTREG(PRI_RING_START, 0);
1562 }
1563
1564 /* Stop the 2D engine, and turn off the ring buffer. */
1565 void
1566 intelfbhw_2d_stop(struct intelfb_info *dinfo)
1567 {
1568 #if VERBOSE > 0
1569         DBG_MSG("intelfbhw_2d_stop: accel: %d, ring_active: %d\n", dinfo->accel,
1570                 dinfo->ring_active);
1571 #endif
1572
1573         if (!dinfo->accel)
1574                 return;
1575
1576         dinfo->ring_active = 0;
1577         reset_state(dinfo);
1578 }
1579
1580 /*
1581  * Enable the ring buffer, and initialise the 2D engine.
1582  * It is assumed that the graphics engine has been stopped by previously
1583  * calling intelfb_2d_stop().
1584  */
1585 void
1586 intelfbhw_2d_start(struct intelfb_info *dinfo)
1587 {
1588 #if VERBOSE > 0
1589         DBG_MSG("intelfbhw_2d_start: accel: %d, ring_active: %d\n",
1590                 dinfo->accel, dinfo->ring_active);
1591 #endif
1592
1593         if (!dinfo->accel)
1594                 return;
1595
1596         /* Initialise the primary ring buffer. */
1597         OUTREG(PRI_RING_LENGTH, 0);
1598         OUTREG(PRI_RING_TAIL, 0);
1599         OUTREG(PRI_RING_HEAD, 0);
1600
1601         OUTREG(PRI_RING_START, dinfo->ring.physical & RING_START_MASK);
1602         OUTREG(PRI_RING_LENGTH,
1603                 ((dinfo->ring.size - GTT_PAGE_SIZE) & RING_LENGTH_MASK) |
1604                 RING_NO_REPORT | RING_ENABLE);
1605         refresh_ring(dinfo);
1606         dinfo->ring_active = 1;
1607 }
1608
1609 /* 2D fillrect (solid fill or invert) */
1610 void
1611 intelfbhw_do_fillrect(struct intelfb_info *dinfo, u32 x, u32 y, u32 w, u32 h,
1612                       u32 color, u32 pitch, u32 bpp, u32 rop)
1613 {
1614         u32 br00, br09, br13, br14, br16;
1615
1616 #if VERBOSE > 0
1617         DBG_MSG("intelfbhw_do_fillrect: (%d,%d) %dx%d, c 0x%06x, p %d bpp %d, "
1618                 "rop 0x%02x\n", x, y, w, h, color, pitch, bpp, rop);
1619 #endif
1620
1621         br00 = COLOR_BLT_CMD;
1622         br09 = dinfo->fb_start + (y * pitch + x * (bpp / 8));
1623         br13 = (rop << ROP_SHIFT) | pitch;
1624         br14 = (h << HEIGHT_SHIFT) | ((w * (bpp / 8)) << WIDTH_SHIFT);
1625         br16 = color;
1626
1627         switch (bpp) {
1628         case 8:
1629                 br13 |= COLOR_DEPTH_8;
1630                 break;
1631         case 16:
1632                 br13 |= COLOR_DEPTH_16;
1633                 break;
1634         case 32:
1635                 br13 |= COLOR_DEPTH_32;
1636                 br00 |= WRITE_ALPHA | WRITE_RGB;
1637                 break;
1638         }
1639
1640         START_RING(6);
1641         OUT_RING(br00);
1642         OUT_RING(br13);
1643         OUT_RING(br14);
1644         OUT_RING(br09);
1645         OUT_RING(br16);
1646         OUT_RING(MI_NOOP);
1647         ADVANCE_RING();
1648
1649 #if VERBOSE > 0
1650         DBG_MSG("ring = 0x%08x, 0x%08x (%d)\n", dinfo->ring_head,
1651                 dinfo->ring_tail, dinfo->ring_space);
1652 #endif
1653 }
1654
1655 void
1656 intelfbhw_do_bitblt(struct intelfb_info *dinfo, u32 curx, u32 cury,
1657                     u32 dstx, u32 dsty, u32 w, u32 h, u32 pitch, u32 bpp)
1658 {
1659         u32 br00, br09, br11, br12, br13, br22, br23, br26;
1660
1661 #if VERBOSE > 0
1662         DBG_MSG("intelfbhw_do_bitblt: (%d,%d)->(%d,%d) %dx%d, p %d bpp %d\n",
1663                 curx, cury, dstx, dsty, w, h, pitch, bpp);
1664 #endif
1665
1666         br00 = XY_SRC_COPY_BLT_CMD;
1667         br09 = dinfo->fb_start;
1668         br11 = (pitch << PITCH_SHIFT);
1669         br12 = dinfo->fb_start;
1670         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1671         br22 = (dstx << WIDTH_SHIFT) | (dsty << HEIGHT_SHIFT);
1672         br23 = ((dstx + w) << WIDTH_SHIFT) |
1673                ((dsty + h) << HEIGHT_SHIFT);
1674         br26 = (curx << WIDTH_SHIFT) | (cury << HEIGHT_SHIFT);
1675
1676         switch (bpp) {
1677         case 8:
1678                 br13 |= COLOR_DEPTH_8;
1679                 break;
1680         case 16:
1681                 br13 |= COLOR_DEPTH_16;
1682                 break;
1683         case 32:
1684                 br13 |= COLOR_DEPTH_32;
1685                 br00 |= WRITE_ALPHA | WRITE_RGB;
1686                 break;
1687         }
1688
1689         START_RING(8);
1690         OUT_RING(br00);
1691         OUT_RING(br13);
1692         OUT_RING(br22);
1693         OUT_RING(br23);
1694         OUT_RING(br09);
1695         OUT_RING(br26);
1696         OUT_RING(br11);
1697         OUT_RING(br12);
1698         ADVANCE_RING();
1699 }
1700
1701 int
1702 intelfbhw_do_drawglyph(struct intelfb_info *dinfo, u32 fg, u32 bg, u32 w,
1703                        u32 h, const u8* cdat, u32 x, u32 y, u32 pitch, u32 bpp)
1704 {
1705         int nbytes, ndwords, pad, tmp;
1706         u32 br00, br09, br13, br18, br19, br22, br23;
1707         int dat, ix, iy, iw;
1708         int i, j;
1709
1710 #if VERBOSE > 0
1711         DBG_MSG("intelfbhw_do_drawglyph: (%d,%d) %dx%d\n", x, y, w, h);
1712 #endif
1713
1714         /* size in bytes of a padded scanline */
1715         nbytes = ROUND_UP_TO(w, 16) / 8;
1716
1717         /* Total bytes of padded scanline data to write out. */
1718         nbytes = nbytes * h;
1719
1720         /*
1721          * Check if the glyph data exceeds the immediate mode limit.
1722          * It would take a large font (1K pixels) to hit this limit.
1723          */
1724         if (nbytes > MAX_MONO_IMM_SIZE)
1725                 return 0;
1726
1727         /* Src data is packaged a dword (32-bit) at a time. */
1728         ndwords = ROUND_UP_TO(nbytes, 4) / 4;
1729
1730         /*
1731          * Ring has to be padded to a quad word. But because the command starts
1732            with 7 bytes, pad only if there is an even number of ndwords
1733          */
1734         pad = !(ndwords % 2);
1735
1736         tmp = (XY_MONO_SRC_IMM_BLT_CMD & DW_LENGTH_MASK) + ndwords;
1737         br00 = (XY_MONO_SRC_IMM_BLT_CMD & ~DW_LENGTH_MASK) | tmp;
1738         br09 = dinfo->fb_start;
1739         br13 = (SRC_ROP_GXCOPY << ROP_SHIFT) | (pitch << PITCH_SHIFT);
1740         br18 = bg;
1741         br19 = fg;
1742         br22 = (x << WIDTH_SHIFT) | (y << HEIGHT_SHIFT);
1743         br23 = ((x + w) << WIDTH_SHIFT) | ((y + h) << HEIGHT_SHIFT);
1744
1745         switch (bpp) {
1746         case 8:
1747                 br13 |= COLOR_DEPTH_8;
1748                 break;
1749         case 16:
1750                 br13 |= COLOR_DEPTH_16;
1751                 break;
1752         case 32:
1753                 br13 |= COLOR_DEPTH_32;
1754                 br00 |= WRITE_ALPHA | WRITE_RGB;
1755                 break;
1756         }
1757
1758         START_RING(8 + ndwords);
1759         OUT_RING(br00);
1760         OUT_RING(br13);
1761         OUT_RING(br22);
1762         OUT_RING(br23);
1763         OUT_RING(br09);
1764         OUT_RING(br18);
1765         OUT_RING(br19);
1766         ix = iy = 0;
1767         iw = ROUND_UP_TO(w, 8) / 8;
1768         while (ndwords--) {
1769                 dat = 0;
1770                 for (j = 0; j < 2; ++j) {
1771                         for (i = 0; i < 2; ++i) {
1772                                 if (ix != iw || i == 0)
1773                                         dat |= cdat[iy*iw + ix++] << (i+j*2)*8;
1774                         }
1775                         if (ix == iw && iy != (h-1)) {
1776                                 ix = 0;
1777                                 ++iy;
1778                         }
1779                 }
1780                 OUT_RING(dat);
1781         }
1782         if (pad)
1783                 OUT_RING(MI_NOOP);
1784         ADVANCE_RING();
1785
1786         return 1;
1787 }
1788
1789 /* HW cursor functions. */
1790 void
1791 intelfbhw_cursor_init(struct intelfb_info *dinfo)
1792 {
1793         u32 tmp;
1794
1795 #if VERBOSE > 0
1796         DBG_MSG("intelfbhw_cursor_init\n");
1797 #endif
1798
1799         if (dinfo->mobile || IS_I9XX(dinfo)) {
1800                 if (!dinfo->cursor.physical)
1801                         return;
1802                 tmp = INREG(CURSOR_A_CONTROL);
1803                 tmp &= ~(CURSOR_MODE_MASK | CURSOR_MOBILE_GAMMA_ENABLE |
1804                          CURSOR_MEM_TYPE_LOCAL |
1805                          (1 << CURSOR_PIPE_SELECT_SHIFT));
1806                 tmp |= CURSOR_MODE_DISABLE;
1807                 OUTREG(CURSOR_A_CONTROL, tmp);
1808                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1809         } else {
1810                 tmp = INREG(CURSOR_CONTROL);
1811                 tmp &= ~(CURSOR_FORMAT_MASK | CURSOR_GAMMA_ENABLE |
1812                          CURSOR_ENABLE | CURSOR_STRIDE_MASK);
1813                 tmp = CURSOR_FORMAT_3C;
1814                 OUTREG(CURSOR_CONTROL, tmp);
1815                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.offset << 12);
1816                 tmp = (64 << CURSOR_SIZE_H_SHIFT) |
1817                       (64 << CURSOR_SIZE_V_SHIFT);
1818                 OUTREG(CURSOR_SIZE, tmp);
1819         }
1820 }
1821
1822 void
1823 intelfbhw_cursor_hide(struct intelfb_info *dinfo)
1824 {
1825         u32 tmp;
1826
1827 #if VERBOSE > 0
1828         DBG_MSG("intelfbhw_cursor_hide\n");
1829 #endif
1830
1831         dinfo->cursor_on = 0;
1832         if (dinfo->mobile || IS_I9XX(dinfo)) {
1833                 if (!dinfo->cursor.physical)
1834                         return;
1835                 tmp = INREG(CURSOR_A_CONTROL);
1836                 tmp &= ~CURSOR_MODE_MASK;
1837                 tmp |= CURSOR_MODE_DISABLE;
1838                 OUTREG(CURSOR_A_CONTROL, tmp);
1839                 /* Flush changes */
1840                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1841         } else {
1842                 tmp = INREG(CURSOR_CONTROL);
1843                 tmp &= ~CURSOR_ENABLE;
1844                 OUTREG(CURSOR_CONTROL, tmp);
1845         }
1846 }
1847
1848 void
1849 intelfbhw_cursor_show(struct intelfb_info *dinfo)
1850 {
1851         u32 tmp;
1852
1853 #if VERBOSE > 0
1854         DBG_MSG("intelfbhw_cursor_show\n");
1855 #endif
1856
1857         dinfo->cursor_on = 1;
1858
1859         if (dinfo->cursor_blanked)
1860                 return;
1861
1862         if (dinfo->mobile || IS_I9XX(dinfo)) {
1863                 if (!dinfo->cursor.physical)
1864                         return;
1865                 tmp = INREG(CURSOR_A_CONTROL);
1866                 tmp &= ~CURSOR_MODE_MASK;
1867                 tmp |= CURSOR_MODE_64_4C_AX;
1868                 OUTREG(CURSOR_A_CONTROL, tmp);
1869                 /* Flush changes */
1870                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1871         } else {
1872                 tmp = INREG(CURSOR_CONTROL);
1873                 tmp |= CURSOR_ENABLE;
1874                 OUTREG(CURSOR_CONTROL, tmp);
1875         }
1876 }
1877
1878 void
1879 intelfbhw_cursor_setpos(struct intelfb_info *dinfo, int x, int y)
1880 {
1881         u32 tmp;
1882
1883 #if VERBOSE > 0
1884         DBG_MSG("intelfbhw_cursor_setpos: (%d, %d)\n", x, y);
1885 #endif
1886
1887         /*
1888          * Sets the position. The coordinates are assumed to already
1889          * have any offset adjusted. Assume that the cursor is never
1890          * completely off-screen, and that x, y are always >= 0.
1891          */
1892
1893         tmp = ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT) |
1894               ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
1895         OUTREG(CURSOR_A_POSITION, tmp);
1896
1897         if (IS_I9XX(dinfo)) {
1898                 OUTREG(CURSOR_A_BASEADDR, dinfo->cursor.physical);
1899         }
1900 }
1901
1902 void
1903 intelfbhw_cursor_setcolor(struct intelfb_info *dinfo, u32 bg, u32 fg)
1904 {
1905 #if VERBOSE > 0
1906         DBG_MSG("intelfbhw_cursor_setcolor\n");
1907 #endif
1908
1909         OUTREG(CURSOR_A_PALETTE0, bg & CURSOR_PALETTE_MASK);
1910         OUTREG(CURSOR_A_PALETTE1, fg & CURSOR_PALETTE_MASK);
1911         OUTREG(CURSOR_A_PALETTE2, fg & CURSOR_PALETTE_MASK);
1912         OUTREG(CURSOR_A_PALETTE3, bg & CURSOR_PALETTE_MASK);
1913 }
1914
1915 void
1916 intelfbhw_cursor_load(struct intelfb_info *dinfo, int width, int height,
1917                       u8 *data)
1918 {
1919         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1920         int i, j, w = width / 8;
1921         int mod = width % 8, t_mask, d_mask;
1922
1923 #if VERBOSE > 0
1924         DBG_MSG("intelfbhw_cursor_load\n");
1925 #endif
1926
1927         if (!dinfo->cursor.virtual)
1928                 return;
1929
1930         t_mask = 0xff >> mod;
1931         d_mask = ~(0xff >> mod);
1932         for (i = height; i--; ) {
1933                 for (j = 0; j < w; j++) {
1934                         writeb(0x00, addr + j);
1935                         writeb(*(data++), addr + j+8);
1936                 }
1937                 if (mod) {
1938                         writeb(t_mask, addr + j);
1939                         writeb(*(data++) & d_mask, addr + j+8);
1940                 }
1941                 addr += 16;
1942         }
1943 }
1944
1945 void
1946 intelfbhw_cursor_reset(struct intelfb_info *dinfo) {
1947         u8 __iomem *addr = (u8 __iomem *)dinfo->cursor.virtual;
1948         int i, j;
1949
1950 #if VERBOSE > 0
1951         DBG_MSG("intelfbhw_cursor_reset\n");
1952 #endif
1953
1954         if (!dinfo->cursor.virtual)
1955                 return;
1956
1957         for (i = 64; i--; ) {
1958                 for (j = 0; j < 8; j++) {
1959                         writeb(0xff, addr + j+0);
1960                         writeb(0x00, addr + j+8);
1961                 }
1962                 addr += 16;
1963         }
1964 }
1965
1966 static irqreturn_t
1967 intelfbhw_irq(int irq, void *dev_id) {
1968         int handled = 0;
1969         u16 tmp;
1970         struct intelfb_info *dinfo = (struct intelfb_info *)dev_id;
1971
1972         spin_lock(&dinfo->int_lock);
1973
1974         tmp = INREG16(IIR);
1975         tmp &= VSYNC_PIPE_A_INTERRUPT;
1976
1977         if (tmp == 0) {
1978                 spin_unlock(&dinfo->int_lock);
1979                 return IRQ_RETVAL(handled);
1980         }
1981
1982         OUTREG16(IIR, tmp);
1983
1984         if (tmp & VSYNC_PIPE_A_INTERRUPT) {
1985                 dinfo->vsync.count++;
1986                 if (dinfo->vsync.pan_display) {
1987                         dinfo->vsync.pan_display = 0;
1988                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
1989                 }
1990                 wake_up_interruptible(&dinfo->vsync.wait);
1991                 handled = 1;
1992         }
1993
1994         spin_unlock(&dinfo->int_lock);
1995
1996         return IRQ_RETVAL(handled);
1997 }
1998
1999 int
2000 intelfbhw_enable_irq(struct intelfb_info *dinfo, int reenable) {
2001
2002         if (!test_and_set_bit(0, &dinfo->irq_flags)) {
2003                 if (request_irq(dinfo->pdev->irq, intelfbhw_irq, IRQF_SHARED,
2004                      "intelfb", dinfo)) {
2005                         clear_bit(0, &dinfo->irq_flags);
2006                         return -EINVAL;
2007                 }
2008
2009                 spin_lock_irq(&dinfo->int_lock);
2010                 OUTREG16(HWSTAM, 0xfffe);
2011                 OUTREG16(IMR, 0x0);
2012                 OUTREG16(IER, VSYNC_PIPE_A_INTERRUPT);
2013                 spin_unlock_irq(&dinfo->int_lock);
2014         } else if (reenable) {
2015                 u16 ier;
2016
2017                 spin_lock_irq(&dinfo->int_lock);
2018                 ier = INREG16(IER);
2019                 if ((ier & VSYNC_PIPE_A_INTERRUPT)) {
2020                         DBG_MSG("someone disabled the IRQ [%08X]\n", ier);
2021                         OUTREG(IER, VSYNC_PIPE_A_INTERRUPT);
2022                 }
2023                 spin_unlock_irq(&dinfo->int_lock);
2024         }
2025         return 0;
2026 }
2027
2028 void
2029 intelfbhw_disable_irq(struct intelfb_info *dinfo) {
2030         u16 tmp;
2031
2032         if (test_and_clear_bit(0, &dinfo->irq_flags)) {
2033                 if (dinfo->vsync.pan_display) {
2034                         dinfo->vsync.pan_display = 0;
2035                         OUTREG(DSPABASE, dinfo->vsync.pan_offset);
2036                 }
2037                 spin_lock_irq(&dinfo->int_lock);
2038                 OUTREG16(HWSTAM, 0xffff);
2039                 OUTREG16(IMR, 0xffff);
2040                 OUTREG16(IER, 0x0);
2041
2042                 tmp = INREG16(IIR);
2043                 OUTREG16(IIR, tmp);
2044                 spin_unlock_irq(&dinfo->int_lock);
2045
2046                 free_irq(dinfo->pdev->irq, dinfo);
2047         }
2048 }
2049
2050 int
2051 intelfbhw_wait_for_vsync(struct intelfb_info *dinfo, u32 pipe) {
2052         struct intelfb_vsync *vsync;
2053         unsigned int count;
2054         int ret;
2055
2056         switch (pipe) {
2057                 case 0:
2058                         vsync = &dinfo->vsync;
2059                         break;
2060                 default:
2061                         return -ENODEV;
2062         }
2063
2064         ret = intelfbhw_enable_irq(dinfo, 0);
2065         if (ret) {
2066                 return ret;
2067         }
2068
2069         count = vsync->count;
2070         ret = wait_event_interruptible_timeout(vsync->wait, count != vsync->count, HZ/10);
2071         if (ret < 0) {
2072                 return ret;
2073         }
2074         if (ret == 0) {
2075                 intelfbhw_enable_irq(dinfo, 1);
2076                 DBG_MSG("wait_for_vsync timed out!\n");
2077                 return -ETIMEDOUT;
2078         }
2079
2080         return 0;
2081 }