2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
78 #include <asm/machdep.h>
80 #include "../macmodes.h"
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /* - must be large enough to catch all GUI-Regs */
109 /* - must be aligned to a PAGE boundary */
110 #define GUI_RESERVE (1 * PAGE_SIZE)
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114 if (!(var->activate & FB_ACTIVATE_TEST)) \
115 printk(KERN_CRIT "atyfb: " msg "\n"); \
118 #define FAIL_MAX(msg, x, _max_) do { \
120 if (!(var->activate & FB_ACTIVATE_TEST)) \
121 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
126 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #define DPRINTK(fmt, args...)
131 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
135 static const u32 lt_lcd_regs[] = {
142 0, /* EXT_VERT_STRETCH */
147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149 if (M64_HAS(LT_LCD_REGS)) {
150 aty_st_le32(lt_lcd_regs[index], val, par);
154 /* write addr byte */
155 temp = aty_ld_le32(LCD_INDEX, par);
156 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
157 /* write the register value */
158 aty_st_le32(LCD_DATA, val, par);
162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164 if (M64_HAS(LT_LCD_REGS)) {
165 return aty_ld_le32(lt_lcd_regs[index], par);
169 /* write addr byte */
170 temp = aty_ld_le32(LCD_INDEX, par);
171 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
172 /* read the register value */
173 return aty_ld_le32(LCD_DATA, par);
176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
182 * Reduce a fraction by factoring out the largest common divider of the
183 * fraction's numerator and denominator.
185 static void ATIReduceRatio(int *Numerator, int *Denominator)
187 int Multiplier, Divider, Remainder;
189 Multiplier = *Numerator;
190 Divider = *Denominator;
192 while ((Remainder = Multiplier % Divider))
194 Multiplier = Divider;
198 *Numerator /= Divider;
199 *Denominator /= Divider;
203 * The Hardware parameters for each card
206 struct pci_mmap_map {
210 unsigned long prot_flag;
211 unsigned long prot_mask;
214 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
216 .type = FB_TYPE_PACKED_PIXELS,
217 .visual = FB_VISUAL_PSEUDOCOLOR,
223 * Frame buffer device API
226 static int atyfb_open(struct fb_info *info, int user);
227 static int atyfb_release(struct fb_info *info, int user);
228 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
229 static int atyfb_set_par(struct fb_info *info);
230 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
231 u_int transp, struct fb_info *info);
232 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
233 static int atyfb_blank(int blank, struct fb_info *info);
234 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
236 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
238 static int atyfb_sync(struct fb_info *info);
244 static int aty_init(struct fb_info *info);
245 static void aty_resume_chip(struct fb_info *info);
247 static int store_video_par(char *videopar, unsigned char m64_num);
250 static struct crtc saved_crtc;
251 static union aty_pll saved_pll;
252 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
254 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
255 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
256 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
257 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
259 static int read_aty_sense(const struct atyfb_par *par);
264 * Interface used by the world
267 static struct fb_var_screeninfo default_var = {
268 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
269 640, 480, 640, 480, 0, 0, 8, 0,
270 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
271 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
272 0, FB_VMODE_NONINTERLACED
275 static struct fb_videomode defmode = {
276 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
277 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
278 0, FB_VMODE_NONINTERLACED
281 static struct fb_ops atyfb_ops = {
282 .owner = THIS_MODULE,
283 .fb_open = atyfb_open,
284 .fb_release = atyfb_release,
285 .fb_check_var = atyfb_check_var,
286 .fb_set_par = atyfb_set_par,
287 .fb_setcolreg = atyfb_setcolreg,
288 .fb_pan_display = atyfb_pan_display,
289 .fb_blank = atyfb_blank,
290 .fb_ioctl = atyfb_ioctl,
291 .fb_fillrect = atyfb_fillrect,
292 .fb_copyarea = atyfb_copyarea,
293 .fb_imageblit = atyfb_imageblit,
295 .fb_mmap = atyfb_mmap,
297 .fb_sync = atyfb_sync,
308 static int comp_sync __devinitdata = -1;
312 static int default_vmode __devinitdata = VMODE_CHOOSE;
313 static int default_cmode __devinitdata = CMODE_CHOOSE;
315 module_param_named(vmode, default_vmode, int, 0);
316 MODULE_PARM_DESC(vmode, "int: video mode for mac");
317 module_param_named(cmode, default_cmode, int, 0);
318 MODULE_PARM_DESC(cmode, "int: color mode for mac");
322 static unsigned int mach64_count __devinitdata = 0;
323 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
324 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
325 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
328 /* top -> down is an evolution of mach64 chipset, any corrections? */
329 #define ATI_CHIP_88800GX (M64F_GX)
330 #define ATI_CHIP_88800CX (M64F_GX)
332 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
333 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
335 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
336 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
338 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
339 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
340 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
342 /* FIXME what is this chip? */
343 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
345 /* make sets shorter */
346 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
349 /*#define ATI_CHIP_264GTDVD ?*/
350 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
352 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
353 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
354 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
356 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
357 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
362 int pll, mclk, xclk, ecp_max;
364 } aty_chips[] __devinitdata = {
365 #ifdef CONFIG_FB_ATY_GX
367 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
368 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
369 #endif /* CONFIG_FB_ATY_GX */
371 #ifdef CONFIG_FB_ATY_CT
372 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
373 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
375 /* FIXME what is this chip? */
376 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
378 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
379 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
381 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
382 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
384 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
386 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
388 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
389 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
390 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
391 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
393 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
394 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
395 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
396 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
397 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
399 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
400 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
401 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
402 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
403 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
405 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
406 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
407 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
408 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
409 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
410 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
412 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
413 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
414 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
415 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
416 #endif /* CONFIG_FB_ATY_CT */
420 static int __devinit correct_chipset(struct atyfb_par *par)
428 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
429 if (par->pci_id == aty_chips[i].pci_id)
432 name = aty_chips[i].name;
433 par->pll_limits.pll_max = aty_chips[i].pll;
434 par->pll_limits.mclk = aty_chips[i].mclk;
435 par->pll_limits.xclk = aty_chips[i].xclk;
436 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
437 par->features = aty_chips[i].features;
439 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
440 type = chip_id & CFG_CHIP_TYPE;
441 rev = (chip_id & CFG_CHIP_REV) >> 24;
443 switch(par->pci_id) {
444 #ifdef CONFIG_FB_ATY_GX
445 case PCI_CHIP_MACH64GX:
449 case PCI_CHIP_MACH64CX:
454 #ifdef CONFIG_FB_ATY_CT
455 case PCI_CHIP_MACH64VT:
456 switch (rev & 0x07) {
458 switch (rev & 0xc0) {
460 name = "ATI264VT (A3) (Mach64 VT)";
461 par->pll_limits.pll_max = 170;
462 par->pll_limits.mclk = 67;
463 par->pll_limits.xclk = 67;
464 par->pll_limits.ecp_max = 80;
465 par->features = ATI_CHIP_264VT;
468 name = "ATI264VT2 (A4) (Mach64 VT)";
469 par->pll_limits.pll_max = 200;
470 par->pll_limits.mclk = 67;
471 par->pll_limits.xclk = 67;
472 par->pll_limits.ecp_max = 80;
473 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
478 name = "ATI264VT3 (B1) (Mach64 VT)";
479 par->pll_limits.pll_max = 200;
480 par->pll_limits.mclk = 67;
481 par->pll_limits.xclk = 67;
482 par->pll_limits.ecp_max = 80;
483 par->features = ATI_CHIP_264VTB;
486 name = "ATI264VT3 (B2) (Mach64 VT)";
487 par->pll_limits.pll_max = 200;
488 par->pll_limits.mclk = 67;
489 par->pll_limits.xclk = 67;
490 par->pll_limits.ecp_max = 80;
491 par->features = ATI_CHIP_264VT3;
495 case PCI_CHIP_MACH64GT:
496 switch (rev & 0x07) {
498 name = "3D RAGE II (Mach64 GT)";
499 par->pll_limits.pll_max = 170;
500 par->pll_limits.mclk = 67;
501 par->pll_limits.xclk = 67;
502 par->pll_limits.ecp_max = 80;
503 par->features = ATI_CHIP_264GTB;
506 name = "3D RAGE II+ (Mach64 GT)";
507 par->pll_limits.pll_max = 200;
508 par->pll_limits.mclk = 67;
509 par->pll_limits.xclk = 67;
510 par->pll_limits.ecp_max = 100;
511 par->features = ATI_CHIP_264GTB;
518 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
522 static char ram_dram[] __devinitdata = "DRAM";
523 static char ram_resv[] __devinitdata = "RESV";
524 #ifdef CONFIG_FB_ATY_GX
525 static char ram_vram[] __devinitdata = "VRAM";
526 #endif /* CONFIG_FB_ATY_GX */
527 #ifdef CONFIG_FB_ATY_CT
528 static char ram_edo[] __devinitdata = "EDO";
529 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
530 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
531 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
532 static char ram_off[] __devinitdata = "OFF";
533 #endif /* CONFIG_FB_ATY_CT */
536 static u32 pseudo_palette[17];
538 #ifdef CONFIG_FB_ATY_GX
539 static char *aty_gx_ram[8] __devinitdata = {
540 ram_dram, ram_vram, ram_vram, ram_dram,
541 ram_dram, ram_vram, ram_vram, ram_resv
543 #endif /* CONFIG_FB_ATY_GX */
545 #ifdef CONFIG_FB_ATY_CT
546 static char *aty_ct_ram[8] __devinitdata = {
547 ram_off, ram_dram, ram_edo, ram_edo,
548 ram_sdram, ram_sgram, ram_sdram32, ram_resv
550 #endif /* CONFIG_FB_ATY_CT */
552 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
554 u32 pixclock = var->pixclock;
555 #ifdef CONFIG_FB_ATY_GENERIC_LCD
557 par->pll.ct.xres = 0;
558 if (par->lcd_table != 0) {
559 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
560 if(lcd_on_off & LCD_ON) {
561 par->pll.ct.xres = var->xres;
562 pixclock = par->lcd_pixclock;
569 #if defined(CONFIG_PPC)
572 * Apple monitor sense
575 static int __devinit read_aty_sense(const struct atyfb_par *par)
579 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
581 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
583 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
584 sense = ((i & 0x3000) >> 3) | (i & 0x100);
586 /* drive each sense line low in turn and collect the other 2 */
587 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
589 i = aty_ld_le32(GP_IO, par);
590 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
591 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
594 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
596 i = aty_ld_le32(GP_IO, par);
597 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
598 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
601 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
603 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
604 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
608 #endif /* defined(CONFIG_PPC) */
610 /* ------------------------------------------------------------------------- */
616 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
618 #ifdef CONFIG_FB_ATY_GENERIC_LCD
619 if (par->lcd_table != 0) {
620 if(!M64_HAS(LT_LCD_REGS)) {
621 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
622 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
624 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
625 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
628 /* switch to non shadow registers */
629 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
630 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
632 /* save stretching */
633 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
634 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
635 if (!M64_HAS(LT_LCD_REGS))
636 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
639 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
640 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
641 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
642 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
643 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
644 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
645 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
647 #ifdef CONFIG_FB_ATY_GENERIC_LCD
648 if (par->lcd_table != 0) {
649 /* switch to shadow registers */
650 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
651 SHADOW_EN | SHADOW_RW_EN, par);
653 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
654 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
655 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
656 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
658 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
660 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
663 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
665 #ifdef CONFIG_FB_ATY_GENERIC_LCD
666 if (par->lcd_table != 0) {
668 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
670 /* update non-shadow registers first */
671 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
672 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
673 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
675 /* temporarily disable stretching */
676 aty_st_lcd(HORZ_STRETCHING,
677 crtc->horz_stretching &
678 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
679 aty_st_lcd(VERT_STRETCHING,
680 crtc->vert_stretching &
681 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
682 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
686 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
688 DPRINTK("setting up CRTC\n");
689 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
690 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
691 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
692 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
694 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
695 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
696 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
697 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
698 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
699 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
700 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
702 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
703 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
704 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
705 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
706 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
707 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
709 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
712 if (par->accel_flags & FB_ACCELF_TEXT)
713 aty_init_engine(par, info);
715 #ifdef CONFIG_FB_ATY_GENERIC_LCD
716 /* after setting the CRTC registers we should set the LCD registers. */
717 if (par->lcd_table != 0) {
718 /* switch to shadow registers */
719 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
720 (SHADOW_EN | SHADOW_RW_EN), par);
722 DPRINTK("set shadow CRT to %ix%i %c%c\n",
723 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
724 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
726 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
727 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
728 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
729 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
731 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
732 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
733 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
734 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
736 /* restore CRTC selection & shadow state and enable stretching */
737 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
738 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
739 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
740 if(!M64_HAS(LT_LCD_REGS))
741 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
743 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
744 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
745 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
746 if(!M64_HAS(LT_LCD_REGS)) {
747 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
748 aty_ld_le32(LCD_INDEX, par);
749 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
752 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
755 static int aty_var_to_crtc(const struct fb_info *info,
756 const struct fb_var_screeninfo *var, struct crtc *crtc)
758 struct atyfb_par *par = (struct atyfb_par *) info->par;
759 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
760 u32 sync, vmode, vdisplay;
761 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
762 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
763 u32 pix_width, dp_pix_width, dp_chain_mask;
768 vxres = var->xres_virtual;
769 vyres = var->yres_virtual;
770 xoffset = var->xoffset;
771 yoffset = var->yoffset;
772 bpp = var->bits_per_pixel;
774 bpp = (var->green.length == 5) ? 15 : 16;
778 /* convert (and round up) and validate */
779 if (vxres < xres + xoffset)
780 vxres = xres + xoffset;
783 if (vyres < yres + yoffset)
784 vyres = yres + yoffset;
789 pix_width = CRTC_PIX_WIDTH_8BPP;
791 HOST_8BPP | SRC_8BPP | DST_8BPP |
792 BYTE_ORDER_LSB_TO_MSB;
793 dp_chain_mask = DP_CHAIN_8BPP;
794 } else if (bpp <= 15) {
796 pix_width = CRTC_PIX_WIDTH_15BPP;
797 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
798 BYTE_ORDER_LSB_TO_MSB;
799 dp_chain_mask = DP_CHAIN_15BPP;
800 } else if (bpp <= 16) {
802 pix_width = CRTC_PIX_WIDTH_16BPP;
803 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
804 BYTE_ORDER_LSB_TO_MSB;
805 dp_chain_mask = DP_CHAIN_16BPP;
806 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
808 pix_width = CRTC_PIX_WIDTH_24BPP;
810 HOST_8BPP | SRC_8BPP | DST_8BPP |
811 BYTE_ORDER_LSB_TO_MSB;
812 dp_chain_mask = DP_CHAIN_24BPP;
813 } else if (bpp <= 32) {
815 pix_width = CRTC_PIX_WIDTH_32BPP;
816 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
817 BYTE_ORDER_LSB_TO_MSB;
818 dp_chain_mask = DP_CHAIN_32BPP;
822 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
823 FAIL("not enough video RAM");
825 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
826 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
828 if((xres > 1600) || (yres > 1200)) {
829 FAIL("MACH64 chips are designed for max 1600x1200\n"
830 "select anoter resolution.");
832 h_sync_strt = h_disp + var->right_margin;
833 h_sync_end = h_sync_strt + var->hsync_len;
834 h_sync_dly = var->right_margin & 7;
835 h_total = h_sync_end + h_sync_dly + var->left_margin;
837 v_sync_strt = v_disp + var->lower_margin;
838 v_sync_end = v_sync_strt + var->vsync_len;
839 v_total = v_sync_end + var->upper_margin;
841 #ifdef CONFIG_FB_ATY_GENERIC_LCD
842 if (par->lcd_table != 0) {
843 if(!M64_HAS(LT_LCD_REGS)) {
844 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
845 crtc->lcd_index = lcd_index &
846 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
847 aty_st_le32(LCD_INDEX, lcd_index, par);
850 if (!M64_HAS(MOBIL_BUS))
851 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
853 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
854 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
856 crtc->lcd_gen_cntl &=
857 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
858 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
859 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
860 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
862 if((crtc->lcd_gen_cntl & LCD_ON) &&
863 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
864 /* We cannot display the mode on the LCD. If the CRT is enabled
865 we can turn off the LCD.
866 If the CRT is off, it isn't a good idea to switch it on; we don't
867 know if one is connected. So it's better to fail then.
869 if (crtc->lcd_gen_cntl & CRT_ON) {
870 if (!(var->activate & FB_ACTIVATE_TEST))
871 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
872 crtc->lcd_gen_cntl &= ~LCD_ON;
873 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
875 if (!(var->activate & FB_ACTIVATE_TEST))
876 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
882 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
884 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
885 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
886 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
888 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
890 /* This is horror! When we simulate, say 640x480 on an 800x600
891 LCD monitor, the CRTC should be programmed 800x600 values for
892 the non visible part, but 640x480 for the visible part.
893 This code has been tested on a laptop with it's 1400x1050 LCD
894 monitor and a conventional monitor both switched on.
895 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
896 works with little glitches also with DOUBLESCAN modes
898 if (yres < par->lcd_height) {
899 VScan = par->lcd_height / yres;
902 vmode |= FB_VMODE_DOUBLE;
906 h_sync_strt = h_disp + par->lcd_right_margin;
907 h_sync_end = h_sync_strt + par->lcd_hsync_len;
908 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
909 h_total = h_disp + par->lcd_hblank_len;
911 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
912 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
913 v_total = v_disp + par->lcd_vblank_len / VScan;
915 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
917 h_disp = (h_disp >> 3) - 1;
918 h_sync_strt = (h_sync_strt >> 3) - 1;
919 h_sync_end = (h_sync_end >> 3) - 1;
920 h_total = (h_total >> 3) - 1;
921 h_sync_wid = h_sync_end - h_sync_strt;
923 FAIL_MAX("h_disp too large", h_disp, 0xff);
924 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
925 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
926 if(h_sync_wid > 0x1f)
928 FAIL_MAX("h_total too large", h_total, 0x1ff);
930 if (vmode & FB_VMODE_DOUBLE) {
938 #ifdef CONFIG_FB_ATY_GENERIC_LCD
939 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
940 vdisplay = par->lcd_height;
947 v_sync_wid = v_sync_end - v_sync_strt;
949 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
950 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
951 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
952 if(v_sync_wid > 0x1f)
954 FAIL_MAX("v_total too large", v_total, 0x7ff);
956 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
961 crtc->xoffset = xoffset;
962 crtc->yoffset = yoffset;
964 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
965 crtc->vline_crnt_vline = 0;
967 crtc->h_tot_disp = h_total | (h_disp<<16);
968 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
969 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
970 crtc->v_tot_disp = v_total | (v_disp<<16);
971 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
973 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
974 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
975 crtc->gen_cntl |= CRTC_VGA_LINEAR;
977 /* Enable doublescan mode if requested */
978 if (vmode & FB_VMODE_DOUBLE)
979 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
980 /* Enable interlaced mode if requested */
981 if (vmode & FB_VMODE_INTERLACED)
982 crtc->gen_cntl |= CRTC_INTERLACE_EN;
983 #ifdef CONFIG_FB_ATY_GENERIC_LCD
984 if (par->lcd_table != 0) {
986 if(vmode & FB_VMODE_DOUBLE)
988 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
989 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
990 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
991 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
992 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
994 /* MOBILITY M1 tested, FIXME: LT */
995 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
996 if (!M64_HAS(LT_LCD_REGS))
997 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
998 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1000 crtc->horz_stretching &=
1001 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1002 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1003 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1006 * The horizontal blender misbehaves when HDisplay is less than a
1007 * a certain threshold (440 for a 1024-wide panel). It doesn't
1008 * stretch such modes enough. Use pixel replication instead of
1009 * blending to stretch modes that can be made to exactly fit the
1010 * panel width. The undocumented "NoLCDBlend" option allows the
1011 * pixel-replicated mode to be slightly wider or narrower than the
1012 * panel width. It also causes a mode that is exactly half as wide
1013 * as the panel to be pixel-replicated, rather than blended.
1015 int HDisplay = xres & ~7;
1016 int nStretch = par->lcd_width / HDisplay;
1017 int Remainder = par->lcd_width % HDisplay;
1019 if ((!Remainder && ((nStretch > 2))) ||
1020 (((HDisplay * 16) / par->lcd_width) < 7)) {
1021 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1022 int horz_stretch_loop = -1, BestRemainder;
1023 int Numerator = HDisplay, Denominator = par->lcd_width;
1025 ATIReduceRatio(&Numerator, &Denominator);
1027 BestRemainder = (Numerator * 16) / Denominator;
1028 while (--Index >= 0) {
1029 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1031 if (Remainder < BestRemainder) {
1032 horz_stretch_loop = Index;
1033 if (!(BestRemainder = Remainder))
1038 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1039 int horz_stretch_ratio = 0, Accumulator = 0;
1040 int reuse_previous = 1;
1042 Index = StretchLoops[horz_stretch_loop];
1044 while (--Index >= 0) {
1045 if (Accumulator > 0)
1046 horz_stretch_ratio |= reuse_previous;
1048 Accumulator += Denominator;
1049 Accumulator -= Numerator;
1050 reuse_previous <<= 1;
1053 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1054 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1055 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1056 break; /* Out of the do { ... } while (0) */
1060 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1061 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1065 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1066 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1067 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1069 if (!M64_HAS(LT_LCD_REGS) &&
1070 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1071 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1074 * Don't use vertical blending if the mode is too wide or not
1075 * vertically stretched.
1077 crtc->vert_stretching = 0;
1079 /* copy to shadow crtc */
1080 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1081 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1082 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1083 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1085 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1087 if (M64_HAS(MAGIC_FIFO)) {
1088 /* FIXME: display FIFO low watermark values */
1089 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1091 crtc->dp_pix_width = dp_pix_width;
1092 crtc->dp_chain_mask = dp_chain_mask;
1097 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1099 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1100 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1102 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1104 u32 double_scan, interlace;
1107 h_total = crtc->h_tot_disp & 0x1ff;
1108 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1109 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1110 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1111 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1112 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1113 v_total = crtc->v_tot_disp & 0x7ff;
1114 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1115 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1116 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1117 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1118 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1119 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1120 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1121 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1124 xres = (h_disp + 1) * 8;
1126 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1127 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1128 hslen = h_sync_wid * 8;
1129 upper = v_total - v_sync_strt - v_sync_wid;
1130 lower = v_sync_strt - v_disp;
1132 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1133 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1134 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1136 switch (pix_width) {
1138 case CRTC_PIX_WIDTH_4BPP:
1140 var->red.offset = 0;
1141 var->red.length = 8;
1142 var->green.offset = 0;
1143 var->green.length = 8;
1144 var->blue.offset = 0;
1145 var->blue.length = 8;
1146 var->transp.offset = 0;
1147 var->transp.length = 0;
1150 case CRTC_PIX_WIDTH_8BPP:
1152 var->red.offset = 0;
1153 var->red.length = 8;
1154 var->green.offset = 0;
1155 var->green.length = 8;
1156 var->blue.offset = 0;
1157 var->blue.length = 8;
1158 var->transp.offset = 0;
1159 var->transp.length = 0;
1161 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1163 var->red.offset = 10;
1164 var->red.length = 5;
1165 var->green.offset = 5;
1166 var->green.length = 5;
1167 var->blue.offset = 0;
1168 var->blue.length = 5;
1169 var->transp.offset = 0;
1170 var->transp.length = 0;
1172 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1174 var->red.offset = 11;
1175 var->red.length = 5;
1176 var->green.offset = 5;
1177 var->green.length = 6;
1178 var->blue.offset = 0;
1179 var->blue.length = 5;
1180 var->transp.offset = 0;
1181 var->transp.length = 0;
1183 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1185 var->red.offset = 16;
1186 var->red.length = 8;
1187 var->green.offset = 8;
1188 var->green.length = 8;
1189 var->blue.offset = 0;
1190 var->blue.length = 8;
1191 var->transp.offset = 0;
1192 var->transp.length = 0;
1194 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1196 var->red.offset = 16;
1197 var->red.length = 8;
1198 var->green.offset = 8;
1199 var->green.length = 8;
1200 var->blue.offset = 0;
1201 var->blue.length = 8;
1202 var->transp.offset = 24;
1203 var->transp.length = 8;
1206 PRINTKE("Invalid pixel width\n");
1213 var->xres_virtual = crtc->vxres;
1214 var->yres_virtual = crtc->vyres;
1215 var->bits_per_pixel = bpp;
1216 var->left_margin = left;
1217 var->right_margin = right;
1218 var->upper_margin = upper;
1219 var->lower_margin = lower;
1220 var->hsync_len = hslen;
1221 var->vsync_len = vslen;
1223 var->vmode = FB_VMODE_NONINTERLACED;
1224 /* In double scan mode, the vertical parameters are doubled, so we need to
1225 half them to get the right values.
1226 In interlaced mode the values are already correct, so no correction is
1230 var->vmode = FB_VMODE_INTERLACED;
1233 var->vmode = FB_VMODE_DOUBLE;
1235 var->upper_margin>>=1;
1236 var->lower_margin>>=1;
1243 /* ------------------------------------------------------------------------- */
1245 static int atyfb_set_par(struct fb_info *info)
1247 struct atyfb_par *par = (struct atyfb_par *) info->par;
1248 struct fb_var_screeninfo *var = &info->var;
1252 struct fb_var_screeninfo debug;
1258 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1261 pixclock = atyfb_get_pixclock(var, par);
1263 if (pixclock == 0) {
1264 PRINTKE("Invalid pixclock\n");
1267 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1271 par->accel_flags = var->accel_flags; /* hack */
1273 if (var->accel_flags) {
1274 info->fbops->fb_sync = atyfb_sync;
1275 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1277 info->fbops->fb_sync = NULL;
1278 info->flags |= FBINFO_HWACCEL_DISABLED;
1281 if (par->blitter_may_be_busy)
1284 aty_set_crtc(par, &par->crtc);
1285 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1286 par->pll_ops->set_pll(info, &par->pll);
1289 if(par->pll_ops && par->pll_ops->pll_to_var)
1290 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1294 if(0 == pixclock_in_ps) {
1295 PRINTKE("ALERT ops->pll_to_var get 0\n");
1296 pixclock_in_ps = pixclock;
1299 memset(&debug, 0, sizeof(debug));
1300 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1301 u32 hSync, vRefresh;
1302 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1303 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1305 h_disp = debug.xres;
1306 h_sync_strt = h_disp + debug.right_margin;
1307 h_sync_end = h_sync_strt + debug.hsync_len;
1308 h_total = h_sync_end + debug.left_margin;
1309 v_disp = debug.yres;
1310 v_sync_strt = v_disp + debug.lower_margin;
1311 v_sync_end = v_sync_strt + debug.vsync_len;
1312 v_total = v_sync_end + debug.upper_margin;
1314 hSync = 1000000000 / (pixclock_in_ps * h_total);
1315 vRefresh = (hSync * 1000) / v_total;
1316 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1318 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1321 DPRINTK("atyfb_set_par\n");
1322 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1323 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1324 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1325 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1326 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1327 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1328 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1329 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1330 h_disp, h_sync_strt, h_sync_end, h_total,
1331 v_disp, v_sync_strt, v_sync_end, v_total);
1332 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1334 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1335 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1339 if (!M64_HAS(INTEGRATED)) {
1340 /* Don't forget MEM_CNTL */
1341 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1342 switch (var->bits_per_pixel) {
1353 aty_st_le32(MEM_CNTL, tmp, par);
1355 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1356 if (!M64_HAS(MAGIC_POSTDIV))
1357 tmp |= par->mem_refresh_rate << 20;
1358 switch (var->bits_per_pixel) {
1370 if (M64_HAS(CT_BUS)) {
1371 aty_st_le32(DAC_CNTL, 0x87010184, par);
1372 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1373 } else if (M64_HAS(VT_BUS)) {
1374 aty_st_le32(DAC_CNTL, 0x87010184, par);
1375 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1376 } else if (M64_HAS(MOBIL_BUS)) {
1377 aty_st_le32(DAC_CNTL, 0x80010102, par);
1378 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1381 aty_st_le32(DAC_CNTL, 0x86010102, par);
1382 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1383 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1385 aty_st_le32(MEM_CNTL, tmp, par);
1387 aty_st_8(DAC_MASK, 0xff, par);
1389 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1390 info->fix.visual = var->bits_per_pixel <= 8 ?
1391 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1393 /* Initialize the graphics engine */
1394 if (par->accel_flags & FB_ACCELF_TEXT)
1395 aty_init_engine(par, info);
1397 #ifdef CONFIG_BOOTX_TEXT
1398 btext_update_display(info->fix.smem_start,
1399 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1400 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1401 var->bits_per_pixel,
1402 par->crtc.vxres * var->bits_per_pixel / 8);
1403 #endif /* CONFIG_BOOTX_TEXT */
1405 /* switch to accelerator mode */
1406 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1407 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1411 /* dump non shadow CRTC, pll, LCD registers */
1414 /* CRTC registers */
1416 printk("debug atyfb: Mach64 non-shadow register values:");
1417 for (i = 0; i < 256; i = i+4) {
1418 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1419 printk(" %08X", aty_ld_le32(i, par));
1423 #ifdef CONFIG_FB_ATY_CT
1426 printk("debug atyfb: Mach64 PLL register values:");
1427 for (i = 0; i < 64; i++) {
1428 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1429 if(i%4 == 0) printk(" ");
1430 printk("%02X", aty_ld_pll_ct(i, par));
1433 #endif /* CONFIG_FB_ATY_CT */
1435 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1436 if (par->lcd_table != 0) {
1439 printk("debug atyfb: LCD register values:");
1440 if(M64_HAS(LT_LCD_REGS)) {
1441 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1442 if(i == EXT_VERT_STRETCH)
1444 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1445 printk(" %08X", aty_ld_lcd(i, par));
1449 for (i = 0; i < 64; i++) {
1450 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1451 printk(" %08X", aty_ld_lcd(i, par));
1456 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1462 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1464 struct atyfb_par *par = (struct atyfb_par *) info->par;
1470 memcpy(&pll, &(par->pll), sizeof(pll));
1472 if((err = aty_var_to_crtc(info, var, &crtc)))
1475 pixclock = atyfb_get_pixclock(var, par);
1477 if (pixclock == 0) {
1478 if (!(var->activate & FB_ACTIVATE_TEST))
1479 PRINTKE("Invalid pixclock\n");
1482 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1486 if (var->accel_flags & FB_ACCELF_TEXT)
1487 info->var.accel_flags = FB_ACCELF_TEXT;
1489 info->var.accel_flags = 0;
1491 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1492 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1495 aty_crtc_to_var(&crtc, var);
1496 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1500 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1502 u32 xoffset = info->var.xoffset;
1503 u32 yoffset = info->var.yoffset;
1504 u32 vxres = par->crtc.vxres;
1505 u32 bpp = info->var.bits_per_pixel;
1507 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1512 * Open/Release the frame buffer device
1515 static int atyfb_open(struct fb_info *info, int user)
1517 struct atyfb_par *par = (struct atyfb_par *) info->par;
1528 static irqreturn_t aty_irq(int irq, void *dev_id)
1530 struct atyfb_par *par = dev_id;
1534 spin_lock(&par->int_lock);
1536 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1538 if (int_cntl & CRTC_VBLANK_INT) {
1539 /* clear interrupt */
1540 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1541 par->vblank.count++;
1542 if (par->vblank.pan_display) {
1543 par->vblank.pan_display = 0;
1544 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1546 wake_up_interruptible(&par->vblank.wait);
1550 spin_unlock(&par->int_lock);
1552 return IRQ_RETVAL(handled);
1555 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1559 if (!test_and_set_bit(0, &par->irq_flags)) {
1560 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1561 clear_bit(0, &par->irq_flags);
1564 spin_lock_irq(&par->int_lock);
1565 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1566 /* clear interrupt */
1567 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1568 /* enable interrupt */
1569 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1570 spin_unlock_irq(&par->int_lock);
1571 } else if (reenable) {
1572 spin_lock_irq(&par->int_lock);
1573 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1574 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1575 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1576 /* re-enable interrupt */
1577 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1579 spin_unlock_irq(&par->int_lock);
1585 static int aty_disable_irq(struct atyfb_par *par)
1589 if (test_and_clear_bit(0, &par->irq_flags)) {
1590 if (par->vblank.pan_display) {
1591 par->vblank.pan_display = 0;
1592 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1594 spin_lock_irq(&par->int_lock);
1595 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1596 /* disable interrupt */
1597 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1598 spin_unlock_irq(&par->int_lock);
1599 free_irq(par->irq, par);
1605 static int atyfb_release(struct fb_info *info, int user)
1607 struct atyfb_par *par = (struct atyfb_par *) info->par;
1614 int was_mmaped = par->mmaped;
1619 struct fb_var_screeninfo var;
1621 /* Now reset the default display config, we have no
1622 * idea what the program(s) which mmap'd the chip did
1623 * to the configuration, nor whether it restored it
1628 var.accel_flags &= ~FB_ACCELF_TEXT;
1630 var.accel_flags |= FB_ACCELF_TEXT;
1631 if (var.yres == var.yres_virtual) {
1632 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1633 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1634 if (var.yres_virtual < var.yres)
1635 var.yres_virtual = var.yres;
1639 aty_disable_irq(par);
1646 * Pan or Wrap the Display
1648 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1653 struct atyfb_par *par = (struct atyfb_par *) info->par;
1654 u32 xres, yres, xoffset, yoffset;
1656 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1657 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1658 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1660 xoffset = (var->xoffset + 7) & ~7;
1661 yoffset = var->yoffset;
1662 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1664 info->var.xoffset = xoffset;
1665 info->var.yoffset = yoffset;
1669 set_off_pitch(par, info);
1670 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1671 par->vblank.pan_display = 1;
1673 par->vblank.pan_display = 0;
1674 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1680 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1682 struct aty_interrupt *vbl;
1694 ret = aty_enable_irq(par, 0);
1699 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1704 aty_enable_irq(par, 1);
1713 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1714 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1720 u8 mclk_post_div; /* 1,2,3,4,8 */
1721 u8 mclk_fb_mult; /* 2 or 4 */
1722 u8 xclk_post_div; /* 1,2,3,4,8 */
1724 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1725 u32 dsp_xclks_per_row; /* 0-16383 */
1726 u32 dsp_loop_latency; /* 0-15 */
1727 u32 dsp_precision; /* 0-7 */
1728 u32 dsp_on; /* 0-2047 */
1729 u32 dsp_off; /* 0-2047 */
1732 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1733 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1736 #ifndef FBIO_WAITFORVSYNC
1737 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1742 struct atyfb_par *par = (struct atyfb_par *) info->par;
1744 struct fbtype fbtyp;
1750 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1751 fbtyp.fb_width = par->crtc.vxres;
1752 fbtyp.fb_height = par->crtc.vyres;
1753 fbtyp.fb_depth = info->var.bits_per_pixel;
1754 fbtyp.fb_cmsize = info->cmap.len;
1755 fbtyp.fb_size = info->fix.smem_len;
1756 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1759 #endif /* __sparc__ */
1761 case FBIO_WAITFORVSYNC:
1765 if (get_user(crtc, (__u32 __user *) arg))
1768 return aty_waitforvblank(par, crtc);
1772 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1774 if (M64_HAS(INTEGRATED)) {
1776 union aty_pll *pll = &(par->pll);
1777 u32 dsp_config = pll->ct.dsp_config;
1778 u32 dsp_on_off = pll->ct.dsp_on_off;
1779 clk.ref_clk_per = par->ref_clk_per;
1780 clk.pll_ref_div = pll->ct.pll_ref_div;
1781 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1782 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1783 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1784 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1785 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1786 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1787 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1788 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1789 clk.dsp_precision = (dsp_config >> 20) & 7;
1790 clk.dsp_off = dsp_on_off & 0x7ff;
1791 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1792 if (copy_to_user((struct atyclk __user *) arg, &clk,
1799 if (M64_HAS(INTEGRATED)) {
1801 union aty_pll *pll = &(par->pll);
1802 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1804 par->ref_clk_per = clk.ref_clk_per;
1805 pll->ct.pll_ref_div = clk.pll_ref_div;
1806 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1807 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1808 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1809 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1810 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1811 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1812 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1813 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1814 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1815 /*aty_calc_pll_ct(info, &pll->ct);*/
1816 aty_set_pll_ct(info, pll);
1821 if (get_user(par->features, (u32 __user *) arg))
1825 if (put_user(par->features, (u32 __user *) arg))
1828 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1835 static int atyfb_sync(struct fb_info *info)
1837 struct atyfb_par *par = (struct atyfb_par *) info->par;
1839 if (par->blitter_may_be_busy)
1845 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1847 struct atyfb_par *par = (struct atyfb_par *) info->par;
1848 unsigned int size, page, map_size = 0;
1849 unsigned long map_offset = 0;
1856 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1859 off = vma->vm_pgoff << PAGE_SHIFT;
1860 size = vma->vm_end - vma->vm_start;
1862 /* To stop the swapper from even considering these pages. */
1863 vma->vm_flags |= (VM_IO | VM_RESERVED);
1865 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1866 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1867 off += 0x8000000000000000UL;
1869 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1871 /* Each page, see which map applies */
1872 for (page = 0; page < size;) {
1874 for (i = 0; par->mmap_map[i].size; i++) {
1875 unsigned long start = par->mmap_map[i].voff;
1876 unsigned long end = start + par->mmap_map[i].size;
1877 unsigned long offset = off + page;
1884 map_size = par->mmap_map[i].size - (offset - start);
1886 par->mmap_map[i].poff + (offset - start);
1893 if (page + map_size > size)
1894 map_size = size - page;
1896 pgprot_val(vma->vm_page_prot) &=
1897 ~(par->mmap_map[i].prot_mask);
1898 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1900 if (remap_pfn_range(vma, vma->vm_start + page,
1901 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1922 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1926 for (i = 0; i < 256; i++) {
1927 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1928 if (M64_HAS(EXTRA_BRIGHT))
1930 aty_st_8(DAC_CNTL, tmp, par);
1931 aty_st_8(DAC_MASK, 0xff, par);
1933 aty_st_8(DAC_R_INDEX, i, par);
1934 atyfb_save.r[enter][i] = aty_ld_8(DAC_DATA, par);
1935 atyfb_save.g[enter][i] = aty_ld_8(DAC_DATA, par);
1936 atyfb_save.b[enter][i] = aty_ld_8(DAC_DATA, par);
1937 aty_st_8(DAC_W_INDEX, i, par);
1938 aty_st_8(DAC_DATA, atyfb_save.r[1 - enter][i], par);
1939 aty_st_8(DAC_DATA, atyfb_save.g[1 - enter][i], par);
1940 aty_st_8(DAC_DATA, atyfb_save.b[1 - enter][i], par);
1944 static void atyfb_palette(int enter)
1946 struct atyfb_par *par;
1947 struct fb_info *info;
1950 for (i = 0; i < FB_MAX; i++) {
1951 info = registered_fb[i];
1952 if (info && info->fbops == &atyfb_ops) {
1953 par = (struct atyfb_par *) info->par;
1955 atyfb_save_palette(par, enter);
1957 atyfb_save.yoffset = info->var.yoffset;
1958 info->var.yoffset = 0;
1959 set_off_pitch(par, info);
1961 info->var.yoffset = atyfb_save.yoffset;
1962 set_off_pitch(par, info);
1964 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1969 #endif /* __sparc__ */
1973 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1975 #ifdef CONFIG_PPC_PMAC
1976 /* Power management routines. Those are used for PowerBook sleep.
1978 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1983 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1984 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1985 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1986 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1992 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1993 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1995 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1997 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2001 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2003 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2005 if ((--timeout) == 0)
2007 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2011 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2012 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2015 pm |= (PWR_BLON | AUTO_PWR_UP);
2016 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2017 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2020 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2022 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2024 if ((--timeout) == 0)
2026 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2030 return timeout ? 0 : -EIO;
2034 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2036 struct fb_info *info = pci_get_drvdata(pdev);
2037 struct atyfb_par *par = (struct atyfb_par *) info->par;
2039 if (state.event == pdev->dev.power.power_state.event)
2042 acquire_console_sem();
2044 fb_set_suspend(info, 1);
2046 /* Idle & reset engine */
2048 aty_reset_engine(par);
2050 /* Blank display and LCD */
2051 atyfb_blank(FB_BLANK_POWERDOWN, info);
2054 par->lock_blank = 1;
2056 #ifdef CONFIG_PPC_PMAC
2057 /* Set chip to "suspend" mode */
2058 if (aty_power_mgmt(1, par)) {
2060 par->lock_blank = 0;
2061 atyfb_blank(FB_BLANK_UNBLANK, info);
2062 fb_set_suspend(info, 0);
2063 release_console_sem();
2067 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2070 release_console_sem();
2072 pdev->dev.power.power_state = state;
2077 static int atyfb_pci_resume(struct pci_dev *pdev)
2079 struct fb_info *info = pci_get_drvdata(pdev);
2080 struct atyfb_par *par = (struct atyfb_par *) info->par;
2082 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2085 acquire_console_sem();
2087 #ifdef CONFIG_PPC_PMAC
2088 if (pdev->dev.power.power_state.event == 2)
2089 aty_power_mgmt(0, par);
2091 pci_set_power_state(pdev, PCI_D0);
2094 aty_resume_chip(info);
2098 /* Restore display */
2099 atyfb_set_par(info);
2102 fb_set_suspend(info, 0);
2105 par->lock_blank = 0;
2106 atyfb_blank(FB_BLANK_UNBLANK, info);
2108 release_console_sem();
2110 pdev->dev.power.power_state = PMSG_ON;
2115 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2118 #ifdef CONFIG_FB_ATY_BACKLIGHT
2119 #define MAX_LEVEL 0xFF
2121 static struct backlight_properties aty_bl_data;
2123 /* Call with fb_info->bl_mutex held */
2124 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2126 struct fb_info *info = pci_get_drvdata(par->pdev);
2129 /* Get and convert the value */
2130 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2134 else if (atylevel > MAX_LEVEL)
2135 atylevel = MAX_LEVEL;
2140 /* Call with fb_info->bl_mutex held */
2141 static int __aty_bl_update_status(struct backlight_device *bd)
2143 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2144 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2147 if (bd->props->power != FB_BLANK_UNBLANK ||
2148 bd->props->fb_blank != FB_BLANK_UNBLANK)
2151 level = bd->props->brightness;
2153 reg |= (BLMOD_EN | BIASMOD_EN);
2155 reg &= ~BIAS_MOD_LEVEL_MASK;
2156 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2158 reg &= ~BIAS_MOD_LEVEL_MASK;
2159 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2161 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2166 static int aty_bl_update_status(struct backlight_device *bd)
2168 struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2169 struct fb_info *info = pci_get_drvdata(par->pdev);
2172 mutex_lock(&info->bl_mutex);
2173 ret = __aty_bl_update_status(bd);
2174 mutex_unlock(&info->bl_mutex);
2179 static int aty_bl_get_brightness(struct backlight_device *bd)
2181 return bd->props->brightness;
2184 static struct backlight_properties aty_bl_data = {
2185 .owner = THIS_MODULE,
2186 .get_brightness = aty_bl_get_brightness,
2187 .update_status = aty_bl_update_status,
2188 .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2191 static void aty_bl_set_power(struct fb_info *info, int power)
2193 mutex_lock(&info->bl_mutex);
2196 down(&info->bl_dev->sem);
2197 info->bl_dev->props->power = power;
2198 __aty_bl_update_status(info->bl_dev);
2199 up(&info->bl_dev->sem);
2202 mutex_unlock(&info->bl_mutex);
2205 static void aty_bl_init(struct atyfb_par *par)
2207 struct fb_info *info = pci_get_drvdata(par->pdev);
2208 struct backlight_device *bd;
2211 #ifdef CONFIG_PMAC_BACKLIGHT
2212 if (!pmac_has_backlight_type("ati"))
2216 snprintf(name, sizeof(name), "atybl%d", info->node);
2218 bd = backlight_device_register(name, par, &aty_bl_data);
2220 info->bl_dev = NULL;
2221 printk(KERN_WARNING "aty: Backlight registration failed\n");
2225 mutex_lock(&info->bl_mutex);
2227 fb_bl_default_curve(info, 0,
2228 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2229 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2230 mutex_unlock(&info->bl_mutex);
2233 bd->props->brightness = aty_bl_data.max_brightness;
2234 bd->props->power = FB_BLANK_UNBLANK;
2235 bd->props->update_status(bd);
2238 #ifdef CONFIG_PMAC_BACKLIGHT
2239 mutex_lock(&pmac_backlight_mutex);
2240 if (!pmac_backlight)
2241 pmac_backlight = bd;
2242 mutex_unlock(&pmac_backlight_mutex);
2245 printk("aty: Backlight initialized (%s)\n", name);
2253 static void aty_bl_exit(struct atyfb_par *par)
2255 struct fb_info *info = pci_get_drvdata(par->pdev);
2257 #ifdef CONFIG_PMAC_BACKLIGHT
2258 mutex_lock(&pmac_backlight_mutex);
2261 mutex_lock(&info->bl_mutex);
2263 #ifdef CONFIG_PMAC_BACKLIGHT
2264 if (pmac_backlight == info->bl_dev)
2265 pmac_backlight = NULL;
2268 backlight_device_unregister(info->bl_dev);
2270 printk("aty: Backlight unloaded\n");
2272 mutex_unlock(&info->bl_mutex);
2274 #ifdef CONFIG_PMAC_BACKLIGHT
2275 mutex_unlock(&pmac_backlight_mutex);
2279 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2281 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2283 const int ragepro_tbl[] = {
2284 44, 50, 55, 66, 75, 80, 100
2286 const int ragexl_tbl[] = {
2287 50, 66, 75, 83, 90, 95, 100, 105,
2288 110, 115, 120, 125, 133, 143, 166
2290 const int *refresh_tbl;
2293 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2294 refresh_tbl = ragexl_tbl;
2295 size = ARRAY_SIZE(ragexl_tbl);
2297 refresh_tbl = ragepro_tbl;
2298 size = ARRAY_SIZE(ragepro_tbl);
2301 for (i=0; i < size; i++) {
2302 if (xclk < refresh_tbl[i])
2305 par->mem_refresh_rate = i;
2312 static struct fb_info *fb_list = NULL;
2314 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2315 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2316 struct fb_var_screeninfo *var)
2320 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2322 var->xres = var->xres_virtual = par->lcd_hdisp;
2323 var->right_margin = par->lcd_right_margin;
2324 var->left_margin = par->lcd_hblank_len -
2325 (par->lcd_right_margin + par->lcd_hsync_dly +
2326 par->lcd_hsync_len);
2327 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2328 var->yres = var->yres_virtual = par->lcd_vdisp;
2329 var->lower_margin = par->lcd_lower_margin;
2330 var->upper_margin = par->lcd_vblank_len -
2331 (par->lcd_lower_margin + par->lcd_vsync_len);
2332 var->vsync_len = par->lcd_vsync_len;
2333 var->pixclock = par->lcd_pixclock;
2339 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2341 static int __devinit aty_init(struct fb_info *info)
2343 struct atyfb_par *par = (struct atyfb_par *) info->par;
2344 const char *ramname = NULL, *xtal;
2345 int gtb_memsize, has_var = 0;
2346 struct fb_var_screeninfo var;
2348 init_waitqueue_head(&par->vblank.wait);
2349 spin_lock_init(&par->int_lock);
2351 #ifdef CONFIG_PPC_PMAC
2352 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2353 * and set the frequency manually. */
2354 if (machine_is_compatible("PowerBook2,1")) {
2355 par->pll_limits.mclk = 70;
2356 par->pll_limits.xclk = 53;
2360 par->pll_limits.pll_max = pll;
2362 par->pll_limits.mclk = mclk;
2364 par->pll_limits.xclk = xclk;
2366 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2367 par->pll_per = 1000000/par->pll_limits.pll_max;
2368 par->mclk_per = 1000000/par->pll_limits.mclk;
2369 par->xclk_per = 1000000/par->pll_limits.xclk;
2371 par->ref_clk_per = 1000000000000ULL / 14318180;
2374 #ifdef CONFIG_FB_ATY_GX
2375 if (!M64_HAS(INTEGRATED)) {
2377 u8 dac_type, dac_subtype, clk_type;
2378 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2379 par->bus_type = (stat0 >> 0) & 0x07;
2380 par->ram_type = (stat0 >> 3) & 0x07;
2381 ramname = aty_gx_ram[par->ram_type];
2382 /* FIXME: clockchip/RAMDAC probing? */
2383 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2385 clk_type = CLK_ATI18818_1;
2386 dac_type = (stat0 >> 9) & 0x07;
2387 if (dac_type == 0x07)
2388 dac_subtype = DAC_ATT20C408;
2390 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2392 dac_type = DAC_IBMRGB514;
2393 dac_subtype = DAC_IBMRGB514;
2394 clk_type = CLK_IBMRGB514;
2396 switch (dac_subtype) {
2398 par->dac_ops = &aty_dac_ibm514;
2400 case DAC_ATI68860_B:
2401 case DAC_ATI68860_C:
2402 par->dac_ops = &aty_dac_ati68860b;
2406 par->dac_ops = &aty_dac_att21c498;
2409 PRINTKI("aty_init: DAC type not implemented yet!\n");
2410 par->dac_ops = &aty_dac_unsupported;
2415 case CLK_ATI18818_1:
2416 par->pll_ops = &aty_pll_ati18818_1;
2420 par->pll_ops = &aty_pll_ibm514;
2423 #if 0 /* dead code */
2425 par->pll_ops = &aty_pll_stg1703;
2428 par->pll_ops = &aty_pll_ch8398;
2431 par->pll_ops = &aty_pll_att20c408;
2435 PRINTKI("aty_init: CLK type not implemented yet!");
2436 par->pll_ops = &aty_pll_unsupported;
2440 #endif /* CONFIG_FB_ATY_GX */
2441 #ifdef CONFIG_FB_ATY_CT
2442 if (M64_HAS(INTEGRATED)) {
2443 par->dac_ops = &aty_dac_ct;
2444 par->pll_ops = &aty_pll_ct;
2445 par->bus_type = PCI;
2446 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2447 ramname = aty_ct_ram[par->ram_type];
2448 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2449 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2450 par->pll_limits.mclk = 63;
2453 if (M64_HAS(GTB_DSP)) {
2454 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2458 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2459 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2464 if (diff2 < diff1) {
2465 par->ref_clk_per = 1000000000000ULL / 29498928;
2470 #endif /* CONFIG_FB_ATY_CT */
2472 /* save previous video mode */
2473 aty_get_crtc(par, &saved_crtc);
2474 if(par->pll_ops->get_pll)
2475 par->pll_ops->get_pll(info, &saved_pll);
2477 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2478 gtb_memsize = M64_HAS(GTB_DSP);
2480 switch (par->mem_cntl & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2482 info->fix.smem_len = 0x80000;
2485 info->fix.smem_len = 0x100000;
2487 case MEM_SIZE_2M_GTB:
2488 info->fix.smem_len = 0x200000;
2490 case MEM_SIZE_4M_GTB:
2491 info->fix.smem_len = 0x400000;
2493 case MEM_SIZE_6M_GTB:
2494 info->fix.smem_len = 0x600000;
2496 case MEM_SIZE_8M_GTB:
2497 info->fix.smem_len = 0x800000;
2500 info->fix.smem_len = 0x80000;
2502 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2504 info->fix.smem_len = 0x80000;
2507 info->fix.smem_len = 0x100000;
2510 info->fix.smem_len = 0x200000;
2513 info->fix.smem_len = 0x400000;
2516 info->fix.smem_len = 0x600000;
2519 info->fix.smem_len = 0x800000;
2522 info->fix.smem_len = 0x80000;
2525 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2526 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2527 info->fix.smem_len += 0x400000;
2531 info->fix.smem_len = vram * 1024;
2532 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2533 if (info->fix.smem_len <= 0x80000)
2534 par->mem_cntl |= MEM_SIZE_512K;
2535 else if (info->fix.smem_len <= 0x100000)
2536 par->mem_cntl |= MEM_SIZE_1M;
2537 else if (info->fix.smem_len <= 0x200000)
2538 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2539 else if (info->fix.smem_len <= 0x400000)
2540 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2541 else if (info->fix.smem_len <= 0x600000)
2542 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2544 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2545 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2549 * Reg Block 0 (CT-compatible block) is at mmio_start
2550 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2553 info->fix.mmio_len = 0x400;
2554 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2555 } else if (M64_HAS(CT)) {
2556 info->fix.mmio_len = 0x400;
2557 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2558 } else if (M64_HAS(VT)) {
2559 info->fix.mmio_start -= 0x400;
2560 info->fix.mmio_len = 0x800;
2561 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2563 info->fix.mmio_start -= 0x400;
2564 info->fix.mmio_len = 0x800;
2565 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2568 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2569 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2570 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2571 par->pll_limits.mclk, par->pll_limits.xclk);
2573 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2574 if (M64_HAS(INTEGRATED)) {
2576 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2577 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2578 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2580 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2581 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2582 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2583 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2584 for (i = 0; i < 40; i++)
2585 printk(" %02x", aty_ld_pll_ct(i, par));
2589 if(par->pll_ops->init_pll)
2590 par->pll_ops->init_pll(info, &par->pll);
2591 if (par->pll_ops->resume_pll)
2592 par->pll_ops->resume_pll(info, &par->pll);
2595 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2596 * unless the auxiliary register aperture is used.
2599 if (!par->aux_start &&
2600 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2601 info->fix.smem_len -= GUI_RESERVE;
2604 * Disable register access through the linear aperture
2605 * if the auxiliary aperture is used so we can access
2606 * the full 8 MB of video RAM on 8 MB boards.
2609 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2612 par->mtrr_aper = -1;
2615 /* Cover the whole resource. */
2616 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2617 if (par->mtrr_aper >= 0 && !par->aux_start) {
2618 /* Make a hole for mmio. */
2619 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2620 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2621 if (par->mtrr_reg < 0) {
2622 mtrr_del(par->mtrr_aper, 0, 0);
2623 par->mtrr_aper = -1;
2629 info->fbops = &atyfb_ops;
2630 info->pseudo_palette = pseudo_palette;
2631 info->flags = FBINFO_DEFAULT |
2632 FBINFO_HWACCEL_IMAGEBLIT |
2633 FBINFO_HWACCEL_FILLRECT |
2634 FBINFO_HWACCEL_COPYAREA |
2635 FBINFO_HWACCEL_YPAN;
2637 #ifdef CONFIG_PMAC_BACKLIGHT
2638 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2639 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2640 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2641 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2644 if (M64_HAS(MOBIL_BUS)) {
2645 #ifdef CONFIG_FB_ATY_BACKLIGHT
2650 memset(&var, 0, sizeof(var));
2652 if (machine_is(powermac)) {
2654 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2655 * applies to all Mac video cards
2658 if (mac_find_mode(&var, info, mode, 8))
2661 if (default_vmode == VMODE_CHOOSE) {
2663 if (M64_HAS(G3_PB_1024x768))
2664 /* G3 PowerBook with 1024x768 LCD */
2665 default_vmode = VMODE_1024_768_60;
2666 else if (machine_is_compatible("iMac"))
2667 default_vmode = VMODE_1024_768_75;
2668 else if (machine_is_compatible
2670 /* iBook with 800x600 LCD */
2671 default_vmode = VMODE_800_600_60;
2673 default_vmode = VMODE_640_480_67;
2674 sense = read_aty_sense(par);
2675 PRINTKI("monitor sense=%x, mode %d\n",
2676 sense, mac_map_monitor_sense(sense));
2678 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2679 default_vmode = VMODE_640_480_60;
2680 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2681 default_cmode = CMODE_8;
2682 if (!mac_vmode_to_var(default_vmode, default_cmode,
2688 #endif /* !CONFIG_PPC */
2690 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2691 if (!atyfb_get_timings_from_lcd(par, &var))
2695 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2702 var.accel_flags &= ~FB_ACCELF_TEXT;
2704 var.accel_flags |= FB_ACCELF_TEXT;
2706 if (comp_sync != -1) {
2708 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2710 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2713 if (var.yres == var.yres_virtual) {
2714 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2715 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2716 if (var.yres_virtual < var.yres)
2717 var.yres_virtual = var.yres;
2720 if (atyfb_check_var(&var, info)) {
2721 PRINTKE("can't set default video mode\n");
2726 atyfb_save_palette(par, 0);
2729 #ifdef CONFIG_FB_ATY_CT
2730 if (!noaccel && M64_HAS(INTEGRATED))
2731 aty_init_cursor(info);
2732 #endif /* CONFIG_FB_ATY_CT */
2735 fb_alloc_cmap(&info->cmap, 256, 0);
2737 if (register_framebuffer(info) < 0)
2742 PRINTKI("fb%d: %s frame buffer device on %s\n",
2743 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2747 /* restore video mode */
2748 aty_set_crtc(par, &saved_crtc);
2749 par->pll_ops->set_pll(info, &saved_pll);
2752 if (par->mtrr_reg >= 0) {
2753 mtrr_del(par->mtrr_reg, 0, 0);
2756 if (par->mtrr_aper >= 0) {
2757 mtrr_del(par->mtrr_aper, 0, 0);
2758 par->mtrr_aper = -1;
2764 static void aty_resume_chip(struct fb_info *info)
2766 struct atyfb_par *par = info->par;
2768 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2770 if (par->pll_ops->resume_pll)
2771 par->pll_ops->resume_pll(info, &par->pll);
2774 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2778 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2781 unsigned long vmembase, size, guiregbase;
2783 PRINTKI("store_video_par() '%s' \n", video_str);
2785 if (!(p = strsep(&video_str, ";")) || !*p)
2786 goto mach64_invalid;
2787 vmembase = simple_strtoul(p, NULL, 0);
2788 if (!(p = strsep(&video_str, ";")) || !*p)
2789 goto mach64_invalid;
2790 size = simple_strtoul(p, NULL, 0);
2791 if (!(p = strsep(&video_str, ";")) || !*p)
2792 goto mach64_invalid;
2793 guiregbase = simple_strtoul(p, NULL, 0);
2795 phys_vmembase[m64_num] = vmembase;
2796 phys_size[m64_num] = size;
2797 phys_guiregbase[m64_num] = guiregbase;
2798 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2803 phys_vmembase[m64_num] = 0;
2806 #endif /* CONFIG_ATARI */
2809 * Blank the display.
2812 static int atyfb_blank(int blank, struct fb_info *info)
2814 struct atyfb_par *par = (struct atyfb_par *) info->par;
2817 if (par->lock_blank || par->asleep)
2820 #ifdef CONFIG_FB_ATY_BACKLIGHT
2821 if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2822 aty_bl_set_power(info, FB_BLANK_POWERDOWN);
2823 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2824 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2825 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2826 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2828 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2832 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2833 gen_cntl &= ~0x400004c;
2835 case FB_BLANK_UNBLANK:
2837 case FB_BLANK_NORMAL:
2838 gen_cntl |= 0x4000040;
2840 case FB_BLANK_VSYNC_SUSPEND:
2841 gen_cntl |= 0x4000048;
2843 case FB_BLANK_HSYNC_SUSPEND:
2844 gen_cntl |= 0x4000044;
2846 case FB_BLANK_POWERDOWN:
2847 gen_cntl |= 0x400004c;
2850 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2852 #ifdef CONFIG_FB_ATY_BACKLIGHT
2853 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2854 aty_bl_set_power(info, FB_BLANK_UNBLANK);
2855 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2856 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2857 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2858 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2860 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2867 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2868 const struct atyfb_par *par)
2870 aty_st_8(DAC_W_INDEX, regno, par);
2871 aty_st_8(DAC_DATA, red, par);
2872 aty_st_8(DAC_DATA, green, par);
2873 aty_st_8(DAC_DATA, blue, par);
2877 * Set a single color register. The values supplied are already
2878 * rounded down to the hardware's capabilities (according to the
2879 * entries in the var structure). Return != 0 for invalid regno.
2880 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2883 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2884 u_int transp, struct fb_info *info)
2886 struct atyfb_par *par = (struct atyfb_par *) info->par;
2888 u32 *pal = info->pseudo_palette;
2890 depth = info->var.bits_per_pixel;
2892 depth = (info->var.green.length == 5) ? 15 : 16;
2898 (depth == 16 && regno > 63) ||
2899 (depth == 15 && regno > 31))
2906 par->palette[regno].red = red;
2907 par->palette[regno].green = green;
2908 par->palette[regno].blue = blue;
2913 pal[regno] = (regno << 10) | (regno << 5) | regno;
2916 pal[regno] = (regno << 11) | (regno << 5) | regno;
2919 pal[regno] = (regno << 16) | (regno << 8) | regno;
2922 i = (regno << 8) | regno;
2923 pal[regno] = (i << 16) | i;
2928 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2929 if (M64_HAS(EXTRA_BRIGHT))
2930 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2931 aty_st_8(DAC_CNTL, i, par);
2932 aty_st_8(DAC_MASK, 0xff, par);
2934 if (M64_HAS(INTEGRATED)) {
2937 aty_st_pal(regno << 3, red,
2938 par->palette[regno<<1].green,
2940 red = par->palette[regno>>1].red;
2941 blue = par->palette[regno>>1].blue;
2943 } else if (depth == 15) {
2945 for(i = 0; i < 8; i++) {
2946 aty_st_pal(regno + i, red, green, blue, par);
2950 aty_st_pal(regno, red, green, blue, par);
2959 extern void (*prom_palette) (int);
2961 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2962 struct fb_info *info, unsigned long addr)
2964 extern int con_is_present(void);
2966 struct atyfb_par *par = info->par;
2967 struct pcidev_cookie *pcp;
2969 int node, len, i, j, ret;
2972 /* Do not attach when we have a serial console. */
2973 if (!con_is_present())
2977 * Map memory-mapped registers.
2979 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2980 info->fix.mmio_start = addr + 0x7ffc00UL;
2983 * Map in big-endian aperture.
2985 info->screen_base = (char *) (addr + 0x800000UL);
2986 info->fix.smem_start = addr + 0x800000UL;
2989 * Figure mmap addresses from PCI config space.
2990 * Split Framebuffer in big- and little-endian halfs.
2992 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2996 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2997 if (!par->mmap_map) {
2998 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
3001 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
3003 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
3004 struct resource *rp = &pdev->resource[i];
3005 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3011 io = (rp->flags & IORESOURCE_IO);
3013 size = rp->end - base + 1;
3015 pci_read_config_dword(pdev, breg, &pbase);
3021 * Map the framebuffer a second time, this time without
3022 * the braindead _PAGE_IE setting. This is used by the
3023 * fixed Xserver, but we need to maintain the old mapping
3024 * to stay compatible with older ones...
3027 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3028 par->mmap_map[j].poff = base & PAGE_MASK;
3029 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3030 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3031 par->mmap_map[j].prot_flag = _PAGE_E;
3036 * Here comes the old framebuffer mapping with _PAGE_IE
3037 * set for the big endian half of the framebuffer...
3040 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3041 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3042 par->mmap_map[j].size = 0x800000;
3043 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3044 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3049 par->mmap_map[j].voff = pbase & PAGE_MASK;
3050 par->mmap_map[j].poff = base & PAGE_MASK;
3051 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3052 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3053 par->mmap_map[j].prot_flag = _PAGE_E;
3057 if((ret = correct_chipset(par)))
3060 if (IS_XL(pdev->device)) {
3062 * Fix PROMs idea of MEM_CNTL settings...
3064 mem = aty_ld_le32(MEM_CNTL, par);
3065 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3066 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3067 switch (mem & 0x0f) {
3069 mem = (mem & ~(0x0f)) | 2;
3072 mem = (mem & ~(0x0f)) | 3;
3075 mem = (mem & ~(0x0f)) | 4;
3078 mem = (mem & ~(0x0f)) | 5;
3083 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3084 mem &= ~(0x00700000);
3086 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
3087 aty_st_le32(MEM_CNTL, mem, par);
3091 * If this is the console device, we will set default video
3092 * settings to what the PROM left us with.
3094 node = prom_getchild(prom_root_node);
3095 node = prom_searchsiblings(node, "aliases");
3097 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3100 node = prom_finddevice(prop);
3105 pcp = pdev->sysdata;
3106 if (node == pcp->prom_node->node) {
3107 struct fb_var_screeninfo *var = &default_var;
3108 unsigned int N, P, Q, M, T, R;
3109 u32 v_total, h_total;
3114 crtc.vxres = prom_getintdefault(node, "width", 1024);
3115 crtc.vyres = prom_getintdefault(node, "height", 768);
3116 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3117 var->xoffset = var->yoffset = 0;
3118 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3119 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3120 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3121 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3122 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3123 aty_crtc_to_var(&crtc, var);
3125 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3126 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3129 * Read the PLL to figure actual Refresh Rate.
3131 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3132 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3133 for (i = 0; i < 16; i++)
3134 pll_regs[i] = aty_ld_pll_ct(i, par);
3137 * PLL Reference Divider M:
3142 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3144 N = pll_regs[7 + (clock_cntl & 3)];
3147 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3149 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3163 * where R is XTALIN (= 14318 or 29498 kHz).
3165 if (IS_XL(pdev->device))
3172 default_var.pixclock = 1000000000 / T;
3178 #else /* __sparc__ */
3181 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3182 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3184 u32 driv_inf_tab, sig;
3187 /* To support an LCD panel, we should know it's dimensions and
3188 * it's desired pixel clock.
3189 * There are two ways to do it:
3190 * - Check the startup video mode and calculate the panel
3191 * size from it. This is unreliable.
3192 * - Read it from the driver information table in the video BIOS.
3194 /* Address of driver information table is at offset 0x78. */
3195 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3197 /* Check for the driver information table signature. */
3198 sig = (*(u32 *)driv_inf_tab);
3199 if ((sig == 0x54504c24) || /* Rage LT pro */
3200 (sig == 0x544d5224) || /* Rage mobility */
3201 (sig == 0x54435824) || /* Rage XC */
3202 (sig == 0x544c5824)) { /* Rage XL */
3203 PRINTKI("BIOS contains driver information table.\n");
3204 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3207 par->lcd_table = bios_base + lcd_ofs;
3211 if (par->lcd_table != 0) {
3214 char refresh_rates_buf[100];
3215 int id, tech, f, i, m, default_refresh_rate;
3220 u16 width, height, panel_type, refresh_rates;
3223 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3224 /* The most important information is the panel size at
3225 * offset 25 and 27, but there's some other nice information
3226 * which we print to the screen.
3228 id = *(u8 *)par->lcd_table;
3229 strncpy(model,(char *)par->lcd_table+1,24);
3232 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3233 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3234 panel_type = *(u16 *)(par->lcd_table+29);
3236 txtcolour = "colour";
3238 txtcolour = "monochrome";
3240 txtdual = "dual (split) ";
3243 tech = (panel_type>>2) & 63;
3246 txtmonitor = "passive matrix";
3249 txtmonitor = "active matrix";
3252 txtmonitor = "active addressed STN";
3258 txtmonitor = "plasma";
3261 txtmonitor = "unknown";
3263 format = *(u32 *)(par->lcd_table+57);
3264 if (tech == 0 || tech == 2) {
3265 switch (format & 7) {
3267 txtformat = "12 bit interface";
3270 txtformat = "16 bit interface";
3273 txtformat = "24 bit interface";
3276 txtformat = "unkown format";
3279 switch (format & 7) {
3281 txtformat = "8 colours";
3284 txtformat = "512 colours";
3287 txtformat = "4096 colours";
3290 txtformat = "262144 colours (LT mode)";
3293 txtformat = "16777216 colours";
3296 txtformat = "262144 colours (FDPI-2 mode)";
3299 txtformat = "unkown format";
3302 PRINTKI("%s%s %s monitor detected: %s\n",
3303 txtdual ,txtcolour, txtmonitor, model);
3304 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3305 id, width, height, txtformat);
3306 refresh_rates_buf[0] = 0;
3307 refresh_rates = *(u16 *)(par->lcd_table+62);
3310 for (i=0;i<16;i++) {
3311 if (refresh_rates & m) {
3313 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3316 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3318 strcat(refresh_rates_buf,strbuf);
3322 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3323 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3324 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3325 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3326 /* We now need to determine the crtc parameters for the
3327 * LCD monitor. This is tricky, because they are not stored
3328 * individually in the BIOS. Instead, the BIOS contains a
3329 * table of display modes that work for this monitor.
3331 * The idea is that we search for a mode of the same dimensions
3332 * as the dimensions of the LCD monitor. Say our LCD monitor
3333 * is 800x600 pixels, we search for a 800x600 monitor.
3334 * The CRTC parameters we find here are the ones that we need
3335 * to use to simulate other resolutions on the LCD screen.
3337 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3338 while (*lcdmodeptr != 0) {
3340 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3341 modeptr = bios_base + *lcdmodeptr;
3343 mwidth = *((u16 *)(modeptr+0));
3344 mheight = *((u16 *)(modeptr+2));
3346 if (mwidth == width && mheight == height) {
3347 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3348 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3349 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3350 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3351 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3352 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3354 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3355 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3356 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3357 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3359 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3360 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3361 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3362 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3368 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3369 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3370 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3371 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3377 if (*lcdmodeptr == 0) {
3378 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3379 /* To do: Switch to CRT if possible. */
3381 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3382 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3384 par->lcd_hdisp + par->lcd_right_margin,
3385 par->lcd_hdisp + par->lcd_right_margin
3386 + par->lcd_hsync_dly + par->lcd_hsync_len,
3389 par->lcd_vdisp + par->lcd_lower_margin,
3390 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3392 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3394 par->lcd_hblank_len - (par->lcd_right_margin +
3395 par->lcd_hsync_dly + par->lcd_hsync_len),
3397 par->lcd_right_margin,
3399 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3401 par->lcd_lower_margin,
3402 par->lcd_vsync_len);
3406 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3408 static int __devinit init_from_bios(struct atyfb_par *par)
3410 u32 bios_base, rom_addr;
3413 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3414 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3416 /* The BIOS starts with 0xaa55. */
3417 if (*((u16 *)bios_base) == 0xaa55) {
3420 u16 rom_table_offset, freq_table_offset;
3421 PLL_BLOCK_MACH64 pll_block;
3423 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3425 /* check for frequncy table */
3426 bios_ptr = (u8*)bios_base;
3427 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3428 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3429 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3431 PRINTKI("BIOS frequency table:\n");
3432 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3433 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3434 pll_block.ref_freq, pll_block.ref_divider);
3435 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3436 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3437 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3439 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3440 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3441 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3442 par->pll_limits.ref_div = pll_block.ref_divider;
3443 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3444 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3445 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3446 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3447 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3448 aty_init_lcd(par, bios_base);
3452 PRINTKE("no BIOS frequency table found, use parameters\n");
3455 iounmap((void* __iomem )bios_base);
3459 #endif /* __i386__ */
3461 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3463 struct atyfb_par *par = info->par;
3465 unsigned long raddr;
3466 struct resource *rrp;
3469 raddr = addr + 0x7ff000UL;
3470 rrp = &pdev->resource[2];
3471 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3472 par->aux_start = rrp->start;
3473 par->aux_size = rrp->end - rrp->start + 1;
3475 PRINTKI("using auxiliary register aperture\n");
3478 info->fix.mmio_start = raddr;
3479 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3480 if (par->ati_regbase == 0)
3483 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3484 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3487 * Enable memory-space accesses using config-space
3490 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3491 if (!(tmp & PCI_COMMAND_MEMORY)) {
3492 tmp |= PCI_COMMAND_MEMORY;
3493 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3496 /* Use the big-endian aperture */
3500 /* Map in frame buffer */
3501 info->fix.smem_start = addr;
3502 info->screen_base = ioremap(addr, 0x800000);
3503 if (info->screen_base == NULL) {
3505 goto atyfb_setup_generic_fail;
3508 if((ret = correct_chipset(par)))
3509 goto atyfb_setup_generic_fail;
3511 if((ret = init_from_bios(par)))
3512 goto atyfb_setup_generic_fail;
3514 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3515 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3517 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3519 /* according to ATI, we should use clock 3 for acelerated mode */
3520 par->clk_wr_offset = 3;
3524 atyfb_setup_generic_fail:
3525 iounmap(par->ati_regbase);
3526 par->ati_regbase = NULL;
3527 if (info->screen_base) {
3528 iounmap(info->screen_base);
3529 info->screen_base = NULL;
3534 #endif /* !__sparc__ */
3536 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3538 unsigned long addr, res_start, res_size;
3539 struct fb_info *info;
3540 struct resource *rp;
3541 struct atyfb_par *par;
3542 int i, rc = -ENOMEM;
3544 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3545 if (pdev->device == aty_chips[i].pci_id)
3551 /* Enable device in PCI config */
3552 if (pci_enable_device(pdev)) {
3553 PRINTKE("Cannot enable PCI device\n");
3557 /* Find which resource to use */
3558 rp = &pdev->resource[0];
3559 if (rp->flags & IORESOURCE_IO)
3560 rp = &pdev->resource[1];
3566 res_start = rp->start;
3567 res_size = rp->end - rp->start + 1;
3568 if (!request_mem_region (res_start, res_size, "atyfb"))
3571 /* Allocate framebuffer */
3572 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3574 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3578 info->fix = atyfb_fix;
3579 info->device = &pdev->dev;
3580 par->pci_id = aty_chips[i].pci_id;
3581 par->res_start = res_start;
3582 par->res_size = res_size;
3583 par->irq = pdev->irq;
3586 /* Setup "info" structure */
3588 rc = atyfb_setup_sparc(pdev, info, addr);
3590 rc = atyfb_setup_generic(pdev, info, addr);
3593 goto err_release_mem;
3595 pci_set_drvdata(pdev, info);
3597 /* Init chip & register framebuffer */
3599 goto err_release_io;
3603 prom_palette = atyfb_palette;
3606 * Add /dev/fb mmap values.
3608 par->mmap_map[0].voff = 0x8000000000000000UL;
3609 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3610 par->mmap_map[0].size = info->fix.smem_len;
3611 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3612 par->mmap_map[0].prot_flag = _PAGE_E;
3613 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3614 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3615 par->mmap_map[1].size = PAGE_SIZE;
3616 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3617 par->mmap_map[1].prot_flag = _PAGE_E;
3618 #endif /* __sparc__ */
3624 kfree(par->mmap_map);
3626 if (par->ati_regbase)
3627 iounmap(par->ati_regbase);
3628 if (info->screen_base)
3629 iounmap(info->screen_base);
3633 release_mem_region(par->aux_start, par->aux_size);
3635 release_mem_region(par->res_start, par->res_size);
3636 framebuffer_release(info);
3641 #endif /* CONFIG_PCI */
3645 static int __init atyfb_atari_probe(void)
3647 struct atyfb_par *par;
3648 struct fb_info *info;
3653 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3654 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3655 !phys_guiregbase[m64_num]) {
3656 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3660 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3662 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3667 info->fix = atyfb_fix;
3669 par->irq = (unsigned int) -1; /* something invalid */
3672 * Map the video memory (physical address given) to somewhere in the
3673 * kernel address space.
3675 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3676 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3677 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3679 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3681 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3682 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3684 switch (clock_r & 0x003F) {
3686 par->clk_wr_offset = 3; /* */
3689 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3692 par->clk_wr_offset = 1; /* */
3695 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3699 /* Fake pci_id for correct_chipset() */
3700 switch (aty_ld_le32(CONFIG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3702 par->pci_id = PCI_CHIP_MACH64GX;
3705 par->pci_id = PCI_CHIP_MACH64CX;
3711 if (correct_chipset(par) || aty_init(info)) {
3712 iounmap(info->screen_base);
3713 iounmap(par->ati_regbase);
3714 framebuffer_release(info);
3720 return num_found ? 0 : -ENXIO;
3723 #endif /* CONFIG_ATARI */
3727 static void __devexit atyfb_remove(struct fb_info *info)
3729 struct atyfb_par *par = (struct atyfb_par *) info->par;
3731 /* restore video mode */
3732 aty_set_crtc(par, &saved_crtc);
3733 par->pll_ops->set_pll(info, &saved_pll);
3735 #ifdef CONFIG_FB_ATY_BACKLIGHT
3736 if (M64_HAS(MOBIL_BUS))
3740 unregister_framebuffer(info);
3743 if (par->mtrr_reg >= 0) {
3744 mtrr_del(par->mtrr_reg, 0, 0);
3747 if (par->mtrr_aper >= 0) {
3748 mtrr_del(par->mtrr_aper, 0, 0);
3749 par->mtrr_aper = -1;
3753 if (par->ati_regbase)
3754 iounmap(par->ati_regbase);
3755 if (info->screen_base)
3756 iounmap(info->screen_base);
3758 if (info->sprite.addr)
3759 iounmap(info->sprite.addr);
3763 kfree(par->mmap_map);
3766 release_mem_region(par->aux_start, par->aux_size);
3769 release_mem_region(par->res_start, par->res_size);
3771 framebuffer_release(info);
3775 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3777 struct fb_info *info = pci_get_drvdata(pdev);
3783 * This driver uses its own matching table. That will be more difficult
3784 * to fix, so for now, we just match against any ATI ID and let the
3785 * probe() function find out what's up. That also mean we don't have
3786 * a module ID table though.
3788 static struct pci_device_id atyfb_pci_tbl[] = {
3789 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3790 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3794 static struct pci_driver atyfb_driver = {
3796 .id_table = atyfb_pci_tbl,
3797 .probe = atyfb_pci_probe,
3798 .remove = __devexit_p(atyfb_pci_remove),
3800 .suspend = atyfb_pci_suspend,
3801 .resume = atyfb_pci_resume,
3802 #endif /* CONFIG_PM */
3805 #endif /* CONFIG_PCI */
3808 static int __init atyfb_setup(char *options)
3812 if (!options || !*options)
3815 while ((this_opt = strsep(&options, ",")) != NULL) {
3816 if (!strncmp(this_opt, "noaccel", 7)) {
3819 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3822 } else if (!strncmp(this_opt, "vram:", 5))
3823 vram = simple_strtoul(this_opt + 5, NULL, 0);
3824 else if (!strncmp(this_opt, "pll:", 4))
3825 pll = simple_strtoul(this_opt + 4, NULL, 0);
3826 else if (!strncmp(this_opt, "mclk:", 5))
3827 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3828 else if (!strncmp(this_opt, "xclk:", 5))
3829 xclk = simple_strtoul(this_opt+5, NULL, 0);
3830 else if (!strncmp(this_opt, "comp_sync:", 10))
3831 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3833 else if (!strncmp(this_opt, "vmode:", 6)) {
3834 unsigned int vmode =
3835 simple_strtoul(this_opt + 6, NULL, 0);
3836 if (vmode > 0 && vmode <= VMODE_MAX)
3837 default_vmode = vmode;
3838 } else if (!strncmp(this_opt, "cmode:", 6)) {
3839 unsigned int cmode =
3840 simple_strtoul(this_opt + 6, NULL, 0);
3844 default_cmode = CMODE_8;
3848 default_cmode = CMODE_16;
3852 default_cmode = CMODE_32;
3859 * Why do we need this silly Mach64 argument?
3860 * We are already here because of mach64= so its redundant.
3862 else if (MACH_IS_ATARI
3863 && (!strncmp(this_opt, "Mach64:", 7))) {
3864 static unsigned char m64_num;
3865 static char mach64_str[80];
3866 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3867 if (!store_video_par(mach64_str, m64_num)) {
3869 mach64_count = m64_num;
3880 static int __init atyfb_init(void)
3882 int err1 = 1, err2 = 1;
3884 char *option = NULL;
3886 if (fb_get_options("atyfb", &option))
3888 atyfb_setup(option);
3892 err1 = pci_register_driver(&atyfb_driver);
3895 err2 = atyfb_atari_probe();
3898 return (err1 && err2) ? -ENODEV : 0;
3901 static void __exit atyfb_exit(void)
3904 pci_unregister_driver(&atyfb_driver);
3908 module_init(atyfb_init);
3909 module_exit(atyfb_exit);
3911 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3912 MODULE_LICENSE("GPL");
3913 module_param(noaccel, bool, 0);
3914 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3915 module_param(vram, int, 0);
3916 MODULE_PARM_DESC(vram, "int: override size of video ram");
3917 module_param(pll, int, 0);
3918 MODULE_PARM_DESC(pll, "int: override video clock");
3919 module_param(mclk, int, 0);
3920 MODULE_PARM_DESC(mclk, "int: override memory clock");
3921 module_param(xclk, int, 0);
3922 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3923 module_param(comp_sync, int, 0);
3924 MODULE_PARM_DESC(comp_sync,
3925 "Set composite sync signal to low (0) or high (1)");
3926 module_param(mode, charp, 0);
3927 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3929 module_param(nomtrr, bool, 0);
3930 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob