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   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/config.h>
  53 #include <linux/module.h>
  54 #include <linux/moduleparam.h>
  55 #include <linux/kernel.h>
  56 #include <linux/errno.h>
  57 #include <linux/string.h>
  58 #include <linux/mm.h>
  59 #include <linux/slab.h>
  60 #include <linux/vmalloc.h>
  61 #include <linux/delay.h>
  62 #include <linux/console.h>
  63 #include <linux/fb.h>
  64 #include <linux/init.h>
  65 #include <linux/pci.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/spinlock.h>
  68 #include <linux/wait.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/prom.h>
  79 #include "../macmodes.h"
  80 #endif
  81 #ifdef __sparc__
  82 #include <asm/pbm.h>
  83 #include <asm/fbio.h>
  84 #endif
  85
  86 #ifdef CONFIG_ADB_PMU
  87 #include <linux/adb.h>
  88 #include <linux/pmu.h>
  89 #endif
  90 #ifdef CONFIG_BOOTX_TEXT
  91 #include <asm/btext.h>
  92 #endif
  93 #ifdef CONFIG_PMAC_BACKLIGHT
  94 #include <asm/backlight.h>
  95 #endif
  96 #ifdef CONFIG_MTRR
  97 #include <asm/mtrr.h>
  98 #endif
  99
 100 /*
 101  * Debug flags.
 102  */
 103 #undef DEBUG
 104 /*#define DEBUG*/
 105
 106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 107 /*  - must be large enough to catch all GUI-Regs   */
 108 /*  - must be aligned to a PAGE boundary           */
 109 #define GUI_RESERVE     (1 * PAGE_SIZE)
 110
 111 /* FIXME: remove the FAIL definition */
 112 #define FAIL(msg) do { \
 113         if (!(var->activate & FB_ACTIVATE_TEST)) \
 114                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 115         return -EINVAL; \
 116 } while (0)
 117 #define FAIL_MAX(msg, x, _max_) do { \
 118         if (x > _max_) { \
 119                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 120                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 121                 return -EINVAL; \
 122         } \
 123 } while (0)
 124 #ifdef DEBUG
 125 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 126 #else
 127 #define DPRINTK(fmt, args...)
 128 #endif
 129
 130 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 131 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 132
 133 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 134 static const u32 lt_lcd_regs[] = {
 135         CONFIG_PANEL_LG,
 136         LCD_GEN_CNTL_LG,
 137         DSTN_CONTROL_LG,
 138         HFB_PITCH_ADDR_LG,
 139         HORZ_STRETCHING_LG,
 140         VERT_STRETCHING_LG,
 141         0, /* EXT_VERT_STRETCH */
 142         LT_GIO_LG,
 143         POWER_MANAGEMENT_LG
 144 };
 145
 146 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 147 {
 148         if (M64_HAS(LT_LCD_REGS)) {
 149                 aty_st_le32(lt_lcd_regs[index], val, par);
 150         } else {
 151                 unsigned long temp;
 152
 153                 /* write addr byte */
 154                 temp = aty_ld_le32(LCD_INDEX, par);
 155                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 156                 /* write the register value */
 157                 aty_st_le32(LCD_DATA, val, par);
 158         }
 159 }
 160
 161 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 162 {
 163         if (M64_HAS(LT_LCD_REGS)) {
 164                 return aty_ld_le32(lt_lcd_regs[index], par);
 165         } else {
 166                 unsigned long temp;
 167
 168                 /* write addr byte */
 169                 temp = aty_ld_le32(LCD_INDEX, par);
 170                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 171                 /* read the register value */
 172                 return aty_ld_le32(LCD_DATA, par);
 173         }
 174 }
 175 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 176
 177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 178 /*
 179  * ATIReduceRatio --
 180  *
 181  * Reduce a fraction by factoring out the largest common divider of the
 182  * fraction's numerator and denominator.
 183  */
 184 static void ATIReduceRatio(int *Numerator, int *Denominator)
 185 {
 186     int Multiplier, Divider, Remainder;
 187
 188     Multiplier = *Numerator;
 189     Divider = *Denominator;
 190
 191     while ((Remainder = Multiplier % Divider))
 192     {
 193         Multiplier = Divider;
 194         Divider = Remainder;
 195     }
 196
 197     *Numerator /= Divider;
 198     *Denominator /= Divider;
 199 }
 200 #endif
 201     /*
 202      *  The Hardware parameters for each card
 203      */
 204
 205 struct aty_cmap_regs {
 206         u8 windex;
 207         u8 lut;
 208         u8 mask;
 209         u8 rindex;
 210         u8 cntl;
 211 };
 212
 213 struct pci_mmap_map {
 214         unsigned long voff;
 215         unsigned long poff;
 216         unsigned long size;
 217         unsigned long prot_flag;
 218         unsigned long prot_mask;
 219 };
 220
 221 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 222         .id             = "ATY Mach64",
 223         .type           = FB_TYPE_PACKED_PIXELS,
 224         .visual         = FB_VISUAL_PSEUDOCOLOR,
 225         .xpanstep       = 8,
 226         .ypanstep       = 1,
 227 };
 228
 229     /*
 230      *  Frame buffer device API
 231      */
 232
 233 static int atyfb_open(struct fb_info *info, int user);
 234 static int atyfb_release(struct fb_info *info, int user);
 235 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 236 static int atyfb_set_par(struct fb_info *info);
 237 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 238         u_int transp, struct fb_info *info);
 239 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 240 static int atyfb_blank(int blank, struct fb_info *info);
 241 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 242 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
 243 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 244 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
 245 #ifdef __sparc__
 246 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 247 #endif
 248 static int atyfb_sync(struct fb_info *info);
 249
 250     /*
 251      *  Internal routines
 252      */
 253
 254 static int aty_init(struct fb_info *info, const char *name);
 255 #ifdef CONFIG_ATARI
 256 static int store_video_par(char *videopar, unsigned char m64_num);
 257 #endif
 258
 259 static struct crtc saved_crtc;
 260 static union aty_pll saved_pll;
 261 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 262
 263 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 264 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 265 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 266 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 267 #ifdef CONFIG_PPC
 268 static int read_aty_sense(const struct atyfb_par *par);
 269 #endif
 270
 271
 272     /*
 273      *  Interface used by the world
 274      */
 275
 276 static struct fb_var_screeninfo default_var = {
 277         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 278         640, 480, 640, 480, 0, 0, 8, 0,
 279         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 280         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 281         0, FB_VMODE_NONINTERLACED
 282 };
 283
 284 static struct fb_videomode defmode = {
 285         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 286         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 287         0, FB_VMODE_NONINTERLACED
 288 };
 289
 290 static struct fb_ops atyfb_ops = {
 291         .owner          = THIS_MODULE,
 292         .fb_open        = atyfb_open,
 293         .fb_release     = atyfb_release,
 294         .fb_check_var   = atyfb_check_var,
 295         .fb_set_par     = atyfb_set_par,
 296         .fb_setcolreg   = atyfb_setcolreg,
 297         .fb_pan_display = atyfb_pan_display,
 298         .fb_blank       = atyfb_blank,
 299         .fb_ioctl       = atyfb_ioctl,
 300         .fb_fillrect    = atyfb_fillrect,
 301         .fb_copyarea    = atyfb_copyarea,
 302         .fb_imageblit   = atyfb_imageblit,
 303 #ifdef __sparc__
 304         .fb_mmap        = atyfb_mmap,
 305 #endif
 306         .fb_sync        = atyfb_sync,
 307 };
 308
 309 static int noaccel;
 310 #ifdef CONFIG_MTRR
 311 static int nomtrr;
 312 #endif
 313 static int vram;
 314 static int pll;
 315 static int mclk;
 316 static int xclk;
 317 static int comp_sync __initdata = -1;
 318 static char *mode;
 319
 320 #ifdef CONFIG_PPC
 321 static int default_vmode __initdata = VMODE_CHOOSE;
 322 static int default_cmode __initdata = CMODE_CHOOSE;
 323
 324 module_param_named(vmode, default_vmode, int, 0);
 325 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 326 module_param_named(cmode, default_cmode, int, 0);
 327 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 328 #endif
 329
 330 #ifdef CONFIG_ATARI
 331 static unsigned int mach64_count __initdata = 0;
 332 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
 333 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
 334 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
 335 #endif
 336
 337 /* top -> down is an evolution of mach64 chipset, any corrections? */
 338 #define ATI_CHIP_88800GX   (M64F_GX)
 339 #define ATI_CHIP_88800CX   (M64F_GX)
 340
 341 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 342 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 343
 344 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 345 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 346
 347 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 348 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 349 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 350
 351 /* FIXME what is this chip? */
 352 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 353
 354 /* make sets shorter */
 355 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 356
 357 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 358 /*#define ATI_CHIP_264GTDVD  ?*/
 359 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 360
 361 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 362 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 363 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 364
 365 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 366 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 367
 368 static struct {
 369         u16 pci_id;
 370         const char *name;
 371         int pll, mclk, xclk, ecp_max;
 372         u32 features;
 373 } aty_chips[] __devinitdata = {
 374 #ifdef CONFIG_FB_ATY_GX
 375         /* Mach64 GX */
 376         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 377         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 378 #endif /* CONFIG_FB_ATY_GX */
 379
 380 #ifdef CONFIG_FB_ATY_CT
 381         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 382         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 383
 384         /* FIXME what is this chip? */
 385         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 386
 387         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 388         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 389
 390         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 391         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 392
 393         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 394
 395         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 396
 397         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 398         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 399         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 400         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 401
 402         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 403         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 404         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 405         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 406         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 407
 408         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 409         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 410         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 411         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 412         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 413
 414         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 415         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 416         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 417         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 418         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 419         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 420
 421         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 422         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 423         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 424         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 425 #endif /* CONFIG_FB_ATY_CT */
 426 };
 427
 428 /* can not fail */
 429 static int __devinit correct_chipset(struct atyfb_par *par)
 430 {
 431         u8 rev;
 432         u16 type;
 433         u32 chip_id;
 434         const char *name;
 435         int i;
 436
 437         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
 438                 if (par->pci_id == aty_chips[i].pci_id)
 439                         break;
 440
 441         name = aty_chips[i].name;
 442         par->pll_limits.pll_max = aty_chips[i].pll;
 443         par->pll_limits.mclk = aty_chips[i].mclk;
 444         par->pll_limits.xclk = aty_chips[i].xclk;
 445         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 446         par->features = aty_chips[i].features;
 447
 448         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 449         type = chip_id & CFG_CHIP_TYPE;
 450         rev = (chip_id & CFG_CHIP_REV) >> 24;
 451
 452         switch(par->pci_id) {
 453 #ifdef CONFIG_FB_ATY_GX
 454         case PCI_CHIP_MACH64GX:
 455                 if(type != 0x00d7)
 456                         return -ENODEV;
 457                 break;
 458         case PCI_CHIP_MACH64CX:
 459                 if(type != 0x0057)
 460                         return -ENODEV;
 461                 break;
 462 #endif
 463 #ifdef CONFIG_FB_ATY_CT
 464         case PCI_CHIP_MACH64VT:
 465                 switch (rev & 0x07) {
 466                 case 0x00:
 467                         switch (rev & 0xc0) {
 468                         case 0x00:
 469                                 name = "ATI264VT (A3) (Mach64 VT)";
 470                                 par->pll_limits.pll_max = 170;
 471                                 par->pll_limits.mclk = 67;
 472                                 par->pll_limits.xclk = 67;
 473                                 par->pll_limits.ecp_max = 80;
 474                                 par->features = ATI_CHIP_264VT;
 475                                 break;
 476                         case 0x40:
 477                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 478                                 par->pll_limits.pll_max = 200;
 479                                 par->pll_limits.mclk = 67;
 480                                 par->pll_limits.xclk = 67;
 481                                 par->pll_limits.ecp_max = 80;
 482                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 483                                 break;
 484                         }
 485                         break;
 486                 case 0x01:
 487                         name = "ATI264VT3 (B1) (Mach64 VT)";
 488                         par->pll_limits.pll_max = 200;
 489                         par->pll_limits.mclk = 67;
 490                         par->pll_limits.xclk = 67;
 491                         par->pll_limits.ecp_max = 80;
 492                         par->features = ATI_CHIP_264VTB;
 493                         break;
 494                 case 0x02:
 495                         name = "ATI264VT3 (B2) (Mach64 VT)";
 496                         par->pll_limits.pll_max = 200;
 497                         par->pll_limits.mclk = 67;
 498                         par->pll_limits.xclk = 67;
 499                         par->pll_limits.ecp_max = 80;
 500                         par->features = ATI_CHIP_264VT3;
 501                         break;
 502                 }
 503                 break;
 504         case PCI_CHIP_MACH64GT:
 505                 switch (rev & 0x07) {
 506                 case 0x01:
 507                         name = "3D RAGE II (Mach64 GT)";
 508                         par->pll_limits.pll_max = 170;
 509                         par->pll_limits.mclk = 67;
 510                         par->pll_limits.xclk = 67;
 511                         par->pll_limits.ecp_max = 80;
 512                         par->features = ATI_CHIP_264GTB;
 513                         break;
 514                 case 0x02:
 515                         name = "3D RAGE II+ (Mach64 GT)";
 516                         par->pll_limits.pll_max = 200;
 517                         par->pll_limits.mclk = 67;
 518                         par->pll_limits.xclk = 67;
 519                         par->pll_limits.ecp_max = 100;
 520                         par->features = ATI_CHIP_264GTB;
 521                         break;
 522                 }
 523                 break;
 524 #endif
 525         }
 526
 527         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 528         return 0;
 529 }
 530
 531 static char ram_dram[] __devinitdata = "DRAM";
 532 static char ram_resv[] __devinitdata = "RESV";
 533 #ifdef CONFIG_FB_ATY_GX
 534 static char ram_vram[] __devinitdata = "VRAM";
 535 #endif /* CONFIG_FB_ATY_GX */
 536 #ifdef CONFIG_FB_ATY_CT
 537 static char ram_edo[] __devinitdata = "EDO";
 538 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 539 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 540 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 541 static char ram_off[] __devinitdata = "OFF";
 542 #endif /* CONFIG_FB_ATY_CT */
 543
 544
 545 static u32 pseudo_palette[17];
 546
 547 #ifdef CONFIG_FB_ATY_GX
 548 static char *aty_gx_ram[8] __devinitdata = {
 549         ram_dram, ram_vram, ram_vram, ram_dram,
 550         ram_dram, ram_vram, ram_vram, ram_resv
 551 };
 552 #endif /* CONFIG_FB_ATY_GX */
 553
 554 #ifdef CONFIG_FB_ATY_CT
 555 static char *aty_ct_ram[8] __devinitdata = {
 556         ram_off, ram_dram, ram_edo, ram_edo,
 557         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 558 };
 559 #endif /* CONFIG_FB_ATY_CT */
 560
 561 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 562 {
 563         u32 pixclock = var->pixclock;
 564 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 565         u32 lcd_on_off;
 566         par->pll.ct.xres = 0;
 567         if (par->lcd_table != 0) {
 568                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 569                 if(lcd_on_off & LCD_ON) {
 570                         par->pll.ct.xres = var->xres;
 571                         pixclock = par->lcd_pixclock;
 572                 }
 573         }
 574 #endif
 575         return pixclock;
 576 }
 577
 578 #if defined(CONFIG_PPC)
 579
 580 /*
 581  *  Apple monitor sense
 582  */
 583
 584 static int __init read_aty_sense(const struct atyfb_par *par)
 585 {
 586         int sense, i;
 587
 588         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 589         __delay(200);
 590         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 591         __delay(2000);
 592         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 593         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 594
 595         /* drive each sense line low in turn and collect the other 2 */
 596         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 597         __delay(2000);
 598         i = aty_ld_le32(GP_IO, par);
 599         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 600         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 601         __delay(200);
 602
 603         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 604         __delay(2000);
 605         i = aty_ld_le32(GP_IO, par);
 606         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 607         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 608         __delay(200);
 609
 610         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 611         __delay(2000);
 612         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 613         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 614         return sense;
 615 }
 616
 617 #endif /* defined(CONFIG_PPC) */
 618
 619 /* ------------------------------------------------------------------------- */
 620
 621 /*
 622  *  CRTC programming
 623  */
 624
 625 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 626 {
 627 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 628         if (par->lcd_table != 0) {
 629                 if(!M64_HAS(LT_LCD_REGS)) {
 630                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 631                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 632                 }
 633                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 634                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 635
 636
 637                 /* switch to non shadow registers */
 638                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 639                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 640
 641                 /* save stretching */
 642                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 643                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 644                 if (!M64_HAS(LT_LCD_REGS))
 645                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 646         }
 647 #endif
 648         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 649         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 650         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 651         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 652         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 653         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 654         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 655
 656 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 657         if (par->lcd_table != 0) {
 658                 /* switch to shadow registers */
 659                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 660                         SHADOW_EN | SHADOW_RW_EN, par);
 661
 662                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 663                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 664                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 665                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 666
 667                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 668         }
 669 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 670 }
 671
 672 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 673 {
 674 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 675         if (par->lcd_table != 0) {
 676                 /* stop CRTC */
 677                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 678
 679                 /* update non-shadow registers first */
 680                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 681                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 682                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 683
 684                 /* temporarily disable stretching */
 685                 aty_st_lcd(HORZ_STRETCHING,
 686                         crtc->horz_stretching &
 687                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 688                 aty_st_lcd(VERT_STRETCHING,
 689                         crtc->vert_stretching &
 690                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 691                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 692         }
 693 #endif
 694         /* turn off CRT */
 695         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 696
 697         DPRINTK("setting up CRTC\n");
 698         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 699             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 700             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 701             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 702
 703         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 704         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 705         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 706         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 707         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 708         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 709         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 710
 711         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 712         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 713         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 714         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 715         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 716         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 717
 718         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 719 #if 0
 720         FIXME
 721         if (par->accel_flags & FB_ACCELF_TEXT)
 722                 aty_init_engine(par, info);
 723 #endif
 724 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 725         /* after setting the CRTC registers we should set the LCD registers. */
 726         if (par->lcd_table != 0) {
 727                 /* switch to shadow registers */
 728                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 729                         (SHADOW_EN | SHADOW_RW_EN), par);
 730
 731                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 732                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 733                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 734
 735                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 736                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 737                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 738                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 739
 740                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 741                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 742                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 743                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 744
 745                 /* restore CRTC selection & shadow state and enable stretching */
 746                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 747                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 748                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 749                 if(!M64_HAS(LT_LCD_REGS))
 750                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 751
 752                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 753                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 754                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 755                 if(!M64_HAS(LT_LCD_REGS)) {
 756                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 757                     aty_ld_le32(LCD_INDEX, par);
 758                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 759                 }
 760         }
 761 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 762 }
 763
 764 static int aty_var_to_crtc(const struct fb_info *info,
 765         const struct fb_var_screeninfo *var, struct crtc *crtc)
 766 {
 767         struct atyfb_par *par = (struct atyfb_par *) info->par;
 768         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 769         u32 sync, vmode, vdisplay;
 770         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 771         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 772         u32 pix_width, dp_pix_width, dp_chain_mask;
 773
 774         /* input */
 775         xres = var->xres;
 776         yres = var->yres;
 777         vxres = var->xres_virtual;
 778         vyres = var->yres_virtual;
 779         xoffset = var->xoffset;
 780         yoffset = var->yoffset;
 781         bpp = var->bits_per_pixel;
 782         if (bpp == 16)
 783                 bpp = (var->green.length == 5) ? 15 : 16;
 784         sync = var->sync;
 785         vmode = var->vmode;
 786
 787         /* convert (and round up) and validate */
 788         if (vxres < xres + xoffset)
 789                 vxres = xres + xoffset;
 790         h_disp = xres;
 791
 792         if (vyres < yres + yoffset)
 793                 vyres = yres + yoffset;
 794         v_disp = yres;
 795
 796         if (bpp <= 8) {
 797                 bpp = 8;
 798                 pix_width = CRTC_PIX_WIDTH_8BPP;
 799                 dp_pix_width =
 800                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 801                     BYTE_ORDER_LSB_TO_MSB;
 802                 dp_chain_mask = DP_CHAIN_8BPP;
 803         } else if (bpp <= 15) {
 804                 bpp = 16;
 805                 pix_width = CRTC_PIX_WIDTH_15BPP;
 806                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 807                     BYTE_ORDER_LSB_TO_MSB;
 808                 dp_chain_mask = DP_CHAIN_15BPP;
 809         } else if (bpp <= 16) {
 810                 bpp = 16;
 811                 pix_width = CRTC_PIX_WIDTH_16BPP;
 812                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 813                     BYTE_ORDER_LSB_TO_MSB;
 814                 dp_chain_mask = DP_CHAIN_16BPP;
 815         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 816                 bpp = 24;
 817                 pix_width = CRTC_PIX_WIDTH_24BPP;
 818                 dp_pix_width =
 819                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 820                     BYTE_ORDER_LSB_TO_MSB;
 821                 dp_chain_mask = DP_CHAIN_24BPP;
 822         } else if (bpp <= 32) {
 823                 bpp = 32;
 824                 pix_width = CRTC_PIX_WIDTH_32BPP;
 825                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 826                     BYTE_ORDER_LSB_TO_MSB;
 827                 dp_chain_mask = DP_CHAIN_32BPP;
 828         } else
 829                 FAIL("invalid bpp");
 830
 831         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 832                 FAIL("not enough video RAM");
 833
 834         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 835         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 836
 837         if((xres > 1600) || (yres > 1200)) {
 838                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 839                 "select anoter resolution.");
 840         }
 841         h_sync_strt = h_disp + var->right_margin;
 842         h_sync_end = h_sync_strt + var->hsync_len;
 843         h_sync_dly  = var->right_margin & 7;
 844         h_total = h_sync_end + h_sync_dly + var->left_margin;
 845
 846         v_sync_strt = v_disp + var->lower_margin;
 847         v_sync_end = v_sync_strt + var->vsync_len;
 848         v_total = v_sync_end + var->upper_margin;
 849
 850 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 851         if (par->lcd_table != 0) {
 852                 if(!M64_HAS(LT_LCD_REGS)) {
 853                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 854                     crtc->lcd_index = lcd_index &
 855                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 856                     aty_st_le32(LCD_INDEX, lcd_index, par);
 857                 }
 858
 859                 if (!M64_HAS(MOBIL_BUS))
 860                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 861
 862                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 863                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 864
 865                 crtc->lcd_gen_cntl &=
 866                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 867                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 868                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 869                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 870
 871                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 872                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 873                         /* We cannot display the mode on the LCD. If the CRT is enabled
 874                            we can turn off the LCD.
 875                            If the CRT is off, it isn't a good idea to switch it on; we don't
 876                            know if one is connected. So it's better to fail then.
 877                          */
 878                         if (crtc->lcd_gen_cntl & CRT_ON) {
 879                                 if (!(var->activate & FB_ACTIVATE_TEST))
 880                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 881                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 882                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 883                         } else {
 884                                 if (!(var->activate & FB_ACTIVATE_TEST))
 885                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 886                                 return -EINVAL;
 887                         }
 888                 }
 889         }
 890
 891         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 892                 int VScan = 1;
 893                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 894                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 895                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 896
 897                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 898
 899                 /* This is horror! When we simulate, say 640x480 on an 800x600
 900                    LCD monitor, the CRTC should be programmed 800x600 values for
 901                    the non visible part, but 640x480 for the visible part.
 902                    This code has been tested on a laptop with it's 1400x1050 LCD
 903                    monitor and a conventional monitor both switched on.
 904                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 905                     works with little glitches also with DOUBLESCAN modes
 906                  */
 907                 if (yres < par->lcd_height) {
 908                         VScan = par->lcd_height / yres;
 909                         if(VScan > 1) {
 910                                 VScan = 2;
 911                                 vmode |= FB_VMODE_DOUBLE;
 912                         }
 913                 }
 914
 915                 h_sync_strt = h_disp + par->lcd_right_margin;
 916                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 917                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 918                 h_total = h_disp + par->lcd_hblank_len;
 919
 920                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 921                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 922                 v_total = v_disp + par->lcd_vblank_len / VScan;
 923         }
 924 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 925
 926         h_disp = (h_disp >> 3) - 1;
 927         h_sync_strt = (h_sync_strt >> 3) - 1;
 928         h_sync_end = (h_sync_end >> 3) - 1;
 929         h_total = (h_total >> 3) - 1;
 930         h_sync_wid = h_sync_end - h_sync_strt;
 931
 932         FAIL_MAX("h_disp too large", h_disp, 0xff);
 933         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 934         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 935         if(h_sync_wid > 0x1f)
 936                 h_sync_wid = 0x1f;
 937         FAIL_MAX("h_total too large", h_total, 0x1ff);
 938
 939         if (vmode & FB_VMODE_DOUBLE) {
 940                 v_disp <<= 1;
 941                 v_sync_strt <<= 1;
 942                 v_sync_end <<= 1;
 943                 v_total <<= 1;
 944         }
 945
 946         vdisplay = yres;
 947 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 948         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 949                 vdisplay  = par->lcd_height;
 950 #endif
 951
 952         v_disp--;
 953         v_sync_strt--;
 954         v_sync_end--;
 955         v_total--;
 956         v_sync_wid = v_sync_end - v_sync_strt;
 957
 958         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 959         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 960         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 961         if(v_sync_wid > 0x1f)
 962                 v_sync_wid = 0x1f;
 963         FAIL_MAX("v_total too large", v_total, 0x7ff);
 964
 965         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 966
 967         /* output */
 968         crtc->vxres = vxres;
 969         crtc->vyres = vyres;
 970         crtc->xoffset = xoffset;
 971         crtc->yoffset = yoffset;
 972         crtc->bpp = bpp;
 973         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 974         crtc->vline_crnt_vline = 0;
 975
 976         crtc->h_tot_disp = h_total | (h_disp<<16);
 977         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 978                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 979         crtc->v_tot_disp = v_total | (v_disp<<16);
 980         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 981
 982         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 983         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 984         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 985
 986         /* Enable doublescan mode if requested */
 987         if (vmode & FB_VMODE_DOUBLE)
 988                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 989         /* Enable interlaced mode if requested */
 990         if (vmode & FB_VMODE_INTERLACED)
 991                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 992 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 993         if (par->lcd_table != 0) {
 994                 vdisplay = yres;
 995                 if(vmode & FB_VMODE_DOUBLE)
 996                         vdisplay <<= 1;
 997                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 998                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 999                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1000                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1001                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1002
1003                 /* MOBILITY M1 tested, FIXME: LT */
1004                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1005                 if (!M64_HAS(LT_LCD_REGS))
1006                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1007                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1008
1009                 crtc->horz_stretching &=
1010                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1011                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1012                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1013                         do {
1014                                 /*
1015                                 * The horizontal blender misbehaves when HDisplay is less than a
1016                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1017                                 * stretch such modes enough.  Use pixel replication instead of
1018                                 * blending to stretch modes that can be made to exactly fit the
1019                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1020                                 * pixel-replicated mode to be slightly wider or narrower than the
1021                                 * panel width.  It also causes a mode that is exactly half as wide
1022                                 * as the panel to be pixel-replicated, rather than blended.
1023                                 */
1024                                 int HDisplay  = xres & ~7;
1025                                 int nStretch  = par->lcd_width / HDisplay;
1026                                 int Remainder = par->lcd_width % HDisplay;
1027
1028                                 if ((!Remainder && ((nStretch > 2))) ||
1029                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1030                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1031                                         int horz_stretch_loop = -1, BestRemainder;
1032                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1033                                         int Index = 5;
1034                                         ATIReduceRatio(&Numerator, &Denominator);
1035
1036                                         BestRemainder = (Numerator * 16) / Denominator;
1037                                         while (--Index >= 0) {
1038                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1039                                                         Denominator;
1040                                                 if (Remainder < BestRemainder) {
1041                                                         horz_stretch_loop = Index;
1042                                                         if (!(BestRemainder = Remainder))
1043                                                                 break;
1044                                                 }
1045                                         }
1046
1047                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1048                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1049                                                 int reuse_previous = 1;
1050
1051                                                 Index = StretchLoops[horz_stretch_loop];
1052
1053                                                 while (--Index >= 0) {
1054                                                         if (Accumulator > 0)
1055                                                                 horz_stretch_ratio |= reuse_previous;
1056                                                         else
1057                                                                 Accumulator += Denominator;
1058                                                         Accumulator -= Numerator;
1059                                                         reuse_previous <<= 1;
1060                                                 }
1061
1062                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1063                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1064                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1065                                                 break;      /* Out of the do { ... } while (0) */
1066                                         }
1067                                 }
1068
1069                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1070                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1071                         } while (0);
1072                 }
1073
1074                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1075                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1076                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1077
1078                         if (!M64_HAS(LT_LCD_REGS) &&
1079                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1080                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1081                 } else {
1082                         /*
1083                          * Don't use vertical blending if the mode is too wide or not
1084                          * vertically stretched.
1085                          */
1086                         crtc->vert_stretching = 0;
1087                 }
1088                 /* copy to shadow crtc */
1089                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1090                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1091                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1092                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1093         }
1094 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1095
1096         if (M64_HAS(MAGIC_FIFO)) {
1097                 /* FIXME: display FIFO low watermark values */
1098                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1099         }
1100         crtc->dp_pix_width = dp_pix_width;
1101         crtc->dp_chain_mask = dp_chain_mask;
1102
1103         return 0;
1104 }
1105
1106 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1107 {
1108         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1109         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1110             h_sync_pol;
1111         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1112         u32 pix_width;
1113         u32 double_scan, interlace;
1114
1115         /* input */
1116         h_total = crtc->h_tot_disp & 0x1ff;
1117         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1118         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1119         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1120         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1121         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1122         v_total = crtc->v_tot_disp & 0x7ff;
1123         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1124         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1125         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1126         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1127         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1128         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1129         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1130         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1131
1132         /* convert */
1133         xres = (h_disp + 1) * 8;
1134         yres = v_disp + 1;
1135         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1136         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1137         hslen = h_sync_wid * 8;
1138         upper = v_total - v_sync_strt - v_sync_wid;
1139         lower = v_sync_strt - v_disp;
1140         vslen = v_sync_wid;
1141         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1142             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1143             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1144
1145         switch (pix_width) {
1146 #if 0
1147         case CRTC_PIX_WIDTH_4BPP:
1148                 bpp = 4;
1149                 var->red.offset = 0;
1150                 var->red.length = 8;
1151                 var->green.offset = 0;
1152                 var->green.length = 8;
1153                 var->blue.offset = 0;
1154                 var->blue.length = 8;
1155                 var->transp.offset = 0;
1156                 var->transp.length = 0;
1157                 break;
1158 #endif
1159         case CRTC_PIX_WIDTH_8BPP:
1160                 bpp = 8;
1161                 var->red.offset = 0;
1162                 var->red.length = 8;
1163                 var->green.offset = 0;
1164                 var->green.length = 8;
1165                 var->blue.offset = 0;
1166                 var->blue.length = 8;
1167                 var->transp.offset = 0;
1168                 var->transp.length = 0;
1169                 break;
1170         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1171                 bpp = 16;
1172                 var->red.offset = 10;
1173                 var->red.length = 5;
1174                 var->green.offset = 5;
1175                 var->green.length = 5;
1176                 var->blue.offset = 0;
1177                 var->blue.length = 5;
1178                 var->transp.offset = 0;
1179                 var->transp.length = 0;
1180                 break;
1181         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1182                 bpp = 16;
1183                 var->red.offset = 11;
1184                 var->red.length = 5;
1185                 var->green.offset = 5;
1186                 var->green.length = 6;
1187                 var->blue.offset = 0;
1188                 var->blue.length = 5;
1189                 var->transp.offset = 0;
1190                 var->transp.length = 0;
1191                 break;
1192         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1193                 bpp = 24;
1194                 var->red.offset = 16;
1195                 var->red.length = 8;
1196                 var->green.offset = 8;
1197                 var->green.length = 8;
1198                 var->blue.offset = 0;
1199                 var->blue.length = 8;
1200                 var->transp.offset = 0;
1201                 var->transp.length = 0;
1202                 break;
1203         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1204                 bpp = 32;
1205                 var->red.offset = 16;
1206                 var->red.length = 8;
1207                 var->green.offset = 8;
1208                 var->green.length = 8;
1209                 var->blue.offset = 0;
1210                 var->blue.length = 8;
1211                 var->transp.offset = 24;
1212                 var->transp.length = 8;
1213                 break;
1214         default:
1215                 PRINTKE("Invalid pixel width\n");
1216                 return -EINVAL;
1217         }
1218
1219         /* output */
1220         var->xres = xres;
1221         var->yres = yres;
1222         var->xres_virtual = crtc->vxres;
1223         var->yres_virtual = crtc->vyres;
1224         var->bits_per_pixel = bpp;
1225         var->left_margin = left;
1226         var->right_margin = right;
1227         var->upper_margin = upper;
1228         var->lower_margin = lower;
1229         var->hsync_len = hslen;
1230         var->vsync_len = vslen;
1231         var->sync = sync;
1232         var->vmode = FB_VMODE_NONINTERLACED;
1233         /* In double scan mode, the vertical parameters are doubled, so we need to
1234            half them to get the right values.
1235            In interlaced mode the values are already correct, so no correction is
1236            necessary.
1237          */
1238         if (interlace)
1239                 var->vmode = FB_VMODE_INTERLACED;
1240
1241         if (double_scan) {
1242                 var->vmode = FB_VMODE_DOUBLE;
1243                 var->yres>>=1;
1244                 var->upper_margin>>=1;
1245                 var->lower_margin>>=1;
1246                 var->vsync_len>>=1;
1247         }
1248
1249         return 0;
1250 }
1251
1252 /* ------------------------------------------------------------------------- */
1253
1254 static int atyfb_set_par(struct fb_info *info)
1255 {
1256         struct atyfb_par *par = (struct atyfb_par *) info->par;
1257         struct fb_var_screeninfo *var = &info->var;
1258         u32 tmp, pixclock;
1259         int err;
1260 #ifdef DEBUG
1261         struct fb_var_screeninfo debug;
1262         u32 pixclock_in_ps;
1263 #endif
1264         if (par->asleep)
1265                 return 0;
1266
1267         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1268                 return err;
1269
1270         pixclock = atyfb_get_pixclock(var, par);
1271
1272         if (pixclock == 0) {
1273                 PRINTKE("Invalid pixclock\n");
1274                 return -EINVAL;
1275         } else {
1276                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1277                         return err;
1278         }
1279
1280         par->accel_flags = var->accel_flags; /* hack */
1281
1282         if (par->blitter_may_be_busy)
1283                 wait_for_idle(par);
1284
1285         aty_set_crtc(par, &par->crtc);
1286         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1287         par->pll_ops->set_pll(info, &par->pll);
1288
1289 #ifdef DEBUG
1290         if(par->pll_ops && par->pll_ops->pll_to_var)
1291                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1292         else
1293                 pixclock_in_ps = 0;
1294
1295         if(0 == pixclock_in_ps) {
1296                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1297                 pixclock_in_ps = pixclock;
1298         }
1299
1300         memset(&debug, 0, sizeof(debug));
1301         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1302                 u32 hSync, vRefresh;
1303                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1304                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1305
1306                 h_disp = debug.xres;
1307                 h_sync_strt = h_disp + debug.right_margin;
1308                 h_sync_end = h_sync_strt + debug.hsync_len;
1309                 h_total = h_sync_end + debug.left_margin;
1310                 v_disp = debug.yres;
1311                 v_sync_strt = v_disp + debug.lower_margin;
1312                 v_sync_end = v_sync_strt + debug.vsync_len;
1313                 v_total = v_sync_end + debug.upper_margin;
1314
1315                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1316                 vRefresh = (hSync * 1000) / v_total;
1317                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1318                 vRefresh *= 2;
1319                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1320                 vRefresh /= 2;
1321
1322                 DPRINTK("atyfb_set_par\n");
1323                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1324                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1325                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1326                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1327                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1328                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1329                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1330                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1331                         h_disp, h_sync_strt, h_sync_end, h_total,
1332                         v_disp, v_sync_strt, v_sync_end, v_total);
1333                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1334                         pixclock_in_ps,
1335                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1336                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1337         }
1338 #endif /* DEBUG */
1339
1340         if (!M64_HAS(INTEGRATED)) {
1341                 /* Don't forget MEM_CNTL */
1342                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1343                 switch (var->bits_per_pixel) {
1344                 case 8:
1345                         tmp |= 0x02000000;
1346                         break;
1347                 case 16:
1348                         tmp |= 0x03000000;
1349                         break;
1350                 case 32:
1351                         tmp |= 0x06000000;
1352                         break;
1353                 }
1354                 aty_st_le32(MEM_CNTL, tmp, par);
1355         } else {
1356                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1357                 if (!M64_HAS(MAGIC_POSTDIV))
1358                         tmp |= par->mem_refresh_rate << 20;
1359                 switch (var->bits_per_pixel) {
1360                 case 8:
1361                 case 24:
1362                         tmp |= 0x00000000;
1363                         break;
1364                 case 16:
1365                         tmp |= 0x04000000;
1366                         break;
1367                 case 32:
1368                         tmp |= 0x08000000;
1369                         break;
1370                 }
1371                 if (M64_HAS(CT_BUS)) {
1372                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1373                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1374                 } else if (M64_HAS(VT_BUS)) {
1375                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1376                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1377                 } else if (M64_HAS(MOBIL_BUS)) {
1378                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1379                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1380                 } else {
1381                         /* GT */
1382                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1383                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1384                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1385                 }
1386                 aty_st_le32(MEM_CNTL, tmp, par);
1387         }
1388         aty_st_8(DAC_MASK, 0xff, par);
1389
1390         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1391         info->fix.visual = var->bits_per_pixel <= 8 ?
1392                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1393
1394         /* Initialize the graphics engine */
1395         if (par->accel_flags & FB_ACCELF_TEXT)
1396                 aty_init_engine(par, info);
1397
1398 #ifdef CONFIG_BOOTX_TEXT
1399         btext_update_display(info->fix.smem_start,
1400                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1401                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1402                 var->bits_per_pixel,
1403                 par->crtc.vxres * var->bits_per_pixel / 8);
1404 #endif /* CONFIG_BOOTX_TEXT */
1405 #if 0
1406         /* switch to accelerator mode */
1407         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1408                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1409 #endif
1410 #ifdef DEBUG
1411 {
1412         /* dump non shadow CRTC, pll, LCD registers */
1413         int i; u32 base;
1414
1415         /* CRTC registers */
1416         base = 0x2000;
1417         printk("debug atyfb: Mach64 non-shadow register values:");
1418         for (i = 0; i < 256; i = i+4) {
1419                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1420                 printk(" %08X", aty_ld_le32(i, par));
1421         }
1422         printk("\n\n");
1423
1424 #ifdef CONFIG_FB_ATY_CT
1425         /* PLL registers */
1426         base = 0x00;
1427         printk("debug atyfb: Mach64 PLL register values:");
1428         for (i = 0; i < 64; i++) {
1429                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1430                 if(i%4 == 0)  printk(" ");
1431                 printk("%02X", aty_ld_pll_ct(i, par));
1432         }
1433         printk("\n\n");
1434 #endif  /* CONFIG_FB_ATY_CT */
1435
1436 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1437         if (par->lcd_table != 0) {
1438                 /* LCD registers */
1439                 base = 0x00;
1440                 printk("debug atyfb: LCD register values:");
1441                 if(M64_HAS(LT_LCD_REGS)) {
1442                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1443                         if(i == EXT_VERT_STRETCH)
1444                             continue;
1445                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1446                         printk(" %08X", aty_ld_lcd(i, par));
1447                     }
1448
1449                 } else {
1450                     for (i = 0; i < 64; i++) {
1451                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1452                         printk(" %08X", aty_ld_lcd(i, par));
1453                     }
1454                 }
1455                 printk("\n\n");
1456         }
1457 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1458 }
1459 #endif /* DEBUG */
1460         return 0;
1461 }
1462
1463 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1464 {
1465         struct atyfb_par *par = (struct atyfb_par *) info->par;
1466         int err;
1467         struct crtc crtc;
1468         union aty_pll pll;
1469         u32 pixclock;
1470
1471         memcpy(&pll, &(par->pll), sizeof(pll));
1472
1473         if((err = aty_var_to_crtc(info, var, &crtc)))
1474                 return err;
1475
1476         pixclock = atyfb_get_pixclock(var, par);
1477
1478         if (pixclock == 0) {
1479                 if (!(var->activate & FB_ACTIVATE_TEST))
1480                         PRINTKE("Invalid pixclock\n");
1481                 return -EINVAL;
1482         } else {
1483                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1484                         return err;
1485         }
1486
1487         if (var->accel_flags & FB_ACCELF_TEXT)
1488                 info->var.accel_flags = FB_ACCELF_TEXT;
1489         else
1490                 info->var.accel_flags = 0;
1491
1492 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1493         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1494                 return -EINVAL;
1495 #endif
1496         aty_crtc_to_var(&crtc, var);
1497         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1498         return 0;
1499 }
1500
1501 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1502 {
1503         u32 xoffset = info->var.xoffset;
1504         u32 yoffset = info->var.yoffset;
1505         u32 vxres = par->crtc.vxres;
1506         u32 bpp = info->var.bits_per_pixel;
1507
1508         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1509 }
1510
1511
1512     /*
1513      *  Open/Release the frame buffer device
1514      */
1515
1516 static int atyfb_open(struct fb_info *info, int user)
1517 {
1518         struct atyfb_par *par = (struct atyfb_par *) info->par;
1519
1520         if (user) {
1521                 par->open++;
1522 #ifdef __sparc__
1523                 par->mmaped = 0;
1524 #endif
1525         }
1526         return (0);
1527 }
1528
1529 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1530 {
1531         struct atyfb_par *par = dev_id;
1532         int handled = 0;
1533         u32 int_cntl;
1534
1535         spin_lock(&par->int_lock);
1536
1537         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1538
1539         if (int_cntl & CRTC_VBLANK_INT) {
1540                 /* clear interrupt */
1541                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1542                 par->vblank.count++;
1543                 if (par->vblank.pan_display) {
1544                         par->vblank.pan_display = 0;
1545                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1546                 }
1547                 wake_up_interruptible(&par->vblank.wait);
1548                 handled = 1;
1549         }
1550
1551         spin_unlock(&par->int_lock);
1552
1553         return IRQ_RETVAL(handled);
1554 }
1555
1556 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1557 {
1558         u32 int_cntl;
1559
1560         if (!test_and_set_bit(0, &par->irq_flags)) {
1561                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1562                         clear_bit(0, &par->irq_flags);
1563                         return -EINVAL;
1564                 }
1565                 spin_lock_irq(&par->int_lock);
1566                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1567                 /* clear interrupt */
1568                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1569                 /* enable interrupt */
1570                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1571                 spin_unlock_irq(&par->int_lock);
1572         } else if (reenable) {
1573                 spin_lock_irq(&par->int_lock);
1574                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1575                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1576                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1577                         /* re-enable interrupt */
1578                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1579                 }
1580                 spin_unlock_irq(&par->int_lock);
1581         }
1582
1583         return 0;
1584 }
1585
1586 static int aty_disable_irq(struct atyfb_par *par)
1587 {
1588         u32 int_cntl;
1589
1590         if (test_and_clear_bit(0, &par->irq_flags)) {
1591                 if (par->vblank.pan_display) {
1592                         par->vblank.pan_display = 0;
1593                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1594                 }
1595                 spin_lock_irq(&par->int_lock);
1596                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1597                 /* disable interrupt */
1598                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1599                 spin_unlock_irq(&par->int_lock);
1600                 free_irq(par->irq, par);
1601         }
1602
1603         return 0;
1604 }
1605
1606 static int atyfb_release(struct fb_info *info, int user)
1607 {
1608         struct atyfb_par *par = (struct atyfb_par *) info->par;
1609         if (user) {
1610                 par->open--;
1611                 mdelay(1);
1612                 wait_for_idle(par);
1613                 if (!par->open) {
1614 #ifdef __sparc__
1615                         int was_mmaped = par->mmaped;
1616
1617                         par->mmaped = 0;
1618
1619                         if (was_mmaped) {
1620                                 struct fb_var_screeninfo var;
1621
1622                                 /* Now reset the default display config, we have no
1623                                  * idea what the program(s) which mmap'd the chip did
1624                                  * to the configuration, nor whether it restored it
1625                                  * correctly.
1626                                  */
1627                                 var = default_var;
1628                                 if (noaccel)
1629                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1630                                 else
1631                                         var.accel_flags |= FB_ACCELF_TEXT;
1632                                 if (var.yres == var.yres_virtual) {
1633                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1634                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1635                                         if (var.yres_virtual < var.yres)
1636                                                 var.yres_virtual = var.yres;
1637                                 }
1638                         }
1639 #endif
1640                         aty_disable_irq(par);
1641                 }
1642         }
1643         return (0);
1644 }
1645
1646     /*
1647      *  Pan or Wrap the Display
1648      *
1649      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1650      */
1651
1652 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1653 {
1654         struct atyfb_par *par = (struct atyfb_par *) info->par;
1655         u32 xres, yres, xoffset, yoffset;
1656
1657         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1658         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1659         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1660                 yres >>= 1;
1661         xoffset = (var->xoffset + 7) & ~7;
1662         yoffset = var->yoffset;
1663         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1664                 return -EINVAL;
1665         info->var.xoffset = xoffset;
1666         info->var.yoffset = yoffset;
1667         if (par->asleep)
1668                 return 0;
1669
1670         set_off_pitch(par, info);
1671         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1672                 par->vblank.pan_display = 1;
1673         } else {
1674                 par->vblank.pan_display = 0;
1675                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1676         }
1677
1678         return 0;
1679 }
1680
1681 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1682 {
1683         struct aty_interrupt *vbl;
1684         unsigned int count;
1685         int ret;
1686
1687         switch (crtc) {
1688         case 0:
1689                 vbl = &par->vblank;
1690                 break;
1691         default:
1692                 return -ENODEV;
1693         }
1694
1695         ret = aty_enable_irq(par, 0);
1696         if (ret)
1697                 return ret;
1698
1699         count = vbl->count;
1700         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1701         if (ret < 0) {
1702                 return ret;
1703         }
1704         if (ret == 0) {
1705                 aty_enable_irq(par, 1);
1706                 return -ETIMEDOUT;
1707         }
1708
1709         return 0;
1710 }
1711
1712
1713 #ifdef DEBUG
1714 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1715 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1716
1717 struct atyclk {
1718         u32 ref_clk_per;
1719         u8 pll_ref_div;
1720         u8 mclk_fb_div;
1721         u8 mclk_post_div;       /* 1,2,3,4,8 */
1722         u8 mclk_fb_mult;        /* 2 or 4 */
1723         u8 xclk_post_div;       /* 1,2,3,4,8 */
1724         u8 vclk_fb_div;
1725         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1726         u32 dsp_xclks_per_row;  /* 0-16383 */
1727         u32 dsp_loop_latency;   /* 0-15 */
1728         u32 dsp_precision;      /* 0-7 */
1729         u32 dsp_on;             /* 0-2047 */
1730         u32 dsp_off;            /* 0-2047 */
1731 };
1732
1733 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1734 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1735 #endif
1736
1737 #ifndef FBIO_WAITFORVSYNC
1738 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1739 #endif
1740
1741 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1742 {
1743         struct atyfb_par *par = (struct atyfb_par *) info->par;
1744 #ifdef __sparc__
1745         struct fbtype fbtyp;
1746 #endif
1747
1748         switch (cmd) {
1749 #ifdef __sparc__
1750         case FBIOGTYPE:
1751                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1752                 fbtyp.fb_width = par->crtc.vxres;
1753                 fbtyp.fb_height = par->crtc.vyres;
1754                 fbtyp.fb_depth = info->var.bits_per_pixel;
1755                 fbtyp.fb_cmsize = info->cmap.len;
1756                 fbtyp.fb_size = info->fix.smem_len;
1757                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1758                         return -EFAULT;
1759                 break;
1760 #endif /* __sparc__ */
1761
1762         case FBIO_WAITFORVSYNC:
1763                 {
1764                         u32 crtc;
1765
1766                         if (get_user(crtc, (__u32 __user *) arg))
1767                                 return -EFAULT;
1768
1769                         return aty_waitforvblank(par, crtc);
1770                 }
1771                 break;
1772
1773 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1774         case ATYIO_CLKR:
1775                 if (M64_HAS(INTEGRATED)) {
1776                         struct atyclk clk;
1777                         union aty_pll *pll = &(par->pll);
1778                         u32 dsp_config = pll->ct.dsp_config;
1779                         u32 dsp_on_off = pll->ct.dsp_on_off;
1780                         clk.ref_clk_per = par->ref_clk_per;
1781                         clk.pll_ref_div = pll->ct.pll_ref_div;
1782                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1783                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1784                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1785                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1786                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1787                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1788                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1789                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1790                         clk.dsp_precision = (dsp_config >> 20) & 7;
1791                         clk.dsp_off = dsp_on_off & 0x7ff;
1792                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1793                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1794                                          sizeof(clk)))
1795                                 return -EFAULT;
1796                 } else
1797                         return -EINVAL;
1798                 break;
1799         case ATYIO_CLKW:
1800                 if (M64_HAS(INTEGRATED)) {
1801                         struct atyclk clk;
1802                         union aty_pll *pll = &(par->pll);
1803                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1804                                 return -EFAULT;
1805                         par->ref_clk_per = clk.ref_clk_per;
1806                         pll->ct.pll_ref_div = clk.pll_ref_div;
1807                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1808                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1809                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1810                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1811                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1812                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1813                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1814                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1815                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1816                         /*aty_calc_pll_ct(info, &pll->ct);*/
1817                         aty_set_pll_ct(info, pll);
1818                 } else
1819                         return -EINVAL;
1820                 break;
1821         case ATYIO_FEATR:
1822                 if (get_user(par->features, (u32 __user *) arg))
1823                         return -EFAULT;
1824                 break;
1825         case ATYIO_FEATW:
1826                 if (put_user(par->features, (u32 __user *) arg))
1827                         return -EFAULT;
1828                 break;
1829 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1830         default:
1831                 return -EINVAL;
1832         }
1833         return 0;
1834 }
1835
1836 static int atyfb_sync(struct fb_info *info)
1837 {
1838         struct atyfb_par *par = (struct atyfb_par *) info->par;
1839
1840         if (par->blitter_may_be_busy)
1841                 wait_for_idle(par);
1842         return 0;
1843 }
1844
1845 #ifdef __sparc__
1846 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1847 {
1848         struct atyfb_par *par = (struct atyfb_par *) info->par;
1849         unsigned int size, page, map_size = 0;
1850         unsigned long map_offset = 0;
1851         unsigned long off;
1852         int i;
1853
1854         if (!par->mmap_map)
1855                 return -ENXIO;
1856
1857         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1858                 return -EINVAL;
1859
1860         off = vma->vm_pgoff << PAGE_SHIFT;
1861         size = vma->vm_end - vma->vm_start;
1862
1863         /* To stop the swapper from even considering these pages. */
1864         vma->vm_flags |= (VM_IO | VM_RESERVED);
1865
1866         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1867             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1868                 off += 0x8000000000000000UL;
1869
1870         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1871
1872         /* Each page, see which map applies */
1873         for (page = 0; page < size;) {
1874                 map_size = 0;
1875                 for (i = 0; par->mmap_map[i].size; i++) {
1876                         unsigned long start = par->mmap_map[i].voff;
1877                         unsigned long end = start + par->mmap_map[i].size;
1878                         unsigned long offset = off + page;
1879
1880                         if (start > offset)
1881                                 continue;
1882                         if (offset >= end)
1883                                 continue;
1884
1885                         map_size = par->mmap_map[i].size - (offset - start);
1886                         map_offset =
1887                             par->mmap_map[i].poff + (offset - start);
1888                         break;
1889                 }
1890                 if (!map_size) {
1891                         page += PAGE_SIZE;
1892                         continue;
1893                 }
1894                 if (page + map_size > size)
1895                         map_size = size - page;
1896
1897                 pgprot_val(vma->vm_page_prot) &=
1898                     ~(par->mmap_map[i].prot_mask);
1899                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1900
1901                 if (remap_pfn_range(vma, vma->vm_start + page,
1902                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1903                         return -EAGAIN;
1904
1905                 page += map_size;
1906         }
1907
1908         if (!map_size)
1909                 return -EINVAL;
1910
1911         if (!par->mmaped)
1912                 par->mmaped = 1;
1913         return 0;
1914 }
1915
1916 static struct {
1917         u32 yoffset;
1918         u8 r[2][256];
1919         u8 g[2][256];
1920         u8 b[2][256];
1921 } atyfb_save;
1922
1923 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1924 {
1925         int i, tmp;
1926
1927         for (i = 0; i < 256; i++) {
1928                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1929                 if (M64_HAS(EXTRA_BRIGHT))
1930                         tmp |= 0x2;
1931                 aty_st_8(DAC_CNTL, tmp, par);
1932                 aty_st_8(DAC_MASK, 0xff, par);
1933
1934                 writeb(i, &par->aty_cmap_regs->rindex);
1935                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1936                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1937                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1938                 writeb(i, &par->aty_cmap_regs->windex);
1939                 writeb(atyfb_save.r[1 - enter][i],
1940                        &par->aty_cmap_regs->lut);
1941                 writeb(atyfb_save.g[1 - enter][i],
1942                        &par->aty_cmap_regs->lut);
1943                 writeb(atyfb_save.b[1 - enter][i],
1944                        &par->aty_cmap_regs->lut);
1945         }
1946 }
1947
1948 static void atyfb_palette(int enter)
1949 {
1950         struct atyfb_par *par;
1951         struct fb_info *info;
1952         int i;
1953
1954         for (i = 0; i < FB_MAX; i++) {
1955                 info = registered_fb[i];
1956                 if (info && info->fbops == &atyfb_ops) {
1957                         par = (struct atyfb_par *) info->par;
1958
1959                         atyfb_save_palette(par, enter);
1960                         if (enter) {
1961                                 atyfb_save.yoffset = info->var.yoffset;
1962                                 info->var.yoffset = 0;
1963                                 set_off_pitch(par, info);
1964                         } else {
1965                                 info->var.yoffset = atyfb_save.yoffset;
1966                                 set_off_pitch(par, info);
1967                         }
1968                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1969                         break;
1970                 }
1971         }
1972 }
1973 #endif /* __sparc__ */
1974
1975
1976
1977 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1978
1979 /* Power management routines. Those are used for PowerBook sleep.
1980  */
1981 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1982 {
1983         u32 pm;
1984         int timeout;
1985
1986         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1987         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1988         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990
1991         timeout = 2000;
1992         if (sleep) {
1993                 /* Sleep */
1994                 pm &= ~PWR_MGT_ON;
1995                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1996                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1997                 udelay(10);
1998                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1999                 pm |= SUSPEND_NOW;
2000                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2001                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2002                 udelay(10);
2003                 pm |= PWR_MGT_ON;
2004                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2005                 do {
2006                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2007                         mdelay(1);
2008                         if ((--timeout) == 0)
2009                                 break;
2010                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2011         } else {
2012                 /* Wakeup */
2013                 pm &= ~PWR_MGT_ON;
2014                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2016                 udelay(10);
2017                 pm &= ~SUSPEND_NOW;
2018                 pm |= (PWR_BLON | AUTO_PWR_UP);
2019                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2020                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2021                 udelay(10);
2022                 pm |= PWR_MGT_ON;
2023                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2024                 do {
2025                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2026                         mdelay(1);
2027                         if ((--timeout) == 0)
2028                                 break;
2029                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2030         }
2031         mdelay(500);
2032
2033         return timeout ? 0 : -EIO;
2034 }
2035
2036 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2037 {
2038         struct fb_info *info = pci_get_drvdata(pdev);
2039         struct atyfb_par *par = (struct atyfb_par *) info->par;
2040
2041 #ifndef CONFIG_PPC_PMAC
2042         /* HACK ALERT ! Once I find a proper way to say to each driver
2043          * individually what will happen with it's PCI slot, I'll change
2044          * that. On laptops, the AGP slot is just unclocked, so D2 is
2045          * expected, while on desktops, the card is powered off
2046          */
2047         return 0;
2048 #endif /* CONFIG_PPC_PMAC */
2049
2050         if (state.event == pdev->dev.power.power_state.event)
2051                 return 0;
2052
2053         acquire_console_sem();
2054
2055         fb_set_suspend(info, 1);
2056
2057         /* Idle & reset engine */
2058         wait_for_idle(par);
2059         aty_reset_engine(par);
2060
2061         /* Blank display and LCD */
2062         atyfb_blank(FB_BLANK_POWERDOWN, info);
2063
2064         par->asleep = 1;
2065         par->lock_blank = 1;
2066
2067         /* Set chip to "suspend" mode */
2068         if (aty_power_mgmt(1, par)) {
2069                 par->asleep = 0;
2070                 par->lock_blank = 0;
2071                 atyfb_blank(FB_BLANK_UNBLANK, info);
2072                 fb_set_suspend(info, 0);
2073                 release_console_sem();
2074                 return -EIO;
2075         }
2076
2077         release_console_sem();
2078
2079         pdev->dev.power.power_state = state;
2080
2081         return 0;
2082 }
2083
2084 static int atyfb_pci_resume(struct pci_dev *pdev)
2085 {
2086         struct fb_info *info = pci_get_drvdata(pdev);
2087         struct atyfb_par *par = (struct atyfb_par *) info->par;
2088
2089         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2090                 return 0;
2091
2092         acquire_console_sem();
2093
2094         if (pdev->dev.power.power_state.event == 2)
2095                 aty_power_mgmt(0, par);
2096         par->asleep = 0;
2097
2098         /* Restore display */
2099         atyfb_set_par(info);
2100
2101         /* Refresh */
2102         fb_set_suspend(info, 0);
2103
2104         /* Unblank */
2105         par->lock_blank = 0;
2106         atyfb_blank(FB_BLANK_UNBLANK, info);
2107
2108         release_console_sem();
2109
2110         pdev->dev.power.power_state = PMSG_ON;
2111
2112         return 0;
2113 }
2114
2115 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2116
2117 #ifdef CONFIG_PMAC_BACKLIGHT
2118
2119     /*
2120      *   LCD backlight control
2121      */
2122
2123 static int backlight_conv[] = {
2124         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2125         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2126 };
2127
2128 static int aty_set_backlight_enable(int on, int level, void *data)
2129 {
2130         struct fb_info *info = (struct fb_info *) data;
2131         struct atyfb_par *par = (struct atyfb_par *) info->par;
2132         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2133
2134         reg |= (BLMOD_EN | BIASMOD_EN);
2135         if (on && level > BACKLIGHT_OFF) {
2136                 reg &= ~BIAS_MOD_LEVEL_MASK;
2137                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2138         } else {
2139                 reg &= ~BIAS_MOD_LEVEL_MASK;
2140                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2141         }
2142         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2143         return 0;
2144 }
2145
2146 static int aty_set_backlight_level(int level, void *data)
2147 {
2148         return aty_set_backlight_enable(1, level, data);
2149 }
2150
2151 static struct backlight_controller aty_backlight_controller = {
2152         aty_set_backlight_enable,
2153         aty_set_backlight_level
2154 };
2155 #endif /* CONFIG_PMAC_BACKLIGHT */
2156
2157 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2158 {
2159         const int ragepro_tbl[] = {
2160                 44, 50, 55, 66, 75, 80, 100
2161         };
2162         const int ragexl_tbl[] = {
2163                 50, 66, 75, 83, 90, 95, 100, 105,
2164                 110, 115, 120, 125, 133, 143, 166
2165         };
2166         const int *refresh_tbl;
2167         int i, size;
2168
2169         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2170                 refresh_tbl = ragexl_tbl;
2171                 size = sizeof(ragexl_tbl)/sizeof(int);
2172         } else {
2173                 refresh_tbl = ragepro_tbl;
2174                 size = sizeof(ragepro_tbl)/sizeof(int);
2175         }
2176
2177         for (i=0; i < size; i++) {
2178                 if (xclk < refresh_tbl[i])
2179                 break;
2180         }
2181         par->mem_refresh_rate = i;
2182 }
2183
2184     /*
2185      *  Initialisation
2186      */
2187
2188 static struct fb_info *fb_list = NULL;
2189
2190 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2191 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2192                                                 struct fb_var_screeninfo *var)
2193 {
2194         int ret = -EINVAL;
2195
2196         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2197                 *var = default_var;
2198                 var->xres = var->xres_virtual = par->lcd_hdisp;
2199                 var->right_margin = par->lcd_right_margin;
2200                 var->left_margin = par->lcd_hblank_len -
2201                         (par->lcd_right_margin + par->lcd_hsync_dly +
2202                          par->lcd_hsync_len);
2203                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2204                 var->yres = var->yres_virtual = par->lcd_vdisp;
2205                 var->lower_margin = par->lcd_lower_margin;
2206                 var->upper_margin = par->lcd_vblank_len -
2207                         (par->lcd_lower_margin + par->lcd_vsync_len);
2208                 var->vsync_len = par->lcd_vsync_len;
2209                 var->pixclock = par->lcd_pixclock;
2210                 ret = 0;
2211         }
2212
2213         return ret;
2214 }
2215 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2216
2217 static int __init aty_init(struct fb_info *info, const char *name)
2218 {
2219         struct atyfb_par *par = (struct atyfb_par *) info->par;
2220         const char *ramname = NULL, *xtal;
2221         int gtb_memsize, has_var = 0;
2222         struct fb_var_screeninfo var;
2223         u8 pll_ref_div;
2224         u32 i;
2225 #if defined(CONFIG_PPC)
2226         int sense;
2227 #endif
2228
2229         init_waitqueue_head(&par->vblank.wait);
2230         spin_lock_init(&par->int_lock);
2231
2232         par->aty_cmap_regs =
2233             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2234
2235 #ifdef CONFIG_PPC_PMAC
2236         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2237          * and set the frequency manually. */
2238         if (machine_is_compatible("PowerBook2,1")) {
2239                 par->pll_limits.mclk = 70;
2240                 par->pll_limits.xclk = 53;
2241         }
2242 #endif
2243         if (pll)
2244                 par->pll_limits.pll_max = pll;
2245         if (mclk)
2246                 par->pll_limits.mclk = mclk;
2247         if (xclk)
2248                 par->pll_limits.xclk = xclk;
2249
2250         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2251         par->pll_per = 1000000/par->pll_limits.pll_max;
2252         par->mclk_per = 1000000/par->pll_limits.mclk;
2253         par->xclk_per = 1000000/par->pll_limits.xclk;
2254
2255         par->ref_clk_per = 1000000000000ULL / 14318180;
2256         xtal = "14.31818";
2257
2258 #ifdef CONFIG_FB_ATY_GX
2259         if (!M64_HAS(INTEGRATED)) {
2260                 u32 stat0;
2261                 u8 dac_type, dac_subtype, clk_type;
2262                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2263                 par->bus_type = (stat0 >> 0) & 0x07;
2264                 par->ram_type = (stat0 >> 3) & 0x07;
2265                 ramname = aty_gx_ram[par->ram_type];
2266                 /* FIXME: clockchip/RAMDAC probing? */
2267                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2268 #ifdef CONFIG_ATARI
2269                 clk_type = CLK_ATI18818_1;
2270                 dac_type = (stat0 >> 9) & 0x07;
2271                 if (dac_type == 0x07)
2272                         dac_subtype = DAC_ATT20C408;
2273                 else
2274                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2275 #else
2276                 dac_type = DAC_IBMRGB514;
2277                 dac_subtype = DAC_IBMRGB514;
2278                 clk_type = CLK_IBMRGB514;
2279 #endif
2280                 switch (dac_subtype) {
2281                 case DAC_IBMRGB514:
2282                         par->dac_ops = &aty_dac_ibm514;
2283                         break;
2284                 case DAC_ATI68860_B:
2285                 case DAC_ATI68860_C:
2286                         par->dac_ops = &aty_dac_ati68860b;
2287                         break;
2288                 case DAC_ATT20C408:
2289                 case DAC_ATT21C498:
2290                         par->dac_ops = &aty_dac_att21c498;
2291                         break;
2292                 default:
2293                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2294                         par->dac_ops = &aty_dac_unsupported;
2295                         break;
2296                 }
2297                 switch (clk_type) {
2298                 case CLK_ATI18818_1:
2299                         par->pll_ops = &aty_pll_ati18818_1;
2300                         break;
2301                 case CLK_IBMRGB514:
2302                         par->pll_ops = &aty_pll_ibm514;
2303                         break;
2304 #if 0 /* dead code */
2305                 case CLK_STG1703:
2306                         par->pll_ops = &aty_pll_stg1703;
2307                         break;
2308                 case CLK_CH8398:
2309                         par->pll_ops = &aty_pll_ch8398;
2310                         break;
2311                 case CLK_ATT20C408:
2312                         par->pll_ops = &aty_pll_att20c408;
2313                         break;
2314 #endif
2315                 default:
2316                         PRINTKI("aty_init: CLK type not implemented yet!");
2317                         par->pll_ops = &aty_pll_unsupported;
2318                         break;
2319                 }
2320         }
2321 #endif /* CONFIG_FB_ATY_GX */
2322 #ifdef CONFIG_FB_ATY_CT
2323         if (M64_HAS(INTEGRATED)) {
2324                 par->dac_ops = &aty_dac_ct;
2325                 par->pll_ops = &aty_pll_ct;
2326                 par->bus_type = PCI;
2327                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2328                 ramname = aty_ct_ram[par->ram_type];
2329                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2330                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2331                         par->pll_limits.mclk = 63;
2332         }
2333
2334         if (M64_HAS(GTB_DSP)
2335             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2336                 int diff1, diff2;
2337                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2338                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2339                 if (diff1 < 0)
2340                         diff1 = -diff1;
2341                 if (diff2 < 0)
2342                         diff2 = -diff2;
2343                 if (diff2 < diff1) {
2344                         par->ref_clk_per = 1000000000000ULL / 29498928;
2345                         xtal = "29.498928";
2346                 }
2347         }
2348 #endif /* CONFIG_FB_ATY_CT */
2349
2350         /* save previous video mode */
2351         aty_get_crtc(par, &saved_crtc);
2352         if(par->pll_ops->get_pll)
2353                 par->pll_ops->get_pll(info, &saved_pll);
2354
2355         i = aty_ld_le32(MEM_CNTL, par);
2356         gtb_memsize = M64_HAS(GTB_DSP);
2357         if (gtb_memsize)
2358                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2359                 case MEM_SIZE_512K:
2360                         info->fix.smem_len = 0x80000;
2361                         break;
2362                 case MEM_SIZE_1M:
2363                         info->fix.smem_len = 0x100000;
2364                         break;
2365                 case MEM_SIZE_2M_GTB:
2366                         info->fix.smem_len = 0x200000;
2367                         break;
2368                 case MEM_SIZE_4M_GTB:
2369                         info->fix.smem_len = 0x400000;
2370                         break;
2371                 case MEM_SIZE_6M_GTB:
2372                         info->fix.smem_len = 0x600000;
2373                         break;
2374                 case MEM_SIZE_8M_GTB:
2375                         info->fix.smem_len = 0x800000;
2376                         break;
2377                 default:
2378                         info->fix.smem_len = 0x80000;
2379         } else
2380                 switch (i & MEM_SIZE_ALIAS) {
2381                 case MEM_SIZE_512K:
2382                         info->fix.smem_len = 0x80000;
2383                         break;
2384                 case MEM_SIZE_1M:
2385                         info->fix.smem_len = 0x100000;
2386                         break;
2387                 case MEM_SIZE_2M:
2388                         info->fix.smem_len = 0x200000;
2389                         break;
2390                 case MEM_SIZE_4M:
2391                         info->fix.smem_len = 0x400000;
2392                         break;
2393                 case MEM_SIZE_6M:
2394                         info->fix.smem_len = 0x600000;
2395                         break;
2396                 case MEM_SIZE_8M:
2397                         info->fix.smem_len = 0x800000;
2398                         break;
2399                 default:
2400                         info->fix.smem_len = 0x80000;
2401                 }
2402
2403         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2404                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2405                         info->fix.smem_len += 0x400000;
2406         }
2407
2408         if (vram) {
2409                 info->fix.smem_len = vram * 1024;
2410                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2411                 if (info->fix.smem_len <= 0x80000)
2412                         i |= MEM_SIZE_512K;
2413                 else if (info->fix.smem_len <= 0x100000)
2414                         i |= MEM_SIZE_1M;
2415                 else if (info->fix.smem_len <= 0x200000)
2416                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2417                 else if (info->fix.smem_len <= 0x400000)
2418                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2419                 else if (info->fix.smem_len <= 0x600000)
2420                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2421                 else
2422                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2423                 aty_st_le32(MEM_CNTL, i, par);
2424         }
2425
2426         /*
2427          *  Reg Block 0 (CT-compatible block) is at mmio_start
2428          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2429          */
2430         if (M64_HAS(GX)) {
2431                 info->fix.mmio_len = 0x400;
2432                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2433         } else if (M64_HAS(CT)) {
2434                 info->fix.mmio_len = 0x400;
2435                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2436         } else if (M64_HAS(VT)) {
2437                 info->fix.mmio_start -= 0x400;
2438                 info->fix.mmio_len = 0x800;
2439                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2440         } else {/* GT */
2441                 info->fix.mmio_start -= 0x400;
2442                 info->fix.mmio_len = 0x800;
2443                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2444         }
2445
2446         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2447                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2448                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2449                par->pll_limits.mclk, par->pll_limits.xclk);
2450
2451 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2452         if (M64_HAS(INTEGRATED)) {
2453                 int i;
2454                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2455                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2456                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2457                        "debug atyfb: PLL",
2458                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2459                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2460                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2461                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2462                 for (i = 0; i < 40; i++)
2463                         printk(" %02x", aty_ld_pll_ct(i, par));
2464                 printk("\n");
2465         }
2466 #endif
2467         if(par->pll_ops->init_pll)
2468                 par->pll_ops->init_pll(info, &par->pll);
2469
2470         /*
2471          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2472          *  FIXME: we should use the auxiliary aperture instead so we can access
2473          *  the full 8 MB of video RAM on 8 MB boards
2474          */
2475
2476         if (!par->aux_start &&
2477                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2478                 info->fix.smem_len -= GUI_RESERVE;
2479
2480         /*
2481          *  Disable register access through the linear aperture
2482          *  if the auxiliary aperture is used so we can access
2483          *  the full 8 MB of video RAM on 8 MB boards.
2484          */
2485         if (par->aux_start)
2486                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2487
2488 #ifdef CONFIG_MTRR
2489         par->mtrr_aper = -1;
2490         par->mtrr_reg = -1;
2491         if (!nomtrr) {
2492                 /* Cover the whole resource. */
2493                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2494                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2495                         /* Make a hole for mmio. */
2496                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2497                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2498                         if (par->mtrr_reg < 0) {
2499                                 mtrr_del(par->mtrr_aper, 0, 0);
2500                                 par->mtrr_aper = -1;
2501                         }
2502                  }
2503         }
2504 #endif
2505
2506         info->fbops = &atyfb_ops;
2507         info->pseudo_palette = pseudo_palette;
2508         info->flags = FBINFO_FLAG_DEFAULT;
2509
2510 #ifdef CONFIG_PMAC_BACKLIGHT
2511         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2512                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2513                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2514                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2515         } else if (M64_HAS(MOBIL_BUS))
2516                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2517 #endif /* CONFIG_PMAC_BACKLIGHT */
2518
2519         memset(&var, 0, sizeof(var));
2520 #ifdef CONFIG_PPC
2521         if (_machine == _MACH_Pmac) {
2522                 /*
2523                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2524                  *         applies to all Mac video cards
2525                  */
2526                 if (mode) {
2527                         if (mac_find_mode(&var, info, mode, 8))
2528                                 has_var = 1;
2529                 } else {
2530                         if (default_vmode == VMODE_CHOOSE) {
2531                                 if (M64_HAS(G3_PB_1024x768))
2532                                         /* G3 PowerBook with 1024x768 LCD */
2533                                         default_vmode = VMODE_1024_768_60;
2534                                 else if (machine_is_compatible("iMac"))
2535                                         default_vmode = VMODE_1024_768_75;
2536                                 else if (machine_is_compatible
2537                                          ("PowerBook2,1"))
2538                                         /* iBook with 800x600 LCD */
2539                                         default_vmode = VMODE_800_600_60;
2540                                 else
2541                                         default_vmode = VMODE_640_480_67;
2542                                 sense = read_aty_sense(par);
2543                                 PRINTKI("monitor sense=%x, mode %d\n",
2544                                         sense,  mac_map_monitor_sense(sense));
2545                         }
2546                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2547                                 default_vmode = VMODE_640_480_60;
2548                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2549                                 default_cmode = CMODE_8;
2550                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2551                                                &var))
2552                                 has_var = 1;
2553                 }
2554         }
2555
2556 #endif /* !CONFIG_PPC */
2557
2558 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2559         if (!atyfb_get_timings_from_lcd(par, &var))
2560                 has_var = 1;
2561 #endif
2562
2563         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2564                 has_var = 1;
2565
2566         if (!has_var)
2567                 var = default_var;
2568
2569         if (noaccel)
2570                 var.accel_flags &= ~FB_ACCELF_TEXT;
2571         else
2572                 var.accel_flags |= FB_ACCELF_TEXT;
2573
2574         if (comp_sync != -1) {
2575                 if (!comp_sync)
2576                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2577                 else
2578                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2579         }
2580
2581         if (var.yres == var.yres_virtual) {
2582                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2583                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2584                 if (var.yres_virtual < var.yres)
2585                         var.yres_virtual = var.yres;
2586         }
2587
2588         if (atyfb_check_var(&var, info)) {
2589                 PRINTKE("can't set default video mode\n");
2590                 goto aty_init_exit;
2591         }
2592
2593 #ifdef __sparc__
2594         atyfb_save_palette(par, 0);
2595 #endif
2596
2597 #ifdef CONFIG_FB_ATY_CT
2598         if (!noaccel && M64_HAS(INTEGRATED))
2599                 aty_init_cursor(info);
2600 #endif /* CONFIG_FB_ATY_CT */
2601         info->var = var;
2602
2603         fb_alloc_cmap(&info->cmap, 256, 0);
2604
2605         if (register_framebuffer(info) < 0)
2606                 goto aty_init_exit;
2607
2608         fb_list = info;
2609
2610         PRINTKI("fb%d: %s frame buffer device on %s\n",
2611                info->node, info->fix.id, name);
2612         return 0;
2613
2614 aty_init_exit:
2615         /* restore video mode */
2616         aty_set_crtc(par, &saved_crtc);
2617         par->pll_ops->set_pll(info, &saved_pll);
2618
2619 #ifdef CONFIG_MTRR
2620         if (par->mtrr_reg >= 0) {
2621             mtrr_del(par->mtrr_reg, 0, 0);
2622             par->mtrr_reg = -1;
2623         }
2624         if (par->mtrr_aper >= 0) {
2625             mtrr_del(par->mtrr_aper, 0, 0);
2626             par->mtrr_aper = -1;
2627         }
2628 #endif
2629         return -1;
2630 }
2631
2632 #ifdef CONFIG_ATARI
2633 static int __init store_video_par(char *video_str, unsigned char m64_num)
2634 {
2635         char *p;
2636         unsigned long vmembase, size, guiregbase;
2637
2638         PRINTKI("store_video_par() '%s' \n", video_str);
2639
2640         if (!(p = strsep(&video_str, ";")) || !*p)
2641                 goto mach64_invalid;
2642         vmembase = simple_strtoul(p, NULL, 0);
2643         if (!(p = strsep(&video_str, ";")) || !*p)
2644                 goto mach64_invalid;
2645         size = simple_strtoul(p, NULL, 0);
2646         if (!(p = strsep(&video_str, ";")) || !*p)
2647                 goto mach64_invalid;
2648         guiregbase = simple_strtoul(p, NULL, 0);
2649
2650         phys_vmembase[m64_num] = vmembase;
2651         phys_size[m64_num] = size;
2652         phys_guiregbase[m64_num] = guiregbase;
2653         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2654                guiregbase);
2655         return 0;
2656
2657       mach64_invalid:
2658         phys_vmembase[m64_num] = 0;
2659         return -1;
2660 }
2661 #endif /* CONFIG_ATARI */
2662
2663     /*
2664      *  Blank the display.
2665      */
2666
2667 static int atyfb_blank(int blank, struct fb_info *info)
2668 {
2669         struct atyfb_par *par = (struct atyfb_par *) info->par;
2670         u32 gen_cntl;
2671
2672         if (par->lock_blank || par->asleep)
2673                 return 0;
2674
2675 #ifdef CONFIG_PMAC_BACKLIGHT
2676         if ((_machine == _MACH_Pmac) && blank > FB_BLANK_NORMAL)
2677                 set_backlight_enable(0);
2678 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2679         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2680             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2681                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2682                 pm &= ~PWR_BLON;
2683                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2684         }
2685 #endif
2686
2687         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2688         switch (blank) {
2689                 case FB_BLANK_UNBLANK:
2690                         gen_cntl &= ~0x400004c;
2691                         break;
2692                 case FB_BLANK_NORMAL:
2693                         gen_cntl |= 0x4000040;
2694                         break;
2695                 case FB_BLANK_VSYNC_SUSPEND:
2696                         gen_cntl |= 0x4000048;
2697                         break;
2698                 case FB_BLANK_HSYNC_SUSPEND:
2699                         gen_cntl |= 0x4000044;
2700                         break;
2701                 case FB_BLANK_POWERDOWN:
2702                         gen_cntl |= 0x400004c;
2703                         break;
2704         }
2705         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2706
2707 #ifdef CONFIG_PMAC_BACKLIGHT
2708         if ((_machine == _MACH_Pmac) && blank <= FB_BLANK_NORMAL)
2709                 set_backlight_enable(1);
2710 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2711         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2712             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2713                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2714                 pm |= PWR_BLON;
2715                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2716         }
2717 #endif
2718
2719         return 0;
2720 }
2721
2722 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2723                        const struct atyfb_par *par)
2724 {
2725 #ifdef CONFIG_ATARI
2726         out_8(&par->aty_cmap_regs->windex, regno);
2727         out_8(&par->aty_cmap_regs->lut, red);
2728         out_8(&par->aty_cmap_regs->lut, green);
2729         out_8(&par->aty_cmap_regs->lut, blue);
2730 #else
2731         writeb(regno, &par->aty_cmap_regs->windex);
2732         writeb(red, &par->aty_cmap_regs->lut);
2733         writeb(green, &par->aty_cmap_regs->lut);
2734         writeb(blue, &par->aty_cmap_regs->lut);
2735 #endif
2736 }
2737
2738     /*
2739      *  Set a single color register. The values supplied are already
2740      *  rounded down to the hardware's capabilities (according to the
2741      *  entries in the var structure). Return != 0 for invalid regno.
2742      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2743      */
2744
2745 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2746         u_int transp, struct fb_info *info)
2747 {
2748         struct atyfb_par *par = (struct atyfb_par *) info->par;
2749         int i, depth;
2750         u32 *pal = info->pseudo_palette;
2751
2752         depth = info->var.bits_per_pixel;
2753         if (depth == 16)
2754                 depth = (info->var.green.length == 5) ? 15 : 16;
2755
2756         if (par->asleep)
2757                 return 0;
2758
2759         if (regno > 255 ||
2760             (depth == 16 && regno > 63) ||
2761             (depth == 15 && regno > 31))
2762                 return 1;
2763
2764         red >>= 8;
2765         green >>= 8;
2766         blue >>= 8;
2767
2768         par->palette[regno].red = red;
2769         par->palette[regno].green = green;
2770         par->palette[regno].blue = blue;
2771
2772         if (regno < 16) {
2773                 switch (depth) {
2774                 case 15:
2775                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2776                         break;
2777                 case 16:
2778                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2779                         break;
2780                 case 24:
2781                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2782                         break;
2783                 case 32:
2784                         i = (regno << 8) | regno;
2785                         pal[regno] = (i << 16) | i;
2786                         break;
2787                 }
2788         }
2789
2790         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2791         if (M64_HAS(EXTRA_BRIGHT))
2792                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2793         aty_st_8(DAC_CNTL, i, par);
2794         aty_st_8(DAC_MASK, 0xff, par);
2795
2796         if (M64_HAS(INTEGRATED)) {
2797                 if (depth == 16) {
2798                         if (regno < 32)
2799                                 aty_st_pal(regno << 3, red,
2800                                            par->palette[regno<<1].green,
2801                                            blue, par);
2802                         red = par->palette[regno>>1].red;
2803                         blue = par->palette[regno>>1].blue;
2804                         regno <<= 2;
2805                 } else if (depth == 15) {
2806                         regno <<= 3;
2807                         for(i = 0; i < 8; i++) {
2808                             aty_st_pal(regno + i, red, green, blue, par);
2809                         }
2810                 }
2811         }
2812         aty_st_pal(regno, red, green, blue, par);
2813
2814         return 0;
2815 }
2816
2817 #ifdef CONFIG_PCI
2818
2819 #ifdef __sparc__
2820
2821 extern void (*prom_palette) (int);
2822
2823 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2824                         struct fb_info *info, unsigned long addr)
2825 {
2826         extern int con_is_present(void);
2827
2828         struct atyfb_par *par = info->par;
2829         struct pcidev_cookie *pcp;
2830         char prop[128];
2831         int node, len, i, j, ret;
2832         u32 mem, chip_id;
2833
2834         /* Do not attach when we have a serial console. */
2835         if (!con_is_present())
2836                 return -ENXIO;
2837
2838         /*
2839          * Map memory-mapped registers.
2840          */
2841         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2842         info->fix.mmio_start = addr + 0x7ffc00UL;
2843
2844         /*
2845          * Map in big-endian aperture.
2846          */
2847         info->screen_base = (char *) (addr + 0x800000UL);
2848         info->fix.smem_start = addr + 0x800000UL;
2849
2850         /*
2851          * Figure mmap addresses from PCI config space.
2852          * Split Framebuffer in big- and little-endian halfs.
2853          */
2854         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2855                 /* nothing */ ;
2856         j = i + 4;
2857
2858         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2859         if (!par->mmap_map) {
2860                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2861                 return -ENOMEM;
2862         }
2863         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2864
2865         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2866                 struct resource *rp = &pdev->resource[i];
2867                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2868                 unsigned long base;
2869                 u32 size, pbase;
2870
2871                 base = rp->start;
2872
2873                 io = (rp->flags & IORESOURCE_IO);
2874
2875                 size = rp->end - base + 1;
2876
2877                 pci_read_config_dword(pdev, breg, &pbase);
2878
2879                 if (io)
2880                         size &= ~1;
2881
2882                 /*
2883                  * Map the framebuffer a second time, this time without
2884                  * the braindead _PAGE_IE setting. This is used by the
2885                  * fixed Xserver, but we need to maintain the old mapping
2886                  * to stay compatible with older ones...
2887                  */
2888                 if (base == addr) {
2889                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2890                         par->mmap_map[j].poff = base & PAGE_MASK;
2891                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2892                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2893                         par->mmap_map[j].prot_flag = _PAGE_E;
2894                         j++;
2895                 }
2896
2897                 /*
2898                  * Here comes the old framebuffer mapping with _PAGE_IE
2899                  * set for the big endian half of the framebuffer...
2900                  */
2901                 if (base == addr) {
2902                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2903                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2904                         par->mmap_map[j].size = 0x800000;
2905                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2906                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2907                         size -= 0x800000;
2908                         j++;
2909                 }
2910
2911                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2912                 par->mmap_map[j].poff = base & PAGE_MASK;
2913                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2914                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2915                 par->mmap_map[j].prot_flag = _PAGE_E;
2916                 j++;
2917         }
2918
2919         if((ret = correct_chipset(par)))
2920                 return ret;
2921
2922         if (IS_XL(pdev->device)) {
2923                 /*
2924                  * Fix PROMs idea of MEM_CNTL settings...
2925                  */
2926                 mem = aty_ld_le32(MEM_CNTL, par);
2927                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2928                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2929                         switch (mem & 0x0f) {
2930                         case 3:
2931                                 mem = (mem & ~(0x0f)) | 2;
2932                                 break;
2933                         case 7:
2934                                 mem = (mem & ~(0x0f)) | 3;
2935                                 break;
2936                         case 9:
2937                                 mem = (mem & ~(0x0f)) | 4;
2938                                 break;
2939                         case 11:
2940                                 mem = (mem & ~(0x0f)) | 5;
2941                                 break;
2942                         default:
2943                                 break;
2944                         }
2945                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2946                                 mem &= ~(0x00700000);
2947                 }
2948                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2949                 aty_st_le32(MEM_CNTL, mem, par);
2950         }
2951
2952         /*
2953          * If this is the console device, we will set default video
2954          * settings to what the PROM left us with.
2955          */
2956         node = prom_getchild(prom_root_node);
2957         node = prom_searchsiblings(node, "aliases");
2958         if (node) {
2959                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2960                 if (len > 0) {
2961                         prop[len] = '\0';
2962                         node = prom_finddevice(prop);
2963                 } else
2964                         node = 0;
2965         }
2966
2967         pcp = pdev->sysdata;
2968         if (node == pcp->prom_node) {
2969                 struct fb_var_screeninfo *var = &default_var;
2970                 unsigned int N, P, Q, M, T, R;
2971                 u32 v_total, h_total;
2972                 struct crtc crtc;
2973                 u8 pll_regs[16];
2974                 u8 clock_cntl;
2975
2976                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2977                 crtc.vyres = prom_getintdefault(node, "height", 768);
2978                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2979                 var->xoffset = var->yoffset = 0;
2980                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2981                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2982                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2983                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2984                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2985                 aty_crtc_to_var(&crtc, var);
2986
2987                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2988                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2989
2990                 /*
2991                  * Read the PLL to figure actual Refresh Rate.
2992                  */
2993                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2994                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2995                 for (i = 0; i < 16; i++)
2996                         pll_regs[i] = aty_ld_pll_ct(i, par);
2997
2998                 /*
2999                  * PLL Reference Divider M:
3000                  */
3001                 M = pll_regs[2];
3002
3003                 /*
3004                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3005                  */
3006                 N = pll_regs[7 + (clock_cntl & 3)];
3007
3008                 /*
3009                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3010                  */
3011                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3012
3013                 /*
3014                  * PLL Divider Q:
3015                  */
3016                 Q = N / P;
3017
3018                 /*
3019                  * Target Frequency:
3020                  *
3021                  *      T * M
3022                  * Q = -------
3023                  *      2 * R
3024                  *
3025                  * where R is XTALIN (= 14318 or 29498 kHz).
3026                  */
3027                 if (IS_XL(pdev->device))
3028                         R = 29498;
3029                 else
3030                         R = 14318;
3031
3032                 T = 2 * Q * R / M;
3033
3034                 default_var.pixclock = 1000000000 / T;
3035         }
3036
3037         return 0;
3038 }
3039
3040 #else /* __sparc__ */
3041
3042 #ifdef __i386__
3043 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3044 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3045 {
3046         u32 driv_inf_tab, sig;
3047         u16 lcd_ofs;
3048
3049         /* To support an LCD panel, we should know it's dimensions and
3050          *  it's desired pixel clock.
3051          * There are two ways to do it:
3052          *  - Check the startup video mode and calculate the panel
3053          *    size from it. This is unreliable.
3054          *  - Read it from the driver information table in the video BIOS.
3055         */
3056         /* Address of driver information table is at offset 0x78. */
3057         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3058
3059         /* Check for the driver information table signature. */
3060         sig = (*(u32 *)driv_inf_tab);
3061         if ((sig == 0x54504c24) || /* Rage LT pro */
3062                 (sig == 0x544d5224) || /* Rage mobility */
3063                 (sig == 0x54435824) || /* Rage XC */
3064                 (sig == 0x544c5824)) { /* Rage XL */
3065                 PRINTKI("BIOS contains driver information table.\n");
3066                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3067                 par->lcd_table = 0;
3068                 if (lcd_ofs != 0) {
3069                         par->lcd_table = bios_base + lcd_ofs;
3070                 }
3071         }
3072
3073         if (par->lcd_table != 0) {
3074                 char model[24];
3075                 char strbuf[16];
3076                 char refresh_rates_buf[100];
3077                 int id, tech, f, i, m, default_refresh_rate;
3078                 char *txtcolour;
3079                 char *txtmonitor;
3080                 char *txtdual;
3081                 char *txtformat;
3082                 u16 width, height, panel_type, refresh_rates;
3083                 u16 *lcdmodeptr;
3084                 u32 format;
3085                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3086                 /* The most important information is the panel size at
3087                  * offset 25 and 27, but there's some other nice information
3088                  * which we print to the screen.
3089                  */
3090                 id = *(u8 *)par->lcd_table;
3091                 strncpy(model,(char *)par->lcd_table+1,24);
3092                 model[23]=0;
3093
3094                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3095                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3096                 panel_type = *(u16 *)(par->lcd_table+29);
3097                 if (panel_type & 1)
3098                         txtcolour = "colour";
3099                 else
3100                         txtcolour = "monochrome";
3101                 if (panel_type & 2)
3102                         txtdual = "dual (split) ";
3103                 else
3104                         txtdual = "";
3105                 tech = (panel_type>>2) & 63;
3106                 switch (tech) {
3107                 case 0:
3108                         txtmonitor = "passive matrix";
3109                         break;
3110                 case 1:
3111                         txtmonitor = "active matrix";
3112                         break;
3113                 case 2:
3114                         txtmonitor = "active addressed STN";
3115                         break;
3116                 case 3:
3117                         txtmonitor = "EL";
3118                         break;
3119                 case 4:
3120                         txtmonitor = "plasma";
3121                         break;
3122                 default:
3123                         txtmonitor = "unknown";
3124                 }
3125                 format = *(u32 *)(par->lcd_table+57);
3126                 if (tech == 0 || tech == 2) {
3127                         switch (format & 7) {
3128                         case 0:
3129                                 txtformat = "12 bit interface";
3130                                 break;
3131                         case 1:
3132                                 txtformat = "16 bit interface";
3133                                 break;
3134                         case 2:
3135                                 txtformat = "24 bit interface";
3136                                 break;
3137                         default:
3138                                 txtformat = "unkown format";
3139                         }
3140                 } else {
3141                         switch (format & 7) {
3142                         case 0:
3143                                 txtformat = "8 colours";
3144                                 break;
3145                         case 1:
3146                                 txtformat = "512 colours";
3147                                 break;
3148                         case 2:
3149                                 txtformat = "4096 colours";
3150                                 break;
3151                         case 4:
3152                                 txtformat = "262144 colours (LT mode)";
3153                                 break;
3154                         case 5:
3155                                 txtformat = "16777216 colours";
3156                                 break;
3157                         case 6:
3158                                 txtformat = "262144 colours (FDPI-2 mode)";
3159                                 break;
3160                         default:
3161                                 txtformat = "unkown format";
3162                         }
3163                 }
3164                 PRINTKI("%s%s %s monitor detected: %s\n",
3165                         txtdual ,txtcolour, txtmonitor, model);
3166                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3167                         id, width, height, txtformat);
3168                 refresh_rates_buf[0] = 0;
3169                 refresh_rates = *(u16 *)(par->lcd_table+62);
3170                 m = 1;
3171                 f = 0;
3172                 for (i=0;i<16;i++) {
3173                         if (refresh_rates & m) {
3174                                 if (f == 0) {
3175                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3176                                         f++;
3177                                 } else {
3178                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3179                                 }
3180                                 strcat(refresh_rates_buf,strbuf);
3181                         }
3182                         m = m << 1;
3183                 }
3184                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3185                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3186                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3187                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3188                 /* We now need to determine the crtc parameters for the
3189                  * LCD monitor. This is tricky, because they are not stored
3190                  * individually in the BIOS. Instead, the BIOS contains a
3191                  * table of display modes that work for this monitor.
3192                  *
3193                  * The idea is that we search for a mode of the same dimensions
3194                  * as the dimensions of the LCD monitor. Say our LCD monitor
3195                  * is 800x600 pixels, we search for a 800x600 monitor.
3196                  * The CRTC parameters we find here are the ones that we need
3197                  * to use to simulate other resolutions on the LCD screen.
3198                  */
3199                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3200                 while (*lcdmodeptr != 0) {
3201                         u32 modeptr;
3202                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3203                         modeptr = bios_base + *lcdmodeptr;
3204
3205                         mwidth = *((u16 *)(modeptr+0));
3206                         mheight = *((u16 *)(modeptr+2));
3207
3208                         if (mwidth == width && mheight == height) {
3209                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3210                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3211                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3212                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3213                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3214                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3215
3216                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3217                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3218                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3219                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3220
3221                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3222                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3223                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3224                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3225
3226                                 par->lcd_vtotal++;
3227                                 par->lcd_vdisp++;
3228                                 lcd_vsync_start++;
3229
3230                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3231                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3232                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3233                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3234                                 break;
3235                         }
3236
3237                         lcdmodeptr++;
3238                 }
3239                 if (*lcdmodeptr == 0) {
3240                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3241                         /* To do: Switch to CRT if possible. */
3242                 } else {
3243                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3244                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3245                                 par->lcd_hdisp,
3246                                 par->lcd_hdisp + par->lcd_right_margin,
3247                                 par->lcd_hdisp + par->lcd_right_margin
3248                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3249                                 par->lcd_htotal,
3250                                 par->lcd_vdisp,
3251                                 par->lcd_vdisp + par->lcd_lower_margin,
3252                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3253                                 par->lcd_vtotal);
3254                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3255                                 par->lcd_pixclock,
3256                                 par->lcd_hblank_len - (par->lcd_right_margin +
3257                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3258                                 par->lcd_hdisp,
3259                                 par->lcd_right_margin,
3260                                 par->lcd_hsync_len,
3261                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3262                                 par->lcd_vdisp,
3263                                 par->lcd_lower_margin,
3264                                 par->lcd_vsync_len);
3265                 }
3266         }
3267 }
3268 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3269
3270 static int __devinit init_from_bios(struct atyfb_par *par)
3271 {
3272         u32 bios_base, rom_addr;
3273         int ret;
3274
3275         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3276         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3277
3278         /* The BIOS starts with 0xaa55. */
3279         if (*((u16 *)bios_base) == 0xaa55) {
3280
3281                 u8 *bios_ptr;
3282                 u16 rom_table_offset, freq_table_offset;
3283                 PLL_BLOCK_MACH64 pll_block;
3284
3285                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3286
3287                 /* check for frequncy table */
3288                 bios_ptr = (u8*)bios_base;
3289                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3290                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3291                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3292
3293                 PRINTKI("BIOS frequency table:\n");
3294                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3295                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3296                         pll_block.ref_freq, pll_block.ref_divider);
3297                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3298                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3299                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3300
3301                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3302                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3303                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3304                 par->pll_limits.ref_div = pll_block.ref_divider;
3305                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3306                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3307                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3308                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3309 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3310                 aty_init_lcd(par, bios_base);
3311 #endif
3312                 ret = 0;
3313         } else {
3314                 PRINTKE("no BIOS frequency table found, use parameters\n");
3315                 ret = -ENXIO;
3316         }
3317         iounmap((void* __iomem )bios_base);
3318
3319         return ret;
3320 }
3321 #endif /* __i386__ */
3322
3323 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3324 {
3325         struct atyfb_par *par = info->par;
3326         u16 tmp;
3327         unsigned long raddr;
3328         struct resource *rrp;
3329         int ret = 0;
3330
3331         raddr = addr + 0x7ff000UL;
3332         rrp = &pdev->resource[2];
3333         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3334                 par->aux_start = rrp->start;
3335                 par->aux_size = rrp->end - rrp->start + 1;
3336                 raddr = rrp->start;
3337                 PRINTKI("using auxiliary register aperture\n");
3338         }
3339
3340         info->fix.mmio_start = raddr;
3341         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3342         if (par->ati_regbase == 0)
3343                 return -ENOMEM;
3344
3345         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3346         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3347
3348         /*
3349          * Enable memory-space accesses using config-space
3350          * command register.
3351          */
3352         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3353         if (!(tmp & PCI_COMMAND_MEMORY)) {
3354                 tmp |= PCI_COMMAND_MEMORY;
3355                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3356         }
3357 #ifdef __BIG_ENDIAN
3358         /* Use the big-endian aperture */
3359         addr += 0x800000;
3360 #endif
3361
3362         /* Map in frame buffer */
3363         info->fix.smem_start = addr;
3364         info->screen_base = ioremap(addr, 0x800000);
3365         if (info->screen_base == NULL) {
3366                 ret = -ENOMEM;
3367                 goto atyfb_setup_generic_fail;
3368         }
3369
3370         if((ret = correct_chipset(par)))
3371                 goto atyfb_setup_generic_fail;
3372 #ifdef __i386__
3373         if((ret = init_from_bios(par)))
3374                 goto atyfb_setup_generic_fail;
3375 #endif
3376         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3377                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3378         else
3379                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3380
3381         /* according to ATI, we should use clock 3 for acelerated mode */
3382         par->clk_wr_offset = 3;
3383
3384         return 0;
3385
3386 atyfb_setup_generic_fail:
3387         iounmap(par->ati_regbase);
3388         par->ati_regbase = NULL;
3389         return ret;
3390 }
3391
3392 #endif /* !__sparc__ */
3393
3394 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3395 {
3396         unsigned long addr, res_start, res_size;
3397         struct fb_info *info;
3398         struct resource *rp;
3399         struct atyfb_par *par;
3400         int i, rc = -ENOMEM;
3401
3402         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3403                 if (pdev->device == aty_chips[i].pci_id)
3404                         break;
3405
3406         if (i < 0)
3407                 return -ENODEV;
3408
3409         /* Enable device in PCI config */
3410         if (pci_enable_device(pdev)) {
3411                 PRINTKE("Cannot enable PCI device\n");
3412                 return -ENXIO;
3413         }
3414
3415         /* Find which resource to use */
3416         rp = &pdev->resource[0];
3417         if (rp->flags & IORESOURCE_IO)
3418                 rp = &pdev->resource[1];
3419         addr = rp->start;
3420         if (!addr)
3421                 return -ENXIO;
3422
3423         /* Reserve space */
3424         res_start = rp->start;
3425         res_size = rp->end - rp->start + 1;
3426         if (!request_mem_region (res_start, res_size, "atyfb"))
3427                 return -EBUSY;
3428
3429         /* Allocate framebuffer */
3430         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3431         if (!info) {
3432                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3433                 return -ENOMEM;
3434         }
3435         par = info->par;
3436         info->fix = atyfb_fix;
3437         info->device = &pdev->dev;
3438         par->pci_id = aty_chips[i].pci_id;
3439         par->res_start = res_start;
3440         par->res_size = res_size;
3441         par->irq = pdev->irq;
3442
3443         /* Setup "info" structure */
3444 #ifdef __sparc__
3445         rc = atyfb_setup_sparc(pdev, info, addr);
3446 #else
3447         rc = atyfb_setup_generic(pdev, info, addr);
3448 #endif
3449         if (rc)
3450                 goto err_release_mem;
3451
3452         pci_set_drvdata(pdev, info);
3453
3454         /* Init chip & register framebuffer */
3455         if (aty_init(info, "PCI"))
3456                 goto err_release_io;
3457
3458 #ifdef __sparc__
3459         if (!prom_palette)
3460                 prom_palette = atyfb_palette;
3461
3462         /*
3463          * Add /dev/fb mmap values.
3464          */
3465         par->mmap_map[0].voff = 0x8000000000000000UL;
3466         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3467         par->mmap_map[0].size = info->fix.smem_len;
3468         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3469         par->mmap_map[0].prot_flag = _PAGE_E;
3470         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3471         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3472         par->mmap_map[1].size = PAGE_SIZE;
3473         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3474         par->mmap_map[1].prot_flag = _PAGE_E;
3475 #endif /* __sparc__ */
3476
3477         return 0;
3478
3479 err_release_io:
3480 #ifdef __sparc__
3481         kfree(par->mmap_map);
3482 #else
3483         if (par->ati_regbase)
3484                 iounmap(par->ati_regbase);
3485         if (info->screen_base)
3486                 iounmap(info->screen_base);
3487 #endif
3488 err_release_mem:
3489         if (par->aux_start)
3490                 release_mem_region(par->aux_start, par->aux_size);
3491
3492         release_mem_region(par->res_start, par->res_size);
3493         framebuffer_release(info);
3494
3495         return rc;
3496 }
3497
3498 #endif /* CONFIG_PCI */
3499
3500 #ifdef CONFIG_ATARI
3501
3502 static int __devinit atyfb_atari_probe(void)
3503 {
3504         struct atyfb_par *par;
3505         struct fb_info *info;
3506         int m64_num;
3507         u32 clock_r;
3508
3509         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3510                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3511                     !phys_guiregbase[m64_num]) {
3512                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3513                         continue;
3514                 }
3515
3516                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3517                 if (!info) {
3518                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3519                         return -ENOMEM;
3520                 }
3521                 par = info->par;
3522
3523                 info->fix = atyfb_fix;
3524
3525                 par->irq = (unsigned int) -1; /* something invalid */
3526
3527                 /*
3528                  *  Map the video memory (physical address given) to somewhere in the
3529                  *  kernel address space.
3530                  */
3531                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3532                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3533                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3534                                                 0xFC00ul;
3535                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3536
3537                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3538                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3539
3540                 switch (clock_r & 0x003F) {
3541                 case 0x12:
3542                         par->clk_wr_offset = 3; /*  */
3543                         break;
3544                 case 0x34:
3545                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3546                         break;
3547                 case 0x16:
3548                         par->clk_wr_offset = 1; /*  */
3549                         break;
3550                 case 0x38:
3551                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3552                         break;
3553                 }
3554
3555                 if (aty_init(info, "ISA bus")) {
3556                         framebuffer_release(info);
3557                         /* This is insufficient! kernel_map has added two large chunks!! */
3558                         return -ENXIO;
3559                 }
3560         }
3561 }
3562
3563 #endif /* CONFIG_ATARI */
3564
3565 static void __devexit atyfb_remove(struct fb_info *info)
3566 {
3567         struct atyfb_par *par = (struct atyfb_par *) info->par;
3568
3569         /* restore video mode */
3570         aty_set_crtc(par, &saved_crtc);
3571         par->pll_ops->set_pll(info, &saved_pll);
3572
3573         unregister_framebuffer(info);
3574
3575 #ifdef CONFIG_MTRR
3576         if (par->mtrr_reg >= 0) {
3577             mtrr_del(par->mtrr_reg, 0, 0);
3578             par->mtrr_reg = -1;
3579         }
3580         if (par->mtrr_aper >= 0) {
3581             mtrr_del(par->mtrr_aper, 0, 0);
3582             par->mtrr_aper = -1;
3583         }
3584 #endif
3585 #ifndef __sparc__
3586         if (par->ati_regbase)
3587                 iounmap(par->ati_regbase);
3588         if (info->screen_base)
3589                 iounmap(info->screen_base);
3590 #ifdef __BIG_ENDIAN
3591         if (info->sprite.addr)
3592                 iounmap(info->sprite.addr);
3593 #endif
3594 #endif
3595 #ifdef __sparc__
3596         kfree(par->mmap_map);
3597 #endif
3598         if (par->aux_start)
3599                 release_mem_region(par->aux_start, par->aux_size);
3600
3601         if (par->res_start)
3602                 release_mem_region(par->res_start, par->res_size);
3603
3604         framebuffer_release(info);
3605 }
3606
3607 #ifdef CONFIG_PCI
3608
3609 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3610 {
3611         struct fb_info *info = pci_get_drvdata(pdev);
3612
3613         atyfb_remove(info);
3614 }
3615
3616 /*
3617  * This driver uses its own matching table. That will be more difficult
3618  * to fix, so for now, we just match against any ATI ID and let the
3619  * probe() function find out what's up. That also mean we don't have
3620  * a module ID table though.
3621  */
3622 static struct pci_device_id atyfb_pci_tbl[] = {
3623         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3624           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3625         { 0, }
3626 };
3627
3628 static struct pci_driver atyfb_driver = {
3629         .name           = "atyfb",
3630         .id_table       = atyfb_pci_tbl,
3631         .probe          = atyfb_pci_probe,
3632         .remove         = __devexit_p(atyfb_pci_remove),
3633 #ifdef CONFIG_PM
3634         .suspend        = atyfb_pci_suspend,
3635         .resume         = atyfb_pci_resume,
3636 #endif /* CONFIG_PM */
3637 };
3638
3639 #endif /* CONFIG_PCI */
3640
3641 #ifndef MODULE
3642 static int __init atyfb_setup(char *options)
3643 {
3644         char *this_opt;
3645
3646         if (!options || !*options)
3647                 return 0;
3648
3649         while ((this_opt = strsep(&options, ",")) != NULL) {
3650                 if (!strncmp(this_opt, "noaccel", 7)) {
3651                         noaccel = 1;
3652 #ifdef CONFIG_MTRR
3653                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3654                         nomtrr = 1;
3655 #endif
3656                 } else if (!strncmp(this_opt, "vram:", 5))
3657                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3658                 else if (!strncmp(this_opt, "pll:", 4))
3659                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3660                 else if (!strncmp(this_opt, "mclk:", 5))
3661                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3662                 else if (!strncmp(this_opt, "xclk:", 5))
3663                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3664                 else if (!strncmp(this_opt, "comp_sync:", 10))
3665                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3666 #ifdef CONFIG_PPC
3667                 else if (!strncmp(this_opt, "vmode:", 6)) {
3668                         unsigned int vmode =
3669                             simple_strtoul(this_opt + 6, NULL, 0);
3670                         if (vmode > 0 && vmode <= VMODE_MAX)
3671                                 default_vmode = vmode;
3672                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3673                         unsigned int cmode =
3674                             simple_strtoul(this_opt + 6, NULL, 0);
3675                         switch (cmode) {
3676                         case 0:
3677                         case 8:
3678                                 default_cmode = CMODE_8;
3679                                 break;
3680                         case 15:
3681                         case 16:
3682                                 default_cmode = CMODE_16;
3683                                 break;
3684                         case 24:
3685                         case 32:
3686                                 default_cmode = CMODE_32;
3687                                 break;
3688                         }
3689                 }
3690 #endif
3691 #ifdef CONFIG_ATARI
3692                 /*
3693                  * Why do we need this silly Mach64 argument?
3694                  * We are already here because of mach64= so its redundant.
3695                  */
3696                 else if (MACH_IS_ATARI
3697                          && (!strncmp(this_opt, "Mach64:", 7))) {
3698                         static unsigned char m64_num;
3699                         static char mach64_str[80];
3700                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3701                         if (!store_video_par(mach64_str, m64_num)) {
3702                                 m64_num++;
3703                                 mach64_count = m64_num;
3704                         }
3705                 }
3706 #endif
3707                 else
3708                         mode = this_opt;
3709         }
3710         return 0;
3711 }
3712 #endif  /*  MODULE  */
3713
3714 static int __init atyfb_init(void)
3715 {
3716 #ifndef MODULE
3717     char *option = NULL;
3718
3719     if (fb_get_options("atyfb", &option))
3720         return -ENODEV;
3721     atyfb_setup(option);
3722 #endif
3723
3724     pci_register_driver(&atyfb_driver);
3725 #ifdef CONFIG_ATARI
3726     atyfb_atari_probe();
3727 #endif
3728     return 0;
3729 }
3730
3731 static void __exit atyfb_exit(void)
3732 {
3733         pci_unregister_driver(&atyfb_driver);
3734 }
3735
3736 module_init(atyfb_init);
3737 module_exit(atyfb_exit);
3738
3739 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3740 MODULE_LICENSE("GPL");
3741 module_param(noaccel, bool, 0);
3742 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3743 module_param(vram, int, 0);
3744 MODULE_PARM_DESC(vram, "int: override size of video ram");
3745 module_param(pll, int, 0);
3746 MODULE_PARM_DESC(pll, "int: override video clock");
3747 module_param(mclk, int, 0);
3748 MODULE_PARM_DESC(mclk, "int: override memory clock");
3749 module_param(xclk, int, 0);
3750 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3751 module_param(comp_sync, int, 0);
3752 MODULE_PARM_DESC(comp_sync,
3753                  "Set composite sync signal to low (0) or high (1)");
3754 module_param(mode, charp, 0);
3755 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3756 #ifdef CONFIG_MTRR
3757 module_param(nomtrr, bool, 0);
3758 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3759 #endif