2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/module.h>
53 #include <linux/moduleparam.h>
54 #include <linux/kernel.h>
55 #include <linux/errno.h>
56 #include <linux/string.h>
58 #include <linux/slab.h>
59 #include <linux/vmalloc.h>
60 #include <linux/delay.h>
61 #include <linux/console.h>
63 #include <linux/init.h>
64 #include <linux/pci.h>
65 #include <linux/interrupt.h>
66 #include <linux/spinlock.h>
67 #include <linux/wait.h>
68 #include <linux/backlight.h>
69 #include <linux/reboot.h>
70 #include <linux/dmi.h>
73 #include <linux/uaccess.h>
75 #include <video/mach64.h>
80 #include <asm/machdep.h>
82 #include "../macmodes.h"
86 #include <asm/oplib.h>
91 #include <linux/adb.h>
92 #include <linux/pmu.h>
94 #ifdef CONFIG_BOOTX_TEXT
95 #include <asm/btext.h>
97 #ifdef CONFIG_PMAC_BACKLIGHT
98 #include <asm/backlight.h>
101 #include <asm/mtrr.h>
110 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
111 /* - must be large enough to catch all GUI-Regs */
112 /* - must be aligned to a PAGE boundary */
113 #define GUI_RESERVE (1 * PAGE_SIZE)
115 /* FIXME: remove the FAIL definition */
116 #define FAIL(msg) do { \
117 if (!(var->activate & FB_ACTIVATE_TEST)) \
118 printk(KERN_CRIT "atyfb: " msg "\n"); \
121 #define FAIL_MAX(msg, x, _max_) do { \
123 if (!(var->activate & FB_ACTIVATE_TEST)) \
124 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
129 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
131 #define DPRINTK(fmt, args...)
134 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
135 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
137 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || \
138 defined (CONFIG_FB_ATY_GENERIC_LCD) || defined(CONFIG_FB_ATY_BACKLIGHT)
139 static const u32 lt_lcd_regs[] = {
146 0, /* EXT_VERT_STRETCH */
151 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
153 if (M64_HAS(LT_LCD_REGS)) {
154 aty_st_le32(lt_lcd_regs[index], val, par);
158 /* write addr byte */
159 temp = aty_ld_le32(LCD_INDEX, par);
160 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
161 /* write the register value */
162 aty_st_le32(LCD_DATA, val, par);
166 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
168 if (M64_HAS(LT_LCD_REGS)) {
169 return aty_ld_le32(lt_lcd_regs[index], par);
173 /* write addr byte */
174 temp = aty_ld_le32(LCD_INDEX, par);
175 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
176 /* read the register value */
177 return aty_ld_le32(LCD_DATA, par);
180 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
182 #ifdef CONFIG_FB_ATY_GENERIC_LCD
186 * Reduce a fraction by factoring out the largest common divider of the
187 * fraction's numerator and denominator.
189 static void ATIReduceRatio(int *Numerator, int *Denominator)
191 int Multiplier, Divider, Remainder;
193 Multiplier = *Numerator;
194 Divider = *Denominator;
196 while ((Remainder = Multiplier % Divider))
198 Multiplier = Divider;
202 *Numerator /= Divider;
203 *Denominator /= Divider;
207 * The Hardware parameters for each card
210 struct pci_mmap_map {
214 unsigned long prot_flag;
215 unsigned long prot_mask;
218 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
220 .type = FB_TYPE_PACKED_PIXELS,
221 .visual = FB_VISUAL_PSEUDOCOLOR,
227 * Frame buffer device API
230 static int atyfb_open(struct fb_info *info, int user);
231 static int atyfb_release(struct fb_info *info, int user);
232 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
233 static int atyfb_set_par(struct fb_info *info);
234 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
235 u_int transp, struct fb_info *info);
236 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
237 static int atyfb_blank(int blank, struct fb_info *info);
238 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
240 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
242 static int atyfb_sync(struct fb_info *info);
248 static int aty_init(struct fb_info *info);
251 static int store_video_par(char *videopar, unsigned char m64_num);
254 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
256 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
257 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
258 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
259 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
261 static int read_aty_sense(const struct atyfb_par *par);
264 static DEFINE_MUTEX(reboot_lock);
265 static struct fb_info *reboot_info;
268 * Interface used by the world
271 static struct fb_var_screeninfo default_var = {
272 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
273 640, 480, 640, 480, 0, 0, 8, 0,
274 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
275 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
276 0, FB_VMODE_NONINTERLACED
279 static struct fb_videomode defmode = {
280 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
281 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
282 0, FB_VMODE_NONINTERLACED
285 static struct fb_ops atyfb_ops = {
286 .owner = THIS_MODULE,
287 .fb_open = atyfb_open,
288 .fb_release = atyfb_release,
289 .fb_check_var = atyfb_check_var,
290 .fb_set_par = atyfb_set_par,
291 .fb_setcolreg = atyfb_setcolreg,
292 .fb_pan_display = atyfb_pan_display,
293 .fb_blank = atyfb_blank,
294 .fb_ioctl = atyfb_ioctl,
295 .fb_fillrect = atyfb_fillrect,
296 .fb_copyarea = atyfb_copyarea,
297 .fb_imageblit = atyfb_imageblit,
299 .fb_mmap = atyfb_mmap,
301 .fb_sync = atyfb_sync,
312 static int comp_sync __devinitdata = -1;
315 #ifdef CONFIG_PMAC_BACKLIGHT
316 static int backlight __devinitdata = 1;
318 static int backlight __devinitdata = 0;
322 static int default_vmode __devinitdata = VMODE_CHOOSE;
323 static int default_cmode __devinitdata = CMODE_CHOOSE;
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
332 static unsigned int mach64_count __devinitdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX (M64F_GX)
340 #define ATI_CHIP_88800CX (M64F_GX)
342 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352 /* FIXME what is this chip? */
353 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
355 /* make sets shorter */
356 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
358 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359 /*#define ATI_CHIP_264GTDVD ?*/
360 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
362 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
363 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
364 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
366 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
367 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
372 int pll, mclk, xclk, ecp_max;
374 } aty_chips[] __devinitdata = {
375 #ifdef CONFIG_FB_ATY_GX
377 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
378 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
379 #endif /* CONFIG_FB_ATY_GX */
381 #ifdef CONFIG_FB_ATY_CT
382 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
383 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
385 /* FIXME what is this chip? */
386 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
388 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
389 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
391 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
392 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
394 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
396 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
398 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
403 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
406 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
407 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
409 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
410 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
412 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1024x768 },
413 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
415 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
416 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
420 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
422 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 #endif /* CONFIG_FB_ATY_CT */
429 static int __devinit correct_chipset(struct atyfb_par *par)
437 for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
438 if (par->pci_id == aty_chips[i].pci_id)
444 name = aty_chips[i].name;
445 par->pll_limits.pll_max = aty_chips[i].pll;
446 par->pll_limits.mclk = aty_chips[i].mclk;
447 par->pll_limits.xclk = aty_chips[i].xclk;
448 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
449 par->features = aty_chips[i].features;
451 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
452 type = chip_id & CFG_CHIP_TYPE;
453 rev = (chip_id & CFG_CHIP_REV) >> 24;
455 switch(par->pci_id) {
456 #ifdef CONFIG_FB_ATY_GX
457 case PCI_CHIP_MACH64GX:
461 case PCI_CHIP_MACH64CX:
466 #ifdef CONFIG_FB_ATY_CT
467 case PCI_CHIP_MACH64VT:
468 switch (rev & 0x07) {
470 switch (rev & 0xc0) {
472 name = "ATI264VT (A3) (Mach64 VT)";
473 par->pll_limits.pll_max = 170;
474 par->pll_limits.mclk = 67;
475 par->pll_limits.xclk = 67;
476 par->pll_limits.ecp_max = 80;
477 par->features = ATI_CHIP_264VT;
480 name = "ATI264VT2 (A4) (Mach64 VT)";
481 par->pll_limits.pll_max = 200;
482 par->pll_limits.mclk = 67;
483 par->pll_limits.xclk = 67;
484 par->pll_limits.ecp_max = 80;
485 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
490 name = "ATI264VT3 (B1) (Mach64 VT)";
491 par->pll_limits.pll_max = 200;
492 par->pll_limits.mclk = 67;
493 par->pll_limits.xclk = 67;
494 par->pll_limits.ecp_max = 80;
495 par->features = ATI_CHIP_264VTB;
498 name = "ATI264VT3 (B2) (Mach64 VT)";
499 par->pll_limits.pll_max = 200;
500 par->pll_limits.mclk = 67;
501 par->pll_limits.xclk = 67;
502 par->pll_limits.ecp_max = 80;
503 par->features = ATI_CHIP_264VT3;
507 case PCI_CHIP_MACH64GT:
508 switch (rev & 0x07) {
510 name = "3D RAGE II (Mach64 GT)";
511 par->pll_limits.pll_max = 170;
512 par->pll_limits.mclk = 67;
513 par->pll_limits.xclk = 67;
514 par->pll_limits.ecp_max = 80;
515 par->features = ATI_CHIP_264GTB;
518 name = "3D RAGE II+ (Mach64 GT)";
519 par->pll_limits.pll_max = 200;
520 par->pll_limits.mclk = 67;
521 par->pll_limits.xclk = 67;
522 par->pll_limits.ecp_max = 100;
523 par->features = ATI_CHIP_264GTB;
530 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
534 static char ram_dram[] __devinitdata = "DRAM";
535 static char ram_resv[] __devinitdata = "RESV";
536 #ifdef CONFIG_FB_ATY_GX
537 static char ram_vram[] __devinitdata = "VRAM";
538 #endif /* CONFIG_FB_ATY_GX */
539 #ifdef CONFIG_FB_ATY_CT
540 static char ram_edo[] __devinitdata = "EDO";
541 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
542 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
543 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
544 static char ram_off[] __devinitdata = "OFF";
545 #endif /* CONFIG_FB_ATY_CT */
548 #ifdef CONFIG_FB_ATY_GX
549 static char *aty_gx_ram[8] __devinitdata = {
550 ram_dram, ram_vram, ram_vram, ram_dram,
551 ram_dram, ram_vram, ram_vram, ram_resv
553 #endif /* CONFIG_FB_ATY_GX */
555 #ifdef CONFIG_FB_ATY_CT
556 static char *aty_ct_ram[8] __devinitdata = {
557 ram_off, ram_dram, ram_edo, ram_edo,
558 ram_sdram, ram_sgram, ram_sdram32, ram_resv
560 #endif /* CONFIG_FB_ATY_CT */
562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
564 u32 pixclock = var->pixclock;
565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
567 par->pll.ct.xres = 0;
568 if (par->lcd_table != 0) {
569 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
570 if(lcd_on_off & LCD_ON) {
571 par->pll.ct.xres = var->xres;
572 pixclock = par->lcd_pixclock;
579 #if defined(CONFIG_PPC)
582 * Apple monitor sense
585 static int __devinit read_aty_sense(const struct atyfb_par *par)
589 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
591 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
593 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
594 sense = ((i & 0x3000) >> 3) | (i & 0x100);
596 /* drive each sense line low in turn and collect the other 2 */
597 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
599 i = aty_ld_le32(GP_IO, par);
600 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
601 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
604 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
606 i = aty_ld_le32(GP_IO, par);
607 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
608 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
611 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
613 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
614 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
618 #endif /* defined(CONFIG_PPC) */
620 /* ------------------------------------------------------------------------- */
626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
629 if (par->lcd_table != 0) {
630 if(!M64_HAS(LT_LCD_REGS)) {
631 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
632 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
634 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par);
635 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
638 /* switch to non shadow registers */
639 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
640 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
642 /* save stretching */
643 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
644 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
645 if (!M64_HAS(LT_LCD_REGS))
646 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
649 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
650 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
651 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
652 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
653 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
654 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
655 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
658 if (par->lcd_table != 0) {
659 /* switch to shadow registers */
660 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
661 SHADOW_EN | SHADOW_RW_EN, par);
663 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
664 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
665 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
666 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
668 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
676 if (par->lcd_table != 0) {
678 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
680 /* update non-shadow registers first */
681 aty_st_lcd(CNFG_PANEL, crtc->lcd_config_panel, par);
682 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
683 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
685 /* temporarily disable stretching */
686 aty_st_lcd(HORZ_STRETCHING,
687 crtc->horz_stretching &
688 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
689 aty_st_lcd(VERT_STRETCHING,
690 crtc->vert_stretching &
691 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
692 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
696 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
698 DPRINTK("setting up CRTC\n");
699 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
700 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
701 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
702 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
704 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
705 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
706 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
707 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
708 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
709 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
710 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
712 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
713 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
714 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
715 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
716 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
717 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
719 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
722 if (par->accel_flags & FB_ACCELF_TEXT)
723 aty_init_engine(par, info);
725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
726 /* after setting the CRTC registers we should set the LCD registers. */
727 if (par->lcd_table != 0) {
728 /* switch to shadow registers */
729 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
730 (SHADOW_EN | SHADOW_RW_EN), par);
732 DPRINTK("set shadow CRT to %ix%i %c%c\n",
733 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
734 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
736 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
737 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
738 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
739 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
741 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
742 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
743 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
744 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
746 /* restore CRTC selection & shadow state and enable stretching */
747 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
748 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
749 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
750 if(!M64_HAS(LT_LCD_REGS))
751 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
753 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
754 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
755 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
756 if(!M64_HAS(LT_LCD_REGS)) {
757 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
758 aty_ld_le32(LCD_INDEX, par);
759 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
765 static int aty_var_to_crtc(const struct fb_info *info,
766 const struct fb_var_screeninfo *var, struct crtc *crtc)
768 struct atyfb_par *par = (struct atyfb_par *) info->par;
769 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
770 u32 sync, vmode, vdisplay;
771 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
772 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
773 u32 pix_width, dp_pix_width, dp_chain_mask;
778 vxres = var->xres_virtual;
779 vyres = var->yres_virtual;
780 xoffset = var->xoffset;
781 yoffset = var->yoffset;
782 bpp = var->bits_per_pixel;
784 bpp = (var->green.length == 5) ? 15 : 16;
788 /* convert (and round up) and validate */
789 if (vxres < xres + xoffset)
790 vxres = xres + xoffset;
793 if (vyres < yres + yoffset)
794 vyres = yres + yoffset;
799 pix_width = CRTC_PIX_WIDTH_8BPP;
801 HOST_8BPP | SRC_8BPP | DST_8BPP |
802 BYTE_ORDER_LSB_TO_MSB;
803 dp_chain_mask = DP_CHAIN_8BPP;
804 } else if (bpp <= 15) {
806 pix_width = CRTC_PIX_WIDTH_15BPP;
807 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
808 BYTE_ORDER_LSB_TO_MSB;
809 dp_chain_mask = DP_CHAIN_15BPP;
810 } else if (bpp <= 16) {
812 pix_width = CRTC_PIX_WIDTH_16BPP;
813 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
814 BYTE_ORDER_LSB_TO_MSB;
815 dp_chain_mask = DP_CHAIN_16BPP;
816 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
818 pix_width = CRTC_PIX_WIDTH_24BPP;
820 HOST_8BPP | SRC_8BPP | DST_8BPP |
821 BYTE_ORDER_LSB_TO_MSB;
822 dp_chain_mask = DP_CHAIN_24BPP;
823 } else if (bpp <= 32) {
825 pix_width = CRTC_PIX_WIDTH_32BPP;
826 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
827 BYTE_ORDER_LSB_TO_MSB;
828 dp_chain_mask = DP_CHAIN_32BPP;
832 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
833 FAIL("not enough video RAM");
835 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
836 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
838 if((xres > 1600) || (yres > 1200)) {
839 FAIL("MACH64 chips are designed for max 1600x1200\n"
840 "select anoter resolution.");
842 h_sync_strt = h_disp + var->right_margin;
843 h_sync_end = h_sync_strt + var->hsync_len;
844 h_sync_dly = var->right_margin & 7;
845 h_total = h_sync_end + h_sync_dly + var->left_margin;
847 v_sync_strt = v_disp + var->lower_margin;
848 v_sync_end = v_sync_strt + var->vsync_len;
849 v_total = v_sync_end + var->upper_margin;
851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
852 if (par->lcd_table != 0) {
853 if(!M64_HAS(LT_LCD_REGS)) {
854 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
855 crtc->lcd_index = lcd_index &
856 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
857 aty_st_le32(LCD_INDEX, lcd_index, par);
860 if (!M64_HAS(MOBIL_BUS))
861 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
863 crtc->lcd_config_panel = aty_ld_lcd(CNFG_PANEL, par) | 0x4000;
864 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
866 crtc->lcd_gen_cntl &=
867 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
868 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
869 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
870 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
872 if((crtc->lcd_gen_cntl & LCD_ON) &&
873 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
874 /* We cannot display the mode on the LCD. If the CRT is enabled
875 we can turn off the LCD.
876 If the CRT is off, it isn't a good idea to switch it on; we don't
877 know if one is connected. So it's better to fail then.
879 if (crtc->lcd_gen_cntl & CRT_ON) {
880 if (!(var->activate & FB_ACTIVATE_TEST))
881 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
882 crtc->lcd_gen_cntl &= ~LCD_ON;
883 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
885 if (!(var->activate & FB_ACTIVATE_TEST))
886 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
892 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
894 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
895 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
896 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
898 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
900 /* This is horror! When we simulate, say 640x480 on an 800x600
901 LCD monitor, the CRTC should be programmed 800x600 values for
902 the non visible part, but 640x480 for the visible part.
903 This code has been tested on a laptop with it's 1400x1050 LCD
904 monitor and a conventional monitor both switched on.
905 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
906 works with little glitches also with DOUBLESCAN modes
908 if (yres < par->lcd_height) {
909 VScan = par->lcd_height / yres;
912 vmode |= FB_VMODE_DOUBLE;
916 h_sync_strt = h_disp + par->lcd_right_margin;
917 h_sync_end = h_sync_strt + par->lcd_hsync_len;
918 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
919 h_total = h_disp + par->lcd_hblank_len;
921 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
922 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
923 v_total = v_disp + par->lcd_vblank_len / VScan;
925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
927 h_disp = (h_disp >> 3) - 1;
928 h_sync_strt = (h_sync_strt >> 3) - 1;
929 h_sync_end = (h_sync_end >> 3) - 1;
930 h_total = (h_total >> 3) - 1;
931 h_sync_wid = h_sync_end - h_sync_strt;
933 FAIL_MAX("h_disp too large", h_disp, 0xff);
934 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
935 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
936 if(h_sync_wid > 0x1f)
938 FAIL_MAX("h_total too large", h_total, 0x1ff);
940 if (vmode & FB_VMODE_DOUBLE) {
948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
949 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
950 vdisplay = par->lcd_height;
957 v_sync_wid = v_sync_end - v_sync_strt;
959 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
960 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
961 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
962 if(v_sync_wid > 0x1f)
964 FAIL_MAX("v_total too large", v_total, 0x7ff);
966 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
971 crtc->xoffset = xoffset;
972 crtc->yoffset = yoffset;
974 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
975 crtc->vline_crnt_vline = 0;
977 crtc->h_tot_disp = h_total | (h_disp<<16);
978 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
979 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
980 crtc->v_tot_disp = v_total | (v_disp<<16);
981 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
983 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
984 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
985 crtc->gen_cntl |= CRTC_VGA_LINEAR;
987 /* Enable doublescan mode if requested */
988 if (vmode & FB_VMODE_DOUBLE)
989 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
990 /* Enable interlaced mode if requested */
991 if (vmode & FB_VMODE_INTERLACED)
992 crtc->gen_cntl |= CRTC_INTERLACE_EN;
993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
994 if (par->lcd_table != 0) {
996 if(vmode & FB_VMODE_DOUBLE)
998 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
999 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1004 /* MOBILITY M1 tested, FIXME: LT */
1005 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006 if (!M64_HAS(LT_LCD_REGS))
1007 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1010 crtc->horz_stretching &=
1011 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1016 * The horizontal blender misbehaves when HDisplay is less than a
1017 * a certain threshold (440 for a 1024-wide panel). It doesn't
1018 * stretch such modes enough. Use pixel replication instead of
1019 * blending to stretch modes that can be made to exactly fit the
1020 * panel width. The undocumented "NoLCDBlend" option allows the
1021 * pixel-replicated mode to be slightly wider or narrower than the
1022 * panel width. It also causes a mode that is exactly half as wide
1023 * as the panel to be pixel-replicated, rather than blended.
1025 int HDisplay = xres & ~7;
1026 int nStretch = par->lcd_width / HDisplay;
1027 int Remainder = par->lcd_width % HDisplay;
1029 if ((!Remainder && ((nStretch > 2))) ||
1030 (((HDisplay * 16) / par->lcd_width) < 7)) {
1031 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032 int horz_stretch_loop = -1, BestRemainder;
1033 int Numerator = HDisplay, Denominator = par->lcd_width;
1035 ATIReduceRatio(&Numerator, &Denominator);
1037 BestRemainder = (Numerator * 16) / Denominator;
1038 while (--Index >= 0) {
1039 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1041 if (Remainder < BestRemainder) {
1042 horz_stretch_loop = Index;
1043 if (!(BestRemainder = Remainder))
1048 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049 int horz_stretch_ratio = 0, Accumulator = 0;
1050 int reuse_previous = 1;
1052 Index = StretchLoops[horz_stretch_loop];
1054 while (--Index >= 0) {
1055 if (Accumulator > 0)
1056 horz_stretch_ratio |= reuse_previous;
1058 Accumulator += Denominator;
1059 Accumulator -= Numerator;
1060 reuse_previous <<= 1;
1063 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066 break; /* Out of the do { ... } while (0) */
1070 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1075 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1079 if (!M64_HAS(LT_LCD_REGS) &&
1080 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1084 * Don't use vertical blending if the mode is too wide or not
1085 * vertically stretched.
1087 crtc->vert_stretching = 0;
1089 /* copy to shadow crtc */
1090 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1097 if (M64_HAS(MAGIC_FIFO)) {
1098 /* FIXME: display FIFO low watermark values */
1099 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1101 crtc->dp_pix_width = dp_pix_width;
1102 crtc->dp_chain_mask = dp_chain_mask;
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1109 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1112 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1114 u32 double_scan, interlace;
1117 h_total = crtc->h_tot_disp & 0x1ff;
1118 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123 v_total = crtc->v_tot_disp & 0x7ff;
1124 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1134 xres = (h_disp + 1) * 8;
1136 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138 hslen = h_sync_wid * 8;
1139 upper = v_total - v_sync_strt - v_sync_wid;
1140 lower = v_sync_strt - v_disp;
1142 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1146 switch (pix_width) {
1148 case CRTC_PIX_WIDTH_4BPP:
1150 var->red.offset = 0;
1151 var->red.length = 8;
1152 var->green.offset = 0;
1153 var->green.length = 8;
1154 var->blue.offset = 0;
1155 var->blue.length = 8;
1156 var->transp.offset = 0;
1157 var->transp.length = 0;
1160 case CRTC_PIX_WIDTH_8BPP:
1162 var->red.offset = 0;
1163 var->red.length = 8;
1164 var->green.offset = 0;
1165 var->green.length = 8;
1166 var->blue.offset = 0;
1167 var->blue.length = 8;
1168 var->transp.offset = 0;
1169 var->transp.length = 0;
1171 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1173 var->red.offset = 10;
1174 var->red.length = 5;
1175 var->green.offset = 5;
1176 var->green.length = 5;
1177 var->blue.offset = 0;
1178 var->blue.length = 5;
1179 var->transp.offset = 0;
1180 var->transp.length = 0;
1182 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1184 var->red.offset = 11;
1185 var->red.length = 5;
1186 var->green.offset = 5;
1187 var->green.length = 6;
1188 var->blue.offset = 0;
1189 var->blue.length = 5;
1190 var->transp.offset = 0;
1191 var->transp.length = 0;
1193 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1195 var->red.offset = 16;
1196 var->red.length = 8;
1197 var->green.offset = 8;
1198 var->green.length = 8;
1199 var->blue.offset = 0;
1200 var->blue.length = 8;
1201 var->transp.offset = 0;
1202 var->transp.length = 0;
1204 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1206 var->red.offset = 16;
1207 var->red.length = 8;
1208 var->green.offset = 8;
1209 var->green.length = 8;
1210 var->blue.offset = 0;
1211 var->blue.length = 8;
1212 var->transp.offset = 24;
1213 var->transp.length = 8;
1216 PRINTKE("Invalid pixel width\n");
1223 var->xres_virtual = crtc->vxres;
1224 var->yres_virtual = crtc->vyres;
1225 var->bits_per_pixel = bpp;
1226 var->left_margin = left;
1227 var->right_margin = right;
1228 var->upper_margin = upper;
1229 var->lower_margin = lower;
1230 var->hsync_len = hslen;
1231 var->vsync_len = vslen;
1233 var->vmode = FB_VMODE_NONINTERLACED;
1234 /* In double scan mode, the vertical parameters are doubled, so we need to
1235 half them to get the right values.
1236 In interlaced mode the values are already correct, so no correction is
1240 var->vmode = FB_VMODE_INTERLACED;
1243 var->vmode = FB_VMODE_DOUBLE;
1245 var->upper_margin>>=1;
1246 var->lower_margin>>=1;
1253 /* ------------------------------------------------------------------------- */
1255 static int atyfb_set_par(struct fb_info *info)
1257 struct atyfb_par *par = (struct atyfb_par *) info->par;
1258 struct fb_var_screeninfo *var = &info->var;
1262 struct fb_var_screeninfo debug;
1268 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1271 pixclock = atyfb_get_pixclock(var, par);
1273 if (pixclock == 0) {
1274 PRINTKE("Invalid pixclock\n");
1277 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1281 par->accel_flags = var->accel_flags; /* hack */
1283 if (var->accel_flags) {
1284 info->fbops->fb_sync = atyfb_sync;
1285 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1287 info->fbops->fb_sync = NULL;
1288 info->flags |= FBINFO_HWACCEL_DISABLED;
1291 if (par->blitter_may_be_busy)
1294 aty_set_crtc(par, &par->crtc);
1295 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1296 par->pll_ops->set_pll(info, &par->pll);
1299 if(par->pll_ops && par->pll_ops->pll_to_var)
1300 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1304 if(0 == pixclock_in_ps) {
1305 PRINTKE("ALERT ops->pll_to_var get 0\n");
1306 pixclock_in_ps = pixclock;
1309 memset(&debug, 0, sizeof(debug));
1310 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1311 u32 hSync, vRefresh;
1312 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1313 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1315 h_disp = debug.xres;
1316 h_sync_strt = h_disp + debug.right_margin;
1317 h_sync_end = h_sync_strt + debug.hsync_len;
1318 h_total = h_sync_end + debug.left_margin;
1319 v_disp = debug.yres;
1320 v_sync_strt = v_disp + debug.lower_margin;
1321 v_sync_end = v_sync_strt + debug.vsync_len;
1322 v_total = v_sync_end + debug.upper_margin;
1324 hSync = 1000000000 / (pixclock_in_ps * h_total);
1325 vRefresh = (hSync * 1000) / v_total;
1326 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1328 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1331 DPRINTK("atyfb_set_par\n");
1332 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1333 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1334 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1335 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1336 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1337 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1338 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1339 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1340 h_disp, h_sync_strt, h_sync_end, h_total,
1341 v_disp, v_sync_strt, v_sync_end, v_total);
1342 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1344 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1345 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1349 if (!M64_HAS(INTEGRATED)) {
1350 /* Don't forget MEM_CNTL */
1351 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1352 switch (var->bits_per_pixel) {
1363 aty_st_le32(MEM_CNTL, tmp, par);
1365 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1366 if (!M64_HAS(MAGIC_POSTDIV))
1367 tmp |= par->mem_refresh_rate << 20;
1368 switch (var->bits_per_pixel) {
1380 if (M64_HAS(CT_BUS)) {
1381 aty_st_le32(DAC_CNTL, 0x87010184, par);
1382 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1383 } else if (M64_HAS(VT_BUS)) {
1384 aty_st_le32(DAC_CNTL, 0x87010184, par);
1385 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1386 } else if (M64_HAS(MOBIL_BUS)) {
1387 aty_st_le32(DAC_CNTL, 0x80010102, par);
1388 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1391 aty_st_le32(DAC_CNTL, 0x86010102, par);
1392 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1393 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1395 aty_st_le32(MEM_CNTL, tmp, par);
1397 aty_st_8(DAC_MASK, 0xff, par);
1399 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1400 info->fix.visual = var->bits_per_pixel <= 8 ?
1401 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1403 /* Initialize the graphics engine */
1404 if (par->accel_flags & FB_ACCELF_TEXT)
1405 aty_init_engine(par, info);
1407 #ifdef CONFIG_BOOTX_TEXT
1408 btext_update_display(info->fix.smem_start,
1409 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1410 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1411 var->bits_per_pixel,
1412 par->crtc.vxres * var->bits_per_pixel / 8);
1413 #endif /* CONFIG_BOOTX_TEXT */
1415 /* switch to accelerator mode */
1416 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1417 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1421 /* dump non shadow CRTC, pll, LCD registers */
1424 /* CRTC registers */
1426 printk("debug atyfb: Mach64 non-shadow register values:");
1427 for (i = 0; i < 256; i = i+4) {
1428 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1429 printk(" %08X", aty_ld_le32(i, par));
1433 #ifdef CONFIG_FB_ATY_CT
1436 printk("debug atyfb: Mach64 PLL register values:");
1437 for (i = 0; i < 64; i++) {
1438 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1439 if(i%4 == 0) printk(" ");
1440 printk("%02X", aty_ld_pll_ct(i, par));
1443 #endif /* CONFIG_FB_ATY_CT */
1445 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1446 if (par->lcd_table != 0) {
1449 printk("debug atyfb: LCD register values:");
1450 if(M64_HAS(LT_LCD_REGS)) {
1451 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1452 if(i == EXT_VERT_STRETCH)
1454 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1455 printk(" %08X", aty_ld_lcd(i, par));
1459 for (i = 0; i < 64; i++) {
1460 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1461 printk(" %08X", aty_ld_lcd(i, par));
1466 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1472 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1474 struct atyfb_par *par = (struct atyfb_par *) info->par;
1480 memcpy(&pll, &(par->pll), sizeof(pll));
1482 if((err = aty_var_to_crtc(info, var, &crtc)))
1485 pixclock = atyfb_get_pixclock(var, par);
1487 if (pixclock == 0) {
1488 if (!(var->activate & FB_ACTIVATE_TEST))
1489 PRINTKE("Invalid pixclock\n");
1492 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1496 if (var->accel_flags & FB_ACCELF_TEXT)
1497 info->var.accel_flags = FB_ACCELF_TEXT;
1499 info->var.accel_flags = 0;
1501 aty_crtc_to_var(&crtc, var);
1502 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1506 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1508 u32 xoffset = info->var.xoffset;
1509 u32 yoffset = info->var.yoffset;
1510 u32 vxres = par->crtc.vxres;
1511 u32 bpp = info->var.bits_per_pixel;
1513 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1518 * Open/Release the frame buffer device
1521 static int atyfb_open(struct fb_info *info, int user)
1523 struct atyfb_par *par = (struct atyfb_par *) info->par;
1534 static irqreturn_t aty_irq(int irq, void *dev_id)
1536 struct atyfb_par *par = dev_id;
1540 spin_lock(&par->int_lock);
1542 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1544 if (int_cntl & CRTC_VBLANK_INT) {
1545 /* clear interrupt */
1546 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1547 par->vblank.count++;
1548 if (par->vblank.pan_display) {
1549 par->vblank.pan_display = 0;
1550 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1552 wake_up_interruptible(&par->vblank.wait);
1556 spin_unlock(&par->int_lock);
1558 return IRQ_RETVAL(handled);
1561 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1565 if (!test_and_set_bit(0, &par->irq_flags)) {
1566 if (request_irq(par->irq, aty_irq, IRQF_SHARED, "atyfb", par)) {
1567 clear_bit(0, &par->irq_flags);
1570 spin_lock_irq(&par->int_lock);
1571 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1572 /* clear interrupt */
1573 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1574 /* enable interrupt */
1575 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1576 spin_unlock_irq(&par->int_lock);
1577 } else if (reenable) {
1578 spin_lock_irq(&par->int_lock);
1579 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1580 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1581 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1582 /* re-enable interrupt */
1583 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1585 spin_unlock_irq(&par->int_lock);
1591 static int aty_disable_irq(struct atyfb_par *par)
1595 if (test_and_clear_bit(0, &par->irq_flags)) {
1596 if (par->vblank.pan_display) {
1597 par->vblank.pan_display = 0;
1598 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1600 spin_lock_irq(&par->int_lock);
1601 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1602 /* disable interrupt */
1603 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1604 spin_unlock_irq(&par->int_lock);
1605 free_irq(par->irq, par);
1611 static int atyfb_release(struct fb_info *info, int user)
1613 struct atyfb_par *par = (struct atyfb_par *) info->par;
1620 int was_mmaped = par->mmaped;
1625 struct fb_var_screeninfo var;
1627 /* Now reset the default display config, we have no
1628 * idea what the program(s) which mmap'd the chip did
1629 * to the configuration, nor whether it restored it
1634 var.accel_flags &= ~FB_ACCELF_TEXT;
1636 var.accel_flags |= FB_ACCELF_TEXT;
1637 if (var.yres == var.yres_virtual) {
1638 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1639 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1640 if (var.yres_virtual < var.yres)
1641 var.yres_virtual = var.yres;
1645 aty_disable_irq(par);
1652 * Pan or Wrap the Display
1654 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1657 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1659 struct atyfb_par *par = (struct atyfb_par *) info->par;
1660 u32 xres, yres, xoffset, yoffset;
1662 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1663 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1664 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1666 xoffset = (var->xoffset + 7) & ~7;
1667 yoffset = var->yoffset;
1668 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1670 info->var.xoffset = xoffset;
1671 info->var.yoffset = yoffset;
1675 set_off_pitch(par, info);
1676 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1677 par->vblank.pan_display = 1;
1679 par->vblank.pan_display = 0;
1680 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1686 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1688 struct aty_interrupt *vbl;
1700 ret = aty_enable_irq(par, 0);
1705 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1710 aty_enable_irq(par, 1);
1719 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1720 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1726 u8 mclk_post_div; /* 1,2,3,4,8 */
1727 u8 mclk_fb_mult; /* 2 or 4 */
1728 u8 xclk_post_div; /* 1,2,3,4,8 */
1730 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1731 u32 dsp_xclks_per_row; /* 0-16383 */
1732 u32 dsp_loop_latency; /* 0-15 */
1733 u32 dsp_precision; /* 0-7 */
1734 u32 dsp_on; /* 0-2047 */
1735 u32 dsp_off; /* 0-2047 */
1738 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1739 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1742 #ifndef FBIO_WAITFORVSYNC
1743 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1746 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1748 struct atyfb_par *par = (struct atyfb_par *) info->par;
1750 struct fbtype fbtyp;
1756 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1757 fbtyp.fb_width = par->crtc.vxres;
1758 fbtyp.fb_height = par->crtc.vyres;
1759 fbtyp.fb_depth = info->var.bits_per_pixel;
1760 fbtyp.fb_cmsize = info->cmap.len;
1761 fbtyp.fb_size = info->fix.smem_len;
1762 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1765 #endif /* __sparc__ */
1767 case FBIO_WAITFORVSYNC:
1771 if (get_user(crtc, (__u32 __user *) arg))
1774 return aty_waitforvblank(par, crtc);
1778 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1780 if (M64_HAS(INTEGRATED)) {
1782 union aty_pll *pll = &(par->pll);
1783 u32 dsp_config = pll->ct.dsp_config;
1784 u32 dsp_on_off = pll->ct.dsp_on_off;
1785 clk.ref_clk_per = par->ref_clk_per;
1786 clk.pll_ref_div = pll->ct.pll_ref_div;
1787 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1788 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1789 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1790 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1791 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1792 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1793 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1794 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1795 clk.dsp_precision = (dsp_config >> 20) & 7;
1796 clk.dsp_off = dsp_on_off & 0x7ff;
1797 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1798 if (copy_to_user((struct atyclk __user *) arg, &clk,
1805 if (M64_HAS(INTEGRATED)) {
1807 union aty_pll *pll = &(par->pll);
1808 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1810 par->ref_clk_per = clk.ref_clk_per;
1811 pll->ct.pll_ref_div = clk.pll_ref_div;
1812 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1813 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1814 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1815 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1816 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1817 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1818 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1819 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1820 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1821 /*aty_calc_pll_ct(info, &pll->ct);*/
1822 aty_set_pll_ct(info, pll);
1827 if (get_user(par->features, (u32 __user *) arg))
1831 if (put_user(par->features, (u32 __user *) arg))
1834 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1841 static int atyfb_sync(struct fb_info *info)
1843 struct atyfb_par *par = (struct atyfb_par *) info->par;
1845 if (par->blitter_may_be_busy)
1851 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1853 struct atyfb_par *par = (struct atyfb_par *) info->par;
1854 unsigned int size, page, map_size = 0;
1855 unsigned long map_offset = 0;
1862 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1865 off = vma->vm_pgoff << PAGE_SHIFT;
1866 size = vma->vm_end - vma->vm_start;
1868 /* To stop the swapper from even considering these pages. */
1869 vma->vm_flags |= (VM_IO | VM_RESERVED);
1871 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1872 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1873 off += 0x8000000000000000UL;
1875 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1877 /* Each page, see which map applies */
1878 for (page = 0; page < size;) {
1880 for (i = 0; par->mmap_map[i].size; i++) {
1881 unsigned long start = par->mmap_map[i].voff;
1882 unsigned long end = start + par->mmap_map[i].size;
1883 unsigned long offset = off + page;
1890 map_size = par->mmap_map[i].size - (offset - start);
1892 par->mmap_map[i].poff + (offset - start);
1899 if (page + map_size > size)
1900 map_size = size - page;
1902 pgprot_val(vma->vm_page_prot) &=
1903 ~(par->mmap_map[i].prot_mask);
1904 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1906 if (remap_pfn_range(vma, vma->vm_start + page,
1907 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1920 #endif /* __sparc__ */
1924 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1926 #ifdef CONFIG_PPC_PMAC
1927 /* Power management routines. Those are used for PowerBook sleep.
1929 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1934 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1935 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1936 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1937 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1943 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1944 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1946 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1948 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1949 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1952 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1954 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1956 if ((--timeout) == 0)
1958 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1962 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1963 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1966 pm |= (PWR_BLON | AUTO_PWR_UP);
1967 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1968 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1971 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1973 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1975 if ((--timeout) == 0)
1977 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
1981 return timeout ? 0 : -EIO;
1983 #endif /* CONFIG_PPC_PMAC */
1985 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
1987 struct fb_info *info = pci_get_drvdata(pdev);
1988 struct atyfb_par *par = (struct atyfb_par *) info->par;
1990 if (state.event == pdev->dev.power.power_state.event)
1993 acquire_console_sem();
1995 fb_set_suspend(info, 1);
1997 /* Idle & reset engine */
1999 aty_reset_engine(par);
2001 /* Blank display and LCD */
2002 atyfb_blank(FB_BLANK_POWERDOWN, info);
2005 par->lock_blank = 1;
2007 /* Because we may change PCI D state ourselves, we need to
2008 * first save the config space content so the core can
2009 * restore it properly on resume.
2011 pci_save_state(pdev);
2013 #ifdef CONFIG_PPC_PMAC
2014 /* Set chip to "suspend" mode */
2015 if (machine_is(powermac) && aty_power_mgmt(1, par)) {
2017 par->lock_blank = 0;
2018 atyfb_blank(FB_BLANK_UNBLANK, info);
2019 fb_set_suspend(info, 0);
2020 release_console_sem();
2024 pci_set_power_state(pdev, pci_choose_state(pdev, state));
2027 release_console_sem();
2029 pdev->dev.power.power_state = state;
2034 static void aty_resume_chip(struct fb_info *info)
2036 struct atyfb_par *par = info->par;
2038 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2040 if (par->pll_ops->resume_pll)
2041 par->pll_ops->resume_pll(info, &par->pll);
2044 aty_st_le32(BUS_CNTL,
2045 aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2048 static int atyfb_pci_resume(struct pci_dev *pdev)
2050 struct fb_info *info = pci_get_drvdata(pdev);
2051 struct atyfb_par *par = (struct atyfb_par *) info->par;
2053 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2056 acquire_console_sem();
2058 /* PCI state will have been restored by the core, so
2059 * we should be in D0 now with our config space fully
2063 #ifdef CONFIG_PPC_PMAC
2064 if (machine_is(powermac) &&
2065 pdev->dev.power.power_state.event == PM_EVENT_SUSPEND)
2066 aty_power_mgmt(0, par);
2069 aty_resume_chip(info);
2073 /* Restore display */
2074 atyfb_set_par(info);
2077 fb_set_suspend(info, 0);
2080 par->lock_blank = 0;
2081 atyfb_blank(FB_BLANK_UNBLANK, info);
2083 release_console_sem();
2085 pdev->dev.power.power_state = PMSG_ON;
2090 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2093 #ifdef CONFIG_FB_ATY_BACKLIGHT
2094 #define MAX_LEVEL 0xFF
2096 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2098 struct fb_info *info = pci_get_drvdata(par->pdev);
2101 /* Get and convert the value */
2102 /* No locking of bl_curve since we read a single value */
2103 atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2107 else if (atylevel > MAX_LEVEL)
2108 atylevel = MAX_LEVEL;
2113 static int aty_bl_update_status(struct backlight_device *bd)
2115 struct atyfb_par *par = bl_get_data(bd);
2116 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2119 if (bd->props.power != FB_BLANK_UNBLANK ||
2120 bd->props.fb_blank != FB_BLANK_UNBLANK)
2123 level = bd->props.brightness;
2125 reg |= (BLMOD_EN | BIASMOD_EN);
2127 reg &= ~BIAS_MOD_LEVEL_MASK;
2128 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2130 reg &= ~BIAS_MOD_LEVEL_MASK;
2131 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2133 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2138 static int aty_bl_get_brightness(struct backlight_device *bd)
2140 return bd->props.brightness;
2143 static struct backlight_ops aty_bl_data = {
2144 .get_brightness = aty_bl_get_brightness,
2145 .update_status = aty_bl_update_status,
2148 static void aty_bl_init(struct atyfb_par *par)
2150 struct fb_info *info = pci_get_drvdata(par->pdev);
2151 struct backlight_device *bd;
2154 #ifdef CONFIG_PMAC_BACKLIGHT
2155 if (!pmac_has_backlight_type("ati"))
2159 snprintf(name, sizeof(name), "atybl%d", info->node);
2161 bd = backlight_device_register(name, info->dev, par, &aty_bl_data);
2163 info->bl_dev = NULL;
2164 printk(KERN_WARNING "aty: Backlight registration failed\n");
2169 fb_bl_default_curve(info, 0,
2170 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2171 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2173 bd->props.max_brightness = FB_BACKLIGHT_LEVELS - 1;
2174 bd->props.brightness = bd->props.max_brightness;
2175 bd->props.power = FB_BLANK_UNBLANK;
2176 backlight_update_status(bd);
2178 printk("aty: Backlight initialized (%s)\n", name);
2186 static void aty_bl_exit(struct backlight_device *bd)
2188 backlight_device_unregister(bd);
2189 printk("aty: Backlight unloaded\n");
2192 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2194 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2196 const int ragepro_tbl[] = {
2197 44, 50, 55, 66, 75, 80, 100
2199 const int ragexl_tbl[] = {
2200 50, 66, 75, 83, 90, 95, 100, 105,
2201 110, 115, 120, 125, 133, 143, 166
2203 const int *refresh_tbl;
2206 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2207 refresh_tbl = ragexl_tbl;
2208 size = ARRAY_SIZE(ragexl_tbl);
2210 refresh_tbl = ragepro_tbl;
2211 size = ARRAY_SIZE(ragepro_tbl);
2214 for (i=0; i < size; i++) {
2215 if (xclk < refresh_tbl[i])
2218 par->mem_refresh_rate = i;
2225 static struct fb_info *fb_list = NULL;
2227 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2228 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2229 struct fb_var_screeninfo *var)
2233 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2235 var->xres = var->xres_virtual = par->lcd_hdisp;
2236 var->right_margin = par->lcd_right_margin;
2237 var->left_margin = par->lcd_hblank_len -
2238 (par->lcd_right_margin + par->lcd_hsync_dly +
2239 par->lcd_hsync_len);
2240 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2241 var->yres = var->yres_virtual = par->lcd_vdisp;
2242 var->lower_margin = par->lcd_lower_margin;
2243 var->upper_margin = par->lcd_vblank_len -
2244 (par->lcd_lower_margin + par->lcd_vsync_len);
2245 var->vsync_len = par->lcd_vsync_len;
2246 var->pixclock = par->lcd_pixclock;
2252 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2254 static int __devinit aty_init(struct fb_info *info)
2256 struct atyfb_par *par = (struct atyfb_par *) info->par;
2257 const char *ramname = NULL, *xtal;
2258 int gtb_memsize, has_var = 0;
2259 struct fb_var_screeninfo var;
2262 init_waitqueue_head(&par->vblank.wait);
2263 spin_lock_init(&par->int_lock);
2265 #ifdef CONFIG_FB_ATY_GX
2266 if (!M64_HAS(INTEGRATED)) {
2268 u8 dac_type, dac_subtype, clk_type;
2269 stat0 = aty_ld_le32(CNFG_STAT0, par);
2270 par->bus_type = (stat0 >> 0) & 0x07;
2271 par->ram_type = (stat0 >> 3) & 0x07;
2272 ramname = aty_gx_ram[par->ram_type];
2273 /* FIXME: clockchip/RAMDAC probing? */
2274 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2276 clk_type = CLK_ATI18818_1;
2277 dac_type = (stat0 >> 9) & 0x07;
2278 if (dac_type == 0x07)
2279 dac_subtype = DAC_ATT20C408;
2281 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2283 dac_type = DAC_IBMRGB514;
2284 dac_subtype = DAC_IBMRGB514;
2285 clk_type = CLK_IBMRGB514;
2287 switch (dac_subtype) {
2289 par->dac_ops = &aty_dac_ibm514;
2292 case DAC_ATI68860_B:
2293 case DAC_ATI68860_C:
2294 par->dac_ops = &aty_dac_ati68860b;
2298 par->dac_ops = &aty_dac_att21c498;
2302 PRINTKI("aty_init: DAC type not implemented yet!\n");
2303 par->dac_ops = &aty_dac_unsupported;
2308 case CLK_ATI18818_1:
2309 par->pll_ops = &aty_pll_ati18818_1;
2313 par->pll_ops = &aty_pll_ibm514;
2316 #if 0 /* dead code */
2318 par->pll_ops = &aty_pll_stg1703;
2321 par->pll_ops = &aty_pll_ch8398;
2324 par->pll_ops = &aty_pll_att20c408;
2328 PRINTKI("aty_init: CLK type not implemented yet!");
2329 par->pll_ops = &aty_pll_unsupported;
2333 #endif /* CONFIG_FB_ATY_GX */
2334 #ifdef CONFIG_FB_ATY_CT
2335 if (M64_HAS(INTEGRATED)) {
2336 par->dac_ops = &aty_dac_ct;
2337 par->pll_ops = &aty_pll_ct;
2338 par->bus_type = PCI;
2339 par->ram_type = (aty_ld_le32(CNFG_STAT0, par) & 0x07);
2340 ramname = aty_ct_ram[par->ram_type];
2341 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2342 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2343 par->pll_limits.mclk = 63;
2344 /* Mobility + 32bit memory interface need halved XCLK. */
2345 if (M64_HAS(MOBIL_BUS) && par->ram_type == SDRAM32)
2346 par->pll_limits.xclk = (par->pll_limits.xclk + 1) >> 1;
2349 #ifdef CONFIG_PPC_PMAC
2350 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2351 * and set the frequency manually. */
2352 if (machine_is_compatible("PowerBook2,1")) {
2353 par->pll_limits.mclk = 70;
2354 par->pll_limits.xclk = 53;
2358 /* Allow command line to override clocks. */
2360 par->pll_limits.pll_max = pll;
2362 par->pll_limits.mclk = mclk;
2364 par->pll_limits.xclk = xclk;
2366 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2367 par->pll_per = 1000000/par->pll_limits.pll_max;
2368 par->mclk_per = 1000000/par->pll_limits.mclk;
2369 par->xclk_per = 1000000/par->pll_limits.xclk;
2371 par->ref_clk_per = 1000000000000ULL / 14318180;
2374 #ifdef CONFIG_FB_ATY_CT
2375 if (M64_HAS(GTB_DSP)) {
2376 u8 pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par);
2380 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2381 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2386 if (diff2 < diff1) {
2387 par->ref_clk_per = 1000000000000ULL / 29498928;
2392 #endif /* CONFIG_FB_ATY_CT */
2394 /* save previous video mode */
2395 aty_get_crtc(par, &par->saved_crtc);
2396 if(par->pll_ops->get_pll)
2397 par->pll_ops->get_pll(info, &par->saved_pll);
2399 par->mem_cntl = aty_ld_le32(MEM_CNTL, par);
2400 gtb_memsize = M64_HAS(GTB_DSP);
2402 switch (par->mem_cntl & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2404 info->fix.smem_len = 0x80000;
2407 info->fix.smem_len = 0x100000;
2409 case MEM_SIZE_2M_GTB:
2410 info->fix.smem_len = 0x200000;
2412 case MEM_SIZE_4M_GTB:
2413 info->fix.smem_len = 0x400000;
2415 case MEM_SIZE_6M_GTB:
2416 info->fix.smem_len = 0x600000;
2418 case MEM_SIZE_8M_GTB:
2419 info->fix.smem_len = 0x800000;
2422 info->fix.smem_len = 0x80000;
2424 switch (par->mem_cntl & MEM_SIZE_ALIAS) {
2426 info->fix.smem_len = 0x80000;
2429 info->fix.smem_len = 0x100000;
2432 info->fix.smem_len = 0x200000;
2435 info->fix.smem_len = 0x400000;
2438 info->fix.smem_len = 0x600000;
2441 info->fix.smem_len = 0x800000;
2444 info->fix.smem_len = 0x80000;
2447 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2448 if (aty_ld_le32(CNFG_STAT1, par) & 0x40000000)
2449 info->fix.smem_len += 0x400000;
2453 info->fix.smem_len = vram * 1024;
2454 par->mem_cntl &= ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2455 if (info->fix.smem_len <= 0x80000)
2456 par->mem_cntl |= MEM_SIZE_512K;
2457 else if (info->fix.smem_len <= 0x100000)
2458 par->mem_cntl |= MEM_SIZE_1M;
2459 else if (info->fix.smem_len <= 0x200000)
2460 par->mem_cntl |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2461 else if (info->fix.smem_len <= 0x400000)
2462 par->mem_cntl |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2463 else if (info->fix.smem_len <= 0x600000)
2464 par->mem_cntl |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2466 par->mem_cntl |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2467 aty_st_le32(MEM_CNTL, par->mem_cntl, par);
2471 * Reg Block 0 (CT-compatible block) is at mmio_start
2472 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2475 info->fix.mmio_len = 0x400;
2476 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2477 } else if (M64_HAS(CT)) {
2478 info->fix.mmio_len = 0x400;
2479 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2480 } else if (M64_HAS(VT)) {
2481 info->fix.mmio_start -= 0x400;
2482 info->fix.mmio_len = 0x800;
2483 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2485 info->fix.mmio_start -= 0x400;
2486 info->fix.mmio_len = 0x800;
2487 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2490 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2491 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2492 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2493 par->pll_limits.mclk, par->pll_limits.xclk);
2495 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
2496 if (M64_HAS(INTEGRATED)) {
2498 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2499 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2500 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2502 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2503 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2504 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2505 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2506 for (i = 0; i < 40; i++)
2507 printk(" %02x", aty_ld_pll_ct(i, par));
2511 if(par->pll_ops->init_pll)
2512 par->pll_ops->init_pll(info, &par->pll);
2513 if (par->pll_ops->resume_pll)
2514 par->pll_ops->resume_pll(info, &par->pll);
2517 * Last page of 8 MB (4 MB on ISA) aperture is MMIO,
2518 * unless the auxiliary register aperture is used.
2521 if (!par->aux_start &&
2522 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2523 info->fix.smem_len -= GUI_RESERVE;
2526 * Disable register access through the linear aperture
2527 * if the auxiliary aperture is used so we can access
2528 * the full 8 MB of video RAM on 8 MB boards.
2531 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2534 par->mtrr_aper = -1;
2537 /* Cover the whole resource. */
2538 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2539 if (par->mtrr_aper >= 0 && !par->aux_start) {
2540 /* Make a hole for mmio. */
2541 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2542 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2543 if (par->mtrr_reg < 0) {
2544 mtrr_del(par->mtrr_aper, 0, 0);
2545 par->mtrr_aper = -1;
2551 info->fbops = &atyfb_ops;
2552 info->pseudo_palette = par->pseudo_palette;
2553 info->flags = FBINFO_DEFAULT |
2554 FBINFO_HWACCEL_IMAGEBLIT |
2555 FBINFO_HWACCEL_FILLRECT |
2556 FBINFO_HWACCEL_COPYAREA |
2557 FBINFO_HWACCEL_YPAN;
2559 #ifdef CONFIG_PMAC_BACKLIGHT
2560 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2561 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2562 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2563 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2566 if (M64_HAS(MOBIL_BUS) && backlight) {
2567 #ifdef CONFIG_FB_ATY_BACKLIGHT
2572 memset(&var, 0, sizeof(var));
2574 if (machine_is(powermac)) {
2576 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2577 * applies to all Mac video cards
2580 if (mac_find_mode(&var, info, mode, 8))
2583 if (default_vmode == VMODE_CHOOSE) {
2585 if (M64_HAS(G3_PB_1024x768))
2586 /* G3 PowerBook with 1024x768 LCD */
2587 default_vmode = VMODE_1024_768_60;
2588 else if (machine_is_compatible("iMac"))
2589 default_vmode = VMODE_1024_768_75;
2590 else if (machine_is_compatible
2592 /* iBook with 800x600 LCD */
2593 default_vmode = VMODE_800_600_60;
2595 default_vmode = VMODE_640_480_67;
2596 sense = read_aty_sense(par);
2597 PRINTKI("monitor sense=%x, mode %d\n",
2598 sense, mac_map_monitor_sense(sense));
2600 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2601 default_vmode = VMODE_640_480_60;
2602 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2603 default_cmode = CMODE_8;
2604 if (!mac_vmode_to_var(default_vmode, default_cmode,
2610 #endif /* !CONFIG_PPC */
2612 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2613 if (!atyfb_get_timings_from_lcd(par, &var))
2617 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2624 var.accel_flags &= ~FB_ACCELF_TEXT;
2626 var.accel_flags |= FB_ACCELF_TEXT;
2628 if (comp_sync != -1) {
2630 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2632 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2635 if (var.yres == var.yres_virtual) {
2636 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2637 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2638 if (var.yres_virtual < var.yres)
2639 var.yres_virtual = var.yres;
2642 ret = atyfb_check_var(&var, info);
2644 PRINTKE("can't set default video mode\n");
2648 #ifdef CONFIG_FB_ATY_CT
2649 if (!noaccel && M64_HAS(INTEGRATED))
2650 aty_init_cursor(info);
2651 #endif /* CONFIG_FB_ATY_CT */
2654 ret = fb_alloc_cmap(&info->cmap, 256, 0);
2658 ret = register_framebuffer(info);
2660 fb_dealloc_cmap(&info->cmap);
2666 PRINTKI("fb%d: %s frame buffer device on %s\n",
2667 info->node, info->fix.id, par->bus_type == ISA ? "ISA" : "PCI");
2671 /* restore video mode */
2672 aty_set_crtc(par, &par->saved_crtc);
2673 par->pll_ops->set_pll(info, &par->saved_pll);
2676 if (par->mtrr_reg >= 0) {
2677 mtrr_del(par->mtrr_reg, 0, 0);
2680 if (par->mtrr_aper >= 0) {
2681 mtrr_del(par->mtrr_aper, 0, 0);
2682 par->mtrr_aper = -1;
2689 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2692 unsigned long vmembase, size, guiregbase;
2694 PRINTKI("store_video_par() '%s' \n", video_str);
2696 if (!(p = strsep(&video_str, ";")) || !*p)
2697 goto mach64_invalid;
2698 vmembase = simple_strtoul(p, NULL, 0);
2699 if (!(p = strsep(&video_str, ";")) || !*p)
2700 goto mach64_invalid;
2701 size = simple_strtoul(p, NULL, 0);
2702 if (!(p = strsep(&video_str, ";")) || !*p)
2703 goto mach64_invalid;
2704 guiregbase = simple_strtoul(p, NULL, 0);
2706 phys_vmembase[m64_num] = vmembase;
2707 phys_size[m64_num] = size;
2708 phys_guiregbase[m64_num] = guiregbase;
2709 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2714 phys_vmembase[m64_num] = 0;
2717 #endif /* CONFIG_ATARI */
2720 * Blank the display.
2723 static int atyfb_blank(int blank, struct fb_info *info)
2725 struct atyfb_par *par = (struct atyfb_par *) info->par;
2728 if (par->lock_blank || par->asleep)
2731 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2732 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2733 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2734 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2736 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2740 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2741 gen_cntl &= ~0x400004c;
2743 case FB_BLANK_UNBLANK:
2745 case FB_BLANK_NORMAL:
2746 gen_cntl |= 0x4000040;
2748 case FB_BLANK_VSYNC_SUSPEND:
2749 gen_cntl |= 0x4000048;
2751 case FB_BLANK_HSYNC_SUSPEND:
2752 gen_cntl |= 0x4000044;
2754 case FB_BLANK_POWERDOWN:
2755 gen_cntl |= 0x400004c;
2758 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2760 #ifdef CONFIG_FB_ATY_GENERIC_LCD
2761 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2762 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2763 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2765 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2772 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2773 const struct atyfb_par *par)
2775 aty_st_8(DAC_W_INDEX, regno, par);
2776 aty_st_8(DAC_DATA, red, par);
2777 aty_st_8(DAC_DATA, green, par);
2778 aty_st_8(DAC_DATA, blue, par);
2782 * Set a single color register. The values supplied are already
2783 * rounded down to the hardware's capabilities (according to the
2784 * entries in the var structure). Return != 0 for invalid regno.
2785 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2788 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2789 u_int transp, struct fb_info *info)
2791 struct atyfb_par *par = (struct atyfb_par *) info->par;
2793 u32 *pal = info->pseudo_palette;
2795 depth = info->var.bits_per_pixel;
2797 depth = (info->var.green.length == 5) ? 15 : 16;
2803 (depth == 16 && regno > 63) ||
2804 (depth == 15 && regno > 31))
2811 par->palette[regno].red = red;
2812 par->palette[regno].green = green;
2813 par->palette[regno].blue = blue;
2818 pal[regno] = (regno << 10) | (regno << 5) | regno;
2821 pal[regno] = (regno << 11) | (regno << 5) | regno;
2824 pal[regno] = (regno << 16) | (regno << 8) | regno;
2827 i = (regno << 8) | regno;
2828 pal[regno] = (i << 16) | i;
2833 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2834 if (M64_HAS(EXTRA_BRIGHT))
2835 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2836 aty_st_8(DAC_CNTL, i, par);
2837 aty_st_8(DAC_MASK, 0xff, par);
2839 if (M64_HAS(INTEGRATED)) {
2842 aty_st_pal(regno << 3, red,
2843 par->palette[regno<<1].green,
2845 red = par->palette[regno>>1].red;
2846 blue = par->palette[regno>>1].blue;
2848 } else if (depth == 15) {
2850 for(i = 0; i < 8; i++) {
2851 aty_st_pal(regno + i, red, green, blue, par);
2855 aty_st_pal(regno, red, green, blue, par);
2864 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2865 struct fb_info *info, unsigned long addr)
2867 struct atyfb_par *par = info->par;
2868 struct device_node *dp;
2870 int node, len, i, j, ret;
2874 * Map memory-mapped registers.
2876 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2877 info->fix.mmio_start = addr + 0x7ffc00UL;
2880 * Map in big-endian aperture.
2882 info->screen_base = (char *) (addr + 0x800000UL);
2883 info->fix.smem_start = addr + 0x800000UL;
2886 * Figure mmap addresses from PCI config space.
2887 * Split Framebuffer in big- and little-endian halfs.
2889 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2893 par->mmap_map = kcalloc(j, sizeof(*par->mmap_map), GFP_ATOMIC);
2894 if (!par->mmap_map) {
2895 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2899 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2900 struct resource *rp = &pdev->resource[i];
2901 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2907 io = (rp->flags & IORESOURCE_IO);
2909 size = rp->end - base + 1;
2911 pci_read_config_dword(pdev, breg, &pbase);
2917 * Map the framebuffer a second time, this time without
2918 * the braindead _PAGE_IE setting. This is used by the
2919 * fixed Xserver, but we need to maintain the old mapping
2920 * to stay compatible with older ones...
2923 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2924 par->mmap_map[j].poff = base & PAGE_MASK;
2925 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2926 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2927 par->mmap_map[j].prot_flag = _PAGE_E;
2932 * Here comes the old framebuffer mapping with _PAGE_IE
2933 * set for the big endian half of the framebuffer...
2936 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2937 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2938 par->mmap_map[j].size = 0x800000;
2939 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2940 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2945 par->mmap_map[j].voff = pbase & PAGE_MASK;
2946 par->mmap_map[j].poff = base & PAGE_MASK;
2947 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2948 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2949 par->mmap_map[j].prot_flag = _PAGE_E;
2953 if((ret = correct_chipset(par)))
2956 if (IS_XL(pdev->device)) {
2958 * Fix PROMs idea of MEM_CNTL settings...
2960 mem = aty_ld_le32(MEM_CNTL, par);
2961 chip_id = aty_ld_le32(CNFG_CHIP_ID, par);
2962 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2963 switch (mem & 0x0f) {
2965 mem = (mem & ~(0x0f)) | 2;
2968 mem = (mem & ~(0x0f)) | 3;
2971 mem = (mem & ~(0x0f)) | 4;
2974 mem = (mem & ~(0x0f)) | 5;
2979 if ((aty_ld_le32(CNFG_STAT0, par) & 7) >= SDRAM)
2980 mem &= ~(0x00700000);
2982 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2983 aty_st_le32(MEM_CNTL, mem, par);
2987 * If this is the console device, we will set default video
2988 * settings to what the PROM left us with.
2990 node = prom_getchild(prom_root_node);
2991 node = prom_searchsiblings(node, "aliases");
2993 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2996 node = prom_finddevice(prop);
3001 dp = pci_device_to_OF_node(pdev);
3002 if (node == dp->node) {
3003 struct fb_var_screeninfo *var = &default_var;
3004 unsigned int N, P, Q, M, T, R;
3005 u32 v_total, h_total;
3010 crtc.vxres = prom_getintdefault(node, "width", 1024);
3011 crtc.vyres = prom_getintdefault(node, "height", 768);
3012 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3013 var->xoffset = var->yoffset = 0;
3014 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3015 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3016 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3017 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3018 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3019 aty_crtc_to_var(&crtc, var);
3021 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3022 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3025 * Read the PLL to figure actual Refresh Rate.
3027 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3028 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3029 for (i = 0; i < 16; i++)
3030 pll_regs[i] = aty_ld_pll_ct(i, par);
3033 * PLL Reference Divider M:
3038 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3040 N = pll_regs[7 + (clock_cntl & 3)];
3043 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3045 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3059 * where R is XTALIN (= 14318 or 29498 kHz).
3061 if (IS_XL(pdev->device))
3068 default_var.pixclock = 1000000000 / T;
3074 #else /* __sparc__ */
3077 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3078 static void __devinit aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3080 u32 driv_inf_tab, sig;
3083 /* To support an LCD panel, we should know it's dimensions and
3084 * it's desired pixel clock.
3085 * There are two ways to do it:
3086 * - Check the startup video mode and calculate the panel
3087 * size from it. This is unreliable.
3088 * - Read it from the driver information table in the video BIOS.
3090 /* Address of driver information table is at offset 0x78. */
3091 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3093 /* Check for the driver information table signature. */
3094 sig = (*(u32 *)driv_inf_tab);
3095 if ((sig == 0x54504c24) || /* Rage LT pro */
3096 (sig == 0x544d5224) || /* Rage mobility */
3097 (sig == 0x54435824) || /* Rage XC */
3098 (sig == 0x544c5824)) { /* Rage XL */
3099 PRINTKI("BIOS contains driver information table.\n");
3100 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3103 par->lcd_table = bios_base + lcd_ofs;
3107 if (par->lcd_table != 0) {
3110 char refresh_rates_buf[100];
3111 int id, tech, f, i, m, default_refresh_rate;
3116 u16 width, height, panel_type, refresh_rates;
3119 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3120 /* The most important information is the panel size at
3121 * offset 25 and 27, but there's some other nice information
3122 * which we print to the screen.
3124 id = *(u8 *)par->lcd_table;
3125 strncpy(model,(char *)par->lcd_table+1,24);
3128 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3129 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3130 panel_type = *(u16 *)(par->lcd_table+29);
3132 txtcolour = "colour";
3134 txtcolour = "monochrome";
3136 txtdual = "dual (split) ";
3139 tech = (panel_type>>2) & 63;
3142 txtmonitor = "passive matrix";
3145 txtmonitor = "active matrix";
3148 txtmonitor = "active addressed STN";
3154 txtmonitor = "plasma";
3157 txtmonitor = "unknown";
3159 format = *(u32 *)(par->lcd_table+57);
3160 if (tech == 0 || tech == 2) {
3161 switch (format & 7) {
3163 txtformat = "12 bit interface";
3166 txtformat = "16 bit interface";
3169 txtformat = "24 bit interface";
3172 txtformat = "unkown format";
3175 switch (format & 7) {
3177 txtformat = "8 colours";
3180 txtformat = "512 colours";
3183 txtformat = "4096 colours";
3186 txtformat = "262144 colours (LT mode)";
3189 txtformat = "16777216 colours";
3192 txtformat = "262144 colours (FDPI-2 mode)";
3195 txtformat = "unkown format";
3198 PRINTKI("%s%s %s monitor detected: %s\n",
3199 txtdual ,txtcolour, txtmonitor, model);
3200 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3201 id, width, height, txtformat);
3202 refresh_rates_buf[0] = 0;
3203 refresh_rates = *(u16 *)(par->lcd_table+62);
3206 for (i=0;i<16;i++) {
3207 if (refresh_rates & m) {
3209 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3212 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3214 strcat(refresh_rates_buf,strbuf);
3218 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3219 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3220 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3221 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3222 /* We now need to determine the crtc parameters for the
3223 * LCD monitor. This is tricky, because they are not stored
3224 * individually in the BIOS. Instead, the BIOS contains a
3225 * table of display modes that work for this monitor.
3227 * The idea is that we search for a mode of the same dimensions
3228 * as the dimensions of the LCD monitor. Say our LCD monitor
3229 * is 800x600 pixels, we search for a 800x600 monitor.
3230 * The CRTC parameters we find here are the ones that we need
3231 * to use to simulate other resolutions on the LCD screen.
3233 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3234 while (*lcdmodeptr != 0) {
3236 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3237 modeptr = bios_base + *lcdmodeptr;
3239 mwidth = *((u16 *)(modeptr+0));
3240 mheight = *((u16 *)(modeptr+2));
3242 if (mwidth == width && mheight == height) {
3243 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3244 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3245 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3246 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3247 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3248 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3250 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3251 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3252 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3253 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3255 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3256 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3257 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3258 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3264 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3265 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3266 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3267 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3273 if (*lcdmodeptr == 0) {
3274 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3275 /* To do: Switch to CRT if possible. */
3277 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3278 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3280 par->lcd_hdisp + par->lcd_right_margin,
3281 par->lcd_hdisp + par->lcd_right_margin
3282 + par->lcd_hsync_dly + par->lcd_hsync_len,
3285 par->lcd_vdisp + par->lcd_lower_margin,
3286 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3288 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3290 par->lcd_hblank_len - (par->lcd_right_margin +
3291 par->lcd_hsync_dly + par->lcd_hsync_len),
3293 par->lcd_right_margin,
3295 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3297 par->lcd_lower_margin,
3298 par->lcd_vsync_len);
3302 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3304 static int __devinit init_from_bios(struct atyfb_par *par)
3306 u32 bios_base, rom_addr;
3309 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3310 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3312 /* The BIOS starts with 0xaa55. */
3313 if (*((u16 *)bios_base) == 0xaa55) {
3316 u16 rom_table_offset, freq_table_offset;
3317 PLL_BLOCK_MACH64 pll_block;
3319 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3321 /* check for frequncy table */
3322 bios_ptr = (u8*)bios_base;
3323 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3324 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3325 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3327 PRINTKI("BIOS frequency table:\n");
3328 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3329 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3330 pll_block.ref_freq, pll_block.ref_divider);
3331 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3332 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3333 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3335 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3336 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3337 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3338 par->pll_limits.ref_div = pll_block.ref_divider;
3339 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3340 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3341 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3342 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3343 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3344 aty_init_lcd(par, bios_base);
3348 PRINTKE("no BIOS frequency table found, use parameters\n");
3351 iounmap((void __iomem *)bios_base);
3355 #endif /* __i386__ */
3357 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3359 struct atyfb_par *par = info->par;
3361 unsigned long raddr;
3362 struct resource *rrp;
3365 raddr = addr + 0x7ff000UL;
3366 rrp = &pdev->resource[2];
3367 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3368 par->aux_start = rrp->start;
3369 par->aux_size = rrp->end - rrp->start + 1;
3371 PRINTKI("using auxiliary register aperture\n");
3374 info->fix.mmio_start = raddr;
3375 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3376 if (par->ati_regbase == NULL)
3379 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3380 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3383 * Enable memory-space accesses using config-space
3386 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3387 if (!(tmp & PCI_COMMAND_MEMORY)) {
3388 tmp |= PCI_COMMAND_MEMORY;
3389 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3392 /* Use the big-endian aperture */
3396 /* Map in frame buffer */
3397 info->fix.smem_start = addr;
3398 info->screen_base = ioremap(addr, 0x800000);
3399 if (info->screen_base == NULL) {
3401 goto atyfb_setup_generic_fail;
3404 if((ret = correct_chipset(par)))
3405 goto atyfb_setup_generic_fail;
3407 if((ret = init_from_bios(par)))
3408 goto atyfb_setup_generic_fail;
3410 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3411 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3413 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3415 /* according to ATI, we should use clock 3 for acelerated mode */
3416 par->clk_wr_offset = 3;
3420 atyfb_setup_generic_fail:
3421 iounmap(par->ati_regbase);
3422 par->ati_regbase = NULL;
3423 if (info->screen_base) {
3424 iounmap(info->screen_base);
3425 info->screen_base = NULL;
3430 #endif /* !__sparc__ */
3432 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3434 unsigned long addr, res_start, res_size;
3435 struct fb_info *info;
3436 struct resource *rp;
3437 struct atyfb_par *par;
3440 /* Enable device in PCI config */
3441 if (pci_enable_device(pdev)) {
3442 PRINTKE("Cannot enable PCI device\n");
3446 /* Find which resource to use */
3447 rp = &pdev->resource[0];
3448 if (rp->flags & IORESOURCE_IO)
3449 rp = &pdev->resource[1];
3455 res_start = rp->start;
3456 res_size = rp->end - rp->start + 1;
3457 if (!request_mem_region (res_start, res_size, "atyfb"))
3460 /* Allocate framebuffer */
3461 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3463 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3467 info->fix = atyfb_fix;
3468 info->device = &pdev->dev;
3469 par->pci_id = pdev->device;
3470 par->res_start = res_start;
3471 par->res_size = res_size;
3472 par->irq = pdev->irq;
3475 /* Setup "info" structure */
3477 rc = atyfb_setup_sparc(pdev, info, addr);
3479 rc = atyfb_setup_generic(pdev, info, addr);
3482 goto err_release_mem;
3484 pci_set_drvdata(pdev, info);
3486 /* Init chip & register framebuffer */
3487 rc = aty_init(info);
3489 goto err_release_io;
3493 * Add /dev/fb mmap values.
3495 par->mmap_map[0].voff = 0x8000000000000000UL;
3496 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3497 par->mmap_map[0].size = info->fix.smem_len;
3498 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3499 par->mmap_map[0].prot_flag = _PAGE_E;
3500 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3501 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3502 par->mmap_map[1].size = PAGE_SIZE;
3503 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3504 par->mmap_map[1].prot_flag = _PAGE_E;
3505 #endif /* __sparc__ */
3507 mutex_lock(&reboot_lock);
3510 mutex_unlock(&reboot_lock);
3516 kfree(par->mmap_map);
3518 if (par->ati_regbase)
3519 iounmap(par->ati_regbase);
3520 if (info->screen_base)
3521 iounmap(info->screen_base);
3525 release_mem_region(par->aux_start, par->aux_size);
3527 release_mem_region(par->res_start, par->res_size);
3528 framebuffer_release(info);
3533 #endif /* CONFIG_PCI */
3537 static int __init atyfb_atari_probe(void)
3539 struct atyfb_par *par;
3540 struct fb_info *info;
3545 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3546 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3547 !phys_guiregbase[m64_num]) {
3548 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3552 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3554 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3559 info->fix = atyfb_fix;
3561 par->irq = (unsigned int) -1; /* something invalid */
3564 * Map the video memory (physical address given) to somewhere in the
3565 * kernel address space.
3567 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3568 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3569 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3571 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3573 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3574 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3576 switch (clock_r & 0x003F) {
3578 par->clk_wr_offset = 3; /* */
3581 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3584 par->clk_wr_offset = 1; /* */
3587 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3591 /* Fake pci_id for correct_chipset() */
3592 switch (aty_ld_le32(CNFG_CHIP_ID, par) & CFG_CHIP_TYPE) {
3594 par->pci_id = PCI_CHIP_MACH64GX;
3597 par->pci_id = PCI_CHIP_MACH64CX;
3603 if (correct_chipset(par) || aty_init(info)) {
3604 iounmap(info->screen_base);
3605 iounmap(par->ati_regbase);
3606 framebuffer_release(info);
3612 return num_found ? 0 : -ENXIO;
3615 #endif /* CONFIG_ATARI */
3619 static void __devexit atyfb_remove(struct fb_info *info)
3621 struct atyfb_par *par = (struct atyfb_par *) info->par;
3623 /* restore video mode */
3624 aty_set_crtc(par, &par->saved_crtc);
3625 par->pll_ops->set_pll(info, &par->saved_pll);
3627 unregister_framebuffer(info);
3629 #ifdef CONFIG_FB_ATY_BACKLIGHT
3630 if (M64_HAS(MOBIL_BUS))
3631 aty_bl_exit(info->bl_dev);
3635 if (par->mtrr_reg >= 0) {
3636 mtrr_del(par->mtrr_reg, 0, 0);
3639 if (par->mtrr_aper >= 0) {
3640 mtrr_del(par->mtrr_aper, 0, 0);
3641 par->mtrr_aper = -1;
3645 if (par->ati_regbase)
3646 iounmap(par->ati_regbase);
3647 if (info->screen_base)
3648 iounmap(info->screen_base);
3650 if (info->sprite.addr)
3651 iounmap(info->sprite.addr);
3655 kfree(par->mmap_map);
3658 release_mem_region(par->aux_start, par->aux_size);
3661 release_mem_region(par->res_start, par->res_size);
3663 framebuffer_release(info);
3667 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3669 struct fb_info *info = pci_get_drvdata(pdev);
3671 mutex_lock(&reboot_lock);
3672 if (reboot_info == info)
3674 mutex_unlock(&reboot_lock);
3679 static struct pci_device_id atyfb_pci_tbl[] = {
3680 #ifdef CONFIG_FB_ATY_GX
3681 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GX) },
3682 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CX) },
3683 #endif /* CONFIG_FB_ATY_GX */
3685 #ifdef CONFIG_FB_ATY_CT
3686 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64CT) },
3687 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64ET) },
3689 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LT) },
3691 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VT) },
3692 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GT) },
3694 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VU) },
3695 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GU) },
3697 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LG) },
3699 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64VV) },
3701 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GV) },
3702 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GW) },
3703 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GY) },
3704 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GZ) },
3706 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GB) },
3707 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GD) },
3708 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GI) },
3709 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GP) },
3710 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GQ) },
3712 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LB) },
3713 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LD) },
3714 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LI) },
3715 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LP) },
3716 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LQ) },
3718 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GM) },
3719 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GN) },
3720 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GO) },
3721 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GL) },
3722 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GR) },
3723 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64GS) },
3725 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LM) },
3726 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LN) },
3727 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LR) },
3728 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_CHIP_MACH64LS) },
3729 #endif /* CONFIG_FB_ATY_CT */
3733 MODULE_DEVICE_TABLE(pci, atyfb_pci_tbl);
3735 static struct pci_driver atyfb_driver = {
3737 .id_table = atyfb_pci_tbl,
3738 .probe = atyfb_pci_probe,
3739 .remove = __devexit_p(atyfb_pci_remove),
3741 .suspend = atyfb_pci_suspend,
3742 .resume = atyfb_pci_resume,
3743 #endif /* CONFIG_PM */
3746 #endif /* CONFIG_PCI */
3749 static int __init atyfb_setup(char *options)
3753 if (!options || !*options)
3756 while ((this_opt = strsep(&options, ",")) != NULL) {
3757 if (!strncmp(this_opt, "noaccel", 7)) {
3760 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3763 } else if (!strncmp(this_opt, "vram:", 5))
3764 vram = simple_strtoul(this_opt + 5, NULL, 0);
3765 else if (!strncmp(this_opt, "pll:", 4))
3766 pll = simple_strtoul(this_opt + 4, NULL, 0);
3767 else if (!strncmp(this_opt, "mclk:", 5))
3768 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3769 else if (!strncmp(this_opt, "xclk:", 5))
3770 xclk = simple_strtoul(this_opt+5, NULL, 0);
3771 else if (!strncmp(this_opt, "comp_sync:", 10))
3772 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3773 else if (!strncmp(this_opt, "backlight:", 10))
3774 backlight = simple_strtoul(this_opt+10, NULL, 0);
3776 else if (!strncmp(this_opt, "vmode:", 6)) {
3777 unsigned int vmode =
3778 simple_strtoul(this_opt + 6, NULL, 0);
3779 if (vmode > 0 && vmode <= VMODE_MAX)
3780 default_vmode = vmode;
3781 } else if (!strncmp(this_opt, "cmode:", 6)) {
3782 unsigned int cmode =
3783 simple_strtoul(this_opt + 6, NULL, 0);
3787 default_cmode = CMODE_8;
3791 default_cmode = CMODE_16;
3795 default_cmode = CMODE_32;
3802 * Why do we need this silly Mach64 argument?
3803 * We are already here because of mach64= so its redundant.
3805 else if (MACH_IS_ATARI
3806 && (!strncmp(this_opt, "Mach64:", 7))) {
3807 static unsigned char m64_num;
3808 static char mach64_str[80];
3809 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3810 if (!store_video_par(mach64_str, m64_num)) {
3812 mach64_count = m64_num;
3823 static int atyfb_reboot_notify(struct notifier_block *nb,
3824 unsigned long code, void *unused)
3826 struct atyfb_par *par;
3828 if (code != SYS_RESTART)
3831 mutex_lock(&reboot_lock);
3836 if (!lock_fb_info(reboot_info))
3839 par = reboot_info->par;
3842 * HP OmniBook 500's BIOS doesn't like the state of the
3843 * hardware after atyfb has been used. Restore the hardware
3844 * to the original state to allow successful reboots.
3846 aty_set_crtc(par, &par->saved_crtc);
3847 par->pll_ops->set_pll(reboot_info, &par->saved_pll);
3849 unlock_fb_info(reboot_info);
3851 mutex_unlock(&reboot_lock);
3856 static struct notifier_block atyfb_reboot_notifier = {
3857 .notifier_call = atyfb_reboot_notify,
3860 static const struct dmi_system_id atyfb_reboot_ids[] = {
3862 .ident = "HP OmniBook 500",
3864 DMI_MATCH(DMI_SYS_VENDOR, "Hewlett-Packard"),
3865 DMI_MATCH(DMI_PRODUCT_NAME, "HP OmniBook PC"),
3866 DMI_MATCH(DMI_PRODUCT_VERSION, "HP OmniBook 500 FA"),
3873 static int __init atyfb_init(void)
3875 int err1 = 1, err2 = 1;
3877 char *option = NULL;
3879 if (fb_get_options("atyfb", &option))
3881 atyfb_setup(option);
3885 err1 = pci_register_driver(&atyfb_driver);
3888 err2 = atyfb_atari_probe();
3894 if (dmi_check_system(atyfb_reboot_ids))
3895 register_reboot_notifier(&atyfb_reboot_notifier);
3900 static void __exit atyfb_exit(void)
3902 if (dmi_check_system(atyfb_reboot_ids))
3903 unregister_reboot_notifier(&atyfb_reboot_notifier);
3906 pci_unregister_driver(&atyfb_driver);
3910 module_init(atyfb_init);
3911 module_exit(atyfb_exit);
3913 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3914 MODULE_LICENSE("GPL");
3915 module_param(noaccel, bool, 0);
3916 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3917 module_param(vram, int, 0);
3918 MODULE_PARM_DESC(vram, "int: override size of video ram");
3919 module_param(pll, int, 0);
3920 MODULE_PARM_DESC(pll, "int: override video clock");
3921 module_param(mclk, int, 0);
3922 MODULE_PARM_DESC(mclk, "int: override memory clock");
3923 module_param(xclk, int, 0);
3924 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3925 module_param(comp_sync, int, 0);
3926 MODULE_PARM_DESC(comp_sync,
3927 "Set composite sync signal to low (0) or high (1)");
3928 module_param(mode, charp, 0);
3929 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3931 module_param(nomtrr, bool, 0);
3932 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob