2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
78 #include <asm/machdep.h>
80 #include "../macmodes.h"
88 #include <linux/adb.h>
89 #include <linux/pmu.h>
91 #ifdef CONFIG_BOOTX_TEXT
92 #include <asm/btext.h>
94 #ifdef CONFIG_PMAC_BACKLIGHT
95 #include <asm/backlight.h>
107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
108 /* - must be large enough to catch all GUI-Regs */
109 /* - must be aligned to a PAGE boundary */
110 #define GUI_RESERVE (1 * PAGE_SIZE)
112 /* FIXME: remove the FAIL definition */
113 #define FAIL(msg) do { \
114 if (!(var->activate & FB_ACTIVATE_TEST)) \
115 printk(KERN_CRIT "atyfb: " msg "\n"); \
118 #define FAIL_MAX(msg, x, _max_) do { \
120 if (!(var->activate & FB_ACTIVATE_TEST)) \
121 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
126 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
128 #define DPRINTK(fmt, args...)
131 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
132 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
135 static const u32 lt_lcd_regs[] = {
142 0, /* EXT_VERT_STRETCH */
147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
149 if (M64_HAS(LT_LCD_REGS)) {
150 aty_st_le32(lt_lcd_regs[index], val, par);
154 /* write addr byte */
155 temp = aty_ld_le32(LCD_INDEX, par);
156 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
157 /* write the register value */
158 aty_st_le32(LCD_DATA, val, par);
162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
164 if (M64_HAS(LT_LCD_REGS)) {
165 return aty_ld_le32(lt_lcd_regs[index], par);
169 /* write addr byte */
170 temp = aty_ld_le32(LCD_INDEX, par);
171 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
172 /* read the register value */
173 return aty_ld_le32(LCD_DATA, par);
176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
182 * Reduce a fraction by factoring out the largest common divider of the
183 * fraction's numerator and denominator.
185 static void ATIReduceRatio(int *Numerator, int *Denominator)
187 int Multiplier, Divider, Remainder;
189 Multiplier = *Numerator;
190 Divider = *Denominator;
192 while ((Remainder = Multiplier % Divider))
194 Multiplier = Divider;
198 *Numerator /= Divider;
199 *Denominator /= Divider;
203 * The Hardware parameters for each card
206 struct aty_cmap_regs {
214 struct pci_mmap_map {
218 unsigned long prot_flag;
219 unsigned long prot_mask;
222 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
224 .type = FB_TYPE_PACKED_PIXELS,
225 .visual = FB_VISUAL_PSEUDOCOLOR,
231 * Frame buffer device API
234 static int atyfb_open(struct fb_info *info, int user);
235 static int atyfb_release(struct fb_info *info, int user);
236 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
237 static int atyfb_set_par(struct fb_info *info);
238 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
239 u_int transp, struct fb_info *info);
240 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
241 static int atyfb_blank(int blank, struct fb_info *info);
242 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
249 static int atyfb_sync(struct fb_info *info);
255 static int aty_init(struct fb_info *info, const char *name);
257 static int store_video_par(char *videopar, unsigned char m64_num);
260 static struct crtc saved_crtc;
261 static union aty_pll saved_pll;
262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269 static int read_aty_sense(const struct atyfb_par *par);
274 * Interface used by the world
277 static struct fb_var_screeninfo default_var = {
278 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
279 640, 480, 640, 480, 0, 0, 8, 0,
280 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
281 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
282 0, FB_VMODE_NONINTERLACED
285 static struct fb_videomode defmode = {
286 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
287 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
288 0, FB_VMODE_NONINTERLACED
291 static struct fb_ops atyfb_ops = {
292 .owner = THIS_MODULE,
293 .fb_open = atyfb_open,
294 .fb_release = atyfb_release,
295 .fb_check_var = atyfb_check_var,
296 .fb_set_par = atyfb_set_par,
297 .fb_setcolreg = atyfb_setcolreg,
298 .fb_pan_display = atyfb_pan_display,
299 .fb_blank = atyfb_blank,
300 .fb_ioctl = atyfb_ioctl,
301 .fb_fillrect = atyfb_fillrect,
302 .fb_copyarea = atyfb_copyarea,
303 .fb_imageblit = atyfb_imageblit,
305 .fb_mmap = atyfb_mmap,
307 .fb_sync = atyfb_sync,
318 static int comp_sync __initdata = -1;
322 static int default_vmode __initdata = VMODE_CHOOSE;
323 static int default_cmode __initdata = CMODE_CHOOSE;
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
332 static unsigned int mach64_count __initdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX (M64F_GX)
340 #define ATI_CHIP_88800CX (M64F_GX)
342 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352 /* FIXME what is this chip? */
353 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
355 /* make sets shorter */
356 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
358 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
359 /*#define ATI_CHIP_264GTDVD ?*/
360 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
362 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
363 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
364 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
366 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
367 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
372 int pll, mclk, xclk, ecp_max;
374 } aty_chips[] __devinitdata = {
375 #ifdef CONFIG_FB_ATY_GX
377 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
378 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
379 #endif /* CONFIG_FB_ATY_GX */
381 #ifdef CONFIG_FB_ATY_CT
382 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
383 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
385 /* FIXME what is this chip? */
386 { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
388 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
389 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
391 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
392 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
394 { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
396 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
398 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
403 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
406 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
407 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
409 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
410 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
412 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
413 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
415 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
416 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
418 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
420 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
422 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
425 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
426 #endif /* CONFIG_FB_ATY_CT */
430 static int __devinit correct_chipset(struct atyfb_par *par)
438 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
439 if (par->pci_id == aty_chips[i].pci_id)
442 name = aty_chips[i].name;
443 par->pll_limits.pll_max = aty_chips[i].pll;
444 par->pll_limits.mclk = aty_chips[i].mclk;
445 par->pll_limits.xclk = aty_chips[i].xclk;
446 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
447 par->features = aty_chips[i].features;
449 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
450 type = chip_id & CFG_CHIP_TYPE;
451 rev = (chip_id & CFG_CHIP_REV) >> 24;
453 switch(par->pci_id) {
454 #ifdef CONFIG_FB_ATY_GX
455 case PCI_CHIP_MACH64GX:
459 case PCI_CHIP_MACH64CX:
464 #ifdef CONFIG_FB_ATY_CT
465 case PCI_CHIP_MACH64VT:
466 switch (rev & 0x07) {
468 switch (rev & 0xc0) {
470 name = "ATI264VT (A3) (Mach64 VT)";
471 par->pll_limits.pll_max = 170;
472 par->pll_limits.mclk = 67;
473 par->pll_limits.xclk = 67;
474 par->pll_limits.ecp_max = 80;
475 par->features = ATI_CHIP_264VT;
478 name = "ATI264VT2 (A4) (Mach64 VT)";
479 par->pll_limits.pll_max = 200;
480 par->pll_limits.mclk = 67;
481 par->pll_limits.xclk = 67;
482 par->pll_limits.ecp_max = 80;
483 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
488 name = "ATI264VT3 (B1) (Mach64 VT)";
489 par->pll_limits.pll_max = 200;
490 par->pll_limits.mclk = 67;
491 par->pll_limits.xclk = 67;
492 par->pll_limits.ecp_max = 80;
493 par->features = ATI_CHIP_264VTB;
496 name = "ATI264VT3 (B2) (Mach64 VT)";
497 par->pll_limits.pll_max = 200;
498 par->pll_limits.mclk = 67;
499 par->pll_limits.xclk = 67;
500 par->pll_limits.ecp_max = 80;
501 par->features = ATI_CHIP_264VT3;
505 case PCI_CHIP_MACH64GT:
506 switch (rev & 0x07) {
508 name = "3D RAGE II (Mach64 GT)";
509 par->pll_limits.pll_max = 170;
510 par->pll_limits.mclk = 67;
511 par->pll_limits.xclk = 67;
512 par->pll_limits.ecp_max = 80;
513 par->features = ATI_CHIP_264GTB;
516 name = "3D RAGE II+ (Mach64 GT)";
517 par->pll_limits.pll_max = 200;
518 par->pll_limits.mclk = 67;
519 par->pll_limits.xclk = 67;
520 par->pll_limits.ecp_max = 100;
521 par->features = ATI_CHIP_264GTB;
528 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
532 static char ram_dram[] __devinitdata = "DRAM";
533 static char ram_resv[] __devinitdata = "RESV";
534 #ifdef CONFIG_FB_ATY_GX
535 static char ram_vram[] __devinitdata = "VRAM";
536 #endif /* CONFIG_FB_ATY_GX */
537 #ifdef CONFIG_FB_ATY_CT
538 static char ram_edo[] __devinitdata = "EDO";
539 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
540 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
541 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
542 static char ram_off[] __devinitdata = "OFF";
543 #endif /* CONFIG_FB_ATY_CT */
546 static u32 pseudo_palette[17];
548 #ifdef CONFIG_FB_ATY_GX
549 static char *aty_gx_ram[8] __devinitdata = {
550 ram_dram, ram_vram, ram_vram, ram_dram,
551 ram_dram, ram_vram, ram_vram, ram_resv
553 #endif /* CONFIG_FB_ATY_GX */
555 #ifdef CONFIG_FB_ATY_CT
556 static char *aty_ct_ram[8] __devinitdata = {
557 ram_off, ram_dram, ram_edo, ram_edo,
558 ram_sdram, ram_sgram, ram_sdram32, ram_resv
560 #endif /* CONFIG_FB_ATY_CT */
562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
564 u32 pixclock = var->pixclock;
565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
567 par->pll.ct.xres = 0;
568 if (par->lcd_table != 0) {
569 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
570 if(lcd_on_off & LCD_ON) {
571 par->pll.ct.xres = var->xres;
572 pixclock = par->lcd_pixclock;
579 #if defined(CONFIG_PPC)
582 * Apple monitor sense
585 static int __init read_aty_sense(const struct atyfb_par *par)
589 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
591 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
593 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
594 sense = ((i & 0x3000) >> 3) | (i & 0x100);
596 /* drive each sense line low in turn and collect the other 2 */
597 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
599 i = aty_ld_le32(GP_IO, par);
600 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
601 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
604 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
606 i = aty_ld_le32(GP_IO, par);
607 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
608 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
611 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
613 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
614 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
618 #endif /* defined(CONFIG_PPC) */
620 /* ------------------------------------------------------------------------- */
626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
629 if (par->lcd_table != 0) {
630 if(!M64_HAS(LT_LCD_REGS)) {
631 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
632 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
634 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
635 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
638 /* switch to non shadow registers */
639 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
640 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
642 /* save stretching */
643 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
644 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
645 if (!M64_HAS(LT_LCD_REGS))
646 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
649 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
650 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
651 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
652 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
653 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
654 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
655 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
658 if (par->lcd_table != 0) {
659 /* switch to shadow registers */
660 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
661 SHADOW_EN | SHADOW_RW_EN, par);
663 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
664 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
665 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
666 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
668 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
676 if (par->lcd_table != 0) {
678 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
680 /* update non-shadow registers first */
681 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
682 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
683 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
685 /* temporarily disable stretching */
686 aty_st_lcd(HORZ_STRETCHING,
687 crtc->horz_stretching &
688 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
689 aty_st_lcd(VERT_STRETCHING,
690 crtc->vert_stretching &
691 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
692 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
696 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
698 DPRINTK("setting up CRTC\n");
699 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
700 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
701 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
702 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
704 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
705 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
706 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
707 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
708 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
709 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
710 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
712 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
713 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
714 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
715 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
716 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
717 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
719 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
722 if (par->accel_flags & FB_ACCELF_TEXT)
723 aty_init_engine(par, info);
725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
726 /* after setting the CRTC registers we should set the LCD registers. */
727 if (par->lcd_table != 0) {
728 /* switch to shadow registers */
729 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
730 (SHADOW_EN | SHADOW_RW_EN), par);
732 DPRINTK("set shadow CRT to %ix%i %c%c\n",
733 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
734 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
736 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
737 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
738 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
739 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
741 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
742 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
743 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
744 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
746 /* restore CRTC selection & shadow state and enable stretching */
747 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
748 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
749 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
750 if(!M64_HAS(LT_LCD_REGS))
751 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
753 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
754 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
755 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
756 if(!M64_HAS(LT_LCD_REGS)) {
757 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
758 aty_ld_le32(LCD_INDEX, par);
759 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
765 static int aty_var_to_crtc(const struct fb_info *info,
766 const struct fb_var_screeninfo *var, struct crtc *crtc)
768 struct atyfb_par *par = (struct atyfb_par *) info->par;
769 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
770 u32 sync, vmode, vdisplay;
771 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
772 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
773 u32 pix_width, dp_pix_width, dp_chain_mask;
778 vxres = var->xres_virtual;
779 vyres = var->yres_virtual;
780 xoffset = var->xoffset;
781 yoffset = var->yoffset;
782 bpp = var->bits_per_pixel;
784 bpp = (var->green.length == 5) ? 15 : 16;
788 /* convert (and round up) and validate */
789 if (vxres < xres + xoffset)
790 vxres = xres + xoffset;
793 if (vyres < yres + yoffset)
794 vyres = yres + yoffset;
799 pix_width = CRTC_PIX_WIDTH_8BPP;
801 HOST_8BPP | SRC_8BPP | DST_8BPP |
802 BYTE_ORDER_LSB_TO_MSB;
803 dp_chain_mask = DP_CHAIN_8BPP;
804 } else if (bpp <= 15) {
806 pix_width = CRTC_PIX_WIDTH_15BPP;
807 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
808 BYTE_ORDER_LSB_TO_MSB;
809 dp_chain_mask = DP_CHAIN_15BPP;
810 } else if (bpp <= 16) {
812 pix_width = CRTC_PIX_WIDTH_16BPP;
813 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
814 BYTE_ORDER_LSB_TO_MSB;
815 dp_chain_mask = DP_CHAIN_16BPP;
816 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
818 pix_width = CRTC_PIX_WIDTH_24BPP;
820 HOST_8BPP | SRC_8BPP | DST_8BPP |
821 BYTE_ORDER_LSB_TO_MSB;
822 dp_chain_mask = DP_CHAIN_24BPP;
823 } else if (bpp <= 32) {
825 pix_width = CRTC_PIX_WIDTH_32BPP;
826 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
827 BYTE_ORDER_LSB_TO_MSB;
828 dp_chain_mask = DP_CHAIN_32BPP;
832 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
833 FAIL("not enough video RAM");
835 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
836 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
838 if((xres > 1600) || (yres > 1200)) {
839 FAIL("MACH64 chips are designed for max 1600x1200\n"
840 "select anoter resolution.");
842 h_sync_strt = h_disp + var->right_margin;
843 h_sync_end = h_sync_strt + var->hsync_len;
844 h_sync_dly = var->right_margin & 7;
845 h_total = h_sync_end + h_sync_dly + var->left_margin;
847 v_sync_strt = v_disp + var->lower_margin;
848 v_sync_end = v_sync_strt + var->vsync_len;
849 v_total = v_sync_end + var->upper_margin;
851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
852 if (par->lcd_table != 0) {
853 if(!M64_HAS(LT_LCD_REGS)) {
854 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
855 crtc->lcd_index = lcd_index &
856 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
857 aty_st_le32(LCD_INDEX, lcd_index, par);
860 if (!M64_HAS(MOBIL_BUS))
861 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
863 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
864 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
866 crtc->lcd_gen_cntl &=
867 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
868 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
869 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
870 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
872 if((crtc->lcd_gen_cntl & LCD_ON) &&
873 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
874 /* We cannot display the mode on the LCD. If the CRT is enabled
875 we can turn off the LCD.
876 If the CRT is off, it isn't a good idea to switch it on; we don't
877 know if one is connected. So it's better to fail then.
879 if (crtc->lcd_gen_cntl & CRT_ON) {
880 if (!(var->activate & FB_ACTIVATE_TEST))
881 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
882 crtc->lcd_gen_cntl &= ~LCD_ON;
883 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
885 if (!(var->activate & FB_ACTIVATE_TEST))
886 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
892 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
894 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
895 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
896 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
898 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
900 /* This is horror! When we simulate, say 640x480 on an 800x600
901 LCD monitor, the CRTC should be programmed 800x600 values for
902 the non visible part, but 640x480 for the visible part.
903 This code has been tested on a laptop with it's 1400x1050 LCD
904 monitor and a conventional monitor both switched on.
905 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
906 works with little glitches also with DOUBLESCAN modes
908 if (yres < par->lcd_height) {
909 VScan = par->lcd_height / yres;
912 vmode |= FB_VMODE_DOUBLE;
916 h_sync_strt = h_disp + par->lcd_right_margin;
917 h_sync_end = h_sync_strt + par->lcd_hsync_len;
918 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
919 h_total = h_disp + par->lcd_hblank_len;
921 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
922 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
923 v_total = v_disp + par->lcd_vblank_len / VScan;
925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
927 h_disp = (h_disp >> 3) - 1;
928 h_sync_strt = (h_sync_strt >> 3) - 1;
929 h_sync_end = (h_sync_end >> 3) - 1;
930 h_total = (h_total >> 3) - 1;
931 h_sync_wid = h_sync_end - h_sync_strt;
933 FAIL_MAX("h_disp too large", h_disp, 0xff);
934 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
935 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
936 if(h_sync_wid > 0x1f)
938 FAIL_MAX("h_total too large", h_total, 0x1ff);
940 if (vmode & FB_VMODE_DOUBLE) {
948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
949 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
950 vdisplay = par->lcd_height;
957 v_sync_wid = v_sync_end - v_sync_strt;
959 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
960 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
961 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
962 if(v_sync_wid > 0x1f)
964 FAIL_MAX("v_total too large", v_total, 0x7ff);
966 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
971 crtc->xoffset = xoffset;
972 crtc->yoffset = yoffset;
974 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
975 crtc->vline_crnt_vline = 0;
977 crtc->h_tot_disp = h_total | (h_disp<<16);
978 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
979 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
980 crtc->v_tot_disp = v_total | (v_disp<<16);
981 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
983 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
984 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
985 crtc->gen_cntl |= CRTC_VGA_LINEAR;
987 /* Enable doublescan mode if requested */
988 if (vmode & FB_VMODE_DOUBLE)
989 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
990 /* Enable interlaced mode if requested */
991 if (vmode & FB_VMODE_INTERLACED)
992 crtc->gen_cntl |= CRTC_INTERLACE_EN;
993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
994 if (par->lcd_table != 0) {
996 if(vmode & FB_VMODE_DOUBLE)
998 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
999 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1004 /* MOBILITY M1 tested, FIXME: LT */
1005 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006 if (!M64_HAS(LT_LCD_REGS))
1007 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1010 crtc->horz_stretching &=
1011 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1016 * The horizontal blender misbehaves when HDisplay is less than a
1017 * a certain threshold (440 for a 1024-wide panel). It doesn't
1018 * stretch such modes enough. Use pixel replication instead of
1019 * blending to stretch modes that can be made to exactly fit the
1020 * panel width. The undocumented "NoLCDBlend" option allows the
1021 * pixel-replicated mode to be slightly wider or narrower than the
1022 * panel width. It also causes a mode that is exactly half as wide
1023 * as the panel to be pixel-replicated, rather than blended.
1025 int HDisplay = xres & ~7;
1026 int nStretch = par->lcd_width / HDisplay;
1027 int Remainder = par->lcd_width % HDisplay;
1029 if ((!Remainder && ((nStretch > 2))) ||
1030 (((HDisplay * 16) / par->lcd_width) < 7)) {
1031 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032 int horz_stretch_loop = -1, BestRemainder;
1033 int Numerator = HDisplay, Denominator = par->lcd_width;
1035 ATIReduceRatio(&Numerator, &Denominator);
1037 BestRemainder = (Numerator * 16) / Denominator;
1038 while (--Index >= 0) {
1039 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1041 if (Remainder < BestRemainder) {
1042 horz_stretch_loop = Index;
1043 if (!(BestRemainder = Remainder))
1048 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049 int horz_stretch_ratio = 0, Accumulator = 0;
1050 int reuse_previous = 1;
1052 Index = StretchLoops[horz_stretch_loop];
1054 while (--Index >= 0) {
1055 if (Accumulator > 0)
1056 horz_stretch_ratio |= reuse_previous;
1058 Accumulator += Denominator;
1059 Accumulator -= Numerator;
1060 reuse_previous <<= 1;
1063 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066 break; /* Out of the do { ... } while (0) */
1070 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1075 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1079 if (!M64_HAS(LT_LCD_REGS) &&
1080 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1084 * Don't use vertical blending if the mode is too wide or not
1085 * vertically stretched.
1087 crtc->vert_stretching = 0;
1089 /* copy to shadow crtc */
1090 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1097 if (M64_HAS(MAGIC_FIFO)) {
1098 /* FIXME: display FIFO low watermark values */
1099 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1101 crtc->dp_pix_width = dp_pix_width;
1102 crtc->dp_chain_mask = dp_chain_mask;
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1109 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1112 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1114 u32 double_scan, interlace;
1117 h_total = crtc->h_tot_disp & 0x1ff;
1118 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123 v_total = crtc->v_tot_disp & 0x7ff;
1124 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1134 xres = (h_disp + 1) * 8;
1136 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138 hslen = h_sync_wid * 8;
1139 upper = v_total - v_sync_strt - v_sync_wid;
1140 lower = v_sync_strt - v_disp;
1142 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1146 switch (pix_width) {
1148 case CRTC_PIX_WIDTH_4BPP:
1150 var->red.offset = 0;
1151 var->red.length = 8;
1152 var->green.offset = 0;
1153 var->green.length = 8;
1154 var->blue.offset = 0;
1155 var->blue.length = 8;
1156 var->transp.offset = 0;
1157 var->transp.length = 0;
1160 case CRTC_PIX_WIDTH_8BPP:
1162 var->red.offset = 0;
1163 var->red.length = 8;
1164 var->green.offset = 0;
1165 var->green.length = 8;
1166 var->blue.offset = 0;
1167 var->blue.length = 8;
1168 var->transp.offset = 0;
1169 var->transp.length = 0;
1171 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1173 var->red.offset = 10;
1174 var->red.length = 5;
1175 var->green.offset = 5;
1176 var->green.length = 5;
1177 var->blue.offset = 0;
1178 var->blue.length = 5;
1179 var->transp.offset = 0;
1180 var->transp.length = 0;
1182 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1184 var->red.offset = 11;
1185 var->red.length = 5;
1186 var->green.offset = 5;
1187 var->green.length = 6;
1188 var->blue.offset = 0;
1189 var->blue.length = 5;
1190 var->transp.offset = 0;
1191 var->transp.length = 0;
1193 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1195 var->red.offset = 16;
1196 var->red.length = 8;
1197 var->green.offset = 8;
1198 var->green.length = 8;
1199 var->blue.offset = 0;
1200 var->blue.length = 8;
1201 var->transp.offset = 0;
1202 var->transp.length = 0;
1204 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1206 var->red.offset = 16;
1207 var->red.length = 8;
1208 var->green.offset = 8;
1209 var->green.length = 8;
1210 var->blue.offset = 0;
1211 var->blue.length = 8;
1212 var->transp.offset = 24;
1213 var->transp.length = 8;
1216 PRINTKE("Invalid pixel width\n");
1223 var->xres_virtual = crtc->vxres;
1224 var->yres_virtual = crtc->vyres;
1225 var->bits_per_pixel = bpp;
1226 var->left_margin = left;
1227 var->right_margin = right;
1228 var->upper_margin = upper;
1229 var->lower_margin = lower;
1230 var->hsync_len = hslen;
1231 var->vsync_len = vslen;
1233 var->vmode = FB_VMODE_NONINTERLACED;
1234 /* In double scan mode, the vertical parameters are doubled, so we need to
1235 half them to get the right values.
1236 In interlaced mode the values are already correct, so no correction is
1240 var->vmode = FB_VMODE_INTERLACED;
1243 var->vmode = FB_VMODE_DOUBLE;
1245 var->upper_margin>>=1;
1246 var->lower_margin>>=1;
1253 /* ------------------------------------------------------------------------- */
1255 static int atyfb_set_par(struct fb_info *info)
1257 struct atyfb_par *par = (struct atyfb_par *) info->par;
1258 struct fb_var_screeninfo *var = &info->var;
1262 struct fb_var_screeninfo debug;
1268 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1271 pixclock = atyfb_get_pixclock(var, par);
1273 if (pixclock == 0) {
1274 PRINTKE("Invalid pixclock\n");
1277 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1281 par->accel_flags = var->accel_flags; /* hack */
1283 if (par->blitter_may_be_busy)
1286 aty_set_crtc(par, &par->crtc);
1287 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1288 par->pll_ops->set_pll(info, &par->pll);
1291 if(par->pll_ops && par->pll_ops->pll_to_var)
1292 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1296 if(0 == pixclock_in_ps) {
1297 PRINTKE("ALERT ops->pll_to_var get 0\n");
1298 pixclock_in_ps = pixclock;
1301 memset(&debug, 0, sizeof(debug));
1302 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1303 u32 hSync, vRefresh;
1304 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1305 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1307 h_disp = debug.xres;
1308 h_sync_strt = h_disp + debug.right_margin;
1309 h_sync_end = h_sync_strt + debug.hsync_len;
1310 h_total = h_sync_end + debug.left_margin;
1311 v_disp = debug.yres;
1312 v_sync_strt = v_disp + debug.lower_margin;
1313 v_sync_end = v_sync_strt + debug.vsync_len;
1314 v_total = v_sync_end + debug.upper_margin;
1316 hSync = 1000000000 / (pixclock_in_ps * h_total);
1317 vRefresh = (hSync * 1000) / v_total;
1318 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1320 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1323 DPRINTK("atyfb_set_par\n");
1324 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1325 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1326 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1327 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1328 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1329 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1330 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1331 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1332 h_disp, h_sync_strt, h_sync_end, h_total,
1333 v_disp, v_sync_strt, v_sync_end, v_total);
1334 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1336 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1337 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1341 if (!M64_HAS(INTEGRATED)) {
1342 /* Don't forget MEM_CNTL */
1343 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1344 switch (var->bits_per_pixel) {
1355 aty_st_le32(MEM_CNTL, tmp, par);
1357 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1358 if (!M64_HAS(MAGIC_POSTDIV))
1359 tmp |= par->mem_refresh_rate << 20;
1360 switch (var->bits_per_pixel) {
1372 if (M64_HAS(CT_BUS)) {
1373 aty_st_le32(DAC_CNTL, 0x87010184, par);
1374 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1375 } else if (M64_HAS(VT_BUS)) {
1376 aty_st_le32(DAC_CNTL, 0x87010184, par);
1377 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1378 } else if (M64_HAS(MOBIL_BUS)) {
1379 aty_st_le32(DAC_CNTL, 0x80010102, par);
1380 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1383 aty_st_le32(DAC_CNTL, 0x86010102, par);
1384 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1385 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1387 aty_st_le32(MEM_CNTL, tmp, par);
1389 aty_st_8(DAC_MASK, 0xff, par);
1391 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1392 info->fix.visual = var->bits_per_pixel <= 8 ?
1393 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1395 /* Initialize the graphics engine */
1396 if (par->accel_flags & FB_ACCELF_TEXT)
1397 aty_init_engine(par, info);
1399 #ifdef CONFIG_BOOTX_TEXT
1400 btext_update_display(info->fix.smem_start,
1401 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1402 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1403 var->bits_per_pixel,
1404 par->crtc.vxres * var->bits_per_pixel / 8);
1405 #endif /* CONFIG_BOOTX_TEXT */
1407 /* switch to accelerator mode */
1408 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1409 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1413 /* dump non shadow CRTC, pll, LCD registers */
1416 /* CRTC registers */
1418 printk("debug atyfb: Mach64 non-shadow register values:");
1419 for (i = 0; i < 256; i = i+4) {
1420 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1421 printk(" %08X", aty_ld_le32(i, par));
1425 #ifdef CONFIG_FB_ATY_CT
1428 printk("debug atyfb: Mach64 PLL register values:");
1429 for (i = 0; i < 64; i++) {
1430 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1431 if(i%4 == 0) printk(" ");
1432 printk("%02X", aty_ld_pll_ct(i, par));
1435 #endif /* CONFIG_FB_ATY_CT */
1437 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1438 if (par->lcd_table != 0) {
1441 printk("debug atyfb: LCD register values:");
1442 if(M64_HAS(LT_LCD_REGS)) {
1443 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1444 if(i == EXT_VERT_STRETCH)
1446 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1447 printk(" %08X", aty_ld_lcd(i, par));
1451 for (i = 0; i < 64; i++) {
1452 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1453 printk(" %08X", aty_ld_lcd(i, par));
1458 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1464 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1466 struct atyfb_par *par = (struct atyfb_par *) info->par;
1472 memcpy(&pll, &(par->pll), sizeof(pll));
1474 if((err = aty_var_to_crtc(info, var, &crtc)))
1477 pixclock = atyfb_get_pixclock(var, par);
1479 if (pixclock == 0) {
1480 if (!(var->activate & FB_ACTIVATE_TEST))
1481 PRINTKE("Invalid pixclock\n");
1484 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1488 if (var->accel_flags & FB_ACCELF_TEXT)
1489 info->var.accel_flags = FB_ACCELF_TEXT;
1491 info->var.accel_flags = 0;
1493 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1494 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1497 aty_crtc_to_var(&crtc, var);
1498 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1502 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1504 u32 xoffset = info->var.xoffset;
1505 u32 yoffset = info->var.yoffset;
1506 u32 vxres = par->crtc.vxres;
1507 u32 bpp = info->var.bits_per_pixel;
1509 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1514 * Open/Release the frame buffer device
1517 static int atyfb_open(struct fb_info *info, int user)
1519 struct atyfb_par *par = (struct atyfb_par *) info->par;
1530 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1532 struct atyfb_par *par = dev_id;
1536 spin_lock(&par->int_lock);
1538 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1540 if (int_cntl & CRTC_VBLANK_INT) {
1541 /* clear interrupt */
1542 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1543 par->vblank.count++;
1544 if (par->vblank.pan_display) {
1545 par->vblank.pan_display = 0;
1546 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1548 wake_up_interruptible(&par->vblank.wait);
1552 spin_unlock(&par->int_lock);
1554 return IRQ_RETVAL(handled);
1557 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1561 if (!test_and_set_bit(0, &par->irq_flags)) {
1562 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1563 clear_bit(0, &par->irq_flags);
1566 spin_lock_irq(&par->int_lock);
1567 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1568 /* clear interrupt */
1569 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1570 /* enable interrupt */
1571 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1572 spin_unlock_irq(&par->int_lock);
1573 } else if (reenable) {
1574 spin_lock_irq(&par->int_lock);
1575 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1577 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1578 /* re-enable interrupt */
1579 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1581 spin_unlock_irq(&par->int_lock);
1587 static int aty_disable_irq(struct atyfb_par *par)
1591 if (test_and_clear_bit(0, &par->irq_flags)) {
1592 if (par->vblank.pan_display) {
1593 par->vblank.pan_display = 0;
1594 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1596 spin_lock_irq(&par->int_lock);
1597 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1598 /* disable interrupt */
1599 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1600 spin_unlock_irq(&par->int_lock);
1601 free_irq(par->irq, par);
1607 static int atyfb_release(struct fb_info *info, int user)
1609 struct atyfb_par *par = (struct atyfb_par *) info->par;
1616 int was_mmaped = par->mmaped;
1621 struct fb_var_screeninfo var;
1623 /* Now reset the default display config, we have no
1624 * idea what the program(s) which mmap'd the chip did
1625 * to the configuration, nor whether it restored it
1630 var.accel_flags &= ~FB_ACCELF_TEXT;
1632 var.accel_flags |= FB_ACCELF_TEXT;
1633 if (var.yres == var.yres_virtual) {
1634 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1635 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1636 if (var.yres_virtual < var.yres)
1637 var.yres_virtual = var.yres;
1641 aty_disable_irq(par);
1648 * Pan or Wrap the Display
1650 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1653 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1655 struct atyfb_par *par = (struct atyfb_par *) info->par;
1656 u32 xres, yres, xoffset, yoffset;
1658 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1659 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1660 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1662 xoffset = (var->xoffset + 7) & ~7;
1663 yoffset = var->yoffset;
1664 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1666 info->var.xoffset = xoffset;
1667 info->var.yoffset = yoffset;
1671 set_off_pitch(par, info);
1672 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1673 par->vblank.pan_display = 1;
1675 par->vblank.pan_display = 0;
1676 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1682 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1684 struct aty_interrupt *vbl;
1696 ret = aty_enable_irq(par, 0);
1701 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1706 aty_enable_irq(par, 1);
1715 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1716 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1722 u8 mclk_post_div; /* 1,2,3,4,8 */
1723 u8 mclk_fb_mult; /* 2 or 4 */
1724 u8 xclk_post_div; /* 1,2,3,4,8 */
1726 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1727 u32 dsp_xclks_per_row; /* 0-16383 */
1728 u32 dsp_loop_latency; /* 0-15 */
1729 u32 dsp_precision; /* 0-7 */
1730 u32 dsp_on; /* 0-2047 */
1731 u32 dsp_off; /* 0-2047 */
1734 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1735 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1738 #ifndef FBIO_WAITFORVSYNC
1739 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1742 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1744 struct atyfb_par *par = (struct atyfb_par *) info->par;
1746 struct fbtype fbtyp;
1752 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1753 fbtyp.fb_width = par->crtc.vxres;
1754 fbtyp.fb_height = par->crtc.vyres;
1755 fbtyp.fb_depth = info->var.bits_per_pixel;
1756 fbtyp.fb_cmsize = info->cmap.len;
1757 fbtyp.fb_size = info->fix.smem_len;
1758 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1761 #endif /* __sparc__ */
1763 case FBIO_WAITFORVSYNC:
1767 if (get_user(crtc, (__u32 __user *) arg))
1770 return aty_waitforvblank(par, crtc);
1774 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1776 if (M64_HAS(INTEGRATED)) {
1778 union aty_pll *pll = &(par->pll);
1779 u32 dsp_config = pll->ct.dsp_config;
1780 u32 dsp_on_off = pll->ct.dsp_on_off;
1781 clk.ref_clk_per = par->ref_clk_per;
1782 clk.pll_ref_div = pll->ct.pll_ref_div;
1783 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1784 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1785 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1786 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1787 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1788 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1789 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1790 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1791 clk.dsp_precision = (dsp_config >> 20) & 7;
1792 clk.dsp_off = dsp_on_off & 0x7ff;
1793 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1794 if (copy_to_user((struct atyclk __user *) arg, &clk,
1801 if (M64_HAS(INTEGRATED)) {
1803 union aty_pll *pll = &(par->pll);
1804 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1806 par->ref_clk_per = clk.ref_clk_per;
1807 pll->ct.pll_ref_div = clk.pll_ref_div;
1808 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1809 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1810 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1811 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1812 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1813 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1814 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1815 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1816 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1817 /*aty_calc_pll_ct(info, &pll->ct);*/
1818 aty_set_pll_ct(info, pll);
1823 if (get_user(par->features, (u32 __user *) arg))
1827 if (put_user(par->features, (u32 __user *) arg))
1830 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1837 static int atyfb_sync(struct fb_info *info)
1839 struct atyfb_par *par = (struct atyfb_par *) info->par;
1841 if (par->blitter_may_be_busy)
1847 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1849 struct atyfb_par *par = (struct atyfb_par *) info->par;
1850 unsigned int size, page, map_size = 0;
1851 unsigned long map_offset = 0;
1858 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1861 off = vma->vm_pgoff << PAGE_SHIFT;
1862 size = vma->vm_end - vma->vm_start;
1864 /* To stop the swapper from even considering these pages. */
1865 vma->vm_flags |= (VM_IO | VM_RESERVED);
1867 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1868 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1869 off += 0x8000000000000000UL;
1871 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1873 /* Each page, see which map applies */
1874 for (page = 0; page < size;) {
1876 for (i = 0; par->mmap_map[i].size; i++) {
1877 unsigned long start = par->mmap_map[i].voff;
1878 unsigned long end = start + par->mmap_map[i].size;
1879 unsigned long offset = off + page;
1886 map_size = par->mmap_map[i].size - (offset - start);
1888 par->mmap_map[i].poff + (offset - start);
1895 if (page + map_size > size)
1896 map_size = size - page;
1898 pgprot_val(vma->vm_page_prot) &=
1899 ~(par->mmap_map[i].prot_mask);
1900 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1902 if (remap_pfn_range(vma, vma->vm_start + page,
1903 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1924 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1928 for (i = 0; i < 256; i++) {
1929 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1930 if (M64_HAS(EXTRA_BRIGHT))
1932 aty_st_8(DAC_CNTL, tmp, par);
1933 aty_st_8(DAC_MASK, 0xff, par);
1935 writeb(i, &par->aty_cmap_regs->rindex);
1936 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1937 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1938 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1939 writeb(i, &par->aty_cmap_regs->windex);
1940 writeb(atyfb_save.r[1 - enter][i],
1941 &par->aty_cmap_regs->lut);
1942 writeb(atyfb_save.g[1 - enter][i],
1943 &par->aty_cmap_regs->lut);
1944 writeb(atyfb_save.b[1 - enter][i],
1945 &par->aty_cmap_regs->lut);
1949 static void atyfb_palette(int enter)
1951 struct atyfb_par *par;
1952 struct fb_info *info;
1955 for (i = 0; i < FB_MAX; i++) {
1956 info = registered_fb[i];
1957 if (info && info->fbops == &atyfb_ops) {
1958 par = (struct atyfb_par *) info->par;
1960 atyfb_save_palette(par, enter);
1962 atyfb_save.yoffset = info->var.yoffset;
1963 info->var.yoffset = 0;
1964 set_off_pitch(par, info);
1966 info->var.yoffset = atyfb_save.yoffset;
1967 set_off_pitch(par, info);
1969 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1974 #endif /* __sparc__ */
1978 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1980 /* Power management routines. Those are used for PowerBook sleep.
1982 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1987 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1988 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1989 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1990 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1997 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1999 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2001 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2002 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2005 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2007 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2009 if ((--timeout) == 0)
2011 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2015 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2016 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2019 pm |= (PWR_BLON | AUTO_PWR_UP);
2020 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2021 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2024 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2026 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2028 if ((--timeout) == 0)
2030 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2034 return timeout ? 0 : -EIO;
2037 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2039 struct fb_info *info = pci_get_drvdata(pdev);
2040 struct atyfb_par *par = (struct atyfb_par *) info->par;
2042 #ifndef CONFIG_PPC_PMAC
2043 /* HACK ALERT ! Once I find a proper way to say to each driver
2044 * individually what will happen with it's PCI slot, I'll change
2045 * that. On laptops, the AGP slot is just unclocked, so D2 is
2046 * expected, while on desktops, the card is powered off
2049 #endif /* CONFIG_PPC_PMAC */
2051 if (state.event == pdev->dev.power.power_state.event)
2054 acquire_console_sem();
2056 fb_set_suspend(info, 1);
2058 /* Idle & reset engine */
2060 aty_reset_engine(par);
2062 /* Blank display and LCD */
2063 atyfb_blank(FB_BLANK_POWERDOWN, info);
2066 par->lock_blank = 1;
2068 /* Set chip to "suspend" mode */
2069 if (aty_power_mgmt(1, par)) {
2071 par->lock_blank = 0;
2072 atyfb_blank(FB_BLANK_UNBLANK, info);
2073 fb_set_suspend(info, 0);
2074 release_console_sem();
2078 release_console_sem();
2080 pdev->dev.power.power_state = state;
2085 static int atyfb_pci_resume(struct pci_dev *pdev)
2087 struct fb_info *info = pci_get_drvdata(pdev);
2088 struct atyfb_par *par = (struct atyfb_par *) info->par;
2090 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2093 acquire_console_sem();
2095 if (pdev->dev.power.power_state.event == 2)
2096 aty_power_mgmt(0, par);
2099 /* Restore display */
2100 atyfb_set_par(info);
2103 fb_set_suspend(info, 0);
2106 par->lock_blank = 0;
2107 atyfb_blank(FB_BLANK_UNBLANK, info);
2109 release_console_sem();
2111 pdev->dev.power.power_state = PMSG_ON;
2116 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2118 #ifdef CONFIG_PMAC_BACKLIGHT
2121 * LCD backlight control
2124 static int backlight_conv[] = {
2125 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2126 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2129 static int aty_set_backlight_enable(int on, int level, void *data)
2131 struct fb_info *info = (struct fb_info *) data;
2132 struct atyfb_par *par = (struct atyfb_par *) info->par;
2133 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2135 reg |= (BLMOD_EN | BIASMOD_EN);
2136 if (on && level > BACKLIGHT_OFF) {
2137 reg &= ~BIAS_MOD_LEVEL_MASK;
2138 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2140 reg &= ~BIAS_MOD_LEVEL_MASK;
2141 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2143 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2147 static int aty_set_backlight_level(int level, void *data)
2149 return aty_set_backlight_enable(1, level, data);
2152 static struct backlight_controller aty_backlight_controller = {
2153 aty_set_backlight_enable,
2154 aty_set_backlight_level
2156 #endif /* CONFIG_PMAC_BACKLIGHT */
2158 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2160 const int ragepro_tbl[] = {
2161 44, 50, 55, 66, 75, 80, 100
2163 const int ragexl_tbl[] = {
2164 50, 66, 75, 83, 90, 95, 100, 105,
2165 110, 115, 120, 125, 133, 143, 166
2167 const int *refresh_tbl;
2170 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2171 refresh_tbl = ragexl_tbl;
2172 size = sizeof(ragexl_tbl)/sizeof(int);
2174 refresh_tbl = ragepro_tbl;
2175 size = sizeof(ragepro_tbl)/sizeof(int);
2178 for (i=0; i < size; i++) {
2179 if (xclk < refresh_tbl[i])
2182 par->mem_refresh_rate = i;
2189 static struct fb_info *fb_list = NULL;
2191 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2192 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2193 struct fb_var_screeninfo *var)
2197 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2199 var->xres = var->xres_virtual = par->lcd_hdisp;
2200 var->right_margin = par->lcd_right_margin;
2201 var->left_margin = par->lcd_hblank_len -
2202 (par->lcd_right_margin + par->lcd_hsync_dly +
2203 par->lcd_hsync_len);
2204 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2205 var->yres = var->yres_virtual = par->lcd_vdisp;
2206 var->lower_margin = par->lcd_lower_margin;
2207 var->upper_margin = par->lcd_vblank_len -
2208 (par->lcd_lower_margin + par->lcd_vsync_len);
2209 var->vsync_len = par->lcd_vsync_len;
2210 var->pixclock = par->lcd_pixclock;
2216 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2218 static int __init aty_init(struct fb_info *info, const char *name)
2220 struct atyfb_par *par = (struct atyfb_par *) info->par;
2221 const char *ramname = NULL, *xtal;
2222 int gtb_memsize, has_var = 0;
2223 struct fb_var_screeninfo var;
2226 #if defined(CONFIG_PPC)
2230 init_waitqueue_head(&par->vblank.wait);
2231 spin_lock_init(&par->int_lock);
2233 par->aty_cmap_regs =
2234 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2236 #ifdef CONFIG_PPC_PMAC
2237 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2238 * and set the frequency manually. */
2239 if (machine_is_compatible("PowerBook2,1")) {
2240 par->pll_limits.mclk = 70;
2241 par->pll_limits.xclk = 53;
2245 par->pll_limits.pll_max = pll;
2247 par->pll_limits.mclk = mclk;
2249 par->pll_limits.xclk = xclk;
2251 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2252 par->pll_per = 1000000/par->pll_limits.pll_max;
2253 par->mclk_per = 1000000/par->pll_limits.mclk;
2254 par->xclk_per = 1000000/par->pll_limits.xclk;
2256 par->ref_clk_per = 1000000000000ULL / 14318180;
2259 #ifdef CONFIG_FB_ATY_GX
2260 if (!M64_HAS(INTEGRATED)) {
2262 u8 dac_type, dac_subtype, clk_type;
2263 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2264 par->bus_type = (stat0 >> 0) & 0x07;
2265 par->ram_type = (stat0 >> 3) & 0x07;
2266 ramname = aty_gx_ram[par->ram_type];
2267 /* FIXME: clockchip/RAMDAC probing? */
2268 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2270 clk_type = CLK_ATI18818_1;
2271 dac_type = (stat0 >> 9) & 0x07;
2272 if (dac_type == 0x07)
2273 dac_subtype = DAC_ATT20C408;
2275 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2277 dac_type = DAC_IBMRGB514;
2278 dac_subtype = DAC_IBMRGB514;
2279 clk_type = CLK_IBMRGB514;
2281 switch (dac_subtype) {
2283 par->dac_ops = &aty_dac_ibm514;
2285 case DAC_ATI68860_B:
2286 case DAC_ATI68860_C:
2287 par->dac_ops = &aty_dac_ati68860b;
2291 par->dac_ops = &aty_dac_att21c498;
2294 PRINTKI("aty_init: DAC type not implemented yet!\n");
2295 par->dac_ops = &aty_dac_unsupported;
2299 case CLK_ATI18818_1:
2300 par->pll_ops = &aty_pll_ati18818_1;
2303 par->pll_ops = &aty_pll_stg1703;
2306 par->pll_ops = &aty_pll_ch8398;
2309 par->pll_ops = &aty_pll_att20c408;
2312 par->pll_ops = &aty_pll_ibm514;
2315 PRINTKI("aty_init: CLK type not implemented yet!");
2316 par->pll_ops = &aty_pll_unsupported;
2320 #endif /* CONFIG_FB_ATY_GX */
2321 #ifdef CONFIG_FB_ATY_CT
2322 if (M64_HAS(INTEGRATED)) {
2323 par->dac_ops = &aty_dac_ct;
2324 par->pll_ops = &aty_pll_ct;
2325 par->bus_type = PCI;
2326 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2327 ramname = aty_ct_ram[par->ram_type];
2328 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2329 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2330 par->pll_limits.mclk = 63;
2333 if (M64_HAS(GTB_DSP)
2334 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2336 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2337 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2342 if (diff2 < diff1) {
2343 par->ref_clk_per = 1000000000000ULL / 29498928;
2347 #endif /* CONFIG_FB_ATY_CT */
2349 /* save previous video mode */
2350 aty_get_crtc(par, &saved_crtc);
2351 if(par->pll_ops->get_pll)
2352 par->pll_ops->get_pll(info, &saved_pll);
2354 i = aty_ld_le32(MEM_CNTL, par);
2355 gtb_memsize = M64_HAS(GTB_DSP);
2357 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2359 info->fix.smem_len = 0x80000;
2362 info->fix.smem_len = 0x100000;
2364 case MEM_SIZE_2M_GTB:
2365 info->fix.smem_len = 0x200000;
2367 case MEM_SIZE_4M_GTB:
2368 info->fix.smem_len = 0x400000;
2370 case MEM_SIZE_6M_GTB:
2371 info->fix.smem_len = 0x600000;
2373 case MEM_SIZE_8M_GTB:
2374 info->fix.smem_len = 0x800000;
2377 info->fix.smem_len = 0x80000;
2379 switch (i & MEM_SIZE_ALIAS) {
2381 info->fix.smem_len = 0x80000;
2384 info->fix.smem_len = 0x100000;
2387 info->fix.smem_len = 0x200000;
2390 info->fix.smem_len = 0x400000;
2393 info->fix.smem_len = 0x600000;
2396 info->fix.smem_len = 0x800000;
2399 info->fix.smem_len = 0x80000;
2402 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2403 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2404 info->fix.smem_len += 0x400000;
2408 info->fix.smem_len = vram * 1024;
2409 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2410 if (info->fix.smem_len <= 0x80000)
2412 else if (info->fix.smem_len <= 0x100000)
2414 else if (info->fix.smem_len <= 0x200000)
2415 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2416 else if (info->fix.smem_len <= 0x400000)
2417 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2418 else if (info->fix.smem_len <= 0x600000)
2419 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2421 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2422 aty_st_le32(MEM_CNTL, i, par);
2426 * Reg Block 0 (CT-compatible block) is at mmio_start
2427 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2430 info->fix.mmio_len = 0x400;
2431 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2432 } else if (M64_HAS(CT)) {
2433 info->fix.mmio_len = 0x400;
2434 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2435 } else if (M64_HAS(VT)) {
2436 info->fix.mmio_start -= 0x400;
2437 info->fix.mmio_len = 0x800;
2438 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2440 info->fix.mmio_start -= 0x400;
2441 info->fix.mmio_len = 0x800;
2442 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2445 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2446 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2447 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2448 par->pll_limits.mclk, par->pll_limits.xclk);
2450 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2451 if (M64_HAS(INTEGRATED)) {
2453 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2454 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2455 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2457 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2458 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2459 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2460 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2461 for (i = 0; i < 40; i++)
2462 printk(" %02x", aty_ld_pll_ct(i, par));
2466 if(par->pll_ops->init_pll)
2467 par->pll_ops->init_pll(info, &par->pll);
2470 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2471 * FIXME: we should use the auxiliary aperture instead so we can access
2472 * the full 8 MB of video RAM on 8 MB boards
2475 if (!par->aux_start &&
2476 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2477 info->fix.smem_len -= GUI_RESERVE;
2480 * Disable register access through the linear aperture
2481 * if the auxiliary aperture is used so we can access
2482 * the full 8 MB of video RAM on 8 MB boards.
2485 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2488 par->mtrr_aper = -1;
2491 /* Cover the whole resource. */
2492 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2493 if (par->mtrr_aper >= 0 && !par->aux_start) {
2494 /* Make a hole for mmio. */
2495 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2496 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2497 if (par->mtrr_reg < 0) {
2498 mtrr_del(par->mtrr_aper, 0, 0);
2499 par->mtrr_aper = -1;
2505 info->fbops = &atyfb_ops;
2506 info->pseudo_palette = pseudo_palette;
2507 info->flags = FBINFO_FLAG_DEFAULT;
2509 #ifdef CONFIG_PMAC_BACKLIGHT
2510 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2511 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2512 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2513 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2514 } else if (M64_HAS(MOBIL_BUS))
2515 register_backlight_controller(&aty_backlight_controller, info, "ati");
2516 #endif /* CONFIG_PMAC_BACKLIGHT */
2518 memset(&var, 0, sizeof(var));
2520 if (machine_is(powermac)) {
2522 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2523 * applies to all Mac video cards
2526 if (mac_find_mode(&var, info, mode, 8))
2529 if (default_vmode == VMODE_CHOOSE) {
2530 if (M64_HAS(G3_PB_1024x768))
2531 /* G3 PowerBook with 1024x768 LCD */
2532 default_vmode = VMODE_1024_768_60;
2533 else if (machine_is_compatible("iMac"))
2534 default_vmode = VMODE_1024_768_75;
2535 else if (machine_is_compatible
2537 /* iBook with 800x600 LCD */
2538 default_vmode = VMODE_800_600_60;
2540 default_vmode = VMODE_640_480_67;
2541 sense = read_aty_sense(par);
2542 PRINTKI("monitor sense=%x, mode %d\n",
2543 sense, mac_map_monitor_sense(sense));
2545 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2546 default_vmode = VMODE_640_480_60;
2547 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2548 default_cmode = CMODE_8;
2549 if (!mac_vmode_to_var(default_vmode, default_cmode,
2555 #endif /* !CONFIG_PPC */
2557 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2558 if (!atyfb_get_timings_from_lcd(par, &var))
2562 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2569 var.accel_flags &= ~FB_ACCELF_TEXT;
2571 var.accel_flags |= FB_ACCELF_TEXT;
2573 if (comp_sync != -1) {
2575 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2577 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2580 if (var.yres == var.yres_virtual) {
2581 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2582 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2583 if (var.yres_virtual < var.yres)
2584 var.yres_virtual = var.yres;
2587 if (atyfb_check_var(&var, info)) {
2588 PRINTKE("can't set default video mode\n");
2593 atyfb_save_palette(par, 0);
2596 #ifdef CONFIG_FB_ATY_CT
2597 if (!noaccel && M64_HAS(INTEGRATED))
2598 aty_init_cursor(info);
2599 #endif /* CONFIG_FB_ATY_CT */
2602 fb_alloc_cmap(&info->cmap, 256, 0);
2604 if (register_framebuffer(info) < 0)
2609 PRINTKI("fb%d: %s frame buffer device on %s\n",
2610 info->node, info->fix.id, name);
2614 /* restore video mode */
2615 aty_set_crtc(par, &saved_crtc);
2616 par->pll_ops->set_pll(info, &saved_pll);
2619 if (par->mtrr_reg >= 0) {
2620 mtrr_del(par->mtrr_reg, 0, 0);
2623 if (par->mtrr_aper >= 0) {
2624 mtrr_del(par->mtrr_aper, 0, 0);
2625 par->mtrr_aper = -1;
2632 static int __init store_video_par(char *video_str, unsigned char m64_num)
2635 unsigned long vmembase, size, guiregbase;
2637 PRINTKI("store_video_par() '%s' \n", video_str);
2639 if (!(p = strsep(&video_str, ";")) || !*p)
2640 goto mach64_invalid;
2641 vmembase = simple_strtoul(p, NULL, 0);
2642 if (!(p = strsep(&video_str, ";")) || !*p)
2643 goto mach64_invalid;
2644 size = simple_strtoul(p, NULL, 0);
2645 if (!(p = strsep(&video_str, ";")) || !*p)
2646 goto mach64_invalid;
2647 guiregbase = simple_strtoul(p, NULL, 0);
2649 phys_vmembase[m64_num] = vmembase;
2650 phys_size[m64_num] = size;
2651 phys_guiregbase[m64_num] = guiregbase;
2652 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2657 phys_vmembase[m64_num] = 0;
2660 #endif /* CONFIG_ATARI */
2663 * Blank the display.
2666 static int atyfb_blank(int blank, struct fb_info *info)
2668 struct atyfb_par *par = (struct atyfb_par *) info->par;
2671 if (par->lock_blank || par->asleep)
2674 #ifdef CONFIG_PMAC_BACKLIGHT
2675 if (machine_is(powermac) && blank > FB_BLANK_NORMAL)
2676 set_backlight_enable(0);
2677 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2678 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2679 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2680 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2682 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2686 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2688 case FB_BLANK_UNBLANK:
2689 gen_cntl &= ~0x400004c;
2691 case FB_BLANK_NORMAL:
2692 gen_cntl |= 0x4000040;
2694 case FB_BLANK_VSYNC_SUSPEND:
2695 gen_cntl |= 0x4000048;
2697 case FB_BLANK_HSYNC_SUSPEND:
2698 gen_cntl |= 0x4000044;
2700 case FB_BLANK_POWERDOWN:
2701 gen_cntl |= 0x400004c;
2704 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2706 #ifdef CONFIG_PMAC_BACKLIGHT
2707 if (machine_is(powermac) && blank <= FB_BLANK_NORMAL)
2708 set_backlight_enable(1);
2709 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2710 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2711 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2712 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2714 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2721 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2722 const struct atyfb_par *par)
2725 out_8(&par->aty_cmap_regs->windex, regno);
2726 out_8(&par->aty_cmap_regs->lut, red);
2727 out_8(&par->aty_cmap_regs->lut, green);
2728 out_8(&par->aty_cmap_regs->lut, blue);
2730 writeb(regno, &par->aty_cmap_regs->windex);
2731 writeb(red, &par->aty_cmap_regs->lut);
2732 writeb(green, &par->aty_cmap_regs->lut);
2733 writeb(blue, &par->aty_cmap_regs->lut);
2738 * Set a single color register. The values supplied are already
2739 * rounded down to the hardware's capabilities (according to the
2740 * entries in the var structure). Return != 0 for invalid regno.
2741 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2744 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2745 u_int transp, struct fb_info *info)
2747 struct atyfb_par *par = (struct atyfb_par *) info->par;
2749 u32 *pal = info->pseudo_palette;
2751 depth = info->var.bits_per_pixel;
2753 depth = (info->var.green.length == 5) ? 15 : 16;
2759 (depth == 16 && regno > 63) ||
2760 (depth == 15 && regno > 31))
2767 par->palette[regno].red = red;
2768 par->palette[regno].green = green;
2769 par->palette[regno].blue = blue;
2774 pal[regno] = (regno << 10) | (regno << 5) | regno;
2777 pal[regno] = (regno << 11) | (regno << 5) | regno;
2780 pal[regno] = (regno << 16) | (regno << 8) | regno;
2783 i = (regno << 8) | regno;
2784 pal[regno] = (i << 16) | i;
2789 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2790 if (M64_HAS(EXTRA_BRIGHT))
2791 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2792 aty_st_8(DAC_CNTL, i, par);
2793 aty_st_8(DAC_MASK, 0xff, par);
2795 if (M64_HAS(INTEGRATED)) {
2798 aty_st_pal(regno << 3, red,
2799 par->palette[regno<<1].green,
2801 red = par->palette[regno>>1].red;
2802 blue = par->palette[regno>>1].blue;
2804 } else if (depth == 15) {
2806 for(i = 0; i < 8; i++) {
2807 aty_st_pal(regno + i, red, green, blue, par);
2811 aty_st_pal(regno, red, green, blue, par);
2820 extern void (*prom_palette) (int);
2822 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2823 struct fb_info *info, unsigned long addr)
2825 extern int con_is_present(void);
2827 struct atyfb_par *par = info->par;
2828 struct pcidev_cookie *pcp;
2830 int node, len, i, j, ret;
2833 /* Do not attach when we have a serial console. */
2834 if (!con_is_present())
2838 * Map memory-mapped registers.
2840 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2841 info->fix.mmio_start = addr + 0x7ffc00UL;
2844 * Map in big-endian aperture.
2846 info->screen_base = (char *) (addr + 0x800000UL);
2847 info->fix.smem_start = addr + 0x800000UL;
2850 * Figure mmap addresses from PCI config space.
2851 * Split Framebuffer in big- and little-endian halfs.
2853 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2857 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2858 if (!par->mmap_map) {
2859 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2862 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2864 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2865 struct resource *rp = &pdev->resource[i];
2866 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2872 io = (rp->flags & IORESOURCE_IO);
2874 size = rp->end - base + 1;
2876 pci_read_config_dword(pdev, breg, &pbase);
2882 * Map the framebuffer a second time, this time without
2883 * the braindead _PAGE_IE setting. This is used by the
2884 * fixed Xserver, but we need to maintain the old mapping
2885 * to stay compatible with older ones...
2888 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2889 par->mmap_map[j].poff = base & PAGE_MASK;
2890 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2891 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2892 par->mmap_map[j].prot_flag = _PAGE_E;
2897 * Here comes the old framebuffer mapping with _PAGE_IE
2898 * set for the big endian half of the framebuffer...
2901 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2902 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2903 par->mmap_map[j].size = 0x800000;
2904 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2905 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2910 par->mmap_map[j].voff = pbase & PAGE_MASK;
2911 par->mmap_map[j].poff = base & PAGE_MASK;
2912 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2913 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2914 par->mmap_map[j].prot_flag = _PAGE_E;
2918 if((ret = correct_chipset(par)))
2921 if (IS_XL(pdev->device)) {
2923 * Fix PROMs idea of MEM_CNTL settings...
2925 mem = aty_ld_le32(MEM_CNTL, par);
2926 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2927 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2928 switch (mem & 0x0f) {
2930 mem = (mem & ~(0x0f)) | 2;
2933 mem = (mem & ~(0x0f)) | 3;
2936 mem = (mem & ~(0x0f)) | 4;
2939 mem = (mem & ~(0x0f)) | 5;
2944 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2945 mem &= ~(0x00700000);
2947 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2948 aty_st_le32(MEM_CNTL, mem, par);
2952 * If this is the console device, we will set default video
2953 * settings to what the PROM left us with.
2955 node = prom_getchild(prom_root_node);
2956 node = prom_searchsiblings(node, "aliases");
2958 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2961 node = prom_finddevice(prop);
2966 pcp = pdev->sysdata;
2967 if (node == pcp->prom_node) {
2968 struct fb_var_screeninfo *var = &default_var;
2969 unsigned int N, P, Q, M, T, R;
2970 u32 v_total, h_total;
2975 crtc.vxres = prom_getintdefault(node, "width", 1024);
2976 crtc.vyres = prom_getintdefault(node, "height", 768);
2977 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2978 var->xoffset = var->yoffset = 0;
2979 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2980 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2981 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2982 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2983 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2984 aty_crtc_to_var(&crtc, var);
2986 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2987 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2990 * Read the PLL to figure actual Refresh Rate.
2992 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2993 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2994 for (i = 0; i < 16; i++)
2995 pll_regs[i] = aty_ld_pll_ct(i, par);
2998 * PLL Reference Divider M:
3003 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3005 N = pll_regs[7 + (clock_cntl & 3)];
3008 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3010 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3024 * where R is XTALIN (= 14318 or 29498 kHz).
3026 if (IS_XL(pdev->device))
3033 default_var.pixclock = 1000000000 / T;
3039 #else /* __sparc__ */
3042 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3043 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3045 u32 driv_inf_tab, sig;
3048 /* To support an LCD panel, we should know it's dimensions and
3049 * it's desired pixel clock.
3050 * There are two ways to do it:
3051 * - Check the startup video mode and calculate the panel
3052 * size from it. This is unreliable.
3053 * - Read it from the driver information table in the video BIOS.
3055 /* Address of driver information table is at offset 0x78. */
3056 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3058 /* Check for the driver information table signature. */
3059 sig = (*(u32 *)driv_inf_tab);
3060 if ((sig == 0x54504c24) || /* Rage LT pro */
3061 (sig == 0x544d5224) || /* Rage mobility */
3062 (sig == 0x54435824) || /* Rage XC */
3063 (sig == 0x544c5824)) { /* Rage XL */
3064 PRINTKI("BIOS contains driver information table.\n");
3065 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3068 par->lcd_table = bios_base + lcd_ofs;
3072 if (par->lcd_table != 0) {
3075 char refresh_rates_buf[100];
3076 int id, tech, f, i, m, default_refresh_rate;
3081 u16 width, height, panel_type, refresh_rates;
3084 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3085 /* The most important information is the panel size at
3086 * offset 25 and 27, but there's some other nice information
3087 * which we print to the screen.
3089 id = *(u8 *)par->lcd_table;
3090 strncpy(model,(char *)par->lcd_table+1,24);
3093 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3094 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3095 panel_type = *(u16 *)(par->lcd_table+29);
3097 txtcolour = "colour";
3099 txtcolour = "monochrome";
3101 txtdual = "dual (split) ";
3104 tech = (panel_type>>2) & 63;
3107 txtmonitor = "passive matrix";
3110 txtmonitor = "active matrix";
3113 txtmonitor = "active addressed STN";
3119 txtmonitor = "plasma";
3122 txtmonitor = "unknown";
3124 format = *(u32 *)(par->lcd_table+57);
3125 if (tech == 0 || tech == 2) {
3126 switch (format & 7) {
3128 txtformat = "12 bit interface";
3131 txtformat = "16 bit interface";
3134 txtformat = "24 bit interface";
3137 txtformat = "unkown format";
3140 switch (format & 7) {
3142 txtformat = "8 colours";
3145 txtformat = "512 colours";
3148 txtformat = "4096 colours";
3151 txtformat = "262144 colours (LT mode)";
3154 txtformat = "16777216 colours";
3157 txtformat = "262144 colours (FDPI-2 mode)";
3160 txtformat = "unkown format";
3163 PRINTKI("%s%s %s monitor detected: %s\n",
3164 txtdual ,txtcolour, txtmonitor, model);
3165 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3166 id, width, height, txtformat);
3167 refresh_rates_buf[0] = 0;
3168 refresh_rates = *(u16 *)(par->lcd_table+62);
3171 for (i=0;i<16;i++) {
3172 if (refresh_rates & m) {
3174 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3177 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3179 strcat(refresh_rates_buf,strbuf);
3183 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3184 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3185 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3186 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3187 /* We now need to determine the crtc parameters for the
3188 * LCD monitor. This is tricky, because they are not stored
3189 * individually in the BIOS. Instead, the BIOS contains a
3190 * table of display modes that work for this monitor.
3192 * The idea is that we search for a mode of the same dimensions
3193 * as the dimensions of the LCD monitor. Say our LCD monitor
3194 * is 800x600 pixels, we search for a 800x600 monitor.
3195 * The CRTC parameters we find here are the ones that we need
3196 * to use to simulate other resolutions on the LCD screen.
3198 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3199 while (*lcdmodeptr != 0) {
3201 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3202 modeptr = bios_base + *lcdmodeptr;
3204 mwidth = *((u16 *)(modeptr+0));
3205 mheight = *((u16 *)(modeptr+2));
3207 if (mwidth == width && mheight == height) {
3208 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3209 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3210 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3211 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3212 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3213 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3215 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3216 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3217 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3218 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3220 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3221 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3222 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3223 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3229 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3230 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3231 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3232 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3238 if (*lcdmodeptr == 0) {
3239 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3240 /* To do: Switch to CRT if possible. */
3242 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3243 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3245 par->lcd_hdisp + par->lcd_right_margin,
3246 par->lcd_hdisp + par->lcd_right_margin
3247 + par->lcd_hsync_dly + par->lcd_hsync_len,
3250 par->lcd_vdisp + par->lcd_lower_margin,
3251 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3253 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3255 par->lcd_hblank_len - (par->lcd_right_margin +
3256 par->lcd_hsync_dly + par->lcd_hsync_len),
3258 par->lcd_right_margin,
3260 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3262 par->lcd_lower_margin,
3263 par->lcd_vsync_len);
3267 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3269 static int __devinit init_from_bios(struct atyfb_par *par)
3271 u32 bios_base, rom_addr;
3274 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3275 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3277 /* The BIOS starts with 0xaa55. */
3278 if (*((u16 *)bios_base) == 0xaa55) {
3281 u16 rom_table_offset, freq_table_offset;
3282 PLL_BLOCK_MACH64 pll_block;
3284 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3286 /* check for frequncy table */
3287 bios_ptr = (u8*)bios_base;
3288 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3289 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3290 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3292 PRINTKI("BIOS frequency table:\n");
3293 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3294 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3295 pll_block.ref_freq, pll_block.ref_divider);
3296 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3297 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3298 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3300 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3301 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3302 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3303 par->pll_limits.ref_div = pll_block.ref_divider;
3304 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3305 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3306 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3307 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3308 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3309 aty_init_lcd(par, bios_base);
3313 PRINTKE("no BIOS frequency table found, use parameters\n");
3316 iounmap((void* __iomem )bios_base);
3320 #endif /* __i386__ */
3322 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3324 struct atyfb_par *par = info->par;
3326 unsigned long raddr;
3327 struct resource *rrp;
3330 raddr = addr + 0x7ff000UL;
3331 rrp = &pdev->resource[2];
3332 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3333 par->aux_start = rrp->start;
3334 par->aux_size = rrp->end - rrp->start + 1;
3336 PRINTKI("using auxiliary register aperture\n");
3339 info->fix.mmio_start = raddr;
3340 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3341 if (par->ati_regbase == 0)
3344 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3345 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3348 * Enable memory-space accesses using config-space
3351 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3352 if (!(tmp & PCI_COMMAND_MEMORY)) {
3353 tmp |= PCI_COMMAND_MEMORY;
3354 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3357 /* Use the big-endian aperture */
3361 /* Map in frame buffer */
3362 info->fix.smem_start = addr;
3363 info->screen_base = ioremap(addr, 0x800000);
3364 if (info->screen_base == NULL) {
3366 goto atyfb_setup_generic_fail;
3369 if((ret = correct_chipset(par)))
3370 goto atyfb_setup_generic_fail;
3372 if((ret = init_from_bios(par)))
3373 goto atyfb_setup_generic_fail;
3375 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3376 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3378 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3380 /* according to ATI, we should use clock 3 for acelerated mode */
3381 par->clk_wr_offset = 3;
3385 atyfb_setup_generic_fail:
3386 iounmap(par->ati_regbase);
3387 par->ati_regbase = NULL;
3391 #endif /* !__sparc__ */
3393 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3395 unsigned long addr, res_start, res_size;
3396 struct fb_info *info;
3397 struct resource *rp;
3398 struct atyfb_par *par;
3399 int i, rc = -ENOMEM;
3401 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3402 if (pdev->device == aty_chips[i].pci_id)
3408 /* Enable device in PCI config */
3409 if (pci_enable_device(pdev)) {
3410 PRINTKE("Cannot enable PCI device\n");
3414 /* Find which resource to use */
3415 rp = &pdev->resource[0];
3416 if (rp->flags & IORESOURCE_IO)
3417 rp = &pdev->resource[1];
3423 res_start = rp->start;
3424 res_size = rp->end - rp->start + 1;
3425 if (!request_mem_region (res_start, res_size, "atyfb"))
3428 /* Allocate framebuffer */
3429 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3431 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3435 info->fix = atyfb_fix;
3436 info->device = &pdev->dev;
3437 par->pci_id = aty_chips[i].pci_id;
3438 par->res_start = res_start;
3439 par->res_size = res_size;
3440 par->irq = pdev->irq;
3442 /* Setup "info" structure */
3444 rc = atyfb_setup_sparc(pdev, info, addr);
3446 rc = atyfb_setup_generic(pdev, info, addr);
3449 goto err_release_mem;
3451 pci_set_drvdata(pdev, info);
3453 /* Init chip & register framebuffer */
3454 if (aty_init(info, "PCI"))
3455 goto err_release_io;
3459 prom_palette = atyfb_palette;
3462 * Add /dev/fb mmap values.
3464 par->mmap_map[0].voff = 0x8000000000000000UL;
3465 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3466 par->mmap_map[0].size = info->fix.smem_len;
3467 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3468 par->mmap_map[0].prot_flag = _PAGE_E;
3469 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3470 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3471 par->mmap_map[1].size = PAGE_SIZE;
3472 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3473 par->mmap_map[1].prot_flag = _PAGE_E;
3474 #endif /* __sparc__ */
3480 kfree(par->mmap_map);
3482 if (par->ati_regbase)
3483 iounmap(par->ati_regbase);
3484 if (info->screen_base)
3485 iounmap(info->screen_base);
3489 release_mem_region(par->aux_start, par->aux_size);
3491 release_mem_region(par->res_start, par->res_size);
3492 framebuffer_release(info);
3497 #endif /* CONFIG_PCI */
3501 static int __devinit atyfb_atari_probe(void)
3503 struct atyfb_par *par;
3504 struct fb_info *info;
3508 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3509 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3510 !phys_guiregbase[m64_num]) {
3511 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3515 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3517 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3522 info->fix = atyfb_fix;
3524 par->irq = (unsigned int) -1; /* something invalid */
3527 * Map the video memory (physical address given) to somewhere in the
3528 * kernel address space.
3530 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3531 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3532 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3534 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3536 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3537 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3539 switch (clock_r & 0x003F) {
3541 par->clk_wr_offset = 3; /* */
3544 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3547 par->clk_wr_offset = 1; /* */
3550 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3554 if (aty_init(info, "ISA bus")) {
3555 framebuffer_release(info);
3556 /* This is insufficient! kernel_map has added two large chunks!! */
3562 #endif /* CONFIG_ATARI */
3564 static void __devexit atyfb_remove(struct fb_info *info)
3566 struct atyfb_par *par = (struct atyfb_par *) info->par;
3568 /* restore video mode */
3569 aty_set_crtc(par, &saved_crtc);
3570 par->pll_ops->set_pll(info, &saved_pll);
3572 unregister_framebuffer(info);
3575 if (par->mtrr_reg >= 0) {
3576 mtrr_del(par->mtrr_reg, 0, 0);
3579 if (par->mtrr_aper >= 0) {
3580 mtrr_del(par->mtrr_aper, 0, 0);
3581 par->mtrr_aper = -1;
3585 if (par->ati_regbase)
3586 iounmap(par->ati_regbase);
3587 if (info->screen_base)
3588 iounmap(info->screen_base);
3590 if (info->sprite.addr)
3591 iounmap(info->sprite.addr);
3595 kfree(par->mmap_map);
3598 release_mem_region(par->aux_start, par->aux_size);
3601 release_mem_region(par->res_start, par->res_size);
3603 framebuffer_release(info);
3608 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3610 struct fb_info *info = pci_get_drvdata(pdev);
3616 * This driver uses its own matching table. That will be more difficult
3617 * to fix, so for now, we just match against any ATI ID and let the
3618 * probe() function find out what's up. That also mean we don't have
3619 * a module ID table though.
3621 static struct pci_device_id atyfb_pci_tbl[] = {
3622 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3623 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3627 static struct pci_driver atyfb_driver = {
3629 .id_table = atyfb_pci_tbl,
3630 .probe = atyfb_pci_probe,
3631 .remove = __devexit_p(atyfb_pci_remove),
3633 .suspend = atyfb_pci_suspend,
3634 .resume = atyfb_pci_resume,
3635 #endif /* CONFIG_PM */
3638 #endif /* CONFIG_PCI */
3641 static int __init atyfb_setup(char *options)
3645 if (!options || !*options)
3648 while ((this_opt = strsep(&options, ",")) != NULL) {
3649 if (!strncmp(this_opt, "noaccel", 7)) {
3652 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3655 } else if (!strncmp(this_opt, "vram:", 5))
3656 vram = simple_strtoul(this_opt + 5, NULL, 0);
3657 else if (!strncmp(this_opt, "pll:", 4))
3658 pll = simple_strtoul(this_opt + 4, NULL, 0);
3659 else if (!strncmp(this_opt, "mclk:", 5))
3660 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3661 else if (!strncmp(this_opt, "xclk:", 5))
3662 xclk = simple_strtoul(this_opt+5, NULL, 0);
3663 else if (!strncmp(this_opt, "comp_sync:", 10))
3664 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3666 else if (!strncmp(this_opt, "vmode:", 6)) {
3667 unsigned int vmode =
3668 simple_strtoul(this_opt + 6, NULL, 0);
3669 if (vmode > 0 && vmode <= VMODE_MAX)
3670 default_vmode = vmode;
3671 } else if (!strncmp(this_opt, "cmode:", 6)) {
3672 unsigned int cmode =
3673 simple_strtoul(this_opt + 6, NULL, 0);
3677 default_cmode = CMODE_8;
3681 default_cmode = CMODE_16;
3685 default_cmode = CMODE_32;
3692 * Why do we need this silly Mach64 argument?
3693 * We are already here because of mach64= so its redundant.
3695 else if (MACH_IS_ATARI
3696 && (!strncmp(this_opt, "Mach64:", 7))) {
3697 static unsigned char m64_num;
3698 static char mach64_str[80];
3699 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3700 if (!store_video_par(mach64_str, m64_num)) {
3702 mach64_count = m64_num;
3713 static int __init atyfb_init(void)
3716 char *option = NULL;
3718 if (fb_get_options("atyfb", &option))
3720 atyfb_setup(option);
3723 pci_register_driver(&atyfb_driver);
3725 atyfb_atari_probe();
3730 static void __exit atyfb_exit(void)
3732 pci_unregister_driver(&atyfb_driver);
3735 module_init(atyfb_init);
3736 module_exit(atyfb_exit);
3738 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3739 MODULE_LICENSE("GPL");
3740 module_param(noaccel, bool, 0);
3741 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3742 module_param(vram, int, 0);
3743 MODULE_PARM_DESC(vram, "int: override size of video ram");
3744 module_param(pll, int, 0);
3745 MODULE_PARM_DESC(pll, "int: override video clock");
3746 module_param(mclk, int, 0);
3747 MODULE_PARM_DESC(mclk, "int: override memory clock");
3748 module_param(xclk, int, 0);
3749 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3750 module_param(comp_sync, int, 0);
3751 MODULE_PARM_DESC(comp_sync,
3752 "Set composite sync signal to low (0) or high (1)");
3753 module_param(mode, charp, 0);
3754 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3756 module_param(nomtrr, bool, 0);
3757 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");