SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/config.h>
  53 #include <linux/module.h>
  54 #include <linux/moduleparam.h>
  55 #include <linux/kernel.h>
  56 #include <linux/errno.h>
  57 #include <linux/string.h>
  58 #include <linux/mm.h>
  59 #include <linux/slab.h>
  60 #include <linux/vmalloc.h>
  61 #include <linux/delay.h>
  62 #include <linux/console.h>
  63 #include <linux/fb.h>
  64 #include <linux/init.h>
  65 #include <linux/pci.h>
  66 #include <linux/interrupt.h>
  67 #include <linux/spinlock.h>
  68 #include <linux/wait.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/prom.h>
  79 #include "../macmodes.h"
  80 #endif
  81 #ifdef __sparc__
  82 #include <asm/pbm.h>
  83 #include <asm/fbio.h>
  84 #endif
  85
  86 #ifdef CONFIG_ADB_PMU
  87 #include <linux/adb.h>
  88 #include <linux/pmu.h>
  89 #endif
  90 #ifdef CONFIG_BOOTX_TEXT
  91 #include <asm/btext.h>
  92 #endif
  93 #ifdef CONFIG_PMAC_BACKLIGHT
  94 #include <asm/backlight.h>
  95 #endif
  96 #ifdef CONFIG_MTRR
  97 #include <asm/mtrr.h>
  98 #endif
  99
 100 /*
 101  * Debug flags.
 102  */
 103 #undef DEBUG
 104 /*#define DEBUG*/
 105
 106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 107 /*  - must be large enough to catch all GUI-Regs   */
 108 /*  - must be aligned to a PAGE boundary           */
 109 #define GUI_RESERVE     (1 * PAGE_SIZE)
 110
 111 /* FIXME: remove the FAIL definition */
 112 #define FAIL(msg) do { printk(KERN_CRIT "atyfb: " msg "\n"); return -EINVAL; } while (0)
 113 #define FAIL_MAX(msg, x, _max_) do { if(x > _max_) { printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); return -EINVAL; } } while (0)
 114
 115 #ifdef DEBUG
 116 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 117 #else
 118 #define DPRINTK(fmt, args...)
 119 #endif
 120
 121 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 122 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 123
 124 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 125 static const u32 lt_lcd_regs[] = {
 126         CONFIG_PANEL_LG,
 127         LCD_GEN_CNTL_LG,
 128         DSTN_CONTROL_LG,
 129         HFB_PITCH_ADDR_LG,
 130         HORZ_STRETCHING_LG,
 131         VERT_STRETCHING_LG,
 132         0, /* EXT_VERT_STRETCH */
 133         LT_GIO_LG,
 134         POWER_MANAGEMENT_LG
 135 };
 136
 137 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 138 {
 139         if (M64_HAS(LT_LCD_REGS)) {
 140                 aty_st_le32(lt_lcd_regs[index], val, par);
 141         } else {
 142                 unsigned long temp;
 143
 144                 /* write addr byte */
 145                 temp = aty_ld_le32(LCD_INDEX, par);
 146                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 147                 /* write the register value */
 148                 aty_st_le32(LCD_DATA, val, par);
 149         }
 150 }
 151
 152 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 153 {
 154         if (M64_HAS(LT_LCD_REGS)) {
 155                 return aty_ld_le32(lt_lcd_regs[index], par);
 156         } else {
 157                 unsigned long temp;
 158
 159                 /* write addr byte */
 160                 temp = aty_ld_le32(LCD_INDEX, par);
 161                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 162                 /* read the register value */
 163                 return aty_ld_le32(LCD_DATA, par);
 164         }
 165 }
 166 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 167
 168 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 169 /*
 170  * ATIReduceRatio --
 171  *
 172  * Reduce a fraction by factoring out the largest common divider of the
 173  * fraction's numerator and denominator.
 174  */
 175 static void ATIReduceRatio(int *Numerator, int *Denominator)
 176 {
 177     int Multiplier, Divider, Remainder;
 178
 179     Multiplier = *Numerator;
 180     Divider = *Denominator;
 181
 182     while ((Remainder = Multiplier % Divider))
 183     {
 184         Multiplier = Divider;
 185         Divider = Remainder;
 186     }
 187
 188     *Numerator /= Divider;
 189     *Denominator /= Divider;
 190 }
 191 #endif
 192     /*
 193      *  The Hardware parameters for each card
 194      */
 195
 196 struct aty_cmap_regs {
 197         u8 windex;
 198         u8 lut;
 199         u8 mask;
 200         u8 rindex;
 201         u8 cntl;
 202 };
 203
 204 struct pci_mmap_map {
 205         unsigned long voff;
 206         unsigned long poff;
 207         unsigned long size;
 208         unsigned long prot_flag;
 209         unsigned long prot_mask;
 210 };
 211
 212 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 213         .id             = "ATY Mach64",
 214         .type           = FB_TYPE_PACKED_PIXELS,
 215         .visual         = FB_VISUAL_PSEUDOCOLOR,
 216         .xpanstep       = 8,
 217         .ypanstep       = 1,
 218 };
 219
 220     /*
 221      *  Frame buffer device API
 222      */
 223
 224 static int atyfb_open(struct fb_info *info, int user);
 225 static int atyfb_release(struct fb_info *info, int user);
 226 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 227 static int atyfb_set_par(struct fb_info *info);
 228 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 229         u_int transp, struct fb_info *info);
 230 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 231 static int atyfb_blank(int blank, struct fb_info *info);
 232 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
 233         u_long arg, struct fb_info *info);
 234 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
 235 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 236 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
 237 #ifdef __sparc__
 238 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
 239 #endif
 240 static int atyfb_sync(struct fb_info *info);
 241
 242     /*
 243      *  Internal routines
 244      */
 245
 246 static int aty_init(struct fb_info *info, const char *name);
 247 #ifdef CONFIG_ATARI
 248 static int store_video_par(char *videopar, unsigned char m64_num);
 249 #endif
 250
 251 static struct crtc saved_crtc;
 252 static union aty_pll saved_pll;
 253 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 254
 255 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 256 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 257 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 258 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 259 #ifdef CONFIG_PPC
 260 static int read_aty_sense(const struct atyfb_par *par);
 261 #endif
 262
 263
 264     /*
 265      *  Interface used by the world
 266      */
 267
 268 static struct fb_var_screeninfo default_var = {
 269         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 270         640, 480, 640, 480, 0, 0, 8, 0,
 271         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 272         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 273         0, FB_VMODE_NONINTERLACED
 274 };
 275
 276 static struct fb_videomode defmode = {
 277         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 278         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 279         0, FB_VMODE_NONINTERLACED
 280 };
 281
 282 static struct fb_ops atyfb_ops = {
 283         .owner          = THIS_MODULE,
 284         .fb_open        = atyfb_open,
 285         .fb_release     = atyfb_release,
 286         .fb_check_var   = atyfb_check_var,
 287         .fb_set_par     = atyfb_set_par,
 288         .fb_setcolreg   = atyfb_setcolreg,
 289         .fb_pan_display = atyfb_pan_display,
 290         .fb_blank       = atyfb_blank,
 291         .fb_ioctl       = atyfb_ioctl,
 292         .fb_fillrect    = atyfb_fillrect,
 293         .fb_copyarea    = atyfb_copyarea,
 294         .fb_imageblit   = atyfb_imageblit,
 295 #ifdef __sparc__
 296         .fb_mmap        = atyfb_mmap,
 297 #endif
 298         .fb_sync        = atyfb_sync,
 299 };
 300
 301 static int noaccel;
 302 #ifdef CONFIG_MTRR
 303 static int nomtrr;
 304 #endif
 305 static int vram;
 306 static int pll;
 307 static int mclk;
 308 static int xclk;
 309 static int comp_sync __initdata = -1;
 310 static char *mode;
 311
 312 #ifdef CONFIG_PPC
 313 static int default_vmode __initdata = VMODE_CHOOSE;
 314 static int default_cmode __initdata = CMODE_CHOOSE;
 315
 316 module_param_named(vmode, default_vmode, int, 0);
 317 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 318 module_param_named(cmode, default_cmode, int, 0);
 319 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 320 #endif
 321
 322 #ifdef CONFIG_ATARI
 323 static unsigned int mach64_count __initdata = 0;
 324 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
 325 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
 326 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
 327 #endif
 328
 329 /* top -> down is an evolution of mach64 chipset, any corrections? */
 330 #define ATI_CHIP_88800GX   (M64F_GX)
 331 #define ATI_CHIP_88800CX   (M64F_GX)
 332
 333 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 334 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 335
 336 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 337 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 338
 339 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 340 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 341 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 342
 343 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 344
 345 /* make sets shorter */
 346 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 349 /*#define ATI_CHIP_264GTDVD  ?*/
 350 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 351
 352 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 353 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 354 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 355
 356 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 357 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 358
 359 static struct {
 360         u16 pci_id;
 361         const char *name;
 362         int pll, mclk, xclk;
 363         u32 features;
 364 } aty_chips[] __devinitdata = {
 365 #ifdef CONFIG_FB_ATY_GX
 366         /* Mach64 GX */
 367         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
 368         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
 369 #endif /* CONFIG_FB_ATY_GX */
 370
 371 #ifdef CONFIG_FB_ATY_CT
 372         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
 373         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
 374         { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
 375         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
 376         /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
 377         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB  },
 378         { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
 379
 380         { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
 381          /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
 382         { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 383
 384         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
 385
 386         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
 387         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
 388         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
 389         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
 390
 391         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
 392         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
 393         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 394         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
 395         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
 396
 397         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
 398         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
 399         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 400         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
 401         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
 402
 403         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
 404         { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
 405         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
 406         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 235, 83, 63, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 407         { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
 408         { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
 409
 410         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
 411         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
 412         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
 413         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
 414 #endif /* CONFIG_FB_ATY_CT */
 415 };
 416
 417 /* can not fail */
 418 static int __devinit correct_chipset(struct atyfb_par *par)
 419 {
 420         u8 rev;
 421         u16 type;
 422         u32 chip_id;
 423         const char *name;
 424         int i;
 425
 426         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
 427                 if (par->pci_id == aty_chips[i].pci_id)
 428                         break;
 429
 430         name = aty_chips[i].name;
 431         par->pll_limits.pll_max = aty_chips[i].pll;
 432         par->pll_limits.mclk = aty_chips[i].mclk;
 433         par->pll_limits.xclk = aty_chips[i].xclk;
 434         par->features = aty_chips[i].features;
 435
 436         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 437         type = chip_id & CFG_CHIP_TYPE;
 438         rev = (chip_id & CFG_CHIP_REV) >> 24;
 439
 440         switch(par->pci_id) {
 441 #ifdef CONFIG_FB_ATY_GX
 442         case PCI_CHIP_MACH64GX:
 443                 if(type != 0x00d7)
 444                         return -ENODEV;
 445                 break;
 446         case PCI_CHIP_MACH64CX:
 447                 if(type != 0x0057)
 448                         return -ENODEV;
 449                 break;
 450 #endif
 451 #ifdef CONFIG_FB_ATY_CT
 452         case PCI_CHIP_MACH64VT:
 453                 rev &= 0xc7;
 454                 if(rev == 0x00) {
 455                         name = "ATI264VTA3 (Mach64 VT)";
 456                         par->pll_limits.pll_max = 170;
 457                         par->pll_limits.mclk = 67;
 458                         par->pll_limits.xclk = 67;
 459                         par->features = ATI_CHIP_264VT;
 460                 } else if(rev == 0x40) {
 461                         name = "ATI264VTA4 (Mach64 VT)";
 462                         par->pll_limits.pll_max = 200;
 463                         par->pll_limits.mclk = 67;
 464                         par->pll_limits.xclk = 67;
 465                         par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 466                 } else {
 467                         name = "ATI264VTB (Mach64 VT)";
 468                         par->pll_limits.pll_max = 200;
 469                         par->pll_limits.mclk = 67;
 470                         par->pll_limits.xclk = 67;
 471                         par->features = ATI_CHIP_264VTB;
 472                 }
 473                 break;
 474         case PCI_CHIP_MACH64GT:
 475                 rev &= 0x07;
 476                 if(rev == 0x01) {
 477                         par->pll_limits.pll_max = 170;
 478                         par->pll_limits.mclk = 67;
 479                         par->pll_limits.xclk = 67;
 480                         par->features = ATI_CHIP_264GTB;
 481                 } else if(rev == 0x02) {
 482                         par->pll_limits.pll_max = 200;
 483                         par->pll_limits.mclk = 67;
 484                         par->pll_limits.xclk = 67;
 485                         par->features = ATI_CHIP_264GTB;
 486                 }
 487                 break;
 488 #endif
 489         }
 490
 491         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 492         return 0;
 493 }
 494
 495 static char ram_dram[] __devinitdata = "DRAM";
 496 static char ram_resv[] __devinitdata = "RESV";
 497 #ifdef CONFIG_FB_ATY_GX
 498 static char ram_vram[] __devinitdata = "VRAM";
 499 #endif /* CONFIG_FB_ATY_GX */
 500 #ifdef CONFIG_FB_ATY_CT
 501 static char ram_edo[] __devinitdata = "EDO";
 502 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 503 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 504 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 505 static char ram_off[] __devinitdata = "OFF";
 506 #endif /* CONFIG_FB_ATY_CT */
 507
 508
 509 static u32 pseudo_palette[17];
 510
 511 #ifdef CONFIG_FB_ATY_GX
 512 static char *aty_gx_ram[8] __devinitdata = {
 513         ram_dram, ram_vram, ram_vram, ram_dram,
 514         ram_dram, ram_vram, ram_vram, ram_resv
 515 };
 516 #endif /* CONFIG_FB_ATY_GX */
 517
 518 #ifdef CONFIG_FB_ATY_CT
 519 static char *aty_ct_ram[8] __devinitdata = {
 520         ram_off, ram_dram, ram_edo, ram_edo,
 521         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 522 };
 523 #endif /* CONFIG_FB_ATY_CT */
 524
 525 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 526 {
 527         u32 pixclock = var->pixclock;
 528 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 529         u32 lcd_on_off;
 530         par->pll.ct.xres = 0;
 531         if (par->lcd_table != 0) {
 532                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 533                 if(lcd_on_off & LCD_ON) {
 534                         par->pll.ct.xres = var->xres;
 535                         pixclock = par->lcd_pixclock;
 536                 }
 537         }
 538 #endif
 539         return pixclock;
 540 }
 541
 542 #if defined(CONFIG_PPC)
 543
 544 /*
 545  *  Apple monitor sense
 546  */
 547
 548 static int __init read_aty_sense(const struct atyfb_par *par)
 549 {
 550         int sense, i;
 551
 552         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 553         __delay(200);
 554         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 555         __delay(2000);
 556         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 557         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 558
 559         /* drive each sense line low in turn and collect the other 2 */
 560         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 561         __delay(2000);
 562         i = aty_ld_le32(GP_IO, par);
 563         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 564         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 565         __delay(200);
 566
 567         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 568         __delay(2000);
 569         i = aty_ld_le32(GP_IO, par);
 570         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 571         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 572         __delay(200);
 573
 574         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 575         __delay(2000);
 576         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 577         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 578         return sense;
 579 }
 580
 581 #endif /* defined(CONFIG_PPC) */
 582
 583 /* ------------------------------------------------------------------------- */
 584
 585 /*
 586  *  CRTC programming
 587  */
 588
 589 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 590 {
 591 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 592         if (par->lcd_table != 0) {
 593                 if(!M64_HAS(LT_LCD_REGS)) {
 594                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 595                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 596                 }
 597                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 598                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 599
 600
 601                 /* switch to non shadow registers */
 602                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 603                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 604
 605                 /* save stretching */
 606                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 607                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 608                 if (!M64_HAS(LT_LCD_REGS))
 609                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 610         }
 611 #endif
 612         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 613         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 614         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 615         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 616         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 617         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 618         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 619
 620 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 621         if (par->lcd_table != 0) {
 622                 /* switch to shadow registers */
 623                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 624                         SHADOW_EN | SHADOW_RW_EN, par);
 625
 626                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 627                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 628                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 629                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 630
 631                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 632         }
 633 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 634 }
 635
 636 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 637 {
 638 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 639         if (par->lcd_table != 0) {
 640                 /* stop CRTC */
 641                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 642
 643                 /* update non-shadow registers first */
 644                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 645                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 646                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 647
 648                 /* temporarily disable stretching */
 649                 aty_st_lcd(HORZ_STRETCHING,
 650                         crtc->horz_stretching &
 651                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 652                 aty_st_lcd(VERT_STRETCHING,
 653                         crtc->vert_stretching &
 654                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 655                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 656         }
 657 #endif
 658         /* turn off CRT */
 659         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 660
 661         DPRINTK("setting up CRTC\n");
 662         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 663             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 664             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 665             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 666
 667         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 668         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 669         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 670         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 671         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 672         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 673         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 674
 675         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 676         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 677         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 678         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 679         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 680         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 681
 682         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 683 #if 0
 684         FIXME
 685         if (par->accel_flags & FB_ACCELF_TEXT)
 686                 aty_init_engine(par, info);
 687 #endif
 688 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 689         /* after setting the CRTC registers we should set the LCD registers. */
 690         if (par->lcd_table != 0) {
 691                 /* switch to shadow registers */
 692                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 693                         (SHADOW_EN | SHADOW_RW_EN), par);
 694
 695                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 696                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 697                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 698
 699                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 700                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 701                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 702                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 703
 704                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 705                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 706                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 707                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 708
 709                 /* restore CRTC selection & shadow state and enable stretching */
 710                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 711                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 712                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 713                 if(!M64_HAS(LT_LCD_REGS))
 714                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 715
 716                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 717                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 718                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 719                 if(!M64_HAS(LT_LCD_REGS)) {
 720                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 721                     aty_ld_le32(LCD_INDEX, par);
 722                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 723                 }
 724         }
 725 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 726 }
 727
 728 static int aty_var_to_crtc(const struct fb_info *info,
 729         const struct fb_var_screeninfo *var, struct crtc *crtc)
 730 {
 731         struct atyfb_par *par = (struct atyfb_par *) info->par;
 732         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 733         u32 sync, vmode, vdisplay;
 734         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 735         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 736         u32 pix_width, dp_pix_width, dp_chain_mask;
 737
 738         /* input */
 739         xres = var->xres;
 740         yres = var->yres;
 741         vxres = var->xres_virtual;
 742         vyres = var->yres_virtual;
 743         xoffset = var->xoffset;
 744         yoffset = var->yoffset;
 745         bpp = var->bits_per_pixel;
 746         if (bpp == 16)
 747                 bpp = (var->green.length == 5) ? 15 : 16;
 748         sync = var->sync;
 749         vmode = var->vmode;
 750
 751         /* convert (and round up) and validate */
 752         if (vxres < xres + xoffset)
 753                 vxres = xres + xoffset;
 754         h_disp = xres;
 755
 756         if (vyres < yres + yoffset)
 757                 vyres = yres + yoffset;
 758         v_disp = yres;
 759
 760         if (bpp <= 8) {
 761                 bpp = 8;
 762                 pix_width = CRTC_PIX_WIDTH_8BPP;
 763                 dp_pix_width =
 764                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 765                     BYTE_ORDER_LSB_TO_MSB;
 766                 dp_chain_mask = DP_CHAIN_8BPP;
 767         } else if (bpp <= 15) {
 768                 bpp = 16;
 769                 pix_width = CRTC_PIX_WIDTH_15BPP;
 770                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 771                     BYTE_ORDER_LSB_TO_MSB;
 772                 dp_chain_mask = DP_CHAIN_15BPP;
 773         } else if (bpp <= 16) {
 774                 bpp = 16;
 775                 pix_width = CRTC_PIX_WIDTH_16BPP;
 776                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 777                     BYTE_ORDER_LSB_TO_MSB;
 778                 dp_chain_mask = DP_CHAIN_16BPP;
 779         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 780                 bpp = 24;
 781                 pix_width = CRTC_PIX_WIDTH_24BPP;
 782                 dp_pix_width =
 783                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 784                     BYTE_ORDER_LSB_TO_MSB;
 785                 dp_chain_mask = DP_CHAIN_24BPP;
 786         } else if (bpp <= 32) {
 787                 bpp = 32;
 788                 pix_width = CRTC_PIX_WIDTH_32BPP;
 789                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 790                     BYTE_ORDER_LSB_TO_MSB;
 791                 dp_chain_mask = DP_CHAIN_32BPP;
 792         } else
 793                 FAIL("invalid bpp");
 794
 795         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 796                 FAIL("not enough video RAM");
 797
 798         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 799         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 800
 801         if((xres > 1600) || (yres > 1200)) {
 802                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 803                 "select anoter resolution.");
 804         }
 805         h_sync_strt = h_disp + var->right_margin;
 806         h_sync_end = h_sync_strt + var->hsync_len;
 807         h_sync_dly  = var->right_margin & 7;
 808         h_total = h_sync_end + h_sync_dly + var->left_margin;
 809
 810         v_sync_strt = v_disp + var->lower_margin;
 811         v_sync_end = v_sync_strt + var->vsync_len;
 812         v_total = v_sync_end + var->upper_margin;
 813
 814 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 815         if (par->lcd_table != 0) {
 816                 if(!M64_HAS(LT_LCD_REGS)) {
 817                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 818                     crtc->lcd_index = lcd_index &
 819                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 820                     aty_st_le32(LCD_INDEX, lcd_index, par);
 821                 }
 822
 823                 if (!M64_HAS(MOBIL_BUS))
 824                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 825
 826                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 827                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 828
 829                 crtc->lcd_gen_cntl &=
 830                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 831                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 832                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 833                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 834
 835                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 836                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 837                         /* We cannot display the mode on the LCD. If the CRT is enabled
 838                            we can turn off the LCD.
 839                            If the CRT is off, it isn't a good idea to switch it on; we don't
 840                            know if one is connected. So it's better to fail then.
 841                          */
 842                         if (crtc->lcd_gen_cntl & CRT_ON) {
 843                                 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 844                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 845                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 846                         } else {
 847                                 FAIL("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.");
 848                         }
 849                 }
 850         }
 851
 852         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 853                 int VScan = 1;
 854                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 855                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 856                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 857
 858                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 859
 860                 /* This is horror! When we simulate, say 640x480 on an 800x600
 861                    LCD monitor, the CRTC should be programmed 800x600 values for
 862                    the non visible part, but 640x480 for the visible part.
 863                    This code has been tested on a laptop with it's 1400x1050 LCD
 864                    monitor and a conventional monitor both switched on.
 865                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 866                     works with little glitches also with DOUBLESCAN modes
 867                  */
 868                 if (yres < par->lcd_height) {
 869                         VScan = par->lcd_height / yres;
 870                         if(VScan > 1) {
 871                                 VScan = 2;
 872                                 vmode |= FB_VMODE_DOUBLE;
 873                         }
 874                 }
 875
 876                 h_sync_strt = h_disp + par->lcd_right_margin;
 877                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 878                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 879                 h_total = h_disp + par->lcd_hblank_len;
 880
 881                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 882                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 883                 v_total = v_disp + par->lcd_vblank_len / VScan;
 884         }
 885 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 886
 887         h_disp = (h_disp >> 3) - 1;
 888         h_sync_strt = (h_sync_strt >> 3) - 1;
 889         h_sync_end = (h_sync_end >> 3) - 1;
 890         h_total = (h_total >> 3) - 1;
 891         h_sync_wid = h_sync_end - h_sync_strt;
 892
 893         FAIL_MAX("h_disp too large", h_disp, 0xff);
 894         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 895         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 896         if(h_sync_wid > 0x1f)
 897                 h_sync_wid = 0x1f;
 898         FAIL_MAX("h_total too large", h_total, 0x1ff);
 899
 900         if (vmode & FB_VMODE_DOUBLE) {
 901                 v_disp <<= 1;
 902                 v_sync_strt <<= 1;
 903                 v_sync_end <<= 1;
 904                 v_total <<= 1;
 905         }
 906
 907         vdisplay = yres;
 908 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 909         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 910                 vdisplay  = par->lcd_height;
 911 #endif
 912
 913         v_disp--;
 914         v_sync_strt--;
 915         v_sync_end--;
 916         v_total--;
 917         v_sync_wid = v_sync_end - v_sync_strt;
 918
 919         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 920         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 921         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 922         if(v_sync_wid > 0x1f)
 923                 v_sync_wid = 0x1f;
 924         FAIL_MAX("v_total too large", v_total, 0x7ff);
 925
 926         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 927
 928         /* output */
 929         crtc->vxres = vxres;
 930         crtc->vyres = vyres;
 931         crtc->xoffset = xoffset;
 932         crtc->yoffset = yoffset;
 933         crtc->bpp = bpp;
 934         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 935         crtc->vline_crnt_vline = 0;
 936
 937         crtc->h_tot_disp = h_total | (h_disp<<16);
 938         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 939                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 940         crtc->v_tot_disp = v_total | (v_disp<<16);
 941         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 942
 943         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 944         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 945         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 946
 947         /* Enable doublescan mode if requested */
 948         if (vmode & FB_VMODE_DOUBLE)
 949                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 950         /* Enable interlaced mode if requested */
 951         if (vmode & FB_VMODE_INTERLACED)
 952                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 953 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 954         if (par->lcd_table != 0) {
 955                 vdisplay = yres;
 956                 if(vmode & FB_VMODE_DOUBLE)
 957                         vdisplay <<= 1;
 958                 if(vmode & FB_VMODE_INTERLACED) {
 959                         vdisplay >>= 1;
 960
 961                         /* The prefered mode for the LCD is not interlaced, so disable it if
 962                            it was enabled. For doublescan there is no problem, because we can
 963                            compensate for it in the hardware stretching (we stretch half as much)
 964                          */
 965                         vmode &= ~FB_VMODE_INTERLACED;
 966                         /*crtc->gen_cntl &= ~CRTC_INTERLACE_EN;*/
 967                 }
 968                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 969                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
 970                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
 971                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 972                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
 973
 974                 /* MOBILITY M1 tested, FIXME: LT */
 975                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 976                 if (!M64_HAS(LT_LCD_REGS))
 977                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
 978                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
 979
 980                 crtc->horz_stretching &=
 981                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
 982                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
 983                 if (xres < par->lcd_width) {
 984                         do {
 985                                 /*
 986                                 * The horizontal blender misbehaves when HDisplay is less than a
 987                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
 988                                 * stretch such modes enough.  Use pixel replication instead of
 989                                 * blending to stretch modes that can be made to exactly fit the
 990                                 * panel width.  The undocumented "NoLCDBlend" option allows the
 991                                 * pixel-replicated mode to be slightly wider or narrower than the
 992                                 * panel width.  It also causes a mode that is exactly half as wide
 993                                 * as the panel to be pixel-replicated, rather than blended.
 994                                 */
 995                                 int HDisplay  = xres & ~7;
 996                                 int nStretch  = par->lcd_width / HDisplay;
 997                                 int Remainder = par->lcd_width % HDisplay;
 998
 999                                 if ((!Remainder && ((nStretch > 2))) ||
1000                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1001                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1002                                         int horz_stretch_loop = -1, BestRemainder;
1003                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1004                                         int Index = 5;
1005                                         ATIReduceRatio(&Numerator, &Denominator);
1006
1007                                         BestRemainder = (Numerator * 16) / Denominator;
1008                                         while (--Index >= 0) {
1009                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1010                                                         Denominator;
1011                                                 if (Remainder < BestRemainder) {
1012                                                         horz_stretch_loop = Index;
1013                                                         if (!(BestRemainder = Remainder))
1014                                                                 break;
1015                                                 }
1016                                         }
1017
1018                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1019                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1020                                                 int reuse_previous = 1;
1021
1022                                                 Index = StretchLoops[horz_stretch_loop];
1023
1024                                                 while (--Index >= 0) {
1025                                                         if (Accumulator > 0)
1026                                                                 horz_stretch_ratio |= reuse_previous;
1027                                                         else
1028                                                                 Accumulator += Denominator;
1029                                                         Accumulator -= Numerator;
1030                                                         reuse_previous <<= 1;
1031                                                 }
1032
1033                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1034                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1035                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1036                                                 break;      /* Out of the do { ... } while (0) */
1037                                         }
1038                                 }
1039
1040                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1041                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1042                         } while (0);
1043                 }
1044
1045                 if (vdisplay < par->lcd_height) {
1046                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1047                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1048
1049                         if (!M64_HAS(LT_LCD_REGS) &&
1050                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1051                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1052                 } else {
1053                         /*
1054                          * Don't use vertical blending if the mode is too wide or not
1055                          * vertically stretched.
1056                          */
1057                         crtc->vert_stretching = 0;
1058                 }
1059                 /* copy to shadow crtc */
1060                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1061                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1062                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1063                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1064         }
1065 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1066
1067         if (M64_HAS(MAGIC_FIFO)) {
1068                 /* Not VTB/GTB */
1069                 /* FIXME: magic FIFO values */
1070                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC2_PIX_WIDTH);
1071         }
1072         crtc->dp_pix_width = dp_pix_width;
1073         crtc->dp_chain_mask = dp_chain_mask;
1074
1075         return 0;
1076 }
1077
1078 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1079 {
1080         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1081         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1082             h_sync_pol;
1083         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1084         u32 pix_width;
1085         u32 double_scan, interlace;
1086
1087         /* input */
1088         h_total = crtc->h_tot_disp & 0x1ff;
1089         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1090         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1091         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1092         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1093         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1094         v_total = crtc->v_tot_disp & 0x7ff;
1095         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1096         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1097         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1098         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1099         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1100         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1101         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1102         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1103
1104         /* convert */
1105         xres = (h_disp + 1) * 8;
1106         yres = v_disp + 1;
1107         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1108         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1109         hslen = h_sync_wid * 8;
1110         upper = v_total - v_sync_strt - v_sync_wid;
1111         lower = v_sync_strt - v_disp;
1112         vslen = v_sync_wid;
1113         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1114             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1115             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1116
1117         switch (pix_width) {
1118 #if 0
1119         case CRTC_PIX_WIDTH_4BPP:
1120                 bpp = 4;
1121                 var->red.offset = 0;
1122                 var->red.length = 8;
1123                 var->green.offset = 0;
1124                 var->green.length = 8;
1125                 var->blue.offset = 0;
1126                 var->blue.length = 8;
1127                 var->transp.offset = 0;
1128                 var->transp.length = 0;
1129                 break;
1130 #endif
1131         case CRTC_PIX_WIDTH_8BPP:
1132                 bpp = 8;
1133                 var->red.offset = 0;
1134                 var->red.length = 8;
1135                 var->green.offset = 0;
1136                 var->green.length = 8;
1137                 var->blue.offset = 0;
1138                 var->blue.length = 8;
1139                 var->transp.offset = 0;
1140                 var->transp.length = 0;
1141                 break;
1142         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1143                 bpp = 16;
1144                 var->red.offset = 10;
1145                 var->red.length = 5;
1146                 var->green.offset = 5;
1147                 var->green.length = 5;
1148                 var->blue.offset = 0;
1149                 var->blue.length = 5;
1150                 var->transp.offset = 0;
1151                 var->transp.length = 0;
1152                 break;
1153         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1154                 bpp = 16;
1155                 var->red.offset = 11;
1156                 var->red.length = 5;
1157                 var->green.offset = 5;
1158                 var->green.length = 6;
1159                 var->blue.offset = 0;
1160                 var->blue.length = 5;
1161                 var->transp.offset = 0;
1162                 var->transp.length = 0;
1163                 break;
1164         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1165                 bpp = 24;
1166                 var->red.offset = 16;
1167                 var->red.length = 8;
1168                 var->green.offset = 8;
1169                 var->green.length = 8;
1170                 var->blue.offset = 0;
1171                 var->blue.length = 8;
1172                 var->transp.offset = 0;
1173                 var->transp.length = 0;
1174                 break;
1175         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1176                 bpp = 32;
1177                 var->red.offset = 16;
1178                 var->red.length = 8;
1179                 var->green.offset = 8;
1180                 var->green.length = 8;
1181                 var->blue.offset = 0;
1182                 var->blue.length = 8;
1183                 var->transp.offset = 24;
1184                 var->transp.length = 8;
1185                 break;
1186         default:
1187                 FAIL("Invalid pixel width");
1188         }
1189
1190         /* output */
1191         var->xres = xres;
1192         var->yres = yres;
1193         var->xres_virtual = crtc->vxres;
1194         var->yres_virtual = crtc->vyres;
1195         var->bits_per_pixel = bpp;
1196         var->left_margin = left;
1197         var->right_margin = right;
1198         var->upper_margin = upper;
1199         var->lower_margin = lower;
1200         var->hsync_len = hslen;
1201         var->vsync_len = vslen;
1202         var->sync = sync;
1203         var->vmode = FB_VMODE_NONINTERLACED;
1204         /* In double scan mode, the vertical parameters are doubled, so we need to
1205            half them to get the right values.
1206            In interlaced mode the values are already correct, so no correction is
1207            necessary.
1208          */
1209         if (interlace)
1210                 var->vmode = FB_VMODE_INTERLACED;
1211
1212         if (double_scan) {
1213                 var->vmode = FB_VMODE_DOUBLE;
1214                 var->yres>>=1;
1215                 var->upper_margin>>=1;
1216                 var->lower_margin>>=1;
1217                 var->vsync_len>>=1;
1218         }
1219
1220         return 0;
1221 }
1222
1223 /* ------------------------------------------------------------------------- */
1224
1225 static int atyfb_set_par(struct fb_info *info)
1226 {
1227         struct atyfb_par *par = (struct atyfb_par *) info->par;
1228         struct fb_var_screeninfo *var = &info->var;
1229         u32 tmp, pixclock;
1230         int err;
1231 #ifdef DEBUG
1232         struct fb_var_screeninfo debug;
1233         u32 pixclock_in_ps;
1234 #endif
1235         if (par->asleep)
1236                 return 0;
1237
1238         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1239                 return err;
1240
1241         pixclock = atyfb_get_pixclock(var, par);
1242
1243         if (pixclock == 0) {
1244                 FAIL("Invalid pixclock");
1245         } else {
1246                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1247                         return err;
1248         }
1249
1250         par->accel_flags = var->accel_flags; /* hack */
1251
1252         if (par->blitter_may_be_busy)
1253                 wait_for_idle(par);
1254
1255         aty_set_crtc(par, &par->crtc);
1256         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1257         par->pll_ops->set_pll(info, &par->pll);
1258
1259 #ifdef DEBUG
1260         if(par->pll_ops && par->pll_ops->pll_to_var)
1261                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1262         else
1263                 pixclock_in_ps = 0;
1264
1265         if(0 == pixclock_in_ps) {
1266                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1267                 pixclock_in_ps = pixclock;
1268         }
1269
1270         memset(&debug, 0, sizeof(debug));
1271         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1272                 u32 hSync, vRefresh;
1273                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1274                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1275
1276                 h_disp = debug.xres;
1277                 h_sync_strt = h_disp + debug.right_margin;
1278                 h_sync_end = h_sync_strt + debug.hsync_len;
1279                 h_total = h_sync_end + debug.left_margin;
1280                 v_disp = debug.yres;
1281                 v_sync_strt = v_disp + debug.lower_margin;
1282                 v_sync_end = v_sync_strt + debug.vsync_len;
1283                 v_total = v_sync_end + debug.upper_margin;
1284
1285                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1286                 vRefresh = (hSync * 1000) / v_total;
1287                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1288                 vRefresh *= 2;
1289                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1290                 vRefresh /= 2;
1291
1292                 DPRINTK("atyfb_set_par\n");
1293                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1294                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1295                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1296                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1297                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1298                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1299                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1300                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1301                         h_disp, h_sync_strt, h_sync_end, h_total,
1302                         v_disp, v_sync_strt, v_sync_end, v_total);
1303                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1304                         pixclock_in_ps,
1305                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1306                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1307         }
1308 #endif /* DEBUG */
1309
1310         if (!M64_HAS(INTEGRATED)) {
1311                 /* Don't forget MEM_CNTL */
1312                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1313                 switch (var->bits_per_pixel) {
1314                 case 8:
1315                         tmp |= 0x02000000;
1316                         break;
1317                 case 16:
1318                         tmp |= 0x03000000;
1319                         break;
1320                 case 32:
1321                         tmp |= 0x06000000;
1322                         break;
1323                 }
1324                 aty_st_le32(MEM_CNTL, tmp, par);
1325         } else {
1326                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1327                 if (!M64_HAS(MAGIC_POSTDIV))
1328                         tmp |= par->mem_refresh_rate << 20;
1329                 switch (var->bits_per_pixel) {
1330                 case 8:
1331                 case 24:
1332                         tmp |= 0x00000000;
1333                         break;
1334                 case 16:
1335                         tmp |= 0x04000000;
1336                         break;
1337                 case 32:
1338                         tmp |= 0x08000000;
1339                         break;
1340                 }
1341                 if (M64_HAS(CT_BUS)) {
1342                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1343                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1344                 } else if (M64_HAS(VT_BUS)) {
1345                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1346                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1347                 } else if (M64_HAS(MOBIL_BUS)) {
1348                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1349                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1350                 } else {
1351                         /* GT */
1352                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1353                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1354                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1355                 }
1356                 aty_st_le32(MEM_CNTL, tmp, par);
1357         }
1358         aty_st_8(DAC_MASK, 0xff, par);
1359
1360         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1361         info->fix.visual = var->bits_per_pixel <= 8 ?
1362                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1363
1364         /* Initialize the graphics engine */
1365         if (par->accel_flags & FB_ACCELF_TEXT)
1366                 aty_init_engine(par, info);
1367
1368 #ifdef CONFIG_BOOTX_TEXT
1369         btext_update_display(info->fix.smem_start,
1370                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1371                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1372                 var->bits_per_pixel,
1373                 par->crtc.vxres * var->bits_per_pixel / 8);
1374 #endif /* CONFIG_BOOTX_TEXT */
1375 #if 0
1376         /* switch to accelerator mode */
1377         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1378                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1379 #endif
1380 #ifdef DEBUG
1381 {
1382         /* dump non shadow CRTC, pll, LCD registers */
1383         int i; u32 base;
1384
1385         /* CRTC registers */
1386         base = 0x2000;
1387         printk("debug atyfb: Mach64 non-shadow register values:");
1388         for (i = 0; i < 256; i = i+4) {
1389                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1390                 printk(" %08X", aty_ld_le32(i, par));
1391         }
1392         printk("\n\n");
1393
1394 #ifdef CONFIG_FB_ATY_CT
1395         /* PLL registers */
1396         base = 0x00;
1397         printk("debug atyfb: Mach64 PLL register values:");
1398         for (i = 0; i < 64; i++) {
1399                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1400                 if(i%4 == 0)  printk(" ");
1401                 printk("%02X", aty_ld_pll_ct(i, par));
1402         }
1403         printk("\n\n");
1404 #endif  /* CONFIG_FB_ATY_CT */
1405
1406 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1407         if (par->lcd_table != 0) {
1408                 /* LCD registers */
1409                 base = 0x00;
1410                 printk("debug atyfb: LCD register values:");
1411                 if(M64_HAS(LT_LCD_REGS)) {
1412                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1413                         if(i == EXT_VERT_STRETCH)
1414                             continue;
1415                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1416                         printk(" %08X", aty_ld_lcd(i, par));
1417                     }
1418
1419                 } else {
1420                     for (i = 0; i < 64; i++) {
1421                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1422                         printk(" %08X", aty_ld_lcd(i, par));
1423                     }
1424                 }
1425                 printk("\n\n");
1426         }
1427 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1428 }
1429 #endif /* DEBUG */
1430         return 0;
1431 }
1432
1433 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1434 {
1435         struct atyfb_par *par = (struct atyfb_par *) info->par;
1436         int err;
1437         struct crtc crtc;
1438         union aty_pll pll;
1439         u32 pixclock;
1440
1441         memcpy(&pll, &(par->pll), sizeof(pll));
1442
1443         if((err = aty_var_to_crtc(info, var, &crtc)))
1444                 return err;
1445
1446         pixclock = atyfb_get_pixclock(var, par);
1447
1448         if (pixclock == 0) {
1449                 FAIL("Invalid pixclock");
1450         } else {
1451                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1452                         return err;
1453         }
1454
1455         if (var->accel_flags & FB_ACCELF_TEXT)
1456                 info->var.accel_flags = FB_ACCELF_TEXT;
1457         else
1458                 info->var.accel_flags = 0;
1459
1460 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1461         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1462                 return -EINVAL;
1463 #endif
1464         aty_crtc_to_var(&crtc, var);
1465         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1466         return 0;
1467 }
1468
1469 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1470 {
1471         u32 xoffset = info->var.xoffset;
1472         u32 yoffset = info->var.yoffset;
1473         u32 vxres = par->crtc.vxres;
1474         u32 bpp = info->var.bits_per_pixel;
1475
1476         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1477 }
1478
1479
1480     /*
1481      *  Open/Release the frame buffer device
1482      */
1483
1484 static int atyfb_open(struct fb_info *info, int user)
1485 {
1486         struct atyfb_par *par = (struct atyfb_par *) info->par;
1487
1488         if (user) {
1489                 par->open++;
1490 #ifdef __sparc__
1491                 par->mmaped = 0;
1492 #endif
1493         }
1494         return (0);
1495 }
1496
1497 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1498 {
1499         struct atyfb_par *par = dev_id;
1500         int handled = 0;
1501         u32 int_cntl;
1502
1503         spin_lock(&par->int_lock);
1504
1505         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1506
1507         if (int_cntl & CRTC_VBLANK_INT) {
1508                 /* clear interrupt */
1509                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1510                 par->vblank.count++;
1511                 if (par->vblank.pan_display) {
1512                         par->vblank.pan_display = 0;
1513                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1514                 }
1515                 wake_up_interruptible(&par->vblank.wait);
1516                 handled = 1;
1517         }
1518
1519         spin_unlock(&par->int_lock);
1520
1521         return IRQ_RETVAL(handled);
1522 }
1523
1524 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1525 {
1526         u32 int_cntl;
1527
1528         if (!test_and_set_bit(0, &par->irq_flags)) {
1529                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1530                         clear_bit(0, &par->irq_flags);
1531                         return -EINVAL;
1532                 }
1533                 spin_lock_irq(&par->int_lock);
1534                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1535                 /* clear interrupt */
1536                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1537                 /* enable interrupt */
1538                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1539                 spin_unlock_irq(&par->int_lock);
1540         } else if (reenable) {
1541                 spin_lock_irq(&par->int_lock);
1542                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1543                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1544                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1545                         /* re-enable interrupt */
1546                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1547                 }
1548                 spin_unlock_irq(&par->int_lock);
1549         }
1550
1551         return 0;
1552 }
1553
1554 static int aty_disable_irq(struct atyfb_par *par)
1555 {
1556         u32 int_cntl;
1557
1558         if (test_and_clear_bit(0, &par->irq_flags)) {
1559                 if (par->vblank.pan_display) {
1560                         par->vblank.pan_display = 0;
1561                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1562                 }
1563                 spin_lock_irq(&par->int_lock);
1564                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1565                 /* disable interrupt */
1566                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1567                 spin_unlock_irq(&par->int_lock);
1568                 free_irq(par->irq, par);
1569         }
1570
1571         return 0;
1572 }
1573
1574 static int atyfb_release(struct fb_info *info, int user)
1575 {
1576         struct atyfb_par *par = (struct atyfb_par *) info->par;
1577         if (user) {
1578                 par->open--;
1579                 mdelay(1);
1580                 wait_for_idle(par);
1581                 if (!par->open) {
1582 #ifdef __sparc__
1583                         int was_mmaped = par->mmaped;
1584
1585                         par->mmaped = 0;
1586
1587                         if (was_mmaped) {
1588                                 struct fb_var_screeninfo var;
1589
1590                                 /* Now reset the default display config, we have no
1591                                  * idea what the program(s) which mmap'd the chip did
1592                                  * to the configuration, nor whether it restored it
1593                                  * correctly.
1594                                  */
1595                                 var = default_var;
1596                                 if (noaccel)
1597                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1598                                 else
1599                                         var.accel_flags |= FB_ACCELF_TEXT;
1600                                 if (var.yres == var.yres_virtual) {
1601                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1602                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1603                                         if (var.yres_virtual < var.yres)
1604                                                 var.yres_virtual = var.yres;
1605                                 }
1606                         }
1607 #endif
1608                         aty_disable_irq(par);
1609                 }
1610         }
1611         return (0);
1612 }
1613
1614     /*
1615      *  Pan or Wrap the Display
1616      *
1617      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1618      */
1619
1620 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1621 {
1622         struct atyfb_par *par = (struct atyfb_par *) info->par;
1623         u32 xres, yres, xoffset, yoffset;
1624
1625         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1626         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1627         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1628                 yres >>= 1;
1629         xoffset = (var->xoffset + 7) & ~7;
1630         yoffset = var->yoffset;
1631         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1632                 return -EINVAL;
1633         info->var.xoffset = xoffset;
1634         info->var.yoffset = yoffset;
1635         if (par->asleep)
1636                 return 0;
1637
1638         set_off_pitch(par, info);
1639         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1640                 par->vblank.pan_display = 1;
1641         } else {
1642                 par->vblank.pan_display = 0;
1643                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1644         }
1645
1646         return 0;
1647 }
1648
1649 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1650 {
1651         struct aty_interrupt *vbl;
1652         unsigned int count;
1653         int ret;
1654
1655         switch (crtc) {
1656         case 0:
1657                 vbl = &par->vblank;
1658                 break;
1659         default:
1660                 return -ENODEV;
1661         }
1662
1663         ret = aty_enable_irq(par, 0);
1664         if (ret)
1665                 return ret;
1666
1667         count = vbl->count;
1668         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1669         if (ret < 0) {
1670                 return ret;
1671         }
1672         if (ret == 0) {
1673                 aty_enable_irq(par, 1);
1674                 return -ETIMEDOUT;
1675         }
1676
1677         return 0;
1678 }
1679
1680
1681 #ifdef DEBUG
1682 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1683 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1684
1685 struct atyclk {
1686         u32 ref_clk_per;
1687         u8 pll_ref_div;
1688         u8 mclk_fb_div;
1689         u8 mclk_post_div;       /* 1,2,3,4,8 */
1690         u8 mclk_fb_mult;        /* 2 or 4 */
1691         u8 xclk_post_div;       /* 1,2,3,4,8 */
1692         u8 vclk_fb_div;
1693         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1694         u32 dsp_xclks_per_row;  /* 0-16383 */
1695         u32 dsp_loop_latency;   /* 0-15 */
1696         u32 dsp_precision;      /* 0-7 */
1697         u32 dsp_on;             /* 0-2047 */
1698         u32 dsp_off;            /* 0-2047 */
1699 };
1700
1701 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1702 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1703 #endif
1704
1705 #ifndef FBIO_WAITFORVSYNC
1706 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1707 #endif
1708
1709 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1710         u_long arg, struct fb_info *info)
1711 {
1712         struct atyfb_par *par = (struct atyfb_par *) info->par;
1713 #ifdef __sparc__
1714         struct fbtype fbtyp;
1715 #endif
1716
1717         switch (cmd) {
1718 #ifdef __sparc__
1719         case FBIOGTYPE:
1720                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1721                 fbtyp.fb_width = par->crtc.vxres;
1722                 fbtyp.fb_height = par->crtc.vyres;
1723                 fbtyp.fb_depth = info->var.bits_per_pixel;
1724                 fbtyp.fb_cmsize = info->cmap.len;
1725                 fbtyp.fb_size = info->fix.smem_len;
1726                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1727                         return -EFAULT;
1728                 break;
1729 #endif /* __sparc__ */
1730
1731         case FBIO_WAITFORVSYNC:
1732                 {
1733                         u32 crtc;
1734
1735                         if (get_user(crtc, (__u32 __user *) arg))
1736                                 return -EFAULT;
1737
1738                         return aty_waitforvblank(par, crtc);
1739                 }
1740                 break;
1741
1742 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1743         case ATYIO_CLKR:
1744                 if (M64_HAS(INTEGRATED)) {
1745                         struct atyclk clk;
1746                         union aty_pll *pll = &(par->pll);
1747                         u32 dsp_config = pll->ct.dsp_config;
1748                         u32 dsp_on_off = pll->ct.dsp_on_off;
1749                         clk.ref_clk_per = par->ref_clk_per;
1750                         clk.pll_ref_div = pll->ct.pll_ref_div;
1751                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1752                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1753                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1754                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1755                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1756                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1757                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1758                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1759                         clk.dsp_precision = (dsp_config >> 20) & 7;
1760                         clk.dsp_off = dsp_on_off & 0x7ff;
1761                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1762                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1763                                          sizeof(clk)))
1764                                 return -EFAULT;
1765                 } else
1766                         return -EINVAL;
1767                 break;
1768         case ATYIO_CLKW:
1769                 if (M64_HAS(INTEGRATED)) {
1770                         struct atyclk clk;
1771                         union aty_pll *pll = &(par->pll);
1772                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1773                                 return -EFAULT;
1774                         par->ref_clk_per = clk.ref_clk_per;
1775                         pll->ct.pll_ref_div = clk.pll_ref_div;
1776                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1777                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1778                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1779                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1780                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1781                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1782                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1783                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1784                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1785                         /*aty_calc_pll_ct(info, &pll->ct);*/
1786                         aty_set_pll_ct(info, pll);
1787                 } else
1788                         return -EINVAL;
1789                 break;
1790         case ATYIO_FEATR:
1791                 if (get_user(par->features, (u32 __user *) arg))
1792                         return -EFAULT;
1793                 break;
1794         case ATYIO_FEATW:
1795                 if (put_user(par->features, (u32 __user *) arg))
1796                         return -EFAULT;
1797                 break;
1798 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1799         default:
1800                 return -EINVAL;
1801         }
1802         return 0;
1803 }
1804
1805 static int atyfb_sync(struct fb_info *info)
1806 {
1807         struct atyfb_par *par = (struct atyfb_par *) info->par;
1808
1809         if (par->blitter_may_be_busy)
1810                 wait_for_idle(par);
1811         return 0;
1812 }
1813
1814 #ifdef __sparc__
1815 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1816 {
1817         struct atyfb_par *par = (struct atyfb_par *) info->par;
1818         unsigned int size, page, map_size = 0;
1819         unsigned long map_offset = 0;
1820         unsigned long off;
1821         int i;
1822
1823         if (!par->mmap_map)
1824                 return -ENXIO;
1825
1826         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1827                 return -EINVAL;
1828
1829         off = vma->vm_pgoff << PAGE_SHIFT;
1830         size = vma->vm_end - vma->vm_start;
1831
1832         /* To stop the swapper from even considering these pages. */
1833         vma->vm_flags |= (VM_IO | VM_RESERVED);
1834
1835         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1836             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1837                 off += 0x8000000000000000UL;
1838
1839         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1840
1841         /* Each page, see which map applies */
1842         for (page = 0; page < size;) {
1843                 map_size = 0;
1844                 for (i = 0; par->mmap_map[i].size; i++) {
1845                         unsigned long start = par->mmap_map[i].voff;
1846                         unsigned long end = start + par->mmap_map[i].size;
1847                         unsigned long offset = off + page;
1848
1849                         if (start > offset)
1850                                 continue;
1851                         if (offset >= end)
1852                                 continue;
1853
1854                         map_size = par->mmap_map[i].size - (offset - start);
1855                         map_offset =
1856                             par->mmap_map[i].poff + (offset - start);
1857                         break;
1858                 }
1859                 if (!map_size) {
1860                         page += PAGE_SIZE;
1861                         continue;
1862                 }
1863                 if (page + map_size > size)
1864                         map_size = size - page;
1865
1866                 pgprot_val(vma->vm_page_prot) &=
1867                     ~(par->mmap_map[i].prot_mask);
1868                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1869
1870                 if (remap_pfn_range(vma, vma->vm_start + page,
1871                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1872                         return -EAGAIN;
1873
1874                 page += map_size;
1875         }
1876
1877         if (!map_size)
1878                 return -EINVAL;
1879
1880         if (!par->mmaped)
1881                 par->mmaped = 1;
1882         return 0;
1883 }
1884
1885 static struct {
1886         u32 yoffset;
1887         u8 r[2][256];
1888         u8 g[2][256];
1889         u8 b[2][256];
1890 } atyfb_save;
1891
1892 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1893 {
1894         int i, tmp;
1895
1896         for (i = 0; i < 256; i++) {
1897                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1898                 if (M64_HAS(EXTRA_BRIGHT))
1899                         tmp |= 0x2;
1900                 aty_st_8(DAC_CNTL, tmp, par);
1901                 aty_st_8(DAC_MASK, 0xff, par);
1902
1903                 writeb(i, &par->aty_cmap_regs->rindex);
1904                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1905                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1906                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1907                 writeb(i, &par->aty_cmap_regs->windex);
1908                 writeb(atyfb_save.r[1 - enter][i],
1909                        &par->aty_cmap_regs->lut);
1910                 writeb(atyfb_save.g[1 - enter][i],
1911                        &par->aty_cmap_regs->lut);
1912                 writeb(atyfb_save.b[1 - enter][i],
1913                        &par->aty_cmap_regs->lut);
1914         }
1915 }
1916
1917 static void atyfb_palette(int enter)
1918 {
1919         struct atyfb_par *par;
1920         struct fb_info *info;
1921         int i;
1922
1923         for (i = 0; i < FB_MAX; i++) {
1924                 info = registered_fb[i];
1925                 if (info && info->fbops == &atyfb_ops) {
1926                         par = (struct atyfb_par *) info->par;
1927
1928                         atyfb_save_palette(par, enter);
1929                         if (enter) {
1930                                 atyfb_save.yoffset = info->var.yoffset;
1931                                 info->var.yoffset = 0;
1932                                 set_off_pitch(par, info);
1933                         } else {
1934                                 info->var.yoffset = atyfb_save.yoffset;
1935                                 set_off_pitch(par, info);
1936                         }
1937                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1938                         break;
1939                 }
1940         }
1941 }
1942 #endif /* __sparc__ */
1943
1944
1945
1946 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1947
1948 /* Power management routines. Those are used for PowerBook sleep.
1949  */
1950 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1951 {
1952         u32 pm;
1953         int timeout;
1954
1955         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1956         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1957         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1958         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1959
1960         timeout = 2000;
1961         if (sleep) {
1962                 /* Sleep */
1963                 pm &= ~PWR_MGT_ON;
1964                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1965                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1966                 udelay(10);
1967                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1968                 pm |= SUSPEND_NOW;
1969                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1970                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1971                 udelay(10);
1972                 pm |= PWR_MGT_ON;
1973                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1974                 do {
1975                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1976                         mdelay(1);
1977                         if ((--timeout) == 0)
1978                                 break;
1979                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1980         } else {
1981                 /* Wakeup */
1982                 pm &= ~PWR_MGT_ON;
1983                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1984                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1985                 udelay(10);
1986                 pm &= ~SUSPEND_NOW;
1987                 pm |= (PWR_BLON | AUTO_PWR_UP);
1988                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1990                 udelay(10);
1991                 pm |= PWR_MGT_ON;
1992                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1993                 do {
1994                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1995                         mdelay(1);
1996                         if ((--timeout) == 0)
1997                                 break;
1998                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
1999         }
2000         mdelay(500);
2001
2002         return timeout ? 0 : -EIO;
2003 }
2004
2005 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2006 {
2007         struct fb_info *info = pci_get_drvdata(pdev);
2008         struct atyfb_par *par = (struct atyfb_par *) info->par;
2009
2010 #ifndef CONFIG_PPC_PMAC
2011         /* HACK ALERT ! Once I find a proper way to say to each driver
2012          * individually what will happen with it's PCI slot, I'll change
2013          * that. On laptops, the AGP slot is just unclocked, so D2 is
2014          * expected, while on desktops, the card is powered off
2015          */
2016         return 0;
2017 #endif /* CONFIG_PPC_PMAC */
2018
2019         if (state.event == pdev->dev.power.power_state.event)
2020                 return 0;
2021
2022         acquire_console_sem();
2023
2024         fb_set_suspend(info, 1);
2025
2026         /* Idle & reset engine */
2027         wait_for_idle(par);
2028         aty_reset_engine(par);
2029
2030         /* Blank display and LCD */
2031         atyfb_blank(FB_BLANK_POWERDOWN, info);
2032
2033         par->asleep = 1;
2034         par->lock_blank = 1;
2035
2036         /* Set chip to "suspend" mode */
2037         if (aty_power_mgmt(1, par)) {
2038                 par->asleep = 0;
2039                 par->lock_blank = 0;
2040                 atyfb_blank(FB_BLANK_UNBLANK, info);
2041                 fb_set_suspend(info, 0);
2042                 release_console_sem();
2043                 return -EIO;
2044         }
2045
2046         release_console_sem();
2047
2048         pdev->dev.power.power_state = state;
2049
2050         return 0;
2051 }
2052
2053 static int atyfb_pci_resume(struct pci_dev *pdev)
2054 {
2055         struct fb_info *info = pci_get_drvdata(pdev);
2056         struct atyfb_par *par = (struct atyfb_par *) info->par;
2057
2058         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2059                 return 0;
2060
2061         acquire_console_sem();
2062
2063         if (pdev->dev.power.power_state.event == 2)
2064                 aty_power_mgmt(0, par);
2065         par->asleep = 0;
2066
2067         /* Restore display */
2068         atyfb_set_par(info);
2069
2070         /* Refresh */
2071         fb_set_suspend(info, 0);
2072
2073         /* Unblank */
2074         par->lock_blank = 0;
2075         atyfb_blank(FB_BLANK_UNBLANK, info);
2076
2077         release_console_sem();
2078
2079         pdev->dev.power.power_state = PMSG_ON;
2080
2081         return 0;
2082 }
2083
2084 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2085
2086 #ifdef CONFIG_PMAC_BACKLIGHT
2087
2088     /*
2089      *   LCD backlight control
2090      */
2091
2092 static int backlight_conv[] = {
2093         0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2094         0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2095 };
2096
2097 static int aty_set_backlight_enable(int on, int level, void *data)
2098 {
2099         struct fb_info *info = (struct fb_info *) data;
2100         struct atyfb_par *par = (struct atyfb_par *) info->par;
2101         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2102
2103         reg |= (BLMOD_EN | BIASMOD_EN);
2104         if (on && level > BACKLIGHT_OFF) {
2105                 reg &= ~BIAS_MOD_LEVEL_MASK;
2106                 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2107         } else {
2108                 reg &= ~BIAS_MOD_LEVEL_MASK;
2109                 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2110         }
2111         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2112         return 0;
2113 }
2114
2115 static int aty_set_backlight_level(int level, void *data)
2116 {
2117         return aty_set_backlight_enable(1, level, data);
2118 }
2119
2120 static struct backlight_controller aty_backlight_controller = {
2121         aty_set_backlight_enable,
2122         aty_set_backlight_level
2123 };
2124 #endif /* CONFIG_PMAC_BACKLIGHT */
2125
2126 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2127 {
2128         const int ragepro_tbl[] = {
2129                 44, 50, 55, 66, 75, 80, 100
2130         };
2131         const int ragexl_tbl[] = {
2132                 50, 66, 75, 83, 90, 95, 100, 105,
2133                 110, 115, 120, 125, 133, 143, 166
2134         };
2135         const int *refresh_tbl;
2136         int i, size;
2137
2138         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2139                 refresh_tbl = ragexl_tbl;
2140                 size = sizeof(ragexl_tbl)/sizeof(int);
2141         } else {
2142                 refresh_tbl = ragepro_tbl;
2143                 size = sizeof(ragepro_tbl)/sizeof(int);
2144         }
2145
2146         for (i=0; i < size; i++) {
2147                 if (xclk < refresh_tbl[i])
2148                 break;
2149         }
2150         par->mem_refresh_rate = i;
2151 }
2152
2153     /*
2154      *  Initialisation
2155      */
2156
2157 static struct fb_info *fb_list = NULL;
2158
2159 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2160 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2161                                                 struct fb_var_screeninfo *var)
2162 {
2163         int ret = -EINVAL;
2164
2165         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2166                 *var = default_var;
2167                 var->xres = var->xres_virtual = par->lcd_hdisp;
2168                 var->right_margin = par->lcd_right_margin;
2169                 var->left_margin = par->lcd_hblank_len -
2170                         (par->lcd_right_margin + par->lcd_hsync_dly +
2171                          par->lcd_hsync_len);
2172                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2173                 var->yres = var->yres_virtual = par->lcd_vdisp;
2174                 var->lower_margin = par->lcd_lower_margin;
2175                 var->upper_margin = par->lcd_vblank_len -
2176                         (par->lcd_lower_margin + par->lcd_vsync_len);
2177                 var->vsync_len = par->lcd_vsync_len;
2178                 var->pixclock = par->lcd_pixclock;
2179                 ret = 0;
2180         }
2181
2182         return ret;
2183 }
2184 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2185
2186 static int __init aty_init(struct fb_info *info, const char *name)
2187 {
2188         struct atyfb_par *par = (struct atyfb_par *) info->par;
2189         const char *ramname = NULL, *xtal;
2190         int gtb_memsize, has_var = 0;
2191         struct fb_var_screeninfo var;
2192         u8 pll_ref_div;
2193         u32 i;
2194 #if defined(CONFIG_PPC)
2195         int sense;
2196 #endif
2197
2198         init_waitqueue_head(&par->vblank.wait);
2199         spin_lock_init(&par->int_lock);
2200
2201         par->aty_cmap_regs =
2202             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2203
2204 #ifdef CONFIG_PPC_PMAC
2205         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2206          * and set the frequency manually. */
2207         if (machine_is_compatible("PowerBook2,1")) {
2208                 par->pll_limits.mclk = 70;
2209                 par->pll_limits.xclk = 53;
2210         }
2211 #endif
2212         if (pll)
2213                 par->pll_limits.pll_max = pll;
2214         if (mclk)
2215                 par->pll_limits.mclk = mclk;
2216         if (xclk)
2217                 par->pll_limits.xclk = xclk;
2218
2219         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2220         par->pll_per = 1000000/par->pll_limits.pll_max;
2221         par->mclk_per = 1000000/par->pll_limits.mclk;
2222         par->xclk_per = 1000000/par->pll_limits.xclk;
2223
2224         par->ref_clk_per = 1000000000000ULL / 14318180;
2225         xtal = "14.31818";
2226
2227 #ifdef CONFIG_FB_ATY_GX
2228         if (!M64_HAS(INTEGRATED)) {
2229                 u32 stat0;
2230                 u8 dac_type, dac_subtype, clk_type;
2231                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2232                 par->bus_type = (stat0 >> 0) & 0x07;
2233                 par->ram_type = (stat0 >> 3) & 0x07;
2234                 ramname = aty_gx_ram[par->ram_type];
2235                 /* FIXME: clockchip/RAMDAC probing? */
2236                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2237 #ifdef CONFIG_ATARI
2238                 clk_type = CLK_ATI18818_1;
2239                 dac_type = (stat0 >> 9) & 0x07;
2240                 if (dac_type == 0x07)
2241                         dac_subtype = DAC_ATT20C408;
2242                 else
2243                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2244 #else
2245                 dac_type = DAC_IBMRGB514;
2246                 dac_subtype = DAC_IBMRGB514;
2247                 clk_type = CLK_IBMRGB514;
2248 #endif
2249                 switch (dac_subtype) {
2250                 case DAC_IBMRGB514:
2251                         par->dac_ops = &aty_dac_ibm514;
2252                         break;
2253                 case DAC_ATI68860_B:
2254                 case DAC_ATI68860_C:
2255                         par->dac_ops = &aty_dac_ati68860b;
2256                         break;
2257                 case DAC_ATT20C408:
2258                 case DAC_ATT21C498:
2259                         par->dac_ops = &aty_dac_att21c498;
2260                         break;
2261                 default:
2262                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2263                         par->dac_ops = &aty_dac_unsupported;
2264                         break;
2265                 }
2266                 switch (clk_type) {
2267                 case CLK_ATI18818_1:
2268                         par->pll_ops = &aty_pll_ati18818_1;
2269                         break;
2270                 case CLK_STG1703:
2271                         par->pll_ops = &aty_pll_stg1703;
2272                         break;
2273                 case CLK_CH8398:
2274                         par->pll_ops = &aty_pll_ch8398;
2275                         break;
2276                 case CLK_ATT20C408:
2277                         par->pll_ops = &aty_pll_att20c408;
2278                         break;
2279                 case CLK_IBMRGB514:
2280                         par->pll_ops = &aty_pll_ibm514;
2281                         break;
2282                 default:
2283                         PRINTKI("aty_init: CLK type not implemented yet!");
2284                         par->pll_ops = &aty_pll_unsupported;
2285                         break;
2286                 }
2287         }
2288 #endif /* CONFIG_FB_ATY_GX */
2289 #ifdef CONFIG_FB_ATY_CT
2290         if (M64_HAS(INTEGRATED)) {
2291                 par->dac_ops = &aty_dac_ct;
2292                 par->pll_ops = &aty_pll_ct;
2293                 par->bus_type = PCI;
2294                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2295                 ramname = aty_ct_ram[par->ram_type];
2296                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2297                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2298                         par->pll_limits.mclk = 63;
2299         }
2300
2301         if (M64_HAS(GTB_DSP)
2302             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2303                 int diff1, diff2;
2304                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2305                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2306                 if (diff1 < 0)
2307                         diff1 = -diff1;
2308                 if (diff2 < 0)
2309                         diff2 = -diff2;
2310                 if (diff2 < diff1) {
2311                         par->ref_clk_per = 1000000000000ULL / 29498928;
2312                         xtal = "29.498928";
2313                 }
2314         }
2315 #endif /* CONFIG_FB_ATY_CT */
2316
2317         /* save previous video mode */
2318         aty_get_crtc(par, &saved_crtc);
2319         if(par->pll_ops->get_pll)
2320                 par->pll_ops->get_pll(info, &saved_pll);
2321
2322         i = aty_ld_le32(MEM_CNTL, par);
2323         gtb_memsize = M64_HAS(GTB_DSP);
2324         if (gtb_memsize)
2325                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2326                 case MEM_SIZE_512K:
2327                         info->fix.smem_len = 0x80000;
2328                         break;
2329                 case MEM_SIZE_1M:
2330                         info->fix.smem_len = 0x100000;
2331                         break;
2332                 case MEM_SIZE_2M_GTB:
2333                         info->fix.smem_len = 0x200000;
2334                         break;
2335                 case MEM_SIZE_4M_GTB:
2336                         info->fix.smem_len = 0x400000;
2337                         break;
2338                 case MEM_SIZE_6M_GTB:
2339                         info->fix.smem_len = 0x600000;
2340                         break;
2341                 case MEM_SIZE_8M_GTB:
2342                         info->fix.smem_len = 0x800000;
2343                         break;
2344                 default:
2345                         info->fix.smem_len = 0x80000;
2346         } else
2347                 switch (i & MEM_SIZE_ALIAS) {
2348                 case MEM_SIZE_512K:
2349                         info->fix.smem_len = 0x80000;
2350                         break;
2351                 case MEM_SIZE_1M:
2352                         info->fix.smem_len = 0x100000;
2353                         break;
2354                 case MEM_SIZE_2M:
2355                         info->fix.smem_len = 0x200000;
2356                         break;
2357                 case MEM_SIZE_4M:
2358                         info->fix.smem_len = 0x400000;
2359                         break;
2360                 case MEM_SIZE_6M:
2361                         info->fix.smem_len = 0x600000;
2362                         break;
2363                 case MEM_SIZE_8M:
2364                         info->fix.smem_len = 0x800000;
2365                         break;
2366                 default:
2367                         info->fix.smem_len = 0x80000;
2368                 }
2369
2370         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2371                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2372                         info->fix.smem_len += 0x400000;
2373         }
2374
2375         if (vram) {
2376                 info->fix.smem_len = vram * 1024;
2377                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2378                 if (info->fix.smem_len <= 0x80000)
2379                         i |= MEM_SIZE_512K;
2380                 else if (info->fix.smem_len <= 0x100000)
2381                         i |= MEM_SIZE_1M;
2382                 else if (info->fix.smem_len <= 0x200000)
2383                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2384                 else if (info->fix.smem_len <= 0x400000)
2385                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2386                 else if (info->fix.smem_len <= 0x600000)
2387                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2388                 else
2389                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2390                 aty_st_le32(MEM_CNTL, i, par);
2391         }
2392
2393         /*
2394          *  Reg Block 0 (CT-compatible block) is at mmio_start
2395          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2396          */
2397         if (M64_HAS(GX)) {
2398                 info->fix.mmio_len = 0x400;
2399                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2400         } else if (M64_HAS(CT)) {
2401                 info->fix.mmio_len = 0x400;
2402                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2403         } else if (M64_HAS(VT)) {
2404                 info->fix.mmio_start -= 0x400;
2405                 info->fix.mmio_len = 0x800;
2406                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2407         } else {/* GT */
2408                 info->fix.mmio_start -= 0x400;
2409                 info->fix.mmio_len = 0x800;
2410                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2411         }
2412
2413         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2414                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2415                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2416                par->pll_limits.mclk, par->pll_limits.xclk);
2417
2418 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2419         if (M64_HAS(INTEGRATED)) {
2420                 int i;
2421                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2422                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2423                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2424                        "debug atyfb: PLL",
2425                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2426                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2427                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2428                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2429                 for (i = 0; i < 40; i++)
2430                         printk(" %02x", aty_ld_pll_ct(i, par));
2431                 printk("\n");
2432         }
2433 #endif
2434         if(par->pll_ops->init_pll)
2435                 par->pll_ops->init_pll(info, &par->pll);
2436
2437         /*
2438          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2439          *  FIXME: we should use the auxiliary aperture instead so we can access
2440          *  the full 8 MB of video RAM on 8 MB boards
2441          */
2442
2443         if (!par->aux_start &&
2444                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2445                 info->fix.smem_len -= GUI_RESERVE;
2446
2447         /*
2448          *  Disable register access through the linear aperture
2449          *  if the auxiliary aperture is used so we can access
2450          *  the full 8 MB of video RAM on 8 MB boards.
2451          */
2452         if (par->aux_start)
2453                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2454
2455 #ifdef CONFIG_MTRR
2456         par->mtrr_aper = -1;
2457         par->mtrr_reg = -1;
2458         if (!nomtrr) {
2459                 /* Cover the whole resource. */
2460                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2461                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2462                         /* Make a hole for mmio. */
2463                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2464                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2465                         if (par->mtrr_reg < 0) {
2466                                 mtrr_del(par->mtrr_aper, 0, 0);
2467                                 par->mtrr_aper = -1;
2468                         }
2469                  }
2470         }
2471 #endif
2472
2473         info->fbops = &atyfb_ops;
2474         info->pseudo_palette = pseudo_palette;
2475         info->flags = FBINFO_FLAG_DEFAULT;
2476
2477 #ifdef CONFIG_PMAC_BACKLIGHT
2478         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2479                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2480                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2481                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2482         } else if (M64_HAS(MOBIL_BUS))
2483                 register_backlight_controller(&aty_backlight_controller, info, "ati");
2484 #endif /* CONFIG_PMAC_BACKLIGHT */
2485
2486         memset(&var, 0, sizeof(var));
2487 #ifdef CONFIG_PPC
2488         if (_machine == _MACH_Pmac) {
2489                 /*
2490                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2491                  *         applies to all Mac video cards
2492                  */
2493                 if (mode) {
2494                         if (mac_find_mode(&var, info, mode, 8))
2495                                 has_var = 1;
2496                 } else {
2497                         if (default_vmode == VMODE_CHOOSE) {
2498                                 if (M64_HAS(G3_PB_1024x768))
2499                                         /* G3 PowerBook with 1024x768 LCD */
2500                                         default_vmode = VMODE_1024_768_60;
2501                                 else if (machine_is_compatible("iMac"))
2502                                         default_vmode = VMODE_1024_768_75;
2503                                 else if (machine_is_compatible
2504                                          ("PowerBook2,1"))
2505                                         /* iBook with 800x600 LCD */
2506                                         default_vmode = VMODE_800_600_60;
2507                                 else
2508                                         default_vmode = VMODE_640_480_67;
2509                                 sense = read_aty_sense(par);
2510                                 PRINTKI("monitor sense=%x, mode %d\n",
2511                                         sense,  mac_map_monitor_sense(sense));
2512                         }
2513                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2514                                 default_vmode = VMODE_640_480_60;
2515                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2516                                 default_cmode = CMODE_8;
2517                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2518                                                &var))
2519                                 has_var = 1;
2520                 }
2521         }
2522
2523 #endif /* !CONFIG_PPC */
2524
2525 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2526         if (!atyfb_get_timings_from_lcd(par, &var))
2527                 has_var = 1;
2528 #endif
2529
2530         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2531                 has_var = 1;
2532
2533         if (!has_var)
2534                 var = default_var;
2535
2536         if (noaccel)
2537                 var.accel_flags &= ~FB_ACCELF_TEXT;
2538         else
2539                 var.accel_flags |= FB_ACCELF_TEXT;
2540
2541         if (comp_sync != -1) {
2542                 if (!comp_sync)
2543                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2544                 else
2545                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2546         }
2547
2548         if (var.yres == var.yres_virtual) {
2549                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2550                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2551                 if (var.yres_virtual < var.yres)
2552                         var.yres_virtual = var.yres;
2553         }
2554
2555         if (atyfb_check_var(&var, info)) {
2556                 PRINTKE("can't set default video mode\n");
2557                 goto aty_init_exit;
2558         }
2559
2560 #ifdef __sparc__
2561         atyfb_save_palette(par, 0);
2562 #endif
2563
2564 #ifdef CONFIG_FB_ATY_CT
2565         if (!noaccel && M64_HAS(INTEGRATED))
2566                 aty_init_cursor(info);
2567 #endif /* CONFIG_FB_ATY_CT */
2568         info->var = var;
2569
2570         fb_alloc_cmap(&info->cmap, 256, 0);
2571
2572         if (register_framebuffer(info) < 0)
2573                 goto aty_init_exit;
2574
2575         fb_list = info;
2576
2577         PRINTKI("fb%d: %s frame buffer device on %s\n",
2578                info->node, info->fix.id, name);
2579         return 0;
2580
2581 aty_init_exit:
2582         /* restore video mode */
2583         aty_set_crtc(par, &saved_crtc);
2584         par->pll_ops->set_pll(info, &saved_pll);
2585
2586 #ifdef CONFIG_MTRR
2587         if (par->mtrr_reg >= 0) {
2588             mtrr_del(par->mtrr_reg, 0, 0);
2589             par->mtrr_reg = -1;
2590         }
2591         if (par->mtrr_aper >= 0) {
2592             mtrr_del(par->mtrr_aper, 0, 0);
2593             par->mtrr_aper = -1;
2594         }
2595 #endif
2596         return -1;
2597 }
2598
2599 #ifdef CONFIG_ATARI
2600 static int __init store_video_par(char *video_str, unsigned char m64_num)
2601 {
2602         char *p;
2603         unsigned long vmembase, size, guiregbase;
2604
2605         PRINTKI("store_video_par() '%s' \n", video_str);
2606
2607         if (!(p = strsep(&video_str, ";")) || !*p)
2608                 goto mach64_invalid;
2609         vmembase = simple_strtoul(p, NULL, 0);
2610         if (!(p = strsep(&video_str, ";")) || !*p)
2611                 goto mach64_invalid;
2612         size = simple_strtoul(p, NULL, 0);
2613         if (!(p = strsep(&video_str, ";")) || !*p)
2614                 goto mach64_invalid;
2615         guiregbase = simple_strtoul(p, NULL, 0);
2616
2617         phys_vmembase[m64_num] = vmembase;
2618         phys_size[m64_num] = size;
2619         phys_guiregbase[m64_num] = guiregbase;
2620         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2621                guiregbase);
2622         return 0;
2623
2624       mach64_invalid:
2625         phys_vmembase[m64_num] = 0;
2626         return -1;
2627 }
2628 #endif /* CONFIG_ATARI */
2629
2630     /*
2631      *  Blank the display.
2632      */
2633
2634 static int atyfb_blank(int blank, struct fb_info *info)
2635 {
2636         struct atyfb_par *par = (struct atyfb_par *) info->par;
2637         u8 gen_cntl;
2638
2639         if (par->lock_blank || par->asleep)
2640                 return 0;
2641
2642 #ifdef CONFIG_PMAC_BACKLIGHT
2643         if ((_machine == _MACH_Pmac) && blank)
2644                 set_backlight_enable(0);
2645 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2646         if (par->lcd_table && blank &&
2647             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2648                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2649                 pm &= ~PWR_BLON;
2650                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2651         }
2652 #endif
2653
2654         gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2655         switch (blank) {
2656                 case FB_BLANK_UNBLANK:
2657                         gen_cntl &= ~(0x4c);
2658                         break;
2659                 case FB_BLANK_NORMAL:
2660                         gen_cntl |= 0x40;
2661                         break;
2662                 case FB_BLANK_VSYNC_SUSPEND:
2663                         gen_cntl |= 0x8;
2664                         break;
2665                 case FB_BLANK_HSYNC_SUSPEND:
2666                         gen_cntl |= 0x4;
2667                         break;
2668                 case FB_BLANK_POWERDOWN:
2669                         gen_cntl |= 0x4c;
2670                         break;
2671         }
2672         aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2673
2674 #ifdef CONFIG_PMAC_BACKLIGHT
2675         if ((_machine == _MACH_Pmac) && !blank)
2676                 set_backlight_enable(1);
2677 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2678         if (par->lcd_table && !blank &&
2679             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2680                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2681                 pm |= PWR_BLON;
2682                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2683         }
2684 #endif
2685
2686         return 0;
2687 }
2688
2689 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2690                        const struct atyfb_par *par)
2691 {
2692 #ifdef CONFIG_ATARI
2693         out_8(&par->aty_cmap_regs->windex, regno);
2694         out_8(&par->aty_cmap_regs->lut, red);
2695         out_8(&par->aty_cmap_regs->lut, green);
2696         out_8(&par->aty_cmap_regs->lut, blue);
2697 #else
2698         writeb(regno, &par->aty_cmap_regs->windex);
2699         writeb(red, &par->aty_cmap_regs->lut);
2700         writeb(green, &par->aty_cmap_regs->lut);
2701         writeb(blue, &par->aty_cmap_regs->lut);
2702 #endif
2703 }
2704
2705     /*
2706      *  Set a single color register. The values supplied are already
2707      *  rounded down to the hardware's capabilities (according to the
2708      *  entries in the var structure). Return != 0 for invalid regno.
2709      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2710      */
2711
2712 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2713         u_int transp, struct fb_info *info)
2714 {
2715         struct atyfb_par *par = (struct atyfb_par *) info->par;
2716         int i, depth;
2717         u32 *pal = info->pseudo_palette;
2718
2719         depth = info->var.bits_per_pixel;
2720         if (depth == 16)
2721                 depth = (info->var.green.length == 5) ? 15 : 16;
2722
2723         if (par->asleep)
2724                 return 0;
2725
2726         if (regno > 255 ||
2727             (depth == 16 && regno > 63) ||
2728             (depth == 15 && regno > 31))
2729                 return 1;
2730
2731         red >>= 8;
2732         green >>= 8;
2733         blue >>= 8;
2734
2735         par->palette[regno].red = red;
2736         par->palette[regno].green = green;
2737         par->palette[regno].blue = blue;
2738
2739         if (regno < 16) {
2740                 switch (depth) {
2741                 case 15:
2742                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2743                         break;
2744                 case 16:
2745                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2746                         break;
2747                 case 24:
2748                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2749                         break;
2750                 case 32:
2751                         i = (regno << 8) | regno;
2752                         pal[regno] = (i << 16) | i;
2753                         break;
2754                 }
2755         }
2756
2757         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2758         if (M64_HAS(EXTRA_BRIGHT))
2759                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2760         aty_st_8(DAC_CNTL, i, par);
2761         aty_st_8(DAC_MASK, 0xff, par);
2762
2763         if (M64_HAS(INTEGRATED)) {
2764                 if (depth == 16) {
2765                         if (regno < 32)
2766                                 aty_st_pal(regno << 3, red,
2767                                            par->palette[regno<<1].green,
2768                                            blue, par);
2769                         red = par->palette[regno>>1].red;
2770                         blue = par->palette[regno>>1].blue;
2771                         regno <<= 2;
2772                 } else if (depth == 15) {
2773                         regno <<= 3;
2774                         for(i = 0; i < 8; i++) {
2775                             aty_st_pal(regno + i, red, green, blue, par);
2776                         }
2777                 }
2778         }
2779         aty_st_pal(regno, red, green, blue, par);
2780
2781         return 0;
2782 }
2783
2784 #ifdef CONFIG_PCI
2785
2786 #ifdef __sparc__
2787
2788 extern void (*prom_palette) (int);
2789
2790 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2791                         struct fb_info *info, unsigned long addr)
2792 {
2793         extern int con_is_present(void);
2794
2795         struct atyfb_par *par = info->par;
2796         struct pcidev_cookie *pcp;
2797         char prop[128];
2798         int node, len, i, j, ret;
2799         u32 mem, chip_id;
2800
2801         /* Do not attach when we have a serial console. */
2802         if (!con_is_present())
2803                 return -ENXIO;
2804
2805         /*
2806          * Map memory-mapped registers.
2807          */
2808         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2809         info->fix.mmio_start = addr + 0x7ffc00UL;
2810
2811         /*
2812          * Map in big-endian aperture.
2813          */
2814         info->screen_base = (char *) (addr + 0x800000UL);
2815         info->fix.smem_start = addr + 0x800000UL;
2816
2817         /*
2818          * Figure mmap addresses from PCI config space.
2819          * Split Framebuffer in big- and little-endian halfs.
2820          */
2821         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2822                 /* nothing */ ;
2823         j = i + 4;
2824
2825         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2826         if (!par->mmap_map) {
2827                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2828                 return -ENOMEM;
2829         }
2830         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2831
2832         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2833                 struct resource *rp = &pdev->resource[i];
2834                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2835                 unsigned long base;
2836                 u32 size, pbase;
2837
2838                 base = rp->start;
2839
2840                 io = (rp->flags & IORESOURCE_IO);
2841
2842                 size = rp->end - base + 1;
2843
2844                 pci_read_config_dword(pdev, breg, &pbase);
2845
2846                 if (io)
2847                         size &= ~1;
2848
2849                 /*
2850                  * Map the framebuffer a second time, this time without
2851                  * the braindead _PAGE_IE setting. This is used by the
2852                  * fixed Xserver, but we need to maintain the old mapping
2853                  * to stay compatible with older ones...
2854                  */
2855                 if (base == addr) {
2856                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2857                         par->mmap_map[j].poff = base & PAGE_MASK;
2858                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2859                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2860                         par->mmap_map[j].prot_flag = _PAGE_E;
2861                         j++;
2862                 }
2863
2864                 /*
2865                  * Here comes the old framebuffer mapping with _PAGE_IE
2866                  * set for the big endian half of the framebuffer...
2867                  */
2868                 if (base == addr) {
2869                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2870                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2871                         par->mmap_map[j].size = 0x800000;
2872                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
2873                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2874                         size -= 0x800000;
2875                         j++;
2876                 }
2877
2878                 par->mmap_map[j].voff = pbase & PAGE_MASK;
2879                 par->mmap_map[j].poff = base & PAGE_MASK;
2880                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2881                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2882                 par->mmap_map[j].prot_flag = _PAGE_E;
2883                 j++;
2884         }
2885
2886         if((ret = correct_chipset(par)))
2887                 return ret;
2888
2889         if (IS_XL(pdev->device)) {
2890                 /*
2891                  * Fix PROMs idea of MEM_CNTL settings...
2892                  */
2893                 mem = aty_ld_le32(MEM_CNTL, par);
2894                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2895                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2896                         switch (mem & 0x0f) {
2897                         case 3:
2898                                 mem = (mem & ~(0x0f)) | 2;
2899                                 break;
2900                         case 7:
2901                                 mem = (mem & ~(0x0f)) | 3;
2902                                 break;
2903                         case 9:
2904                                 mem = (mem & ~(0x0f)) | 4;
2905                                 break;
2906                         case 11:
2907                                 mem = (mem & ~(0x0f)) | 5;
2908                                 break;
2909                         default:
2910                                 break;
2911                         }
2912                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2913                                 mem &= ~(0x00700000);
2914                 }
2915                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
2916                 aty_st_le32(MEM_CNTL, mem, par);
2917         }
2918
2919         /*
2920          * If this is the console device, we will set default video
2921          * settings to what the PROM left us with.
2922          */
2923         node = prom_getchild(prom_root_node);
2924         node = prom_searchsiblings(node, "aliases");
2925         if (node) {
2926                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2927                 if (len > 0) {
2928                         prop[len] = '\0';
2929                         node = prom_finddevice(prop);
2930                 } else
2931                         node = 0;
2932         }
2933
2934         pcp = pdev->sysdata;
2935         if (node == pcp->prom_node) {
2936                 struct fb_var_screeninfo *var = &default_var;
2937                 unsigned int N, P, Q, M, T, R;
2938                 u32 v_total, h_total;
2939                 struct crtc crtc;
2940                 u8 pll_regs[16];
2941                 u8 clock_cntl;
2942
2943                 crtc.vxres = prom_getintdefault(node, "width", 1024);
2944                 crtc.vyres = prom_getintdefault(node, "height", 768);
2945                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2946                 var->xoffset = var->yoffset = 0;
2947                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2948                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2949                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2950                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2951                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2952                 aty_crtc_to_var(&crtc, var);
2953
2954                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2955                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2956
2957                 /*
2958                  * Read the PLL to figure actual Refresh Rate.
2959                  */
2960                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2961                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2962                 for (i = 0; i < 16; i++)
2963                         pll_regs[i] = aty_ld_pll_ct(i, par);
2964
2965                 /*
2966                  * PLL Reference Divider M:
2967                  */
2968                 M = pll_regs[2];
2969
2970                 /*
2971                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2972                  */
2973                 N = pll_regs[7 + (clock_cntl & 3)];
2974
2975                 /*
2976                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
2977                  */
2978                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2979
2980                 /*
2981                  * PLL Divider Q:
2982                  */
2983                 Q = N / P;
2984
2985                 /*
2986                  * Target Frequency:
2987                  *
2988                  *      T * M
2989                  * Q = -------
2990                  *      2 * R
2991                  *
2992                  * where R is XTALIN (= 14318 or 29498 kHz).
2993                  */
2994                 if (IS_XL(pdev->device))
2995                         R = 29498;
2996                 else
2997                         R = 14318;
2998
2999                 T = 2 * Q * R / M;
3000
3001                 default_var.pixclock = 1000000000 / T;
3002         }
3003
3004         return 0;
3005 }
3006
3007 #else /* __sparc__ */
3008
3009 #ifdef __i386__
3010 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3011 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3012 {
3013         u32 driv_inf_tab, sig;
3014         u16 lcd_ofs;
3015
3016         /* To support an LCD panel, we should know it's dimensions and
3017          *  it's desired pixel clock.
3018          * There are two ways to do it:
3019          *  - Check the startup video mode and calculate the panel
3020          *    size from it. This is unreliable.
3021          *  - Read it from the driver information table in the video BIOS.
3022         */
3023         /* Address of driver information table is at offset 0x78. */
3024         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3025
3026         /* Check for the driver information table signature. */
3027         sig = (*(u32 *)driv_inf_tab);
3028         if ((sig == 0x54504c24) || /* Rage LT pro */
3029                 (sig == 0x544d5224) || /* Rage mobility */
3030                 (sig == 0x54435824) || /* Rage XC */
3031                 (sig == 0x544c5824)) { /* Rage XL */
3032                 PRINTKI("BIOS contains driver information table.\n");
3033                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3034                 par->lcd_table = 0;
3035                 if (lcd_ofs != 0) {
3036                         par->lcd_table = bios_base + lcd_ofs;
3037                 }
3038         }
3039
3040         if (par->lcd_table != 0) {
3041                 char model[24];
3042                 char strbuf[16];
3043                 char refresh_rates_buf[100];
3044                 int id, tech, f, i, m, default_refresh_rate;
3045                 char *txtcolour;
3046                 char *txtmonitor;
3047                 char *txtdual;
3048                 char *txtformat;
3049                 u16 width, height, panel_type, refresh_rates;
3050                 u16 *lcdmodeptr;
3051                 u32 format;
3052                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3053                 /* The most important information is the panel size at
3054                  * offset 25 and 27, but there's some other nice information
3055                  * which we print to the screen.
3056                  */
3057                 id = *(u8 *)par->lcd_table;
3058                 strncpy(model,(char *)par->lcd_table+1,24);
3059                 model[23]=0;
3060
3061                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3062                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3063                 panel_type = *(u16 *)(par->lcd_table+29);
3064                 if (panel_type & 1)
3065                         txtcolour = "colour";
3066                 else
3067                         txtcolour = "monochrome";
3068                 if (panel_type & 2)
3069                         txtdual = "dual (split) ";
3070                 else
3071                         txtdual = "";
3072                 tech = (panel_type>>2) & 63;
3073                 switch (tech) {
3074                 case 0:
3075                         txtmonitor = "passive matrix";
3076                         break;
3077                 case 1:
3078                         txtmonitor = "active matrix";
3079                         break;
3080                 case 2:
3081                         txtmonitor = "active addressed STN";
3082                         break;
3083                 case 3:
3084                         txtmonitor = "EL";
3085                         break;
3086                 case 4:
3087                         txtmonitor = "plasma";
3088                         break;
3089                 default:
3090                         txtmonitor = "unknown";
3091                 }
3092                 format = *(u32 *)(par->lcd_table+57);
3093                 if (tech == 0 || tech == 2) {
3094                         switch (format & 7) {
3095                         case 0:
3096                                 txtformat = "12 bit interface";
3097                                 break;
3098                         case 1:
3099                                 txtformat = "16 bit interface";
3100                                 break;
3101                         case 2:
3102                                 txtformat = "24 bit interface";
3103                                 break;
3104                         default:
3105                                 txtformat = "unkown format";
3106                         }
3107                 } else {
3108                         switch (format & 7) {
3109                         case 0:
3110                                 txtformat = "8 colours";
3111                                 break;
3112                         case 1:
3113                                 txtformat = "512 colours";
3114                                 break;
3115                         case 2:
3116                                 txtformat = "4096 colours";
3117                                 break;
3118                         case 4:
3119                                 txtformat = "262144 colours (LT mode)";
3120                                 break;
3121                         case 5:
3122                                 txtformat = "16777216 colours";
3123                                 break;
3124                         case 6:
3125                                 txtformat = "262144 colours (FDPI-2 mode)";
3126                                 break;
3127                         default:
3128                                 txtformat = "unkown format";
3129                         }
3130                 }
3131                 PRINTKI("%s%s %s monitor detected: %s\n",
3132                         txtdual ,txtcolour, txtmonitor, model);
3133                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3134                         id, width, height, txtformat);
3135                 refresh_rates_buf[0] = 0;
3136                 refresh_rates = *(u16 *)(par->lcd_table+62);
3137                 m = 1;
3138                 f = 0;
3139                 for (i=0;i<16;i++) {
3140                         if (refresh_rates & m) {
3141                                 if (f == 0) {
3142                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3143                                         f++;
3144                                 } else {
3145                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3146                                 }
3147                                 strcat(refresh_rates_buf,strbuf);
3148                         }
3149                         m = m << 1;
3150                 }
3151                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3152                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3153                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3154                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3155                 /* We now need to determine the crtc parameters for the
3156                  * LCD monitor. This is tricky, because they are not stored
3157                  * individually in the BIOS. Instead, the BIOS contains a
3158                  * table of display modes that work for this monitor.
3159                  *
3160                  * The idea is that we search for a mode of the same dimensions
3161                  * as the dimensions of the LCD monitor. Say our LCD monitor
3162                  * is 800x600 pixels, we search for a 800x600 monitor.
3163                  * The CRTC parameters we find here are the ones that we need
3164                  * to use to simulate other resolutions on the LCD screen.
3165                  */
3166                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3167                 while (*lcdmodeptr != 0) {
3168                         u32 modeptr;
3169                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3170                         modeptr = bios_base + *lcdmodeptr;
3171
3172                         mwidth = *((u16 *)(modeptr+0));
3173                         mheight = *((u16 *)(modeptr+2));
3174
3175                         if (mwidth == width && mheight == height) {
3176                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3177                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3178                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3179                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3180                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3181                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3182
3183                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3184                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3185                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3186                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3187
3188                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3189                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3190                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3191                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3192
3193                                 par->lcd_vtotal++;
3194                                 par->lcd_vdisp++;
3195                                 lcd_vsync_start++;
3196
3197                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3198                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3199                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3200                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3201                                 break;
3202                         }
3203
3204                         lcdmodeptr++;
3205                 }
3206                 if (*lcdmodeptr == 0) {
3207                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3208                         /* To do: Switch to CRT if possible. */
3209                 } else {
3210                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3211                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3212                                 par->lcd_hdisp,
3213                                 par->lcd_hdisp + par->lcd_right_margin,
3214                                 par->lcd_hdisp + par->lcd_right_margin
3215                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3216                                 par->lcd_htotal,
3217                                 par->lcd_vdisp,
3218                                 par->lcd_vdisp + par->lcd_lower_margin,
3219                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3220                                 par->lcd_vtotal);
3221                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3222                                 par->lcd_pixclock,
3223                                 par->lcd_hblank_len - (par->lcd_right_margin +
3224                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3225                                 par->lcd_hdisp,
3226                                 par->lcd_right_margin,
3227                                 par->lcd_hsync_len,
3228                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3229                                 par->lcd_vdisp,
3230                                 par->lcd_lower_margin,
3231                                 par->lcd_vsync_len);
3232                 }
3233         }
3234 }
3235 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3236
3237 static int __devinit init_from_bios(struct atyfb_par *par)
3238 {
3239         u32 bios_base, rom_addr;
3240         int ret;
3241
3242         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3243         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3244
3245         /* The BIOS starts with 0xaa55. */
3246         if (*((u16 *)bios_base) == 0xaa55) {
3247
3248                 u8 *bios_ptr;
3249                 u16 rom_table_offset, freq_table_offset;
3250                 PLL_BLOCK_MACH64 pll_block;
3251
3252                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3253
3254                 /* check for frequncy table */
3255                 bios_ptr = (u8*)bios_base;
3256                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3257                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3258                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3259
3260                 PRINTKI("BIOS frequency table:\n");
3261                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3262                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3263                         pll_block.ref_freq, pll_block.ref_divider);
3264                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3265                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3266                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3267
3268                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3269                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3270                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3271                 par->pll_limits.ref_div = pll_block.ref_divider;
3272                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3273                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3274                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3275                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3276 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3277                 aty_init_lcd(par, bios_base);
3278 #endif
3279                 ret = 0;
3280         } else {
3281                 PRINTKE("no BIOS frequency table found, use parameters\n");
3282                 ret = -ENXIO;
3283         }
3284         iounmap((void* __iomem )bios_base);
3285
3286         return ret;
3287 }
3288 #endif /* __i386__ */
3289
3290 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3291 {
3292         struct atyfb_par *par = info->par;
3293         u16 tmp;
3294         unsigned long raddr;
3295         struct resource *rrp;
3296         int ret = 0;
3297
3298         raddr = addr + 0x7ff000UL;
3299         rrp = &pdev->resource[2];
3300         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3301                 par->aux_start = rrp->start;
3302                 par->aux_size = rrp->end - rrp->start + 1;
3303                 raddr = rrp->start;
3304                 PRINTKI("using auxiliary register aperture\n");
3305         }
3306
3307         info->fix.mmio_start = raddr;
3308         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3309         if (par->ati_regbase == 0)
3310                 return -ENOMEM;
3311
3312         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3313         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3314
3315         /*
3316          * Enable memory-space accesses using config-space
3317          * command register.
3318          */
3319         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3320         if (!(tmp & PCI_COMMAND_MEMORY)) {
3321                 tmp |= PCI_COMMAND_MEMORY;
3322                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3323         }
3324 #ifdef __BIG_ENDIAN
3325         /* Use the big-endian aperture */
3326         addr += 0x800000;
3327 #endif
3328
3329         /* Map in frame buffer */
3330         info->fix.smem_start = addr;
3331         info->screen_base = ioremap(addr, 0x800000);
3332         if (info->screen_base == NULL) {
3333                 ret = -ENOMEM;
3334                 goto atyfb_setup_generic_fail;
3335         }
3336
3337         if((ret = correct_chipset(par)))
3338                 goto atyfb_setup_generic_fail;
3339 #ifdef __i386__
3340         if((ret = init_from_bios(par)))
3341                 goto atyfb_setup_generic_fail;
3342 #endif
3343         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3344                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3345         else
3346                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3347
3348         /* according to ATI, we should use clock 3 for acelerated mode */
3349         par->clk_wr_offset = 3;
3350
3351         return 0;
3352
3353 atyfb_setup_generic_fail:
3354         iounmap(par->ati_regbase);
3355         par->ati_regbase = NULL;
3356         return ret;
3357 }
3358
3359 #endif /* !__sparc__ */
3360
3361 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3362 {
3363         unsigned long addr, res_start, res_size;
3364         struct fb_info *info;
3365         struct resource *rp;
3366         struct atyfb_par *par;
3367         int i, rc = -ENOMEM;
3368
3369         for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3370                 if (pdev->device == aty_chips[i].pci_id)
3371                         break;
3372
3373         if (i < 0)
3374                 return -ENODEV;
3375
3376         /* Enable device in PCI config */
3377         if (pci_enable_device(pdev)) {
3378                 PRINTKE("Cannot enable PCI device\n");
3379                 return -ENXIO;
3380         }
3381
3382         /* Find which resource to use */
3383         rp = &pdev->resource[0];
3384         if (rp->flags & IORESOURCE_IO)
3385                 rp = &pdev->resource[1];
3386         addr = rp->start;
3387         if (!addr)
3388                 return -ENXIO;
3389
3390         /* Reserve space */
3391         res_start = rp->start;
3392         res_size = rp->end - rp->start + 1;
3393         if (!request_mem_region (res_start, res_size, "atyfb"))
3394                 return -EBUSY;
3395
3396         /* Allocate framebuffer */
3397         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3398         if (!info) {
3399                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3400                 return -ENOMEM;
3401         }
3402         par = info->par;
3403         info->fix = atyfb_fix;
3404         info->device = &pdev->dev;
3405         par->pci_id = aty_chips[i].pci_id;
3406         par->res_start = res_start;
3407         par->res_size = res_size;
3408         par->irq = pdev->irq;
3409
3410         /* Setup "info" structure */
3411 #ifdef __sparc__
3412         rc = atyfb_setup_sparc(pdev, info, addr);
3413 #else
3414         rc = atyfb_setup_generic(pdev, info, addr);
3415 #endif
3416         if (rc)
3417                 goto err_release_mem;
3418
3419         pci_set_drvdata(pdev, info);
3420
3421         /* Init chip & register framebuffer */
3422         if (aty_init(info, "PCI"))
3423                 goto err_release_io;
3424
3425 #ifdef __sparc__
3426         if (!prom_palette)
3427                 prom_palette = atyfb_palette;
3428
3429         /*
3430          * Add /dev/fb mmap values.
3431          */
3432         par->mmap_map[0].voff = 0x8000000000000000UL;
3433         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3434         par->mmap_map[0].size = info->fix.smem_len;
3435         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3436         par->mmap_map[0].prot_flag = _PAGE_E;
3437         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3438         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3439         par->mmap_map[1].size = PAGE_SIZE;
3440         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3441         par->mmap_map[1].prot_flag = _PAGE_E;
3442 #endif /* __sparc__ */
3443
3444         return 0;
3445
3446 err_release_io:
3447 #ifdef __sparc__
3448         kfree(par->mmap_map);
3449 #else
3450         if (par->ati_regbase)
3451                 iounmap(par->ati_regbase);
3452         if (info->screen_base)
3453                 iounmap(info->screen_base);
3454 #endif
3455 err_release_mem:
3456         if (par->aux_start)
3457                 release_mem_region(par->aux_start, par->aux_size);
3458
3459         release_mem_region(par->res_start, par->res_size);
3460         framebuffer_release(info);
3461
3462         return rc;
3463 }
3464
3465 #endif /* CONFIG_PCI */
3466
3467 #ifdef CONFIG_ATARI
3468
3469 static int __devinit atyfb_atari_probe(void)
3470 {
3471         struct aty_par *par;
3472         struct fb_info *info;
3473         int m64_num;
3474         u32 clock_r;
3475
3476         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3477                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3478                     !phys_guiregbase[m64_num]) {
3479                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3480                         continue;
3481                 }
3482
3483                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3484                 if (!info) {
3485                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3486                         return -ENOMEM;
3487                 }
3488                 par = info->par;
3489
3490                 info->fix = atyfb_fix;
3491
3492                 par->irq = (unsigned int) -1; /* something invalid */
3493
3494                 /*
3495                  *  Map the video memory (physical address given) to somewhere in the
3496                  *  kernel address space.
3497                  */
3498                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3499                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3500                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3501                                                 0xFC00ul;
3502                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3503
3504                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3505                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3506
3507                 switch (clock_r & 0x003F) {
3508                 case 0x12:
3509                         par->clk_wr_offset = 3; /*  */
3510                         break;
3511                 case 0x34:
3512                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3513                         break;
3514                 case 0x16:
3515                         par->clk_wr_offset = 1; /*  */
3516                         break;
3517                 case 0x38:
3518                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3519                         break;
3520                 }
3521
3522                 if (aty_init(info, "ISA bus")) {
3523                         framebuffer_release(info);
3524                         /* This is insufficient! kernel_map has added two large chunks!! */
3525                         return -ENXIO;
3526                 }
3527         }
3528 }
3529
3530 #endif /* CONFIG_ATARI */
3531
3532 static void __devexit atyfb_remove(struct fb_info *info)
3533 {
3534         struct atyfb_par *par = (struct atyfb_par *) info->par;
3535
3536         /* restore video mode */
3537         aty_set_crtc(par, &saved_crtc);
3538         par->pll_ops->set_pll(info, &saved_pll);
3539
3540         unregister_framebuffer(info);
3541
3542 #ifdef CONFIG_MTRR
3543         if (par->mtrr_reg >= 0) {
3544             mtrr_del(par->mtrr_reg, 0, 0);
3545             par->mtrr_reg = -1;
3546         }
3547         if (par->mtrr_aper >= 0) {
3548             mtrr_del(par->mtrr_aper, 0, 0);
3549             par->mtrr_aper = -1;
3550         }
3551 #endif
3552 #ifndef __sparc__
3553         if (par->ati_regbase)
3554                 iounmap(par->ati_regbase);
3555         if (info->screen_base)
3556                 iounmap(info->screen_base);
3557 #ifdef __BIG_ENDIAN
3558         if (info->sprite.addr)
3559                 iounmap(info->sprite.addr);
3560 #endif
3561 #endif
3562 #ifdef __sparc__
3563         kfree(par->mmap_map);
3564 #endif
3565         if (par->aux_start)
3566                 release_mem_region(par->aux_start, par->aux_size);
3567
3568         if (par->res_start)
3569                 release_mem_region(par->res_start, par->res_size);
3570
3571         framebuffer_release(info);
3572 }
3573
3574 #ifdef CONFIG_PCI
3575
3576 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3577 {
3578         struct fb_info *info = pci_get_drvdata(pdev);
3579
3580         atyfb_remove(info);
3581 }
3582
3583 /*
3584  * This driver uses its own matching table. That will be more difficult
3585  * to fix, so for now, we just match against any ATI ID and let the
3586  * probe() function find out what's up. That also mean we don't have
3587  * a module ID table though.
3588  */
3589 static struct pci_device_id atyfb_pci_tbl[] = {
3590         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3591           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3592         { 0, }
3593 };
3594
3595 static struct pci_driver atyfb_driver = {
3596         .name           = "atyfb",
3597         .id_table       = atyfb_pci_tbl,
3598         .probe          = atyfb_pci_probe,
3599         .remove         = __devexit_p(atyfb_pci_remove),
3600 #ifdef CONFIG_PM
3601         .suspend        = atyfb_pci_suspend,
3602         .resume         = atyfb_pci_resume,
3603 #endif /* CONFIG_PM */
3604 };
3605
3606 #endif /* CONFIG_PCI */
3607
3608 #ifndef MODULE
3609 static int __init atyfb_setup(char *options)
3610 {
3611         char *this_opt;
3612
3613         if (!options || !*options)
3614                 return 0;
3615
3616         while ((this_opt = strsep(&options, ",")) != NULL) {
3617                 if (!strncmp(this_opt, "noaccel", 7)) {
3618                         noaccel = 1;
3619 #ifdef CONFIG_MTRR
3620                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3621                         nomtrr = 1;
3622 #endif
3623                 } else if (!strncmp(this_opt, "vram:", 5))
3624                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3625                 else if (!strncmp(this_opt, "pll:", 4))
3626                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3627                 else if (!strncmp(this_opt, "mclk:", 5))
3628                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3629                 else if (!strncmp(this_opt, "xclk:", 5))
3630                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3631                 else if (!strncmp(this_opt, "comp_sync:", 10))
3632                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3633 #ifdef CONFIG_PPC
3634                 else if (!strncmp(this_opt, "vmode:", 6)) {
3635                         unsigned int vmode =
3636                             simple_strtoul(this_opt + 6, NULL, 0);
3637                         if (vmode > 0 && vmode <= VMODE_MAX)
3638                                 default_vmode = vmode;
3639                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3640                         unsigned int cmode =
3641                             simple_strtoul(this_opt + 6, NULL, 0);
3642                         switch (cmode) {
3643                         case 0:
3644                         case 8:
3645                                 default_cmode = CMODE_8;
3646                                 break;
3647                         case 15:
3648                         case 16:
3649                                 default_cmode = CMODE_16;
3650                                 break;
3651                         case 24:
3652                         case 32:
3653                                 default_cmode = CMODE_32;
3654                                 break;
3655                         }
3656                 }
3657 #endif
3658 #ifdef CONFIG_ATARI
3659                 /*
3660                  * Why do we need this silly Mach64 argument?
3661                  * We are already here because of mach64= so its redundant.
3662                  */
3663                 else if (MACH_IS_ATARI
3664                          && (!strncmp(this_opt, "Mach64:", 7))) {
3665                         static unsigned char m64_num;
3666                         static char mach64_str[80];
3667                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3668                         if (!store_video_par(mach64_str, m64_num)) {
3669                                 m64_num++;
3670                                 mach64_count = m64_num;
3671                         }
3672                 }
3673 #endif
3674                 else
3675                         mode = this_opt;
3676         }
3677         return 0;
3678 }
3679 #endif  /*  MODULE  */
3680
3681 static int __init atyfb_init(void)
3682 {
3683 #ifndef MODULE
3684     char *option = NULL;
3685
3686     if (fb_get_options("atyfb", &option))
3687         return -ENODEV;
3688     atyfb_setup(option);
3689 #endif
3690
3691     pci_register_driver(&atyfb_driver);
3692 #ifdef CONFIG_ATARI
3693     atyfb_atari_probe();
3694 #endif
3695     return 0;
3696 }
3697
3698 static void __exit atyfb_exit(void)
3699 {
3700         pci_unregister_driver(&atyfb_driver);
3701 }
3702
3703 module_init(atyfb_init);
3704 module_exit(atyfb_exit);
3705
3706 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3707 MODULE_LICENSE("GPL");
3708 module_param(noaccel, bool, 0);
3709 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3710 module_param(vram, int, 0);
3711 MODULE_PARM_DESC(vram, "int: override size of video ram");
3712 module_param(pll, int, 0);
3713 MODULE_PARM_DESC(pll, "int: override video clock");
3714 module_param(mclk, int, 0);
3715 MODULE_PARM_DESC(mclk, "int: override memory clock");
3716 module_param(xclk, int, 0);
3717 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3718 module_param(comp_sync, int, 0);
3719 MODULE_PARM_DESC(comp_sync,
3720                  "Set composite sync signal to low (0) or high (1)");
3721 module_param(mode, charp, 0);
3722 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3723 #ifdef CONFIG_MTRR
3724 module_param(nomtrr, bool, 0);
3725 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3726 #endif