2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
79 #include "../macmodes.h"
87 #include <linux/adb.h>
88 #include <linux/pmu.h>
90 #ifdef CONFIG_BOOTX_TEXT
91 #include <asm/btext.h>
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 #include <asm/backlight.h>
106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107 /* - must be large enough to catch all GUI-Regs */
108 /* - must be aligned to a PAGE boundary */
109 #define GUI_RESERVE (1 * PAGE_SIZE)
111 /* FIXME: remove the FAIL definition */
112 #define FAIL(msg) do { \
113 if (!(var->activate & FB_ACTIVATE_TEST)) \
114 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 #define FAIL_MAX(msg, x, _max_) do { \
119 if (!(var->activate & FB_ACTIVATE_TEST)) \
120 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
125 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
127 #define DPRINTK(fmt, args...)
130 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
131 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
133 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
134 static const u32 lt_lcd_regs[] = {
141 0, /* EXT_VERT_STRETCH */
146 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
148 if (M64_HAS(LT_LCD_REGS)) {
149 aty_st_le32(lt_lcd_regs[index], val, par);
153 /* write addr byte */
154 temp = aty_ld_le32(LCD_INDEX, par);
155 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
156 /* write the register value */
157 aty_st_le32(LCD_DATA, val, par);
161 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
163 if (M64_HAS(LT_LCD_REGS)) {
164 return aty_ld_le32(lt_lcd_regs[index], par);
168 /* write addr byte */
169 temp = aty_ld_le32(LCD_INDEX, par);
170 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
171 /* read the register value */
172 return aty_ld_le32(LCD_DATA, par);
175 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
181 * Reduce a fraction by factoring out the largest common divider of the
182 * fraction's numerator and denominator.
184 static void ATIReduceRatio(int *Numerator, int *Denominator)
186 int Multiplier, Divider, Remainder;
188 Multiplier = *Numerator;
189 Divider = *Denominator;
191 while ((Remainder = Multiplier % Divider))
193 Multiplier = Divider;
197 *Numerator /= Divider;
198 *Denominator /= Divider;
202 * The Hardware parameters for each card
205 struct aty_cmap_regs {
213 struct pci_mmap_map {
217 unsigned long prot_flag;
218 unsigned long prot_mask;
221 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
223 .type = FB_TYPE_PACKED_PIXELS,
224 .visual = FB_VISUAL_PSEUDOCOLOR,
230 * Frame buffer device API
233 static int atyfb_open(struct fb_info *info, int user);
234 static int atyfb_release(struct fb_info *info, int user);
235 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
236 static int atyfb_set_par(struct fb_info *info);
237 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
238 u_int transp, struct fb_info *info);
239 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
240 static int atyfb_blank(int blank, struct fb_info *info);
241 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
242 u_long arg, struct fb_info *info);
243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
249 static int atyfb_sync(struct fb_info *info);
255 static int aty_init(struct fb_info *info, const char *name);
257 static int store_video_par(char *videopar, unsigned char m64_num);
260 static struct crtc saved_crtc;
261 static union aty_pll saved_pll;
262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269 static int read_aty_sense(const struct atyfb_par *par);
274 * Interface used by the world
277 static struct fb_var_screeninfo default_var = {
278 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
279 640, 480, 640, 480, 0, 0, 8, 0,
280 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
281 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
282 0, FB_VMODE_NONINTERLACED
285 static struct fb_videomode defmode = {
286 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
287 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
288 0, FB_VMODE_NONINTERLACED
291 static struct fb_ops atyfb_ops = {
292 .owner = THIS_MODULE,
293 .fb_open = atyfb_open,
294 .fb_release = atyfb_release,
295 .fb_check_var = atyfb_check_var,
296 .fb_set_par = atyfb_set_par,
297 .fb_setcolreg = atyfb_setcolreg,
298 .fb_pan_display = atyfb_pan_display,
299 .fb_blank = atyfb_blank,
300 .fb_ioctl = atyfb_ioctl,
301 .fb_fillrect = atyfb_fillrect,
302 .fb_copyarea = atyfb_copyarea,
303 .fb_imageblit = atyfb_imageblit,
305 .fb_mmap = atyfb_mmap,
307 .fb_sync = atyfb_sync,
318 static int comp_sync __initdata = -1;
322 static int default_vmode __initdata = VMODE_CHOOSE;
323 static int default_cmode __initdata = CMODE_CHOOSE;
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
332 static unsigned int mach64_count __initdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX (M64F_GX)
340 #define ATI_CHIP_88800CX (M64F_GX)
342 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
354 /* make sets shorter */
355 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
357 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
358 /*#define ATI_CHIP_264GTDVD ?*/
359 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
361 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
362 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
363 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
365 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
366 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
373 } aty_chips[] __devinitdata = {
374 #ifdef CONFIG_FB_ATY_GX
376 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, ATI_CHIP_88800GX },
377 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, ATI_CHIP_88800CX },
378 #endif /* CONFIG_FB_ATY_GX */
380 #ifdef CONFIG_FB_ATY_CT
381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, ATI_CHIP_264CT },
382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, ATI_CHIP_264ET },
383 { PCI_CHIP_MACH64VT, "ATI264VT? (Mach64 VT)", 170, 67, 67, ATI_CHIP_264VT },
384 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, ATI_CHIP_264GT },
385 /* FIXME { ...ATI_264GU, maybe ATI_CHIP_264GTDVD }, */
386 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GTB)", 200, 67, 67, ATI_CHIP_264GTB },
387 { PCI_CHIP_MACH64VU, "ATI264VTB (Mach64 VU)", 200, 67, 67, ATI_CHIP_264VT3 },
389 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, ATI_CHIP_264LT },
390 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
391 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
393 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, ATI_CHIP_264VT4 },
395 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
396 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, ATI_CHIP_264GT2C },
398 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, ATI_CHIP_264GT2C },
400 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, ATI_CHIP_264GTPRO },
401 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, ATI_CHIP_264GTPRO },
402 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
403 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, ATI_CHIP_264GTPRO },
404 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, ATI_CHIP_264GTPRO },
406 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, ATI_CHIP_264LTPRO },
407 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, ATI_CHIP_264LTPRO },
408 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
409 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
410 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, ATI_CHIP_264LTPRO },
412 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP)", 230, 83, 63, ATI_CHIP_264XL },
413 { PCI_CHIP_MACH64GN, "3D RAGE XL (Mach64 GN, AGP)", 230, 83, 63, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66/BGA)", 230, 83, 63, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33MHz)", 235, 83, 63, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
416 { PCI_CHIP_MACH64GL, "3D RAGE XL (Mach64 GL, PCI)", 230, 83, 63, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GS, "3D RAGE XL (Mach64 GS, PCI)", 230, 83, 63, ATI_CHIP_264XL },
419 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
420 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
422 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, ATI_CHIP_MOBILITY },
423 #endif /* CONFIG_FB_ATY_CT */
427 static int __devinit correct_chipset(struct atyfb_par *par)
435 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
436 if (par->pci_id == aty_chips[i].pci_id)
439 name = aty_chips[i].name;
440 par->pll_limits.pll_max = aty_chips[i].pll;
441 par->pll_limits.mclk = aty_chips[i].mclk;
442 par->pll_limits.xclk = aty_chips[i].xclk;
443 par->features = aty_chips[i].features;
445 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
446 type = chip_id & CFG_CHIP_TYPE;
447 rev = (chip_id & CFG_CHIP_REV) >> 24;
449 switch(par->pci_id) {
450 #ifdef CONFIG_FB_ATY_GX
451 case PCI_CHIP_MACH64GX:
455 case PCI_CHIP_MACH64CX:
460 #ifdef CONFIG_FB_ATY_CT
461 case PCI_CHIP_MACH64VT:
464 name = "ATI264VTA3 (Mach64 VT)";
465 par->pll_limits.pll_max = 170;
466 par->pll_limits.mclk = 67;
467 par->pll_limits.xclk = 67;
468 par->features = ATI_CHIP_264VT;
469 } else if(rev == 0x40) {
470 name = "ATI264VTA4 (Mach64 VT)";
471 par->pll_limits.pll_max = 200;
472 par->pll_limits.mclk = 67;
473 par->pll_limits.xclk = 67;
474 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
476 name = "ATI264VTB (Mach64 VT)";
477 par->pll_limits.pll_max = 200;
478 par->pll_limits.mclk = 67;
479 par->pll_limits.xclk = 67;
480 par->features = ATI_CHIP_264VTB;
483 case PCI_CHIP_MACH64GT:
486 par->pll_limits.pll_max = 170;
487 par->pll_limits.mclk = 67;
488 par->pll_limits.xclk = 67;
489 par->features = ATI_CHIP_264GTB;
490 } else if(rev == 0x02) {
491 par->pll_limits.pll_max = 200;
492 par->pll_limits.mclk = 67;
493 par->pll_limits.xclk = 67;
494 par->features = ATI_CHIP_264GTB;
500 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
504 static char ram_dram[] __devinitdata = "DRAM";
505 static char ram_resv[] __devinitdata = "RESV";
506 #ifdef CONFIG_FB_ATY_GX
507 static char ram_vram[] __devinitdata = "VRAM";
508 #endif /* CONFIG_FB_ATY_GX */
509 #ifdef CONFIG_FB_ATY_CT
510 static char ram_edo[] __devinitdata = "EDO";
511 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
512 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
513 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
514 static char ram_off[] __devinitdata = "OFF";
515 #endif /* CONFIG_FB_ATY_CT */
518 static u32 pseudo_palette[17];
520 #ifdef CONFIG_FB_ATY_GX
521 static char *aty_gx_ram[8] __devinitdata = {
522 ram_dram, ram_vram, ram_vram, ram_dram,
523 ram_dram, ram_vram, ram_vram, ram_resv
525 #endif /* CONFIG_FB_ATY_GX */
527 #ifdef CONFIG_FB_ATY_CT
528 static char *aty_ct_ram[8] __devinitdata = {
529 ram_off, ram_dram, ram_edo, ram_edo,
530 ram_sdram, ram_sgram, ram_sdram32, ram_resv
532 #endif /* CONFIG_FB_ATY_CT */
534 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
536 u32 pixclock = var->pixclock;
537 #ifdef CONFIG_FB_ATY_GENERIC_LCD
539 par->pll.ct.xres = 0;
540 if (par->lcd_table != 0) {
541 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
542 if(lcd_on_off & LCD_ON) {
543 par->pll.ct.xres = var->xres;
544 pixclock = par->lcd_pixclock;
551 #if defined(CONFIG_PPC)
554 * Apple monitor sense
557 static int __init read_aty_sense(const struct atyfb_par *par)
561 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
563 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
565 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
566 sense = ((i & 0x3000) >> 3) | (i & 0x100);
568 /* drive each sense line low in turn and collect the other 2 */
569 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
571 i = aty_ld_le32(GP_IO, par);
572 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
573 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
576 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
578 i = aty_ld_le32(GP_IO, par);
579 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
580 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
583 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
585 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
586 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
590 #endif /* defined(CONFIG_PPC) */
592 /* ------------------------------------------------------------------------- */
598 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
600 #ifdef CONFIG_FB_ATY_GENERIC_LCD
601 if (par->lcd_table != 0) {
602 if(!M64_HAS(LT_LCD_REGS)) {
603 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
604 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
606 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
607 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
610 /* switch to non shadow registers */
611 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
612 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
614 /* save stretching */
615 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
616 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
617 if (!M64_HAS(LT_LCD_REGS))
618 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
621 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
622 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
623 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
624 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
625 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
626 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
627 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
629 #ifdef CONFIG_FB_ATY_GENERIC_LCD
630 if (par->lcd_table != 0) {
631 /* switch to shadow registers */
632 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
633 SHADOW_EN | SHADOW_RW_EN, par);
635 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
636 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
637 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
638 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
640 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
642 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
645 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
647 #ifdef CONFIG_FB_ATY_GENERIC_LCD
648 if (par->lcd_table != 0) {
650 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
652 /* update non-shadow registers first */
653 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
654 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
655 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
657 /* temporarily disable stretching */
658 aty_st_lcd(HORZ_STRETCHING,
659 crtc->horz_stretching &
660 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
661 aty_st_lcd(VERT_STRETCHING,
662 crtc->vert_stretching &
663 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
664 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
668 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
670 DPRINTK("setting up CRTC\n");
671 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
672 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
673 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
674 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
676 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
677 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
678 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
679 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
680 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
681 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
682 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
684 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
685 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
686 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
687 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
688 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
689 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
691 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
694 if (par->accel_flags & FB_ACCELF_TEXT)
695 aty_init_engine(par, info);
697 #ifdef CONFIG_FB_ATY_GENERIC_LCD
698 /* after setting the CRTC registers we should set the LCD registers. */
699 if (par->lcd_table != 0) {
700 /* switch to shadow registers */
701 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
702 (SHADOW_EN | SHADOW_RW_EN), par);
704 DPRINTK("set shadow CRT to %ix%i %c%c\n",
705 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
706 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
708 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
709 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
710 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
711 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
713 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
714 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
715 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
716 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
718 /* restore CRTC selection & shadow state and enable stretching */
719 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
720 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
721 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
722 if(!M64_HAS(LT_LCD_REGS))
723 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
725 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
726 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
727 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
728 if(!M64_HAS(LT_LCD_REGS)) {
729 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
730 aty_ld_le32(LCD_INDEX, par);
731 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
734 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
737 static int aty_var_to_crtc(const struct fb_info *info,
738 const struct fb_var_screeninfo *var, struct crtc *crtc)
740 struct atyfb_par *par = (struct atyfb_par *) info->par;
741 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
742 u32 sync, vmode, vdisplay;
743 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
744 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
745 u32 pix_width, dp_pix_width, dp_chain_mask;
750 vxres = var->xres_virtual;
751 vyres = var->yres_virtual;
752 xoffset = var->xoffset;
753 yoffset = var->yoffset;
754 bpp = var->bits_per_pixel;
756 bpp = (var->green.length == 5) ? 15 : 16;
760 /* convert (and round up) and validate */
761 if (vxres < xres + xoffset)
762 vxres = xres + xoffset;
765 if (vyres < yres + yoffset)
766 vyres = yres + yoffset;
771 pix_width = CRTC_PIX_WIDTH_8BPP;
773 HOST_8BPP | SRC_8BPP | DST_8BPP |
774 BYTE_ORDER_LSB_TO_MSB;
775 dp_chain_mask = DP_CHAIN_8BPP;
776 } else if (bpp <= 15) {
778 pix_width = CRTC_PIX_WIDTH_15BPP;
779 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
780 BYTE_ORDER_LSB_TO_MSB;
781 dp_chain_mask = DP_CHAIN_15BPP;
782 } else if (bpp <= 16) {
784 pix_width = CRTC_PIX_WIDTH_16BPP;
785 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
786 BYTE_ORDER_LSB_TO_MSB;
787 dp_chain_mask = DP_CHAIN_16BPP;
788 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
790 pix_width = CRTC_PIX_WIDTH_24BPP;
792 HOST_8BPP | SRC_8BPP | DST_8BPP |
793 BYTE_ORDER_LSB_TO_MSB;
794 dp_chain_mask = DP_CHAIN_24BPP;
795 } else if (bpp <= 32) {
797 pix_width = CRTC_PIX_WIDTH_32BPP;
798 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
799 BYTE_ORDER_LSB_TO_MSB;
800 dp_chain_mask = DP_CHAIN_32BPP;
804 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
805 FAIL("not enough video RAM");
807 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
808 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
810 if((xres > 1600) || (yres > 1200)) {
811 FAIL("MACH64 chips are designed for max 1600x1200\n"
812 "select anoter resolution.");
814 h_sync_strt = h_disp + var->right_margin;
815 h_sync_end = h_sync_strt + var->hsync_len;
816 h_sync_dly = var->right_margin & 7;
817 h_total = h_sync_end + h_sync_dly + var->left_margin;
819 v_sync_strt = v_disp + var->lower_margin;
820 v_sync_end = v_sync_strt + var->vsync_len;
821 v_total = v_sync_end + var->upper_margin;
823 #ifdef CONFIG_FB_ATY_GENERIC_LCD
824 if (par->lcd_table != 0) {
825 if(!M64_HAS(LT_LCD_REGS)) {
826 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
827 crtc->lcd_index = lcd_index &
828 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
829 aty_st_le32(LCD_INDEX, lcd_index, par);
832 if (!M64_HAS(MOBIL_BUS))
833 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
835 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
836 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
838 crtc->lcd_gen_cntl &=
839 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
840 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
841 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
842 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
844 if((crtc->lcd_gen_cntl & LCD_ON) &&
845 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
846 /* We cannot display the mode on the LCD. If the CRT is enabled
847 we can turn off the LCD.
848 If the CRT is off, it isn't a good idea to switch it on; we don't
849 know if one is connected. So it's better to fail then.
851 if (crtc->lcd_gen_cntl & CRT_ON) {
852 if (!(var->activate & FB_ACTIVATE_TEST))
853 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
854 crtc->lcd_gen_cntl &= ~LCD_ON;
855 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
857 if (!(var->activate & FB_ACTIVATE_TEST))
858 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
864 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
866 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
867 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
868 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
870 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
872 /* This is horror! When we simulate, say 640x480 on an 800x600
873 LCD monitor, the CRTC should be programmed 800x600 values for
874 the non visible part, but 640x480 for the visible part.
875 This code has been tested on a laptop with it's 1400x1050 LCD
876 monitor and a conventional monitor both switched on.
877 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
878 works with little glitches also with DOUBLESCAN modes
880 if (yres < par->lcd_height) {
881 VScan = par->lcd_height / yres;
884 vmode |= FB_VMODE_DOUBLE;
888 h_sync_strt = h_disp + par->lcd_right_margin;
889 h_sync_end = h_sync_strt + par->lcd_hsync_len;
890 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
891 h_total = h_disp + par->lcd_hblank_len;
893 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
894 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
895 v_total = v_disp + par->lcd_vblank_len / VScan;
897 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
899 h_disp = (h_disp >> 3) - 1;
900 h_sync_strt = (h_sync_strt >> 3) - 1;
901 h_sync_end = (h_sync_end >> 3) - 1;
902 h_total = (h_total >> 3) - 1;
903 h_sync_wid = h_sync_end - h_sync_strt;
905 FAIL_MAX("h_disp too large", h_disp, 0xff);
906 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
907 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
908 if(h_sync_wid > 0x1f)
910 FAIL_MAX("h_total too large", h_total, 0x1ff);
912 if (vmode & FB_VMODE_DOUBLE) {
920 #ifdef CONFIG_FB_ATY_GENERIC_LCD
921 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
922 vdisplay = par->lcd_height;
929 v_sync_wid = v_sync_end - v_sync_strt;
931 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
932 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
933 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
934 if(v_sync_wid > 0x1f)
936 FAIL_MAX("v_total too large", v_total, 0x7ff);
938 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
943 crtc->xoffset = xoffset;
944 crtc->yoffset = yoffset;
946 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
947 crtc->vline_crnt_vline = 0;
949 crtc->h_tot_disp = h_total | (h_disp<<16);
950 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
951 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
952 crtc->v_tot_disp = v_total | (v_disp<<16);
953 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
955 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
956 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
957 crtc->gen_cntl |= CRTC_VGA_LINEAR;
959 /* Enable doublescan mode if requested */
960 if (vmode & FB_VMODE_DOUBLE)
961 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
962 /* Enable interlaced mode if requested */
963 if (vmode & FB_VMODE_INTERLACED)
964 crtc->gen_cntl |= CRTC_INTERLACE_EN;
965 #ifdef CONFIG_FB_ATY_GENERIC_LCD
966 if (par->lcd_table != 0) {
968 if(vmode & FB_VMODE_DOUBLE)
970 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
971 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
972 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
973 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
974 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
976 /* MOBILITY M1 tested, FIXME: LT */
977 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
978 if (!M64_HAS(LT_LCD_REGS))
979 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
980 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
982 crtc->horz_stretching &=
983 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
984 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
985 if (xres < par->lcd_width) {
988 * The horizontal blender misbehaves when HDisplay is less than a
989 * a certain threshold (440 for a 1024-wide panel). It doesn't
990 * stretch such modes enough. Use pixel replication instead of
991 * blending to stretch modes that can be made to exactly fit the
992 * panel width. The undocumented "NoLCDBlend" option allows the
993 * pixel-replicated mode to be slightly wider or narrower than the
994 * panel width. It also causes a mode that is exactly half as wide
995 * as the panel to be pixel-replicated, rather than blended.
997 int HDisplay = xres & ~7;
998 int nStretch = par->lcd_width / HDisplay;
999 int Remainder = par->lcd_width % HDisplay;
1001 if ((!Remainder && ((nStretch > 2))) ||
1002 (((HDisplay * 16) / par->lcd_width) < 7)) {
1003 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1004 int horz_stretch_loop = -1, BestRemainder;
1005 int Numerator = HDisplay, Denominator = par->lcd_width;
1007 ATIReduceRatio(&Numerator, &Denominator);
1009 BestRemainder = (Numerator * 16) / Denominator;
1010 while (--Index >= 0) {
1011 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1013 if (Remainder < BestRemainder) {
1014 horz_stretch_loop = Index;
1015 if (!(BestRemainder = Remainder))
1020 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1021 int horz_stretch_ratio = 0, Accumulator = 0;
1022 int reuse_previous = 1;
1024 Index = StretchLoops[horz_stretch_loop];
1026 while (--Index >= 0) {
1027 if (Accumulator > 0)
1028 horz_stretch_ratio |= reuse_previous;
1030 Accumulator += Denominator;
1031 Accumulator -= Numerator;
1032 reuse_previous <<= 1;
1035 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1036 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1037 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1038 break; /* Out of the do { ... } while (0) */
1042 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1043 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1047 if (vdisplay < par->lcd_height) {
1048 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1049 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1051 if (!M64_HAS(LT_LCD_REGS) &&
1052 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1053 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1056 * Don't use vertical blending if the mode is too wide or not
1057 * vertically stretched.
1059 crtc->vert_stretching = 0;
1061 /* copy to shadow crtc */
1062 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1063 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1064 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1065 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1067 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1069 if (M64_HAS(MAGIC_FIFO)) {
1070 /* FIXME: display FIFO low watermark values */
1071 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1073 crtc->dp_pix_width = dp_pix_width;
1074 crtc->dp_chain_mask = dp_chain_mask;
1079 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1081 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1082 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1084 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1086 u32 double_scan, interlace;
1089 h_total = crtc->h_tot_disp & 0x1ff;
1090 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1091 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1092 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1093 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1094 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1095 v_total = crtc->v_tot_disp & 0x7ff;
1096 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1097 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1098 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1099 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1100 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1101 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1102 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1103 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1106 xres = (h_disp + 1) * 8;
1108 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1109 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1110 hslen = h_sync_wid * 8;
1111 upper = v_total - v_sync_strt - v_sync_wid;
1112 lower = v_sync_strt - v_disp;
1114 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1115 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1116 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1118 switch (pix_width) {
1120 case CRTC_PIX_WIDTH_4BPP:
1122 var->red.offset = 0;
1123 var->red.length = 8;
1124 var->green.offset = 0;
1125 var->green.length = 8;
1126 var->blue.offset = 0;
1127 var->blue.length = 8;
1128 var->transp.offset = 0;
1129 var->transp.length = 0;
1132 case CRTC_PIX_WIDTH_8BPP:
1134 var->red.offset = 0;
1135 var->red.length = 8;
1136 var->green.offset = 0;
1137 var->green.length = 8;
1138 var->blue.offset = 0;
1139 var->blue.length = 8;
1140 var->transp.offset = 0;
1141 var->transp.length = 0;
1143 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1145 var->red.offset = 10;
1146 var->red.length = 5;
1147 var->green.offset = 5;
1148 var->green.length = 5;
1149 var->blue.offset = 0;
1150 var->blue.length = 5;
1151 var->transp.offset = 0;
1152 var->transp.length = 0;
1154 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1156 var->red.offset = 11;
1157 var->red.length = 5;
1158 var->green.offset = 5;
1159 var->green.length = 6;
1160 var->blue.offset = 0;
1161 var->blue.length = 5;
1162 var->transp.offset = 0;
1163 var->transp.length = 0;
1165 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1167 var->red.offset = 16;
1168 var->red.length = 8;
1169 var->green.offset = 8;
1170 var->green.length = 8;
1171 var->blue.offset = 0;
1172 var->blue.length = 8;
1173 var->transp.offset = 0;
1174 var->transp.length = 0;
1176 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1178 var->red.offset = 16;
1179 var->red.length = 8;
1180 var->green.offset = 8;
1181 var->green.length = 8;
1182 var->blue.offset = 0;
1183 var->blue.length = 8;
1184 var->transp.offset = 24;
1185 var->transp.length = 8;
1188 PRINTKE("Invalid pixel width\n");
1195 var->xres_virtual = crtc->vxres;
1196 var->yres_virtual = crtc->vyres;
1197 var->bits_per_pixel = bpp;
1198 var->left_margin = left;
1199 var->right_margin = right;
1200 var->upper_margin = upper;
1201 var->lower_margin = lower;
1202 var->hsync_len = hslen;
1203 var->vsync_len = vslen;
1205 var->vmode = FB_VMODE_NONINTERLACED;
1206 /* In double scan mode, the vertical parameters are doubled, so we need to
1207 half them to get the right values.
1208 In interlaced mode the values are already correct, so no correction is
1212 var->vmode = FB_VMODE_INTERLACED;
1215 var->vmode = FB_VMODE_DOUBLE;
1217 var->upper_margin>>=1;
1218 var->lower_margin>>=1;
1225 /* ------------------------------------------------------------------------- */
1227 static int atyfb_set_par(struct fb_info *info)
1229 struct atyfb_par *par = (struct atyfb_par *) info->par;
1230 struct fb_var_screeninfo *var = &info->var;
1234 struct fb_var_screeninfo debug;
1240 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1243 pixclock = atyfb_get_pixclock(var, par);
1245 if (pixclock == 0) {
1246 PRINTKE("Invalid pixclock\n");
1249 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1253 par->accel_flags = var->accel_flags; /* hack */
1255 if (par->blitter_may_be_busy)
1258 aty_set_crtc(par, &par->crtc);
1259 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1260 par->pll_ops->set_pll(info, &par->pll);
1263 if(par->pll_ops && par->pll_ops->pll_to_var)
1264 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1268 if(0 == pixclock_in_ps) {
1269 PRINTKE("ALERT ops->pll_to_var get 0\n");
1270 pixclock_in_ps = pixclock;
1273 memset(&debug, 0, sizeof(debug));
1274 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1275 u32 hSync, vRefresh;
1276 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1277 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1279 h_disp = debug.xres;
1280 h_sync_strt = h_disp + debug.right_margin;
1281 h_sync_end = h_sync_strt + debug.hsync_len;
1282 h_total = h_sync_end + debug.left_margin;
1283 v_disp = debug.yres;
1284 v_sync_strt = v_disp + debug.lower_margin;
1285 v_sync_end = v_sync_strt + debug.vsync_len;
1286 v_total = v_sync_end + debug.upper_margin;
1288 hSync = 1000000000 / (pixclock_in_ps * h_total);
1289 vRefresh = (hSync * 1000) / v_total;
1290 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1292 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1295 DPRINTK("atyfb_set_par\n");
1296 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1297 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1298 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1299 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1300 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1301 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1302 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1303 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1304 h_disp, h_sync_strt, h_sync_end, h_total,
1305 v_disp, v_sync_strt, v_sync_end, v_total);
1306 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1308 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1309 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1313 if (!M64_HAS(INTEGRATED)) {
1314 /* Don't forget MEM_CNTL */
1315 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1316 switch (var->bits_per_pixel) {
1327 aty_st_le32(MEM_CNTL, tmp, par);
1329 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1330 if (!M64_HAS(MAGIC_POSTDIV))
1331 tmp |= par->mem_refresh_rate << 20;
1332 switch (var->bits_per_pixel) {
1344 if (M64_HAS(CT_BUS)) {
1345 aty_st_le32(DAC_CNTL, 0x87010184, par);
1346 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1347 } else if (M64_HAS(VT_BUS)) {
1348 aty_st_le32(DAC_CNTL, 0x87010184, par);
1349 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1350 } else if (M64_HAS(MOBIL_BUS)) {
1351 aty_st_le32(DAC_CNTL, 0x80010102, par);
1352 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1355 aty_st_le32(DAC_CNTL, 0x86010102, par);
1356 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1357 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1359 aty_st_le32(MEM_CNTL, tmp, par);
1361 aty_st_8(DAC_MASK, 0xff, par);
1363 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1364 info->fix.visual = var->bits_per_pixel <= 8 ?
1365 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1367 /* Initialize the graphics engine */
1368 if (par->accel_flags & FB_ACCELF_TEXT)
1369 aty_init_engine(par, info);
1371 #ifdef CONFIG_BOOTX_TEXT
1372 btext_update_display(info->fix.smem_start,
1373 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1374 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1375 var->bits_per_pixel,
1376 par->crtc.vxres * var->bits_per_pixel / 8);
1377 #endif /* CONFIG_BOOTX_TEXT */
1379 /* switch to accelerator mode */
1380 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1381 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1385 /* dump non shadow CRTC, pll, LCD registers */
1388 /* CRTC registers */
1390 printk("debug atyfb: Mach64 non-shadow register values:");
1391 for (i = 0; i < 256; i = i+4) {
1392 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1393 printk(" %08X", aty_ld_le32(i, par));
1397 #ifdef CONFIG_FB_ATY_CT
1400 printk("debug atyfb: Mach64 PLL register values:");
1401 for (i = 0; i < 64; i++) {
1402 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1403 if(i%4 == 0) printk(" ");
1404 printk("%02X", aty_ld_pll_ct(i, par));
1407 #endif /* CONFIG_FB_ATY_CT */
1409 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1410 if (par->lcd_table != 0) {
1413 printk("debug atyfb: LCD register values:");
1414 if(M64_HAS(LT_LCD_REGS)) {
1415 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1416 if(i == EXT_VERT_STRETCH)
1418 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1419 printk(" %08X", aty_ld_lcd(i, par));
1423 for (i = 0; i < 64; i++) {
1424 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1425 printk(" %08X", aty_ld_lcd(i, par));
1430 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1436 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1438 struct atyfb_par *par = (struct atyfb_par *) info->par;
1444 memcpy(&pll, &(par->pll), sizeof(pll));
1446 if((err = aty_var_to_crtc(info, var, &crtc)))
1449 pixclock = atyfb_get_pixclock(var, par);
1451 if (pixclock == 0) {
1452 if (!(var->activate & FB_ACTIVATE_TEST))
1453 PRINTKE("Invalid pixclock\n");
1456 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1460 if (var->accel_flags & FB_ACCELF_TEXT)
1461 info->var.accel_flags = FB_ACCELF_TEXT;
1463 info->var.accel_flags = 0;
1465 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1466 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1469 aty_crtc_to_var(&crtc, var);
1470 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1474 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1476 u32 xoffset = info->var.xoffset;
1477 u32 yoffset = info->var.yoffset;
1478 u32 vxres = par->crtc.vxres;
1479 u32 bpp = info->var.bits_per_pixel;
1481 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1486 * Open/Release the frame buffer device
1489 static int atyfb_open(struct fb_info *info, int user)
1491 struct atyfb_par *par = (struct atyfb_par *) info->par;
1502 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1504 struct atyfb_par *par = dev_id;
1508 spin_lock(&par->int_lock);
1510 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1512 if (int_cntl & CRTC_VBLANK_INT) {
1513 /* clear interrupt */
1514 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1515 par->vblank.count++;
1516 if (par->vblank.pan_display) {
1517 par->vblank.pan_display = 0;
1518 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1520 wake_up_interruptible(&par->vblank.wait);
1524 spin_unlock(&par->int_lock);
1526 return IRQ_RETVAL(handled);
1529 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1533 if (!test_and_set_bit(0, &par->irq_flags)) {
1534 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1535 clear_bit(0, &par->irq_flags);
1538 spin_lock_irq(&par->int_lock);
1539 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1540 /* clear interrupt */
1541 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1542 /* enable interrupt */
1543 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1544 spin_unlock_irq(&par->int_lock);
1545 } else if (reenable) {
1546 spin_lock_irq(&par->int_lock);
1547 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1548 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1549 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1550 /* re-enable interrupt */
1551 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1553 spin_unlock_irq(&par->int_lock);
1559 static int aty_disable_irq(struct atyfb_par *par)
1563 if (test_and_clear_bit(0, &par->irq_flags)) {
1564 if (par->vblank.pan_display) {
1565 par->vblank.pan_display = 0;
1566 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1568 spin_lock_irq(&par->int_lock);
1569 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1570 /* disable interrupt */
1571 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1572 spin_unlock_irq(&par->int_lock);
1573 free_irq(par->irq, par);
1579 static int atyfb_release(struct fb_info *info, int user)
1581 struct atyfb_par *par = (struct atyfb_par *) info->par;
1588 int was_mmaped = par->mmaped;
1593 struct fb_var_screeninfo var;
1595 /* Now reset the default display config, we have no
1596 * idea what the program(s) which mmap'd the chip did
1597 * to the configuration, nor whether it restored it
1602 var.accel_flags &= ~FB_ACCELF_TEXT;
1604 var.accel_flags |= FB_ACCELF_TEXT;
1605 if (var.yres == var.yres_virtual) {
1606 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1607 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1608 if (var.yres_virtual < var.yres)
1609 var.yres_virtual = var.yres;
1613 aty_disable_irq(par);
1620 * Pan or Wrap the Display
1622 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1625 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1627 struct atyfb_par *par = (struct atyfb_par *) info->par;
1628 u32 xres, yres, xoffset, yoffset;
1630 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1631 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1632 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1634 xoffset = (var->xoffset + 7) & ~7;
1635 yoffset = var->yoffset;
1636 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1638 info->var.xoffset = xoffset;
1639 info->var.yoffset = yoffset;
1643 set_off_pitch(par, info);
1644 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1645 par->vblank.pan_display = 1;
1647 par->vblank.pan_display = 0;
1648 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1654 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1656 struct aty_interrupt *vbl;
1668 ret = aty_enable_irq(par, 0);
1673 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1678 aty_enable_irq(par, 1);
1687 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1688 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1694 u8 mclk_post_div; /* 1,2,3,4,8 */
1695 u8 mclk_fb_mult; /* 2 or 4 */
1696 u8 xclk_post_div; /* 1,2,3,4,8 */
1698 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1699 u32 dsp_xclks_per_row; /* 0-16383 */
1700 u32 dsp_loop_latency; /* 0-15 */
1701 u32 dsp_precision; /* 0-7 */
1702 u32 dsp_on; /* 0-2047 */
1703 u32 dsp_off; /* 0-2047 */
1706 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1707 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1710 #ifndef FBIO_WAITFORVSYNC
1711 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1714 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1715 u_long arg, struct fb_info *info)
1717 struct atyfb_par *par = (struct atyfb_par *) info->par;
1719 struct fbtype fbtyp;
1725 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1726 fbtyp.fb_width = par->crtc.vxres;
1727 fbtyp.fb_height = par->crtc.vyres;
1728 fbtyp.fb_depth = info->var.bits_per_pixel;
1729 fbtyp.fb_cmsize = info->cmap.len;
1730 fbtyp.fb_size = info->fix.smem_len;
1731 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1734 #endif /* __sparc__ */
1736 case FBIO_WAITFORVSYNC:
1740 if (get_user(crtc, (__u32 __user *) arg))
1743 return aty_waitforvblank(par, crtc);
1747 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1749 if (M64_HAS(INTEGRATED)) {
1751 union aty_pll *pll = &(par->pll);
1752 u32 dsp_config = pll->ct.dsp_config;
1753 u32 dsp_on_off = pll->ct.dsp_on_off;
1754 clk.ref_clk_per = par->ref_clk_per;
1755 clk.pll_ref_div = pll->ct.pll_ref_div;
1756 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1757 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1758 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1759 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1760 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1761 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1762 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1763 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1764 clk.dsp_precision = (dsp_config >> 20) & 7;
1765 clk.dsp_off = dsp_on_off & 0x7ff;
1766 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1767 if (copy_to_user((struct atyclk __user *) arg, &clk,
1774 if (M64_HAS(INTEGRATED)) {
1776 union aty_pll *pll = &(par->pll);
1777 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1779 par->ref_clk_per = clk.ref_clk_per;
1780 pll->ct.pll_ref_div = clk.pll_ref_div;
1781 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1782 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1783 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1784 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1785 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1786 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1787 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1788 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1789 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1790 /*aty_calc_pll_ct(info, &pll->ct);*/
1791 aty_set_pll_ct(info, pll);
1796 if (get_user(par->features, (u32 __user *) arg))
1800 if (put_user(par->features, (u32 __user *) arg))
1803 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1810 static int atyfb_sync(struct fb_info *info)
1812 struct atyfb_par *par = (struct atyfb_par *) info->par;
1814 if (par->blitter_may_be_busy)
1820 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1822 struct atyfb_par *par = (struct atyfb_par *) info->par;
1823 unsigned int size, page, map_size = 0;
1824 unsigned long map_offset = 0;
1831 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1834 off = vma->vm_pgoff << PAGE_SHIFT;
1835 size = vma->vm_end - vma->vm_start;
1837 /* To stop the swapper from even considering these pages. */
1838 vma->vm_flags |= (VM_IO | VM_RESERVED);
1840 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1841 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1842 off += 0x8000000000000000UL;
1844 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1846 /* Each page, see which map applies */
1847 for (page = 0; page < size;) {
1849 for (i = 0; par->mmap_map[i].size; i++) {
1850 unsigned long start = par->mmap_map[i].voff;
1851 unsigned long end = start + par->mmap_map[i].size;
1852 unsigned long offset = off + page;
1859 map_size = par->mmap_map[i].size - (offset - start);
1861 par->mmap_map[i].poff + (offset - start);
1868 if (page + map_size > size)
1869 map_size = size - page;
1871 pgprot_val(vma->vm_page_prot) &=
1872 ~(par->mmap_map[i].prot_mask);
1873 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1875 if (remap_pfn_range(vma, vma->vm_start + page,
1876 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1897 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1901 for (i = 0; i < 256; i++) {
1902 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1903 if (M64_HAS(EXTRA_BRIGHT))
1905 aty_st_8(DAC_CNTL, tmp, par);
1906 aty_st_8(DAC_MASK, 0xff, par);
1908 writeb(i, &par->aty_cmap_regs->rindex);
1909 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1910 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1911 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1912 writeb(i, &par->aty_cmap_regs->windex);
1913 writeb(atyfb_save.r[1 - enter][i],
1914 &par->aty_cmap_regs->lut);
1915 writeb(atyfb_save.g[1 - enter][i],
1916 &par->aty_cmap_regs->lut);
1917 writeb(atyfb_save.b[1 - enter][i],
1918 &par->aty_cmap_regs->lut);
1922 static void atyfb_palette(int enter)
1924 struct atyfb_par *par;
1925 struct fb_info *info;
1928 for (i = 0; i < FB_MAX; i++) {
1929 info = registered_fb[i];
1930 if (info && info->fbops == &atyfb_ops) {
1931 par = (struct atyfb_par *) info->par;
1933 atyfb_save_palette(par, enter);
1935 atyfb_save.yoffset = info->var.yoffset;
1936 info->var.yoffset = 0;
1937 set_off_pitch(par, info);
1939 info->var.yoffset = atyfb_save.yoffset;
1940 set_off_pitch(par, info);
1942 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1947 #endif /* __sparc__ */
1951 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1953 /* Power management routines. Those are used for PowerBook sleep.
1955 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1960 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1961 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1962 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1963 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1969 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1970 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1972 pm &= ~(PWR_BLON | AUTO_PWR_UP);
1974 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1975 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1978 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1980 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1982 if ((--timeout) == 0)
1984 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1992 pm |= (PWR_BLON | AUTO_PWR_UP);
1993 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1994 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1997 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1999 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2001 if ((--timeout) == 0)
2003 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2007 return timeout ? 0 : -EIO;
2010 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2012 struct fb_info *info = pci_get_drvdata(pdev);
2013 struct atyfb_par *par = (struct atyfb_par *) info->par;
2015 #ifndef CONFIG_PPC_PMAC
2016 /* HACK ALERT ! Once I find a proper way to say to each driver
2017 * individually what will happen with it's PCI slot, I'll change
2018 * that. On laptops, the AGP slot is just unclocked, so D2 is
2019 * expected, while on desktops, the card is powered off
2022 #endif /* CONFIG_PPC_PMAC */
2024 if (state.event == pdev->dev.power.power_state.event)
2027 acquire_console_sem();
2029 fb_set_suspend(info, 1);
2031 /* Idle & reset engine */
2033 aty_reset_engine(par);
2035 /* Blank display and LCD */
2036 atyfb_blank(FB_BLANK_POWERDOWN, info);
2039 par->lock_blank = 1;
2041 /* Set chip to "suspend" mode */
2042 if (aty_power_mgmt(1, par)) {
2044 par->lock_blank = 0;
2045 atyfb_blank(FB_BLANK_UNBLANK, info);
2046 fb_set_suspend(info, 0);
2047 release_console_sem();
2051 release_console_sem();
2053 pdev->dev.power.power_state = state;
2058 static int atyfb_pci_resume(struct pci_dev *pdev)
2060 struct fb_info *info = pci_get_drvdata(pdev);
2061 struct atyfb_par *par = (struct atyfb_par *) info->par;
2063 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2066 acquire_console_sem();
2068 if (pdev->dev.power.power_state.event == 2)
2069 aty_power_mgmt(0, par);
2072 /* Restore display */
2073 atyfb_set_par(info);
2076 fb_set_suspend(info, 0);
2079 par->lock_blank = 0;
2080 atyfb_blank(FB_BLANK_UNBLANK, info);
2082 release_console_sem();
2084 pdev->dev.power.power_state = PMSG_ON;
2089 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2091 #ifdef CONFIG_PMAC_BACKLIGHT
2094 * LCD backlight control
2097 static int backlight_conv[] = {
2098 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2099 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2102 static int aty_set_backlight_enable(int on, int level, void *data)
2104 struct fb_info *info = (struct fb_info *) data;
2105 struct atyfb_par *par = (struct atyfb_par *) info->par;
2106 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2108 reg |= (BLMOD_EN | BIASMOD_EN);
2109 if (on && level > BACKLIGHT_OFF) {
2110 reg &= ~BIAS_MOD_LEVEL_MASK;
2111 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2113 reg &= ~BIAS_MOD_LEVEL_MASK;
2114 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2116 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2120 static int aty_set_backlight_level(int level, void *data)
2122 return aty_set_backlight_enable(1, level, data);
2125 static struct backlight_controller aty_backlight_controller = {
2126 aty_set_backlight_enable,
2127 aty_set_backlight_level
2129 #endif /* CONFIG_PMAC_BACKLIGHT */
2131 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2133 const int ragepro_tbl[] = {
2134 44, 50, 55, 66, 75, 80, 100
2136 const int ragexl_tbl[] = {
2137 50, 66, 75, 83, 90, 95, 100, 105,
2138 110, 115, 120, 125, 133, 143, 166
2140 const int *refresh_tbl;
2143 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2144 refresh_tbl = ragexl_tbl;
2145 size = sizeof(ragexl_tbl)/sizeof(int);
2147 refresh_tbl = ragepro_tbl;
2148 size = sizeof(ragepro_tbl)/sizeof(int);
2151 for (i=0; i < size; i++) {
2152 if (xclk < refresh_tbl[i])
2155 par->mem_refresh_rate = i;
2162 static struct fb_info *fb_list = NULL;
2164 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2165 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2166 struct fb_var_screeninfo *var)
2170 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2172 var->xres = var->xres_virtual = par->lcd_hdisp;
2173 var->right_margin = par->lcd_right_margin;
2174 var->left_margin = par->lcd_hblank_len -
2175 (par->lcd_right_margin + par->lcd_hsync_dly +
2176 par->lcd_hsync_len);
2177 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2178 var->yres = var->yres_virtual = par->lcd_vdisp;
2179 var->lower_margin = par->lcd_lower_margin;
2180 var->upper_margin = par->lcd_vblank_len -
2181 (par->lcd_lower_margin + par->lcd_vsync_len);
2182 var->vsync_len = par->lcd_vsync_len;
2183 var->pixclock = par->lcd_pixclock;
2189 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2191 static int __init aty_init(struct fb_info *info, const char *name)
2193 struct atyfb_par *par = (struct atyfb_par *) info->par;
2194 const char *ramname = NULL, *xtal;
2195 int gtb_memsize, has_var = 0;
2196 struct fb_var_screeninfo var;
2199 #if defined(CONFIG_PPC)
2203 init_waitqueue_head(&par->vblank.wait);
2204 spin_lock_init(&par->int_lock);
2206 par->aty_cmap_regs =
2207 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2209 #ifdef CONFIG_PPC_PMAC
2210 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2211 * and set the frequency manually. */
2212 if (machine_is_compatible("PowerBook2,1")) {
2213 par->pll_limits.mclk = 70;
2214 par->pll_limits.xclk = 53;
2218 par->pll_limits.pll_max = pll;
2220 par->pll_limits.mclk = mclk;
2222 par->pll_limits.xclk = xclk;
2224 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2225 par->pll_per = 1000000/par->pll_limits.pll_max;
2226 par->mclk_per = 1000000/par->pll_limits.mclk;
2227 par->xclk_per = 1000000/par->pll_limits.xclk;
2229 par->ref_clk_per = 1000000000000ULL / 14318180;
2232 #ifdef CONFIG_FB_ATY_GX
2233 if (!M64_HAS(INTEGRATED)) {
2235 u8 dac_type, dac_subtype, clk_type;
2236 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2237 par->bus_type = (stat0 >> 0) & 0x07;
2238 par->ram_type = (stat0 >> 3) & 0x07;
2239 ramname = aty_gx_ram[par->ram_type];
2240 /* FIXME: clockchip/RAMDAC probing? */
2241 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2243 clk_type = CLK_ATI18818_1;
2244 dac_type = (stat0 >> 9) & 0x07;
2245 if (dac_type == 0x07)
2246 dac_subtype = DAC_ATT20C408;
2248 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2250 dac_type = DAC_IBMRGB514;
2251 dac_subtype = DAC_IBMRGB514;
2252 clk_type = CLK_IBMRGB514;
2254 switch (dac_subtype) {
2256 par->dac_ops = &aty_dac_ibm514;
2258 case DAC_ATI68860_B:
2259 case DAC_ATI68860_C:
2260 par->dac_ops = &aty_dac_ati68860b;
2264 par->dac_ops = &aty_dac_att21c498;
2267 PRINTKI("aty_init: DAC type not implemented yet!\n");
2268 par->dac_ops = &aty_dac_unsupported;
2272 case CLK_ATI18818_1:
2273 par->pll_ops = &aty_pll_ati18818_1;
2276 par->pll_ops = &aty_pll_stg1703;
2279 par->pll_ops = &aty_pll_ch8398;
2282 par->pll_ops = &aty_pll_att20c408;
2285 par->pll_ops = &aty_pll_ibm514;
2288 PRINTKI("aty_init: CLK type not implemented yet!");
2289 par->pll_ops = &aty_pll_unsupported;
2293 #endif /* CONFIG_FB_ATY_GX */
2294 #ifdef CONFIG_FB_ATY_CT
2295 if (M64_HAS(INTEGRATED)) {
2296 par->dac_ops = &aty_dac_ct;
2297 par->pll_ops = &aty_pll_ct;
2298 par->bus_type = PCI;
2299 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2300 ramname = aty_ct_ram[par->ram_type];
2301 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2302 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2303 par->pll_limits.mclk = 63;
2306 if (M64_HAS(GTB_DSP)
2307 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2309 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2310 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2315 if (diff2 < diff1) {
2316 par->ref_clk_per = 1000000000000ULL / 29498928;
2320 #endif /* CONFIG_FB_ATY_CT */
2322 /* save previous video mode */
2323 aty_get_crtc(par, &saved_crtc);
2324 if(par->pll_ops->get_pll)
2325 par->pll_ops->get_pll(info, &saved_pll);
2327 i = aty_ld_le32(MEM_CNTL, par);
2328 gtb_memsize = M64_HAS(GTB_DSP);
2330 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2332 info->fix.smem_len = 0x80000;
2335 info->fix.smem_len = 0x100000;
2337 case MEM_SIZE_2M_GTB:
2338 info->fix.smem_len = 0x200000;
2340 case MEM_SIZE_4M_GTB:
2341 info->fix.smem_len = 0x400000;
2343 case MEM_SIZE_6M_GTB:
2344 info->fix.smem_len = 0x600000;
2346 case MEM_SIZE_8M_GTB:
2347 info->fix.smem_len = 0x800000;
2350 info->fix.smem_len = 0x80000;
2352 switch (i & MEM_SIZE_ALIAS) {
2354 info->fix.smem_len = 0x80000;
2357 info->fix.smem_len = 0x100000;
2360 info->fix.smem_len = 0x200000;
2363 info->fix.smem_len = 0x400000;
2366 info->fix.smem_len = 0x600000;
2369 info->fix.smem_len = 0x800000;
2372 info->fix.smem_len = 0x80000;
2375 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2376 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2377 info->fix.smem_len += 0x400000;
2381 info->fix.smem_len = vram * 1024;
2382 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2383 if (info->fix.smem_len <= 0x80000)
2385 else if (info->fix.smem_len <= 0x100000)
2387 else if (info->fix.smem_len <= 0x200000)
2388 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2389 else if (info->fix.smem_len <= 0x400000)
2390 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2391 else if (info->fix.smem_len <= 0x600000)
2392 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2394 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2395 aty_st_le32(MEM_CNTL, i, par);
2399 * Reg Block 0 (CT-compatible block) is at mmio_start
2400 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2403 info->fix.mmio_len = 0x400;
2404 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2405 } else if (M64_HAS(CT)) {
2406 info->fix.mmio_len = 0x400;
2407 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2408 } else if (M64_HAS(VT)) {
2409 info->fix.mmio_start -= 0x400;
2410 info->fix.mmio_len = 0x800;
2411 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2413 info->fix.mmio_start -= 0x400;
2414 info->fix.mmio_len = 0x800;
2415 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2418 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2419 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2420 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2421 par->pll_limits.mclk, par->pll_limits.xclk);
2423 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2424 if (M64_HAS(INTEGRATED)) {
2426 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2427 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2428 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2430 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2431 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2432 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2433 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2434 for (i = 0; i < 40; i++)
2435 printk(" %02x", aty_ld_pll_ct(i, par));
2439 if(par->pll_ops->init_pll)
2440 par->pll_ops->init_pll(info, &par->pll);
2443 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2444 * FIXME: we should use the auxiliary aperture instead so we can access
2445 * the full 8 MB of video RAM on 8 MB boards
2448 if (!par->aux_start &&
2449 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2450 info->fix.smem_len -= GUI_RESERVE;
2453 * Disable register access through the linear aperture
2454 * if the auxiliary aperture is used so we can access
2455 * the full 8 MB of video RAM on 8 MB boards.
2458 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2461 par->mtrr_aper = -1;
2464 /* Cover the whole resource. */
2465 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2466 if (par->mtrr_aper >= 0 && !par->aux_start) {
2467 /* Make a hole for mmio. */
2468 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2469 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2470 if (par->mtrr_reg < 0) {
2471 mtrr_del(par->mtrr_aper, 0, 0);
2472 par->mtrr_aper = -1;
2478 info->fbops = &atyfb_ops;
2479 info->pseudo_palette = pseudo_palette;
2480 info->flags = FBINFO_FLAG_DEFAULT;
2482 #ifdef CONFIG_PMAC_BACKLIGHT
2483 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2484 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2485 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2486 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2487 } else if (M64_HAS(MOBIL_BUS))
2488 register_backlight_controller(&aty_backlight_controller, info, "ati");
2489 #endif /* CONFIG_PMAC_BACKLIGHT */
2491 memset(&var, 0, sizeof(var));
2493 if (_machine == _MACH_Pmac) {
2495 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2496 * applies to all Mac video cards
2499 if (mac_find_mode(&var, info, mode, 8))
2502 if (default_vmode == VMODE_CHOOSE) {
2503 if (M64_HAS(G3_PB_1024x768))
2504 /* G3 PowerBook with 1024x768 LCD */
2505 default_vmode = VMODE_1024_768_60;
2506 else if (machine_is_compatible("iMac"))
2507 default_vmode = VMODE_1024_768_75;
2508 else if (machine_is_compatible
2510 /* iBook with 800x600 LCD */
2511 default_vmode = VMODE_800_600_60;
2513 default_vmode = VMODE_640_480_67;
2514 sense = read_aty_sense(par);
2515 PRINTKI("monitor sense=%x, mode %d\n",
2516 sense, mac_map_monitor_sense(sense));
2518 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2519 default_vmode = VMODE_640_480_60;
2520 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2521 default_cmode = CMODE_8;
2522 if (!mac_vmode_to_var(default_vmode, default_cmode,
2528 #endif /* !CONFIG_PPC */
2530 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2531 if (!atyfb_get_timings_from_lcd(par, &var))
2535 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2542 var.accel_flags &= ~FB_ACCELF_TEXT;
2544 var.accel_flags |= FB_ACCELF_TEXT;
2546 if (comp_sync != -1) {
2548 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2550 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2553 if (var.yres == var.yres_virtual) {
2554 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2555 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2556 if (var.yres_virtual < var.yres)
2557 var.yres_virtual = var.yres;
2560 if (atyfb_check_var(&var, info)) {
2561 PRINTKE("can't set default video mode\n");
2566 atyfb_save_palette(par, 0);
2569 #ifdef CONFIG_FB_ATY_CT
2570 if (!noaccel && M64_HAS(INTEGRATED))
2571 aty_init_cursor(info);
2572 #endif /* CONFIG_FB_ATY_CT */
2575 fb_alloc_cmap(&info->cmap, 256, 0);
2577 if (register_framebuffer(info) < 0)
2582 PRINTKI("fb%d: %s frame buffer device on %s\n",
2583 info->node, info->fix.id, name);
2587 /* restore video mode */
2588 aty_set_crtc(par, &saved_crtc);
2589 par->pll_ops->set_pll(info, &saved_pll);
2592 if (par->mtrr_reg >= 0) {
2593 mtrr_del(par->mtrr_reg, 0, 0);
2596 if (par->mtrr_aper >= 0) {
2597 mtrr_del(par->mtrr_aper, 0, 0);
2598 par->mtrr_aper = -1;
2605 static int __init store_video_par(char *video_str, unsigned char m64_num)
2608 unsigned long vmembase, size, guiregbase;
2610 PRINTKI("store_video_par() '%s' \n", video_str);
2612 if (!(p = strsep(&video_str, ";")) || !*p)
2613 goto mach64_invalid;
2614 vmembase = simple_strtoul(p, NULL, 0);
2615 if (!(p = strsep(&video_str, ";")) || !*p)
2616 goto mach64_invalid;
2617 size = simple_strtoul(p, NULL, 0);
2618 if (!(p = strsep(&video_str, ";")) || !*p)
2619 goto mach64_invalid;
2620 guiregbase = simple_strtoul(p, NULL, 0);
2622 phys_vmembase[m64_num] = vmembase;
2623 phys_size[m64_num] = size;
2624 phys_guiregbase[m64_num] = guiregbase;
2625 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2630 phys_vmembase[m64_num] = 0;
2633 #endif /* CONFIG_ATARI */
2636 * Blank the display.
2639 static int atyfb_blank(int blank, struct fb_info *info)
2641 struct atyfb_par *par = (struct atyfb_par *) info->par;
2644 if (par->lock_blank || par->asleep)
2647 #ifdef CONFIG_PMAC_BACKLIGHT
2648 if ((_machine == _MACH_Pmac) && blank)
2649 set_backlight_enable(0);
2650 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2651 if (par->lcd_table && blank &&
2652 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2653 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2655 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2659 gen_cntl = aty_ld_8(CRTC_GEN_CNTL, par);
2661 case FB_BLANK_UNBLANK:
2662 gen_cntl &= ~(0x4c);
2664 case FB_BLANK_NORMAL:
2667 case FB_BLANK_VSYNC_SUSPEND:
2670 case FB_BLANK_HSYNC_SUSPEND:
2673 case FB_BLANK_POWERDOWN:
2677 aty_st_8(CRTC_GEN_CNTL, gen_cntl, par);
2679 #ifdef CONFIG_PMAC_BACKLIGHT
2680 if ((_machine == _MACH_Pmac) && !blank)
2681 set_backlight_enable(1);
2682 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2683 if (par->lcd_table && !blank &&
2684 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2685 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2687 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2694 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2695 const struct atyfb_par *par)
2698 out_8(&par->aty_cmap_regs->windex, regno);
2699 out_8(&par->aty_cmap_regs->lut, red);
2700 out_8(&par->aty_cmap_regs->lut, green);
2701 out_8(&par->aty_cmap_regs->lut, blue);
2703 writeb(regno, &par->aty_cmap_regs->windex);
2704 writeb(red, &par->aty_cmap_regs->lut);
2705 writeb(green, &par->aty_cmap_regs->lut);
2706 writeb(blue, &par->aty_cmap_regs->lut);
2711 * Set a single color register. The values supplied are already
2712 * rounded down to the hardware's capabilities (according to the
2713 * entries in the var structure). Return != 0 for invalid regno.
2714 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2717 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2718 u_int transp, struct fb_info *info)
2720 struct atyfb_par *par = (struct atyfb_par *) info->par;
2722 u32 *pal = info->pseudo_palette;
2724 depth = info->var.bits_per_pixel;
2726 depth = (info->var.green.length == 5) ? 15 : 16;
2732 (depth == 16 && regno > 63) ||
2733 (depth == 15 && regno > 31))
2740 par->palette[regno].red = red;
2741 par->palette[regno].green = green;
2742 par->palette[regno].blue = blue;
2747 pal[regno] = (regno << 10) | (regno << 5) | regno;
2750 pal[regno] = (regno << 11) | (regno << 5) | regno;
2753 pal[regno] = (regno << 16) | (regno << 8) | regno;
2756 i = (regno << 8) | regno;
2757 pal[regno] = (i << 16) | i;
2762 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2763 if (M64_HAS(EXTRA_BRIGHT))
2764 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2765 aty_st_8(DAC_CNTL, i, par);
2766 aty_st_8(DAC_MASK, 0xff, par);
2768 if (M64_HAS(INTEGRATED)) {
2771 aty_st_pal(regno << 3, red,
2772 par->palette[regno<<1].green,
2774 red = par->palette[regno>>1].red;
2775 blue = par->palette[regno>>1].blue;
2777 } else if (depth == 15) {
2779 for(i = 0; i < 8; i++) {
2780 aty_st_pal(regno + i, red, green, blue, par);
2784 aty_st_pal(regno, red, green, blue, par);
2793 extern void (*prom_palette) (int);
2795 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2796 struct fb_info *info, unsigned long addr)
2798 extern int con_is_present(void);
2800 struct atyfb_par *par = info->par;
2801 struct pcidev_cookie *pcp;
2803 int node, len, i, j, ret;
2806 /* Do not attach when we have a serial console. */
2807 if (!con_is_present())
2811 * Map memory-mapped registers.
2813 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2814 info->fix.mmio_start = addr + 0x7ffc00UL;
2817 * Map in big-endian aperture.
2819 info->screen_base = (char *) (addr + 0x800000UL);
2820 info->fix.smem_start = addr + 0x800000UL;
2823 * Figure mmap addresses from PCI config space.
2824 * Split Framebuffer in big- and little-endian halfs.
2826 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2830 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2831 if (!par->mmap_map) {
2832 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2835 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2837 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2838 struct resource *rp = &pdev->resource[i];
2839 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2845 io = (rp->flags & IORESOURCE_IO);
2847 size = rp->end - base + 1;
2849 pci_read_config_dword(pdev, breg, &pbase);
2855 * Map the framebuffer a second time, this time without
2856 * the braindead _PAGE_IE setting. This is used by the
2857 * fixed Xserver, but we need to maintain the old mapping
2858 * to stay compatible with older ones...
2861 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2862 par->mmap_map[j].poff = base & PAGE_MASK;
2863 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2864 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2865 par->mmap_map[j].prot_flag = _PAGE_E;
2870 * Here comes the old framebuffer mapping with _PAGE_IE
2871 * set for the big endian half of the framebuffer...
2874 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2875 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2876 par->mmap_map[j].size = 0x800000;
2877 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2878 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2883 par->mmap_map[j].voff = pbase & PAGE_MASK;
2884 par->mmap_map[j].poff = base & PAGE_MASK;
2885 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2886 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2887 par->mmap_map[j].prot_flag = _PAGE_E;
2891 if((ret = correct_chipset(par)))
2894 if (IS_XL(pdev->device)) {
2896 * Fix PROMs idea of MEM_CNTL settings...
2898 mem = aty_ld_le32(MEM_CNTL, par);
2899 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2900 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2901 switch (mem & 0x0f) {
2903 mem = (mem & ~(0x0f)) | 2;
2906 mem = (mem & ~(0x0f)) | 3;
2909 mem = (mem & ~(0x0f)) | 4;
2912 mem = (mem & ~(0x0f)) | 5;
2917 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2918 mem &= ~(0x00700000);
2920 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2921 aty_st_le32(MEM_CNTL, mem, par);
2925 * If this is the console device, we will set default video
2926 * settings to what the PROM left us with.
2928 node = prom_getchild(prom_root_node);
2929 node = prom_searchsiblings(node, "aliases");
2931 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2934 node = prom_finddevice(prop);
2939 pcp = pdev->sysdata;
2940 if (node == pcp->prom_node) {
2941 struct fb_var_screeninfo *var = &default_var;
2942 unsigned int N, P, Q, M, T, R;
2943 u32 v_total, h_total;
2948 crtc.vxres = prom_getintdefault(node, "width", 1024);
2949 crtc.vyres = prom_getintdefault(node, "height", 768);
2950 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2951 var->xoffset = var->yoffset = 0;
2952 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2953 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2954 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2955 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2956 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2957 aty_crtc_to_var(&crtc, var);
2959 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2960 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2963 * Read the PLL to figure actual Refresh Rate.
2965 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2966 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2967 for (i = 0; i < 16; i++)
2968 pll_regs[i] = aty_ld_pll_ct(i, par);
2971 * PLL Reference Divider M:
2976 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
2978 N = pll_regs[7 + (clock_cntl & 3)];
2981 * PLL Post Divider P (Dependant on CLOCK_CNTL):
2983 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
2997 * where R is XTALIN (= 14318 or 29498 kHz).
2999 if (IS_XL(pdev->device))
3006 default_var.pixclock = 1000000000 / T;
3012 #else /* __sparc__ */
3015 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3016 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3018 u32 driv_inf_tab, sig;
3021 /* To support an LCD panel, we should know it's dimensions and
3022 * it's desired pixel clock.
3023 * There are two ways to do it:
3024 * - Check the startup video mode and calculate the panel
3025 * size from it. This is unreliable.
3026 * - Read it from the driver information table in the video BIOS.
3028 /* Address of driver information table is at offset 0x78. */
3029 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3031 /* Check for the driver information table signature. */
3032 sig = (*(u32 *)driv_inf_tab);
3033 if ((sig == 0x54504c24) || /* Rage LT pro */
3034 (sig == 0x544d5224) || /* Rage mobility */
3035 (sig == 0x54435824) || /* Rage XC */
3036 (sig == 0x544c5824)) { /* Rage XL */
3037 PRINTKI("BIOS contains driver information table.\n");
3038 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3041 par->lcd_table = bios_base + lcd_ofs;
3045 if (par->lcd_table != 0) {
3048 char refresh_rates_buf[100];
3049 int id, tech, f, i, m, default_refresh_rate;
3054 u16 width, height, panel_type, refresh_rates;
3057 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3058 /* The most important information is the panel size at
3059 * offset 25 and 27, but there's some other nice information
3060 * which we print to the screen.
3062 id = *(u8 *)par->lcd_table;
3063 strncpy(model,(char *)par->lcd_table+1,24);
3066 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3067 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3068 panel_type = *(u16 *)(par->lcd_table+29);
3070 txtcolour = "colour";
3072 txtcolour = "monochrome";
3074 txtdual = "dual (split) ";
3077 tech = (panel_type>>2) & 63;
3080 txtmonitor = "passive matrix";
3083 txtmonitor = "active matrix";
3086 txtmonitor = "active addressed STN";
3092 txtmonitor = "plasma";
3095 txtmonitor = "unknown";
3097 format = *(u32 *)(par->lcd_table+57);
3098 if (tech == 0 || tech == 2) {
3099 switch (format & 7) {
3101 txtformat = "12 bit interface";
3104 txtformat = "16 bit interface";
3107 txtformat = "24 bit interface";
3110 txtformat = "unkown format";
3113 switch (format & 7) {
3115 txtformat = "8 colours";
3118 txtformat = "512 colours";
3121 txtformat = "4096 colours";
3124 txtformat = "262144 colours (LT mode)";
3127 txtformat = "16777216 colours";
3130 txtformat = "262144 colours (FDPI-2 mode)";
3133 txtformat = "unkown format";
3136 PRINTKI("%s%s %s monitor detected: %s\n",
3137 txtdual ,txtcolour, txtmonitor, model);
3138 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3139 id, width, height, txtformat);
3140 refresh_rates_buf[0] = 0;
3141 refresh_rates = *(u16 *)(par->lcd_table+62);
3144 for (i=0;i<16;i++) {
3145 if (refresh_rates & m) {
3147 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3150 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3152 strcat(refresh_rates_buf,strbuf);
3156 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3157 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3158 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3159 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3160 /* We now need to determine the crtc parameters for the
3161 * LCD monitor. This is tricky, because they are not stored
3162 * individually in the BIOS. Instead, the BIOS contains a
3163 * table of display modes that work for this monitor.
3165 * The idea is that we search for a mode of the same dimensions
3166 * as the dimensions of the LCD monitor. Say our LCD monitor
3167 * is 800x600 pixels, we search for a 800x600 monitor.
3168 * The CRTC parameters we find here are the ones that we need
3169 * to use to simulate other resolutions on the LCD screen.
3171 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3172 while (*lcdmodeptr != 0) {
3174 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3175 modeptr = bios_base + *lcdmodeptr;
3177 mwidth = *((u16 *)(modeptr+0));
3178 mheight = *((u16 *)(modeptr+2));
3180 if (mwidth == width && mheight == height) {
3181 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3182 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3183 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3184 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3185 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3186 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3188 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3189 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3190 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3191 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3193 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3194 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3195 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3196 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3202 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3203 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3204 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3205 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3211 if (*lcdmodeptr == 0) {
3212 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3213 /* To do: Switch to CRT if possible. */
3215 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3216 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3218 par->lcd_hdisp + par->lcd_right_margin,
3219 par->lcd_hdisp + par->lcd_right_margin
3220 + par->lcd_hsync_dly + par->lcd_hsync_len,
3223 par->lcd_vdisp + par->lcd_lower_margin,
3224 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3226 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3228 par->lcd_hblank_len - (par->lcd_right_margin +
3229 par->lcd_hsync_dly + par->lcd_hsync_len),
3231 par->lcd_right_margin,
3233 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3235 par->lcd_lower_margin,
3236 par->lcd_vsync_len);
3240 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3242 static int __devinit init_from_bios(struct atyfb_par *par)
3244 u32 bios_base, rom_addr;
3247 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3248 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3250 /* The BIOS starts with 0xaa55. */
3251 if (*((u16 *)bios_base) == 0xaa55) {
3254 u16 rom_table_offset, freq_table_offset;
3255 PLL_BLOCK_MACH64 pll_block;
3257 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3259 /* check for frequncy table */
3260 bios_ptr = (u8*)bios_base;
3261 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3262 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3263 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3265 PRINTKI("BIOS frequency table:\n");
3266 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3267 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3268 pll_block.ref_freq, pll_block.ref_divider);
3269 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3270 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3271 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3273 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3274 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3275 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3276 par->pll_limits.ref_div = pll_block.ref_divider;
3277 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3278 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3279 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3280 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3281 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3282 aty_init_lcd(par, bios_base);
3286 PRINTKE("no BIOS frequency table found, use parameters\n");
3289 iounmap((void* __iomem )bios_base);
3293 #endif /* __i386__ */
3295 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3297 struct atyfb_par *par = info->par;
3299 unsigned long raddr;
3300 struct resource *rrp;
3303 raddr = addr + 0x7ff000UL;
3304 rrp = &pdev->resource[2];
3305 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3306 par->aux_start = rrp->start;
3307 par->aux_size = rrp->end - rrp->start + 1;
3309 PRINTKI("using auxiliary register aperture\n");
3312 info->fix.mmio_start = raddr;
3313 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3314 if (par->ati_regbase == 0)
3317 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3318 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3321 * Enable memory-space accesses using config-space
3324 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3325 if (!(tmp & PCI_COMMAND_MEMORY)) {
3326 tmp |= PCI_COMMAND_MEMORY;
3327 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3330 /* Use the big-endian aperture */
3334 /* Map in frame buffer */
3335 info->fix.smem_start = addr;
3336 info->screen_base = ioremap(addr, 0x800000);
3337 if (info->screen_base == NULL) {
3339 goto atyfb_setup_generic_fail;
3342 if((ret = correct_chipset(par)))
3343 goto atyfb_setup_generic_fail;
3345 if((ret = init_from_bios(par)))
3346 goto atyfb_setup_generic_fail;
3348 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3349 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3351 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3353 /* according to ATI, we should use clock 3 for acelerated mode */
3354 par->clk_wr_offset = 3;
3358 atyfb_setup_generic_fail:
3359 iounmap(par->ati_regbase);
3360 par->ati_regbase = NULL;
3364 #endif /* !__sparc__ */
3366 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3368 unsigned long addr, res_start, res_size;
3369 struct fb_info *info;
3370 struct resource *rp;
3371 struct atyfb_par *par;
3372 int i, rc = -ENOMEM;
3374 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3375 if (pdev->device == aty_chips[i].pci_id)
3381 /* Enable device in PCI config */
3382 if (pci_enable_device(pdev)) {
3383 PRINTKE("Cannot enable PCI device\n");
3387 /* Find which resource to use */
3388 rp = &pdev->resource[0];
3389 if (rp->flags & IORESOURCE_IO)
3390 rp = &pdev->resource[1];
3396 res_start = rp->start;
3397 res_size = rp->end - rp->start + 1;
3398 if (!request_mem_region (res_start, res_size, "atyfb"))
3401 /* Allocate framebuffer */
3402 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3404 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3408 info->fix = atyfb_fix;
3409 info->device = &pdev->dev;
3410 par->pci_id = aty_chips[i].pci_id;
3411 par->res_start = res_start;
3412 par->res_size = res_size;
3413 par->irq = pdev->irq;
3415 /* Setup "info" structure */
3417 rc = atyfb_setup_sparc(pdev, info, addr);
3419 rc = atyfb_setup_generic(pdev, info, addr);
3422 goto err_release_mem;
3424 pci_set_drvdata(pdev, info);
3426 /* Init chip & register framebuffer */
3427 if (aty_init(info, "PCI"))
3428 goto err_release_io;
3432 prom_palette = atyfb_palette;
3435 * Add /dev/fb mmap values.
3437 par->mmap_map[0].voff = 0x8000000000000000UL;
3438 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3439 par->mmap_map[0].size = info->fix.smem_len;
3440 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3441 par->mmap_map[0].prot_flag = _PAGE_E;
3442 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3443 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3444 par->mmap_map[1].size = PAGE_SIZE;
3445 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3446 par->mmap_map[1].prot_flag = _PAGE_E;
3447 #endif /* __sparc__ */
3453 kfree(par->mmap_map);
3455 if (par->ati_regbase)
3456 iounmap(par->ati_regbase);
3457 if (info->screen_base)
3458 iounmap(info->screen_base);
3462 release_mem_region(par->aux_start, par->aux_size);
3464 release_mem_region(par->res_start, par->res_size);
3465 framebuffer_release(info);
3470 #endif /* CONFIG_PCI */
3474 static int __devinit atyfb_atari_probe(void)
3476 struct aty_par *par;
3477 struct fb_info *info;
3481 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3482 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3483 !phys_guiregbase[m64_num]) {
3484 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3488 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3490 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3495 info->fix = atyfb_fix;
3497 par->irq = (unsigned int) -1; /* something invalid */
3500 * Map the video memory (physical address given) to somewhere in the
3501 * kernel address space.
3503 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3504 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3505 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3507 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3509 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3510 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3512 switch (clock_r & 0x003F) {
3514 par->clk_wr_offset = 3; /* */
3517 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3520 par->clk_wr_offset = 1; /* */
3523 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3527 if (aty_init(info, "ISA bus")) {
3528 framebuffer_release(info);
3529 /* This is insufficient! kernel_map has added two large chunks!! */
3535 #endif /* CONFIG_ATARI */
3537 static void __devexit atyfb_remove(struct fb_info *info)
3539 struct atyfb_par *par = (struct atyfb_par *) info->par;
3541 /* restore video mode */
3542 aty_set_crtc(par, &saved_crtc);
3543 par->pll_ops->set_pll(info, &saved_pll);
3545 unregister_framebuffer(info);
3548 if (par->mtrr_reg >= 0) {
3549 mtrr_del(par->mtrr_reg, 0, 0);
3552 if (par->mtrr_aper >= 0) {
3553 mtrr_del(par->mtrr_aper, 0, 0);
3554 par->mtrr_aper = -1;
3558 if (par->ati_regbase)
3559 iounmap(par->ati_regbase);
3560 if (info->screen_base)
3561 iounmap(info->screen_base);
3563 if (info->sprite.addr)
3564 iounmap(info->sprite.addr);
3568 kfree(par->mmap_map);
3571 release_mem_region(par->aux_start, par->aux_size);
3574 release_mem_region(par->res_start, par->res_size);
3576 framebuffer_release(info);
3581 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3583 struct fb_info *info = pci_get_drvdata(pdev);
3589 * This driver uses its own matching table. That will be more difficult
3590 * to fix, so for now, we just match against any ATI ID and let the
3591 * probe() function find out what's up. That also mean we don't have
3592 * a module ID table though.
3594 static struct pci_device_id atyfb_pci_tbl[] = {
3595 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3596 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3600 static struct pci_driver atyfb_driver = {
3602 .id_table = atyfb_pci_tbl,
3603 .probe = atyfb_pci_probe,
3604 .remove = __devexit_p(atyfb_pci_remove),
3606 .suspend = atyfb_pci_suspend,
3607 .resume = atyfb_pci_resume,
3608 #endif /* CONFIG_PM */
3611 #endif /* CONFIG_PCI */
3614 static int __init atyfb_setup(char *options)
3618 if (!options || !*options)
3621 while ((this_opt = strsep(&options, ",")) != NULL) {
3622 if (!strncmp(this_opt, "noaccel", 7)) {
3625 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3628 } else if (!strncmp(this_opt, "vram:", 5))
3629 vram = simple_strtoul(this_opt + 5, NULL, 0);
3630 else if (!strncmp(this_opt, "pll:", 4))
3631 pll = simple_strtoul(this_opt + 4, NULL, 0);
3632 else if (!strncmp(this_opt, "mclk:", 5))
3633 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3634 else if (!strncmp(this_opt, "xclk:", 5))
3635 xclk = simple_strtoul(this_opt+5, NULL, 0);
3636 else if (!strncmp(this_opt, "comp_sync:", 10))
3637 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3639 else if (!strncmp(this_opt, "vmode:", 6)) {
3640 unsigned int vmode =
3641 simple_strtoul(this_opt + 6, NULL, 0);
3642 if (vmode > 0 && vmode <= VMODE_MAX)
3643 default_vmode = vmode;
3644 } else if (!strncmp(this_opt, "cmode:", 6)) {
3645 unsigned int cmode =
3646 simple_strtoul(this_opt + 6, NULL, 0);
3650 default_cmode = CMODE_8;
3654 default_cmode = CMODE_16;
3658 default_cmode = CMODE_32;
3665 * Why do we need this silly Mach64 argument?
3666 * We are already here because of mach64= so its redundant.
3668 else if (MACH_IS_ATARI
3669 && (!strncmp(this_opt, "Mach64:", 7))) {
3670 static unsigned char m64_num;
3671 static char mach64_str[80];
3672 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3673 if (!store_video_par(mach64_str, m64_num)) {
3675 mach64_count = m64_num;
3686 static int __init atyfb_init(void)
3689 char *option = NULL;
3691 if (fb_get_options("atyfb", &option))
3693 atyfb_setup(option);
3696 pci_register_driver(&atyfb_driver);
3698 atyfb_atari_probe();
3703 static void __exit atyfb_exit(void)
3705 pci_unregister_driver(&atyfb_driver);
3708 module_init(atyfb_init);
3709 module_exit(atyfb_exit);
3711 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3712 MODULE_LICENSE("GPL");
3713 module_param(noaccel, bool, 0);
3714 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3715 module_param(vram, int, 0);
3716 MODULE_PARM_DESC(vram, "int: override size of video ram");
3717 module_param(pll, int, 0);
3718 MODULE_PARM_DESC(pll, "int: override video clock");
3719 module_param(mclk, int, 0);
3720 MODULE_PARM_DESC(mclk, "int: override memory clock");
3721 module_param(xclk, int, 0);
3722 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3723 module_param(comp_sync, int, 0);
3724 MODULE_PARM_DESC(comp_sync,
3725 "Set composite sync signal to low (0) or high (1)");
3726 module_param(mode, charp, 0);
3727 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3729 module_param(nomtrr, bool, 0);
3730 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob