SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/video/aty/atyfb_base.c

   1 /*
   2  *  ATI Frame Buffer Device Driver Core
   3  *
   4  *      Copyright (C) 2004  Alex Kern <alex.kern@gmx.de>
   5  *      Copyright (C) 1997-2001  Geert Uytterhoeven
   6  *      Copyright (C) 1998  Bernd Harries
   7  *      Copyright (C) 1998  Eddie C. Dost  (ecd@skynet.be)
   8  *
   9  *  This driver supports the following ATI graphics chips:
  10  *    - ATI Mach64
  11  *
  12  *  To do: add support for
  13  *    - ATI Rage128 (from aty128fb.c)
  14  *    - ATI Radeon (from radeonfb.c)
  15  *
  16  *  This driver is partly based on the PowerMac console driver:
  17  *
  18  *      Copyright (C) 1996 Paul Mackerras
  19  *
  20  *  and on the PowerMac ATI/mach64 display driver:
  21  *
  22  *      Copyright (C) 1997 Michael AK Tesch
  23  *
  24  *            with work by Jon Howell
  25  *                         Harry AC Eaton
  26  *                         Anthony Tong <atong@uiuc.edu>
  27  *
  28  *  Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
  29  *  Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
  30  *
  31  *  This file is subject to the terms and conditions of the GNU General Public
  32  *  License. See the file COPYING in the main directory of this archive for
  33  *  more details.
  34  *
  35  *  Many thanks to Nitya from ATI devrel for support and patience !
  36  */
  37
  38 /******************************************************************************
  39
  40   TODO:
  41
  42     - cursor support on all cards and all ramdacs.
  43     - cursor parameters controlable via ioctl()s.
  44     - guess PLL and MCLK based on the original PLL register values initialized
  45       by Open Firmware (if they are initialized). BIOS is done
  46
  47     (Anyone with Mac to help with this?)
  48
  49 ******************************************************************************/
  50
  51
  52 #include <linux/module.h>
  53 #include <linux/moduleparam.h>
  54 #include <linux/kernel.h>
  55 #include <linux/errno.h>
  56 #include <linux/string.h>
  57 #include <linux/mm.h>
  58 #include <linux/slab.h>
  59 #include <linux/vmalloc.h>
  60 #include <linux/delay.h>
  61 #include <linux/console.h>
  62 #include <linux/fb.h>
  63 #include <linux/init.h>
  64 #include <linux/pci.h>
  65 #include <linux/interrupt.h>
  66 #include <linux/spinlock.h>
  67 #include <linux/wait.h>
  68 #include <linux/backlight.h>
  69
  70 #include <asm/io.h>
  71 #include <asm/uaccess.h>
  72
  73 #include <video/mach64.h>
  74 #include "atyfb.h"
  75 #include "ati_ids.h"
  76
  77 #ifdef __powerpc__
  78 #include <asm/machdep.h>
  79 #include <asm/prom.h>
  80 #include "../macmodes.h"
  81 #endif
  82 #ifdef __sparc__
  83 #include <asm/pbm.h>
  84 #include <asm/fbio.h>
  85 #endif
  86
  87 #ifdef CONFIG_ADB_PMU
  88 #include <linux/adb.h>
  89 #include <linux/pmu.h>
  90 #endif
  91 #ifdef CONFIG_BOOTX_TEXT
  92 #include <asm/btext.h>
  93 #endif
  94 #ifdef CONFIG_PMAC_BACKLIGHT
  95 #include <asm/backlight.h>
  96 #endif
  97 #ifdef CONFIG_MTRR
  98 #include <asm/mtrr.h>
  99 #endif
 100
 101 /*
 102  * Debug flags.
 103  */
 104 #undef DEBUG
 105 /*#define DEBUG*/
 106
 107 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
 108 /*  - must be large enough to catch all GUI-Regs   */
 109 /*  - must be aligned to a PAGE boundary           */
 110 #define GUI_RESERVE     (1 * PAGE_SIZE)
 111
 112 /* FIXME: remove the FAIL definition */
 113 #define FAIL(msg) do { \
 114         if (!(var->activate & FB_ACTIVATE_TEST)) \
 115                 printk(KERN_CRIT "atyfb: " msg "\n"); \
 116         return -EINVAL; \
 117 } while (0)
 118 #define FAIL_MAX(msg, x, _max_) do { \
 119         if (x > _max_) { \
 120                 if (!(var->activate & FB_ACTIVATE_TEST)) \
 121                         printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
 122                 return -EINVAL; \
 123         } \
 124 } while (0)
 125 #ifdef DEBUG
 126 #define DPRINTK(fmt, args...)   printk(KERN_DEBUG "atyfb: " fmt, ## args)
 127 #else
 128 #define DPRINTK(fmt, args...)
 129 #endif
 130
 131 #define PRINTKI(fmt, args...)   printk(KERN_INFO "atyfb: " fmt, ## args)
 132 #define PRINTKE(fmt, args...)    printk(KERN_ERR "atyfb: " fmt, ## args)
 133
 134 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
 135 static const u32 lt_lcd_regs[] = {
 136         CONFIG_PANEL_LG,
 137         LCD_GEN_CNTL_LG,
 138         DSTN_CONTROL_LG,
 139         HFB_PITCH_ADDR_LG,
 140         HORZ_STRETCHING_LG,
 141         VERT_STRETCHING_LG,
 142         0, /* EXT_VERT_STRETCH */
 143         LT_GIO_LG,
 144         POWER_MANAGEMENT_LG
 145 };
 146
 147 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
 148 {
 149         if (M64_HAS(LT_LCD_REGS)) {
 150                 aty_st_le32(lt_lcd_regs[index], val, par);
 151         } else {
 152                 unsigned long temp;
 153
 154                 /* write addr byte */
 155                 temp = aty_ld_le32(LCD_INDEX, par);
 156                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 157                 /* write the register value */
 158                 aty_st_le32(LCD_DATA, val, par);
 159         }
 160 }
 161
 162 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
 163 {
 164         if (M64_HAS(LT_LCD_REGS)) {
 165                 return aty_ld_le32(lt_lcd_regs[index], par);
 166         } else {
 167                 unsigned long temp;
 168
 169                 /* write addr byte */
 170                 temp = aty_ld_le32(LCD_INDEX, par);
 171                 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
 172                 /* read the register value */
 173                 return aty_ld_le32(LCD_DATA, par);
 174         }
 175 }
 176 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
 177
 178 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 179 /*
 180  * ATIReduceRatio --
 181  *
 182  * Reduce a fraction by factoring out the largest common divider of the
 183  * fraction's numerator and denominator.
 184  */
 185 static void ATIReduceRatio(int *Numerator, int *Denominator)
 186 {
 187     int Multiplier, Divider, Remainder;
 188
 189     Multiplier = *Numerator;
 190     Divider = *Denominator;
 191
 192     while ((Remainder = Multiplier % Divider))
 193     {
 194         Multiplier = Divider;
 195         Divider = Remainder;
 196     }
 197
 198     *Numerator /= Divider;
 199     *Denominator /= Divider;
 200 }
 201 #endif
 202     /*
 203      *  The Hardware parameters for each card
 204      */
 205
 206 struct aty_cmap_regs {
 207         u8 windex;
 208         u8 lut;
 209         u8 mask;
 210         u8 rindex;
 211         u8 cntl;
 212 };
 213
 214 struct pci_mmap_map {
 215         unsigned long voff;
 216         unsigned long poff;
 217         unsigned long size;
 218         unsigned long prot_flag;
 219         unsigned long prot_mask;
 220 };
 221
 222 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
 223         .id             = "ATY Mach64",
 224         .type           = FB_TYPE_PACKED_PIXELS,
 225         .visual         = FB_VISUAL_PSEUDOCOLOR,
 226         .xpanstep       = 8,
 227         .ypanstep       = 1,
 228 };
 229
 230     /*
 231      *  Frame buffer device API
 232      */
 233
 234 static int atyfb_open(struct fb_info *info, int user);
 235 static int atyfb_release(struct fb_info *info, int user);
 236 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
 237 static int atyfb_set_par(struct fb_info *info);
 238 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
 239         u_int transp, struct fb_info *info);
 240 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
 241 static int atyfb_blank(int blank, struct fb_info *info);
 242 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg);
 243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
 244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
 245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
 246 #ifdef __sparc__
 247 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma);
 248 #endif
 249 static int atyfb_sync(struct fb_info *info);
 250
 251     /*
 252      *  Internal routines
 253      */
 254
 255 static int aty_init(struct fb_info *info, const char *name);
 256 #ifdef CONFIG_ATARI
 257 static int store_video_par(char *videopar, unsigned char m64_num);
 258 #endif
 259
 260 static struct crtc saved_crtc;
 261 static union aty_pll saved_pll;
 262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
 263
 264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
 265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
 266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
 267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
 268 #ifdef CONFIG_PPC
 269 static int read_aty_sense(const struct atyfb_par *par);
 270 #endif
 271
 272
 273     /*
 274      *  Interface used by the world
 275      */
 276
 277 static struct fb_var_screeninfo default_var = {
 278         /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
 279         640, 480, 640, 480, 0, 0, 8, 0,
 280         {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
 281         0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
 282         0, FB_VMODE_NONINTERLACED
 283 };
 284
 285 static struct fb_videomode defmode = {
 286         /* 640x480 @ 60 Hz, 31.5 kHz hsync */
 287         NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
 288         0, FB_VMODE_NONINTERLACED
 289 };
 290
 291 static struct fb_ops atyfb_ops = {
 292         .owner          = THIS_MODULE,
 293         .fb_open        = atyfb_open,
 294         .fb_release     = atyfb_release,
 295         .fb_check_var   = atyfb_check_var,
 296         .fb_set_par     = atyfb_set_par,
 297         .fb_setcolreg   = atyfb_setcolreg,
 298         .fb_pan_display = atyfb_pan_display,
 299         .fb_blank       = atyfb_blank,
 300         .fb_ioctl       = atyfb_ioctl,
 301         .fb_fillrect    = atyfb_fillrect,
 302         .fb_copyarea    = atyfb_copyarea,
 303         .fb_imageblit   = atyfb_imageblit,
 304 #ifdef __sparc__
 305         .fb_mmap        = atyfb_mmap,
 306 #endif
 307         .fb_sync        = atyfb_sync,
 308 };
 309
 310 static int noaccel;
 311 #ifdef CONFIG_MTRR
 312 static int nomtrr;
 313 #endif
 314 static int vram;
 315 static int pll;
 316 static int mclk;
 317 static int xclk;
 318 static int comp_sync __devinitdata = -1;
 319 static char *mode;
 320
 321 #ifdef CONFIG_PPC
 322 static int default_vmode __devinitdata = VMODE_CHOOSE;
 323 static int default_cmode __devinitdata = CMODE_CHOOSE;
 324
 325 module_param_named(vmode, default_vmode, int, 0);
 326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
 327 module_param_named(cmode, default_cmode, int, 0);
 328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
 329 #endif
 330
 331 #ifdef CONFIG_ATARI
 332 static unsigned int mach64_count __devinitdata = 0;
 333 static unsigned long phys_vmembase[FB_MAX] __devinitdata = { 0, };
 334 static unsigned long phys_size[FB_MAX] __devinitdata = { 0, };
 335 static unsigned long phys_guiregbase[FB_MAX] __devinitdata = { 0, };
 336 #endif
 337
 338 /* top -> down is an evolution of mach64 chipset, any corrections? */
 339 #define ATI_CHIP_88800GX   (M64F_GX)
 340 #define ATI_CHIP_88800CX   (M64F_GX)
 341
 342 #define ATI_CHIP_264CT     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 343 #define ATI_CHIP_264ET     (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
 344
 345 #define ATI_CHIP_264VT     (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
 346 #define ATI_CHIP_264GT     (M64F_GT | M64F_INTEGRATED               | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
 347
 348 #define ATI_CHIP_264VTB    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
 349 #define ATI_CHIP_264VT3    (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
 350 #define ATI_CHIP_264VT4    (M64F_VT | M64F_INTEGRATED               | M64F_GTB_DSP)
 351
 352 /* FIXME what is this chip? */
 353 #define ATI_CHIP_264LT     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP)
 354
 355 /* make sets shorter */
 356 #define ATI_MODERN_SET     (M64F_GT | M64F_INTEGRATED               | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
 357
 358 #define ATI_CHIP_264GTB    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 359 /*#define ATI_CHIP_264GTDVD  ?*/
 360 #define ATI_CHIP_264LTG    (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
 361
 362 #define ATI_CHIP_264GT2C   (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
 363 #define ATI_CHIP_264GTPRO  (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 364 #define ATI_CHIP_264LTPRO  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
 365
 366 #define ATI_CHIP_264XL     (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
 367 #define ATI_CHIP_MOBILITY  (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
 368
 369 static struct {
 370         u16 pci_id;
 371         const char *name;
 372         int pll, mclk, xclk, ecp_max;
 373         u32 features;
 374 } aty_chips[] __devinitdata = {
 375 #ifdef CONFIG_FB_ATY_GX
 376         /* Mach64 GX */
 377         { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
 378         { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
 379 #endif /* CONFIG_FB_ATY_GX */
 380
 381 #ifdef CONFIG_FB_ATY_CT
 382         { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
 383         { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
 384
 385         /* FIXME what is this chip? */
 386         { PCI_CHIP_MACH64LT, "ATI264LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
 387
 388         { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
 389         { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
 390
 391         { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
 392         { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
 393
 394         { PCI_CHIP_MACH64LG, "3D RAGE LT (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
 395
 396         { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
 397
 398         { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 399         { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 400         { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 401         { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
 402
 403         { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 404         { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 405         { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
 406         { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 407         { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
 408
 409         { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
 410         { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 411         { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
 412         { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 413         { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
 414
 415         { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 416         { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
 417         { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 418         { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
 419         { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
 420         { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
 421
 422         { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 423         { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 424         { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 425         { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
 426 #endif /* CONFIG_FB_ATY_CT */
 427 };
 428
 429 /* can not fail */
 430 static int __devinit correct_chipset(struct atyfb_par *par)
 431 {
 432         u8 rev;
 433         u16 type;
 434         u32 chip_id;
 435         const char *name;
 436         int i;
 437
 438         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
 439                 if (par->pci_id == aty_chips[i].pci_id)
 440                         break;
 441
 442         name = aty_chips[i].name;
 443         par->pll_limits.pll_max = aty_chips[i].pll;
 444         par->pll_limits.mclk = aty_chips[i].mclk;
 445         par->pll_limits.xclk = aty_chips[i].xclk;
 446         par->pll_limits.ecp_max = aty_chips[i].ecp_max;
 447         par->features = aty_chips[i].features;
 448
 449         chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
 450         type = chip_id & CFG_CHIP_TYPE;
 451         rev = (chip_id & CFG_CHIP_REV) >> 24;
 452
 453         switch(par->pci_id) {
 454 #ifdef CONFIG_FB_ATY_GX
 455         case PCI_CHIP_MACH64GX:
 456                 if(type != 0x00d7)
 457                         return -ENODEV;
 458                 break;
 459         case PCI_CHIP_MACH64CX:
 460                 if(type != 0x0057)
 461                         return -ENODEV;
 462                 break;
 463 #endif
 464 #ifdef CONFIG_FB_ATY_CT
 465         case PCI_CHIP_MACH64VT:
 466                 switch (rev & 0x07) {
 467                 case 0x00:
 468                         switch (rev & 0xc0) {
 469                         case 0x00:
 470                                 name = "ATI264VT (A3) (Mach64 VT)";
 471                                 par->pll_limits.pll_max = 170;
 472                                 par->pll_limits.mclk = 67;
 473                                 par->pll_limits.xclk = 67;
 474                                 par->pll_limits.ecp_max = 80;
 475                                 par->features = ATI_CHIP_264VT;
 476                                 break;
 477                         case 0x40:
 478                                 name = "ATI264VT2 (A4) (Mach64 VT)";
 479                                 par->pll_limits.pll_max = 200;
 480                                 par->pll_limits.mclk = 67;
 481                                 par->pll_limits.xclk = 67;
 482                                 par->pll_limits.ecp_max = 80;
 483                                 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
 484                                 break;
 485                         }
 486                         break;
 487                 case 0x01:
 488                         name = "ATI264VT3 (B1) (Mach64 VT)";
 489                         par->pll_limits.pll_max = 200;
 490                         par->pll_limits.mclk = 67;
 491                         par->pll_limits.xclk = 67;
 492                         par->pll_limits.ecp_max = 80;
 493                         par->features = ATI_CHIP_264VTB;
 494                         break;
 495                 case 0x02:
 496                         name = "ATI264VT3 (B2) (Mach64 VT)";
 497                         par->pll_limits.pll_max = 200;
 498                         par->pll_limits.mclk = 67;
 499                         par->pll_limits.xclk = 67;
 500                         par->pll_limits.ecp_max = 80;
 501                         par->features = ATI_CHIP_264VT3;
 502                         break;
 503                 }
 504                 break;
 505         case PCI_CHIP_MACH64GT:
 506                 switch (rev & 0x07) {
 507                 case 0x01:
 508                         name = "3D RAGE II (Mach64 GT)";
 509                         par->pll_limits.pll_max = 170;
 510                         par->pll_limits.mclk = 67;
 511                         par->pll_limits.xclk = 67;
 512                         par->pll_limits.ecp_max = 80;
 513                         par->features = ATI_CHIP_264GTB;
 514                         break;
 515                 case 0x02:
 516                         name = "3D RAGE II+ (Mach64 GT)";
 517                         par->pll_limits.pll_max = 200;
 518                         par->pll_limits.mclk = 67;
 519                         par->pll_limits.xclk = 67;
 520                         par->pll_limits.ecp_max = 100;
 521                         par->features = ATI_CHIP_264GTB;
 522                         break;
 523                 }
 524                 break;
 525 #endif
 526         }
 527
 528         PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
 529         return 0;
 530 }
 531
 532 static char ram_dram[] __devinitdata = "DRAM";
 533 static char ram_resv[] __devinitdata = "RESV";
 534 #ifdef CONFIG_FB_ATY_GX
 535 static char ram_vram[] __devinitdata = "VRAM";
 536 #endif /* CONFIG_FB_ATY_GX */
 537 #ifdef CONFIG_FB_ATY_CT
 538 static char ram_edo[] __devinitdata = "EDO";
 539 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
 540 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
 541 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
 542 static char ram_off[] __devinitdata = "OFF";
 543 #endif /* CONFIG_FB_ATY_CT */
 544
 545
 546 static u32 pseudo_palette[17];
 547
 548 #ifdef CONFIG_FB_ATY_GX
 549 static char *aty_gx_ram[8] __devinitdata = {
 550         ram_dram, ram_vram, ram_vram, ram_dram,
 551         ram_dram, ram_vram, ram_vram, ram_resv
 552 };
 553 #endif /* CONFIG_FB_ATY_GX */
 554
 555 #ifdef CONFIG_FB_ATY_CT
 556 static char *aty_ct_ram[8] __devinitdata = {
 557         ram_off, ram_dram, ram_edo, ram_edo,
 558         ram_sdram, ram_sgram, ram_sdram32, ram_resv
 559 };
 560 #endif /* CONFIG_FB_ATY_CT */
 561
 562 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
 563 {
 564         u32 pixclock = var->pixclock;
 565 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 566         u32 lcd_on_off;
 567         par->pll.ct.xres = 0;
 568         if (par->lcd_table != 0) {
 569                 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
 570                 if(lcd_on_off & LCD_ON) {
 571                         par->pll.ct.xres = var->xres;
 572                         pixclock = par->lcd_pixclock;
 573                 }
 574         }
 575 #endif
 576         return pixclock;
 577 }
 578
 579 #if defined(CONFIG_PPC)
 580
 581 /*
 582  *  Apple monitor sense
 583  */
 584
 585 static int __devinit read_aty_sense(const struct atyfb_par *par)
 586 {
 587         int sense, i;
 588
 589         aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
 590         __delay(200);
 591         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 592         __delay(2000);
 593         i = aty_ld_le32(GP_IO, par); /* get primary sense value */
 594         sense = ((i & 0x3000) >> 3) | (i & 0x100);
 595
 596         /* drive each sense line low in turn and collect the other 2 */
 597         aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
 598         __delay(2000);
 599         i = aty_ld_le32(GP_IO, par);
 600         sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
 601         aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
 602         __delay(200);
 603
 604         aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
 605         __delay(2000);
 606         i = aty_ld_le32(GP_IO, par);
 607         sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
 608         aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
 609         __delay(200);
 610
 611         aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
 612         __delay(2000);
 613         sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
 614         aty_st_le32(GP_IO, 0, par); /* turn off outputs */
 615         return sense;
 616 }
 617
 618 #endif /* defined(CONFIG_PPC) */
 619
 620 /* ------------------------------------------------------------------------- */
 621
 622 /*
 623  *  CRTC programming
 624  */
 625
 626 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
 627 {
 628 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 629         if (par->lcd_table != 0) {
 630                 if(!M64_HAS(LT_LCD_REGS)) {
 631                     crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
 632                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 633                 }
 634                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
 635                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
 636
 637
 638                 /* switch to non shadow registers */
 639                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 640                     ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 641
 642                 /* save stretching */
 643                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
 644                 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
 645                 if (!M64_HAS(LT_LCD_REGS))
 646                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
 647         }
 648 #endif
 649         crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 650         crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 651         crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 652         crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 653         crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
 654         crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
 655         crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
 656
 657 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 658         if (par->lcd_table != 0) {
 659                 /* switch to shadow registers */
 660                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 661                         SHADOW_EN | SHADOW_RW_EN, par);
 662
 663                 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
 664                 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
 665                 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
 666                 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
 667
 668                 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 669         }
 670 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 671 }
 672
 673 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
 674 {
 675 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 676         if (par->lcd_table != 0) {
 677                 /* stop CRTC */
 678                 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
 679
 680                 /* update non-shadow registers first */
 681                 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
 682                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
 683                         ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
 684
 685                 /* temporarily disable stretching */
 686                 aty_st_lcd(HORZ_STRETCHING,
 687                         crtc->horz_stretching &
 688                         ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
 689                 aty_st_lcd(VERT_STRETCHING,
 690                         crtc->vert_stretching &
 691                         ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
 692                         VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
 693         }
 694 #endif
 695         /* turn off CRT */
 696         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
 697
 698         DPRINTK("setting up CRTC\n");
 699         DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
 700             ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
 701             (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
 702             (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
 703
 704         DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
 705         DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
 706         DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
 707         DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
 708         DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
 709         DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
 710         DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
 711
 712         aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
 713         aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
 714         aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
 715         aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
 716         aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
 717         aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
 718
 719         aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
 720 #if 0
 721         FIXME
 722         if (par->accel_flags & FB_ACCELF_TEXT)
 723                 aty_init_engine(par, info);
 724 #endif
 725 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 726         /* after setting the CRTC registers we should set the LCD registers. */
 727         if (par->lcd_table != 0) {
 728                 /* switch to shadow registers */
 729                 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
 730                         (SHADOW_EN | SHADOW_RW_EN), par);
 731
 732                 DPRINTK("set shadow CRT to %ix%i %c%c\n",
 733                     ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
 734                     (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
 735
 736                 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
 737                 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
 738                 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
 739                 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
 740
 741                 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
 742                 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
 743                 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
 744                 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
 745
 746                 /* restore CRTC selection & shadow state and enable stretching */
 747                 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
 748                 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
 749                 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
 750                 if(!M64_HAS(LT_LCD_REGS))
 751                     DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
 752
 753                 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
 754                 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
 755                 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
 756                 if(!M64_HAS(LT_LCD_REGS)) {
 757                     aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
 758                     aty_ld_le32(LCD_INDEX, par);
 759                     aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
 760                 }
 761         }
 762 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 763 }
 764
 765 static int aty_var_to_crtc(const struct fb_info *info,
 766         const struct fb_var_screeninfo *var, struct crtc *crtc)
 767 {
 768         struct atyfb_par *par = (struct atyfb_par *) info->par;
 769         u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
 770         u32 sync, vmode, vdisplay;
 771         u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
 772         u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
 773         u32 pix_width, dp_pix_width, dp_chain_mask;
 774
 775         /* input */
 776         xres = var->xres;
 777         yres = var->yres;
 778         vxres = var->xres_virtual;
 779         vyres = var->yres_virtual;
 780         xoffset = var->xoffset;
 781         yoffset = var->yoffset;
 782         bpp = var->bits_per_pixel;
 783         if (bpp == 16)
 784                 bpp = (var->green.length == 5) ? 15 : 16;
 785         sync = var->sync;
 786         vmode = var->vmode;
 787
 788         /* convert (and round up) and validate */
 789         if (vxres < xres + xoffset)
 790                 vxres = xres + xoffset;
 791         h_disp = xres;
 792
 793         if (vyres < yres + yoffset)
 794                 vyres = yres + yoffset;
 795         v_disp = yres;
 796
 797         if (bpp <= 8) {
 798                 bpp = 8;
 799                 pix_width = CRTC_PIX_WIDTH_8BPP;
 800                 dp_pix_width =
 801                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 802                     BYTE_ORDER_LSB_TO_MSB;
 803                 dp_chain_mask = DP_CHAIN_8BPP;
 804         } else if (bpp <= 15) {
 805                 bpp = 16;
 806                 pix_width = CRTC_PIX_WIDTH_15BPP;
 807                 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
 808                     BYTE_ORDER_LSB_TO_MSB;
 809                 dp_chain_mask = DP_CHAIN_15BPP;
 810         } else if (bpp <= 16) {
 811                 bpp = 16;
 812                 pix_width = CRTC_PIX_WIDTH_16BPP;
 813                 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
 814                     BYTE_ORDER_LSB_TO_MSB;
 815                 dp_chain_mask = DP_CHAIN_16BPP;
 816         } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
 817                 bpp = 24;
 818                 pix_width = CRTC_PIX_WIDTH_24BPP;
 819                 dp_pix_width =
 820                     HOST_8BPP | SRC_8BPP | DST_8BPP |
 821                     BYTE_ORDER_LSB_TO_MSB;
 822                 dp_chain_mask = DP_CHAIN_24BPP;
 823         } else if (bpp <= 32) {
 824                 bpp = 32;
 825                 pix_width = CRTC_PIX_WIDTH_32BPP;
 826                 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
 827                     BYTE_ORDER_LSB_TO_MSB;
 828                 dp_chain_mask = DP_CHAIN_32BPP;
 829         } else
 830                 FAIL("invalid bpp");
 831
 832         if (vxres * vyres * bpp / 8 > info->fix.smem_len)
 833                 FAIL("not enough video RAM");
 834
 835         h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
 836         v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
 837
 838         if((xres > 1600) || (yres > 1200)) {
 839                 FAIL("MACH64 chips are designed for max 1600x1200\n"
 840                 "select anoter resolution.");
 841         }
 842         h_sync_strt = h_disp + var->right_margin;
 843         h_sync_end = h_sync_strt + var->hsync_len;
 844         h_sync_dly  = var->right_margin & 7;
 845         h_total = h_sync_end + h_sync_dly + var->left_margin;
 846
 847         v_sync_strt = v_disp + var->lower_margin;
 848         v_sync_end = v_sync_strt + var->vsync_len;
 849         v_total = v_sync_end + var->upper_margin;
 850
 851 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 852         if (par->lcd_table != 0) {
 853                 if(!M64_HAS(LT_LCD_REGS)) {
 854                     u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
 855                     crtc->lcd_index = lcd_index &
 856                         ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
 857                     aty_st_le32(LCD_INDEX, lcd_index, par);
 858                 }
 859
 860                 if (!M64_HAS(MOBIL_BUS))
 861                         crtc->lcd_index |= CRTC2_DISPLAY_DIS;
 862
 863                 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
 864                 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
 865
 866                 crtc->lcd_gen_cntl &=
 867                         ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
 868                         /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
 869                         USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
 870                 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
 871
 872                 if((crtc->lcd_gen_cntl & LCD_ON) &&
 873                         ((xres > par->lcd_width) || (yres > par->lcd_height))) {
 874                         /* We cannot display the mode on the LCD. If the CRT is enabled
 875                            we can turn off the LCD.
 876                            If the CRT is off, it isn't a good idea to switch it on; we don't
 877                            know if one is connected. So it's better to fail then.
 878                          */
 879                         if (crtc->lcd_gen_cntl & CRT_ON) {
 880                                 if (!(var->activate & FB_ACTIVATE_TEST))
 881                                         PRINTKI("Disable LCD panel, because video mode does not fit.\n");
 882                                 crtc->lcd_gen_cntl &= ~LCD_ON;
 883                                 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
 884                         } else {
 885                                 if (!(var->activate & FB_ACTIVATE_TEST))
 886                                         PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
 887                                 return -EINVAL;
 888                         }
 889                 }
 890         }
 891
 892         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
 893                 int VScan = 1;
 894                 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
 895                 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
 896                 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 };  */
 897
 898                 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
 899
 900                 /* This is horror! When we simulate, say 640x480 on an 800x600
 901                    LCD monitor, the CRTC should be programmed 800x600 values for
 902                    the non visible part, but 640x480 for the visible part.
 903                    This code has been tested on a laptop with it's 1400x1050 LCD
 904                    monitor and a conventional monitor both switched on.
 905                    Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
 906                     works with little glitches also with DOUBLESCAN modes
 907                  */
 908                 if (yres < par->lcd_height) {
 909                         VScan = par->lcd_height / yres;
 910                         if(VScan > 1) {
 911                                 VScan = 2;
 912                                 vmode |= FB_VMODE_DOUBLE;
 913                         }
 914                 }
 915
 916                 h_sync_strt = h_disp + par->lcd_right_margin;
 917                 h_sync_end = h_sync_strt + par->lcd_hsync_len;
 918                 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
 919                 h_total = h_disp + par->lcd_hblank_len;
 920
 921                 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
 922                 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
 923                 v_total = v_disp + par->lcd_vblank_len / VScan;
 924         }
 925 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
 926
 927         h_disp = (h_disp >> 3) - 1;
 928         h_sync_strt = (h_sync_strt >> 3) - 1;
 929         h_sync_end = (h_sync_end >> 3) - 1;
 930         h_total = (h_total >> 3) - 1;
 931         h_sync_wid = h_sync_end - h_sync_strt;
 932
 933         FAIL_MAX("h_disp too large", h_disp, 0xff);
 934         FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
 935         /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
 936         if(h_sync_wid > 0x1f)
 937                 h_sync_wid = 0x1f;
 938         FAIL_MAX("h_total too large", h_total, 0x1ff);
 939
 940         if (vmode & FB_VMODE_DOUBLE) {
 941                 v_disp <<= 1;
 942                 v_sync_strt <<= 1;
 943                 v_sync_end <<= 1;
 944                 v_total <<= 1;
 945         }
 946
 947         vdisplay = yres;
 948 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 949         if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
 950                 vdisplay  = par->lcd_height;
 951 #endif
 952
 953         v_disp--;
 954         v_sync_strt--;
 955         v_sync_end--;
 956         v_total--;
 957         v_sync_wid = v_sync_end - v_sync_strt;
 958
 959         FAIL_MAX("v_disp too large", v_disp, 0x7ff);
 960         FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
 961         /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
 962         if(v_sync_wid > 0x1f)
 963                 v_sync_wid = 0x1f;
 964         FAIL_MAX("v_total too large", v_total, 0x7ff);
 965
 966         c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
 967
 968         /* output */
 969         crtc->vxres = vxres;
 970         crtc->vyres = vyres;
 971         crtc->xoffset = xoffset;
 972         crtc->yoffset = yoffset;
 973         crtc->bpp = bpp;
 974         crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
 975         crtc->vline_crnt_vline = 0;
 976
 977         crtc->h_tot_disp = h_total | (h_disp<<16);
 978         crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
 979                 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
 980         crtc->v_tot_disp = v_total | (v_disp<<16);
 981         crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
 982
 983         /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
 984         crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
 985         crtc->gen_cntl |= CRTC_VGA_LINEAR;
 986
 987         /* Enable doublescan mode if requested */
 988         if (vmode & FB_VMODE_DOUBLE)
 989                 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
 990         /* Enable interlaced mode if requested */
 991         if (vmode & FB_VMODE_INTERLACED)
 992                 crtc->gen_cntl |= CRTC_INTERLACE_EN;
 993 #ifdef CONFIG_FB_ATY_GENERIC_LCD
 994         if (par->lcd_table != 0) {
 995                 vdisplay = yres;
 996                 if(vmode & FB_VMODE_DOUBLE)
 997                         vdisplay <<= 1;
 998                 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
 999                 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
1000                         /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
1001                         USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1002                 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1003
1004                 /* MOBILITY M1 tested, FIXME: LT */
1005                 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1006                 if (!M64_HAS(LT_LCD_REGS))
1007                         crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1008                                 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1009
1010                 crtc->horz_stretching &=
1011                         ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1012                         HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1013                 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1014                         do {
1015                                 /*
1016                                 * The horizontal blender misbehaves when HDisplay is less than a
1017                                 * a certain threshold (440 for a 1024-wide panel).  It doesn't
1018                                 * stretch such modes enough.  Use pixel replication instead of
1019                                 * blending to stretch modes that can be made to exactly fit the
1020                                 * panel width.  The undocumented "NoLCDBlend" option allows the
1021                                 * pixel-replicated mode to be slightly wider or narrower than the
1022                                 * panel width.  It also causes a mode that is exactly half as wide
1023                                 * as the panel to be pixel-replicated, rather than blended.
1024                                 */
1025                                 int HDisplay  = xres & ~7;
1026                                 int nStretch  = par->lcd_width / HDisplay;
1027                                 int Remainder = par->lcd_width % HDisplay;
1028
1029                                 if ((!Remainder && ((nStretch > 2))) ||
1030                                         (((HDisplay * 16) / par->lcd_width) < 7)) {
1031                                         static const char StretchLoops[] = {10, 12, 13, 15, 16};
1032                                         int horz_stretch_loop = -1, BestRemainder;
1033                                         int Numerator = HDisplay, Denominator = par->lcd_width;
1034                                         int Index = 5;
1035                                         ATIReduceRatio(&Numerator, &Denominator);
1036
1037                                         BestRemainder = (Numerator * 16) / Denominator;
1038                                         while (--Index >= 0) {
1039                                                 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1040                                                         Denominator;
1041                                                 if (Remainder < BestRemainder) {
1042                                                         horz_stretch_loop = Index;
1043                                                         if (!(BestRemainder = Remainder))
1044                                                                 break;
1045                                                 }
1046                                         }
1047
1048                                         if ((horz_stretch_loop >= 0) && !BestRemainder) {
1049                                                 int horz_stretch_ratio = 0, Accumulator = 0;
1050                                                 int reuse_previous = 1;
1051
1052                                                 Index = StretchLoops[horz_stretch_loop];
1053
1054                                                 while (--Index >= 0) {
1055                                                         if (Accumulator > 0)
1056                                                                 horz_stretch_ratio |= reuse_previous;
1057                                                         else
1058                                                                 Accumulator += Denominator;
1059                                                         Accumulator -= Numerator;
1060                                                         reuse_previous <<= 1;
1061                                                 }
1062
1063                                                 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1064                                                         ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1065                                                         (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1066                                                 break;      /* Out of the do { ... } while (0) */
1067                                         }
1068                                 }
1069
1070                                 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1071                                         (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1072                         } while (0);
1073                 }
1074
1075                 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1076                         crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1077                                 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1078
1079                         if (!M64_HAS(LT_LCD_REGS) &&
1080                             xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1081                                 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1082                 } else {
1083                         /*
1084                          * Don't use vertical blending if the mode is too wide or not
1085                          * vertically stretched.
1086                          */
1087                         crtc->vert_stretching = 0;
1088                 }
1089                 /* copy to shadow crtc */
1090                 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1091                 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1092                 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1093                 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1094         }
1095 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1096
1097         if (M64_HAS(MAGIC_FIFO)) {
1098                 /* FIXME: display FIFO low watermark values */
1099                 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1100         }
1101         crtc->dp_pix_width = dp_pix_width;
1102         crtc->dp_chain_mask = dp_chain_mask;
1103
1104         return 0;
1105 }
1106
1107 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1108 {
1109         u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1110         u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1111             h_sync_pol;
1112         u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1113         u32 pix_width;
1114         u32 double_scan, interlace;
1115
1116         /* input */
1117         h_total = crtc->h_tot_disp & 0x1ff;
1118         h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1119         h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1120         h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1121         h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1122         h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1123         v_total = crtc->v_tot_disp & 0x7ff;
1124         v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1125         v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1126         v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1127         v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1128         c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1129         pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1130         double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1131         interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1132
1133         /* convert */
1134         xres = (h_disp + 1) * 8;
1135         yres = v_disp + 1;
1136         left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1137         right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1138         hslen = h_sync_wid * 8;
1139         upper = v_total - v_sync_strt - v_sync_wid;
1140         lower = v_sync_strt - v_disp;
1141         vslen = v_sync_wid;
1142         sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1143             (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1144             (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1145
1146         switch (pix_width) {
1147 #if 0
1148         case CRTC_PIX_WIDTH_4BPP:
1149                 bpp = 4;
1150                 var->red.offset = 0;
1151                 var->red.length = 8;
1152                 var->green.offset = 0;
1153                 var->green.length = 8;
1154                 var->blue.offset = 0;
1155                 var->blue.length = 8;
1156                 var->transp.offset = 0;
1157                 var->transp.length = 0;
1158                 break;
1159 #endif
1160         case CRTC_PIX_WIDTH_8BPP:
1161                 bpp = 8;
1162                 var->red.offset = 0;
1163                 var->red.length = 8;
1164                 var->green.offset = 0;
1165                 var->green.length = 8;
1166                 var->blue.offset = 0;
1167                 var->blue.length = 8;
1168                 var->transp.offset = 0;
1169                 var->transp.length = 0;
1170                 break;
1171         case CRTC_PIX_WIDTH_15BPP:      /* RGB 555 */
1172                 bpp = 16;
1173                 var->red.offset = 10;
1174                 var->red.length = 5;
1175                 var->green.offset = 5;
1176                 var->green.length = 5;
1177                 var->blue.offset = 0;
1178                 var->blue.length = 5;
1179                 var->transp.offset = 0;
1180                 var->transp.length = 0;
1181                 break;
1182         case CRTC_PIX_WIDTH_16BPP:      /* RGB 565 */
1183                 bpp = 16;
1184                 var->red.offset = 11;
1185                 var->red.length = 5;
1186                 var->green.offset = 5;
1187                 var->green.length = 6;
1188                 var->blue.offset = 0;
1189                 var->blue.length = 5;
1190                 var->transp.offset = 0;
1191                 var->transp.length = 0;
1192                 break;
1193         case CRTC_PIX_WIDTH_24BPP:      /* RGB 888 */
1194                 bpp = 24;
1195                 var->red.offset = 16;
1196                 var->red.length = 8;
1197                 var->green.offset = 8;
1198                 var->green.length = 8;
1199                 var->blue.offset = 0;
1200                 var->blue.length = 8;
1201                 var->transp.offset = 0;
1202                 var->transp.length = 0;
1203                 break;
1204         case CRTC_PIX_WIDTH_32BPP:      /* ARGB 8888 */
1205                 bpp = 32;
1206                 var->red.offset = 16;
1207                 var->red.length = 8;
1208                 var->green.offset = 8;
1209                 var->green.length = 8;
1210                 var->blue.offset = 0;
1211                 var->blue.length = 8;
1212                 var->transp.offset = 24;
1213                 var->transp.length = 8;
1214                 break;
1215         default:
1216                 PRINTKE("Invalid pixel width\n");
1217                 return -EINVAL;
1218         }
1219
1220         /* output */
1221         var->xres = xres;
1222         var->yres = yres;
1223         var->xres_virtual = crtc->vxres;
1224         var->yres_virtual = crtc->vyres;
1225         var->bits_per_pixel = bpp;
1226         var->left_margin = left;
1227         var->right_margin = right;
1228         var->upper_margin = upper;
1229         var->lower_margin = lower;
1230         var->hsync_len = hslen;
1231         var->vsync_len = vslen;
1232         var->sync = sync;
1233         var->vmode = FB_VMODE_NONINTERLACED;
1234         /* In double scan mode, the vertical parameters are doubled, so we need to
1235            half them to get the right values.
1236            In interlaced mode the values are already correct, so no correction is
1237            necessary.
1238          */
1239         if (interlace)
1240                 var->vmode = FB_VMODE_INTERLACED;
1241
1242         if (double_scan) {
1243                 var->vmode = FB_VMODE_DOUBLE;
1244                 var->yres>>=1;
1245                 var->upper_margin>>=1;
1246                 var->lower_margin>>=1;
1247                 var->vsync_len>>=1;
1248         }
1249
1250         return 0;
1251 }
1252
1253 /* ------------------------------------------------------------------------- */
1254
1255 static int atyfb_set_par(struct fb_info *info)
1256 {
1257         struct atyfb_par *par = (struct atyfb_par *) info->par;
1258         struct fb_var_screeninfo *var = &info->var;
1259         u32 tmp, pixclock;
1260         int err;
1261 #ifdef DEBUG
1262         struct fb_var_screeninfo debug;
1263         u32 pixclock_in_ps;
1264 #endif
1265         if (par->asleep)
1266                 return 0;
1267
1268         if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1269                 return err;
1270
1271         pixclock = atyfb_get_pixclock(var, par);
1272
1273         if (pixclock == 0) {
1274                 PRINTKE("Invalid pixclock\n");
1275                 return -EINVAL;
1276         } else {
1277                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1278                         return err;
1279         }
1280
1281         par->accel_flags = var->accel_flags; /* hack */
1282
1283         if (var->accel_flags) {
1284                 info->fbops->fb_sync = atyfb_sync;
1285                 info->flags &= ~FBINFO_HWACCEL_DISABLED;
1286         } else {
1287                 info->fbops->fb_sync = NULL;
1288                 info->flags |= FBINFO_HWACCEL_DISABLED;
1289         }
1290
1291         if (par->blitter_may_be_busy)
1292                 wait_for_idle(par);
1293
1294         aty_set_crtc(par, &par->crtc);
1295         par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1296         par->pll_ops->set_pll(info, &par->pll);
1297
1298 #ifdef DEBUG
1299         if(par->pll_ops && par->pll_ops->pll_to_var)
1300                 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1301         else
1302                 pixclock_in_ps = 0;
1303
1304         if(0 == pixclock_in_ps) {
1305                 PRINTKE("ALERT ops->pll_to_var get 0\n");
1306                 pixclock_in_ps = pixclock;
1307         }
1308
1309         memset(&debug, 0, sizeof(debug));
1310         if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1311                 u32 hSync, vRefresh;
1312                 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1313                 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1314
1315                 h_disp = debug.xres;
1316                 h_sync_strt = h_disp + debug.right_margin;
1317                 h_sync_end = h_sync_strt + debug.hsync_len;
1318                 h_total = h_sync_end + debug.left_margin;
1319                 v_disp = debug.yres;
1320                 v_sync_strt = v_disp + debug.lower_margin;
1321                 v_sync_end = v_sync_strt + debug.vsync_len;
1322                 v_total = v_sync_end + debug.upper_margin;
1323
1324                 hSync = 1000000000 / (pixclock_in_ps * h_total);
1325                 vRefresh = (hSync * 1000) / v_total;
1326                 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1327                 vRefresh *= 2;
1328                 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1329                 vRefresh /= 2;
1330
1331                 DPRINTK("atyfb_set_par\n");
1332                 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1333                 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1334                         var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1335                 DPRINTK(" Dot clock:           %i MHz\n", 1000000 / pixclock_in_ps);
1336                 DPRINTK(" Horizontal sync:     %i kHz\n", hSync);
1337                 DPRINTK(" Vertical refresh:    %i Hz\n", vRefresh);
1338                 DPRINTK(" x  style: %i.%03i %i %i %i %i   %i %i %i %i\n",
1339                         1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1340                         h_disp, h_sync_strt, h_sync_end, h_total,
1341                         v_disp, v_sync_strt, v_sync_end, v_total);
1342                 DPRINTK(" fb style: %i  %i %i %i %i %i %i %i %i\n",
1343                         pixclock_in_ps,
1344                         debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1345                         debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1346         }
1347 #endif /* DEBUG */
1348
1349         if (!M64_HAS(INTEGRATED)) {
1350                 /* Don't forget MEM_CNTL */
1351                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1352                 switch (var->bits_per_pixel) {
1353                 case 8:
1354                         tmp |= 0x02000000;
1355                         break;
1356                 case 16:
1357                         tmp |= 0x03000000;
1358                         break;
1359                 case 32:
1360                         tmp |= 0x06000000;
1361                         break;
1362                 }
1363                 aty_st_le32(MEM_CNTL, tmp, par);
1364         } else {
1365                 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1366                 if (!M64_HAS(MAGIC_POSTDIV))
1367                         tmp |= par->mem_refresh_rate << 20;
1368                 switch (var->bits_per_pixel) {
1369                 case 8:
1370                 case 24:
1371                         tmp |= 0x00000000;
1372                         break;
1373                 case 16:
1374                         tmp |= 0x04000000;
1375                         break;
1376                 case 32:
1377                         tmp |= 0x08000000;
1378                         break;
1379                 }
1380                 if (M64_HAS(CT_BUS)) {
1381                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1382                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1383                 } else if (M64_HAS(VT_BUS)) {
1384                         aty_st_le32(DAC_CNTL, 0x87010184, par);
1385                         aty_st_le32(BUS_CNTL, 0x680000f9, par);
1386                 } else if (M64_HAS(MOBIL_BUS)) {
1387                         aty_st_le32(DAC_CNTL, 0x80010102, par);
1388                         aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1389                 } else {
1390                         /* GT */
1391                         aty_st_le32(DAC_CNTL, 0x86010102, par);
1392                         aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1393                         aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1394                 }
1395                 aty_st_le32(MEM_CNTL, tmp, par);
1396         }
1397         aty_st_8(DAC_MASK, 0xff, par);
1398
1399         info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1400         info->fix.visual = var->bits_per_pixel <= 8 ?
1401                 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1402
1403         /* Initialize the graphics engine */
1404         if (par->accel_flags & FB_ACCELF_TEXT)
1405                 aty_init_engine(par, info);
1406
1407 #ifdef CONFIG_BOOTX_TEXT
1408         btext_update_display(info->fix.smem_start,
1409                 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1410                 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1411                 var->bits_per_pixel,
1412                 par->crtc.vxres * var->bits_per_pixel / 8);
1413 #endif /* CONFIG_BOOTX_TEXT */
1414 #if 0
1415         /* switch to accelerator mode */
1416         if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1417                 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1418 #endif
1419 #ifdef DEBUG
1420 {
1421         /* dump non shadow CRTC, pll, LCD registers */
1422         int i; u32 base;
1423
1424         /* CRTC registers */
1425         base = 0x2000;
1426         printk("debug atyfb: Mach64 non-shadow register values:");
1427         for (i = 0; i < 256; i = i+4) {
1428                 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1429                 printk(" %08X", aty_ld_le32(i, par));
1430         }
1431         printk("\n\n");
1432
1433 #ifdef CONFIG_FB_ATY_CT
1434         /* PLL registers */
1435         base = 0x00;
1436         printk("debug atyfb: Mach64 PLL register values:");
1437         for (i = 0; i < 64; i++) {
1438                 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1439                 if(i%4 == 0)  printk(" ");
1440                 printk("%02X", aty_ld_pll_ct(i, par));
1441         }
1442         printk("\n\n");
1443 #endif  /* CONFIG_FB_ATY_CT */
1444
1445 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1446         if (par->lcd_table != 0) {
1447                 /* LCD registers */
1448                 base = 0x00;
1449                 printk("debug atyfb: LCD register values:");
1450                 if(M64_HAS(LT_LCD_REGS)) {
1451                     for(i = 0; i <= POWER_MANAGEMENT; i++) {
1452                         if(i == EXT_VERT_STRETCH)
1453                             continue;
1454                         printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1455                         printk(" %08X", aty_ld_lcd(i, par));
1456                     }
1457
1458                 } else {
1459                     for (i = 0; i < 64; i++) {
1460                         if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1461                         printk(" %08X", aty_ld_lcd(i, par));
1462                     }
1463                 }
1464                 printk("\n\n");
1465         }
1466 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1467 }
1468 #endif /* DEBUG */
1469         return 0;
1470 }
1471
1472 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1473 {
1474         struct atyfb_par *par = (struct atyfb_par *) info->par;
1475         int err;
1476         struct crtc crtc;
1477         union aty_pll pll;
1478         u32 pixclock;
1479
1480         memcpy(&pll, &(par->pll), sizeof(pll));
1481
1482         if((err = aty_var_to_crtc(info, var, &crtc)))
1483                 return err;
1484
1485         pixclock = atyfb_get_pixclock(var, par);
1486
1487         if (pixclock == 0) {
1488                 if (!(var->activate & FB_ACTIVATE_TEST))
1489                         PRINTKE("Invalid pixclock\n");
1490                 return -EINVAL;
1491         } else {
1492                 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1493                         return err;
1494         }
1495
1496         if (var->accel_flags & FB_ACCELF_TEXT)
1497                 info->var.accel_flags = FB_ACCELF_TEXT;
1498         else
1499                 info->var.accel_flags = 0;
1500
1501 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1502         if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1503                 return -EINVAL;
1504 #endif
1505         aty_crtc_to_var(&crtc, var);
1506         var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1507         return 0;
1508 }
1509
1510 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1511 {
1512         u32 xoffset = info->var.xoffset;
1513         u32 yoffset = info->var.yoffset;
1514         u32 vxres = par->crtc.vxres;
1515         u32 bpp = info->var.bits_per_pixel;
1516
1517         par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1518 }
1519
1520
1521     /*
1522      *  Open/Release the frame buffer device
1523      */
1524
1525 static int atyfb_open(struct fb_info *info, int user)
1526 {
1527         struct atyfb_par *par = (struct atyfb_par *) info->par;
1528
1529         if (user) {
1530                 par->open++;
1531 #ifdef __sparc__
1532                 par->mmaped = 0;
1533 #endif
1534         }
1535         return (0);
1536 }
1537
1538 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1539 {
1540         struct atyfb_par *par = dev_id;
1541         int handled = 0;
1542         u32 int_cntl;
1543
1544         spin_lock(&par->int_lock);
1545
1546         int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1547
1548         if (int_cntl & CRTC_VBLANK_INT) {
1549                 /* clear interrupt */
1550                 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1551                 par->vblank.count++;
1552                 if (par->vblank.pan_display) {
1553                         par->vblank.pan_display = 0;
1554                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1555                 }
1556                 wake_up_interruptible(&par->vblank.wait);
1557                 handled = 1;
1558         }
1559
1560         spin_unlock(&par->int_lock);
1561
1562         return IRQ_RETVAL(handled);
1563 }
1564
1565 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1566 {
1567         u32 int_cntl;
1568
1569         if (!test_and_set_bit(0, &par->irq_flags)) {
1570                 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1571                         clear_bit(0, &par->irq_flags);
1572                         return -EINVAL;
1573                 }
1574                 spin_lock_irq(&par->int_lock);
1575                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1576                 /* clear interrupt */
1577                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1578                 /* enable interrupt */
1579                 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1580                 spin_unlock_irq(&par->int_lock);
1581         } else if (reenable) {
1582                 spin_lock_irq(&par->int_lock);
1583                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1584                 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1585                         printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1586                         /* re-enable interrupt */
1587                         aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1588                 }
1589                 spin_unlock_irq(&par->int_lock);
1590         }
1591
1592         return 0;
1593 }
1594
1595 static int aty_disable_irq(struct atyfb_par *par)
1596 {
1597         u32 int_cntl;
1598
1599         if (test_and_clear_bit(0, &par->irq_flags)) {
1600                 if (par->vblank.pan_display) {
1601                         par->vblank.pan_display = 0;
1602                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1603                 }
1604                 spin_lock_irq(&par->int_lock);
1605                 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1606                 /* disable interrupt */
1607                 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1608                 spin_unlock_irq(&par->int_lock);
1609                 free_irq(par->irq, par);
1610         }
1611
1612         return 0;
1613 }
1614
1615 static int atyfb_release(struct fb_info *info, int user)
1616 {
1617         struct atyfb_par *par = (struct atyfb_par *) info->par;
1618         if (user) {
1619                 par->open--;
1620                 mdelay(1);
1621                 wait_for_idle(par);
1622                 if (!par->open) {
1623 #ifdef __sparc__
1624                         int was_mmaped = par->mmaped;
1625
1626                         par->mmaped = 0;
1627
1628                         if (was_mmaped) {
1629                                 struct fb_var_screeninfo var;
1630
1631                                 /* Now reset the default display config, we have no
1632                                  * idea what the program(s) which mmap'd the chip did
1633                                  * to the configuration, nor whether it restored it
1634                                  * correctly.
1635                                  */
1636                                 var = default_var;
1637                                 if (noaccel)
1638                                         var.accel_flags &= ~FB_ACCELF_TEXT;
1639                                 else
1640                                         var.accel_flags |= FB_ACCELF_TEXT;
1641                                 if (var.yres == var.yres_virtual) {
1642                                         u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1643                                         var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1644                                         if (var.yres_virtual < var.yres)
1645                                                 var.yres_virtual = var.yres;
1646                                 }
1647                         }
1648 #endif
1649                         aty_disable_irq(par);
1650                 }
1651         }
1652         return (0);
1653 }
1654
1655     /*
1656      *  Pan or Wrap the Display
1657      *
1658      *  This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1659      */
1660
1661 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1662 {
1663         struct atyfb_par *par = (struct atyfb_par *) info->par;
1664         u32 xres, yres, xoffset, yoffset;
1665
1666         xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1667         yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1668         if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1669                 yres >>= 1;
1670         xoffset = (var->xoffset + 7) & ~7;
1671         yoffset = var->yoffset;
1672         if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1673                 return -EINVAL;
1674         info->var.xoffset = xoffset;
1675         info->var.yoffset = yoffset;
1676         if (par->asleep)
1677                 return 0;
1678
1679         set_off_pitch(par, info);
1680         if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1681                 par->vblank.pan_display = 1;
1682         } else {
1683                 par->vblank.pan_display = 0;
1684                 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1685         }
1686
1687         return 0;
1688 }
1689
1690 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1691 {
1692         struct aty_interrupt *vbl;
1693         unsigned int count;
1694         int ret;
1695
1696         switch (crtc) {
1697         case 0:
1698                 vbl = &par->vblank;
1699                 break;
1700         default:
1701                 return -ENODEV;
1702         }
1703
1704         ret = aty_enable_irq(par, 0);
1705         if (ret)
1706                 return ret;
1707
1708         count = vbl->count;
1709         ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1710         if (ret < 0) {
1711                 return ret;
1712         }
1713         if (ret == 0) {
1714                 aty_enable_irq(par, 1);
1715                 return -ETIMEDOUT;
1716         }
1717
1718         return 0;
1719 }
1720
1721
1722 #ifdef DEBUG
1723 #define ATYIO_CLKR              0x41545900      /* ATY\00 */
1724 #define ATYIO_CLKW              0x41545901      /* ATY\01 */
1725
1726 struct atyclk {
1727         u32 ref_clk_per;
1728         u8 pll_ref_div;
1729         u8 mclk_fb_div;
1730         u8 mclk_post_div;       /* 1,2,3,4,8 */
1731         u8 mclk_fb_mult;        /* 2 or 4 */
1732         u8 xclk_post_div;       /* 1,2,3,4,8 */
1733         u8 vclk_fb_div;
1734         u8 vclk_post_div;       /* 1,2,3,4,6,8,12 */
1735         u32 dsp_xclks_per_row;  /* 0-16383 */
1736         u32 dsp_loop_latency;   /* 0-15 */
1737         u32 dsp_precision;      /* 0-7 */
1738         u32 dsp_on;             /* 0-2047 */
1739         u32 dsp_off;            /* 0-2047 */
1740 };
1741
1742 #define ATYIO_FEATR             0x41545902      /* ATY\02 */
1743 #define ATYIO_FEATW             0x41545903      /* ATY\03 */
1744 #endif
1745
1746 #ifndef FBIO_WAITFORVSYNC
1747 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1748 #endif
1749
1750 static int atyfb_ioctl(struct fb_info *info, u_int cmd, u_long arg)
1751 {
1752         struct atyfb_par *par = (struct atyfb_par *) info->par;
1753 #ifdef __sparc__
1754         struct fbtype fbtyp;
1755 #endif
1756
1757         switch (cmd) {
1758 #ifdef __sparc__
1759         case FBIOGTYPE:
1760                 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1761                 fbtyp.fb_width = par->crtc.vxres;
1762                 fbtyp.fb_height = par->crtc.vyres;
1763                 fbtyp.fb_depth = info->var.bits_per_pixel;
1764                 fbtyp.fb_cmsize = info->cmap.len;
1765                 fbtyp.fb_size = info->fix.smem_len;
1766                 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1767                         return -EFAULT;
1768                 break;
1769 #endif /* __sparc__ */
1770
1771         case FBIO_WAITFORVSYNC:
1772                 {
1773                         u32 crtc;
1774
1775                         if (get_user(crtc, (__u32 __user *) arg))
1776                                 return -EFAULT;
1777
1778                         return aty_waitforvblank(par, crtc);
1779                 }
1780                 break;
1781
1782 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1783         case ATYIO_CLKR:
1784                 if (M64_HAS(INTEGRATED)) {
1785                         struct atyclk clk;
1786                         union aty_pll *pll = &(par->pll);
1787                         u32 dsp_config = pll->ct.dsp_config;
1788                         u32 dsp_on_off = pll->ct.dsp_on_off;
1789                         clk.ref_clk_per = par->ref_clk_per;
1790                         clk.pll_ref_div = pll->ct.pll_ref_div;
1791                         clk.mclk_fb_div = pll->ct.mclk_fb_div;
1792                         clk.mclk_post_div = pll->ct.mclk_post_div_real;
1793                         clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1794                         clk.xclk_post_div = pll->ct.xclk_post_div_real;
1795                         clk.vclk_fb_div = pll->ct.vclk_fb_div;
1796                         clk.vclk_post_div = pll->ct.vclk_post_div_real;
1797                         clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1798                         clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1799                         clk.dsp_precision = (dsp_config >> 20) & 7;
1800                         clk.dsp_off = dsp_on_off & 0x7ff;
1801                         clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1802                         if (copy_to_user((struct atyclk __user *) arg, &clk,
1803                                          sizeof(clk)))
1804                                 return -EFAULT;
1805                 } else
1806                         return -EINVAL;
1807                 break;
1808         case ATYIO_CLKW:
1809                 if (M64_HAS(INTEGRATED)) {
1810                         struct atyclk clk;
1811                         union aty_pll *pll = &(par->pll);
1812                         if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1813                                 return -EFAULT;
1814                         par->ref_clk_per = clk.ref_clk_per;
1815                         pll->ct.pll_ref_div = clk.pll_ref_div;
1816                         pll->ct.mclk_fb_div = clk.mclk_fb_div;
1817                         pll->ct.mclk_post_div_real = clk.mclk_post_div;
1818                         pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1819                         pll->ct.xclk_post_div_real = clk.xclk_post_div;
1820                         pll->ct.vclk_fb_div = clk.vclk_fb_div;
1821                         pll->ct.vclk_post_div_real = clk.vclk_post_div;
1822                         pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1823                                 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1824                         pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1825                         /*aty_calc_pll_ct(info, &pll->ct);*/
1826                         aty_set_pll_ct(info, pll);
1827                 } else
1828                         return -EINVAL;
1829                 break;
1830         case ATYIO_FEATR:
1831                 if (get_user(par->features, (u32 __user *) arg))
1832                         return -EFAULT;
1833                 break;
1834         case ATYIO_FEATW:
1835                 if (put_user(par->features, (u32 __user *) arg))
1836                         return -EFAULT;
1837                 break;
1838 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1839         default:
1840                 return -EINVAL;
1841         }
1842         return 0;
1843 }
1844
1845 static int atyfb_sync(struct fb_info *info)
1846 {
1847         struct atyfb_par *par = (struct atyfb_par *) info->par;
1848
1849         if (par->blitter_may_be_busy)
1850                 wait_for_idle(par);
1851         return 0;
1852 }
1853
1854 #ifdef __sparc__
1855 static int atyfb_mmap(struct fb_info *info, struct vm_area_struct *vma)
1856 {
1857         struct atyfb_par *par = (struct atyfb_par *) info->par;
1858         unsigned int size, page, map_size = 0;
1859         unsigned long map_offset = 0;
1860         unsigned long off;
1861         int i;
1862
1863         if (!par->mmap_map)
1864                 return -ENXIO;
1865
1866         if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1867                 return -EINVAL;
1868
1869         off = vma->vm_pgoff << PAGE_SHIFT;
1870         size = vma->vm_end - vma->vm_start;
1871
1872         /* To stop the swapper from even considering these pages. */
1873         vma->vm_flags |= (VM_IO | VM_RESERVED);
1874
1875         if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1876             ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1877                 off += 0x8000000000000000UL;
1878
1879         vma->vm_pgoff = off >> PAGE_SHIFT;      /* propagate off changes */
1880
1881         /* Each page, see which map applies */
1882         for (page = 0; page < size;) {
1883                 map_size = 0;
1884                 for (i = 0; par->mmap_map[i].size; i++) {
1885                         unsigned long start = par->mmap_map[i].voff;
1886                         unsigned long end = start + par->mmap_map[i].size;
1887                         unsigned long offset = off + page;
1888
1889                         if (start > offset)
1890                                 continue;
1891                         if (offset >= end)
1892                                 continue;
1893
1894                         map_size = par->mmap_map[i].size - (offset - start);
1895                         map_offset =
1896                             par->mmap_map[i].poff + (offset - start);
1897                         break;
1898                 }
1899                 if (!map_size) {
1900                         page += PAGE_SIZE;
1901                         continue;
1902                 }
1903                 if (page + map_size > size)
1904                         map_size = size - page;
1905
1906                 pgprot_val(vma->vm_page_prot) &=
1907                     ~(par->mmap_map[i].prot_mask);
1908                 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1909
1910                 if (remap_pfn_range(vma, vma->vm_start + page,
1911                         map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1912                         return -EAGAIN;
1913
1914                 page += map_size;
1915         }
1916
1917         if (!map_size)
1918                 return -EINVAL;
1919
1920         if (!par->mmaped)
1921                 par->mmaped = 1;
1922         return 0;
1923 }
1924
1925 static struct {
1926         u32 yoffset;
1927         u8 r[2][256];
1928         u8 g[2][256];
1929         u8 b[2][256];
1930 } atyfb_save;
1931
1932 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1933 {
1934         int i, tmp;
1935
1936         for (i = 0; i < 256; i++) {
1937                 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1938                 if (M64_HAS(EXTRA_BRIGHT))
1939                         tmp |= 0x2;
1940                 aty_st_8(DAC_CNTL, tmp, par);
1941                 aty_st_8(DAC_MASK, 0xff, par);
1942
1943                 writeb(i, &par->aty_cmap_regs->rindex);
1944                 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1945                 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1946                 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1947                 writeb(i, &par->aty_cmap_regs->windex);
1948                 writeb(atyfb_save.r[1 - enter][i],
1949                        &par->aty_cmap_regs->lut);
1950                 writeb(atyfb_save.g[1 - enter][i],
1951                        &par->aty_cmap_regs->lut);
1952                 writeb(atyfb_save.b[1 - enter][i],
1953                        &par->aty_cmap_regs->lut);
1954         }
1955 }
1956
1957 static void atyfb_palette(int enter)
1958 {
1959         struct atyfb_par *par;
1960         struct fb_info *info;
1961         int i;
1962
1963         for (i = 0; i < FB_MAX; i++) {
1964                 info = registered_fb[i];
1965                 if (info && info->fbops == &atyfb_ops) {
1966                         par = (struct atyfb_par *) info->par;
1967
1968                         atyfb_save_palette(par, enter);
1969                         if (enter) {
1970                                 atyfb_save.yoffset = info->var.yoffset;
1971                                 info->var.yoffset = 0;
1972                                 set_off_pitch(par, info);
1973                         } else {
1974                                 info->var.yoffset = atyfb_save.yoffset;
1975                                 set_off_pitch(par, info);
1976                         }
1977                         aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1978                         break;
1979                 }
1980         }
1981 }
1982 #endif /* __sparc__ */
1983
1984
1985
1986 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1987
1988 /* Power management routines. Those are used for PowerBook sleep.
1989  */
1990 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1991 {
1992         u32 pm;
1993         int timeout;
1994
1995         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1996         pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1997         aty_st_lcd(POWER_MANAGEMENT, pm, par);
1998         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1999
2000         timeout = 2000;
2001         if (sleep) {
2002                 /* Sleep */
2003                 pm &= ~PWR_MGT_ON;
2004                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2005                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2006                 udelay(10);
2007                 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2008                 pm |= SUSPEND_NOW;
2009                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2010                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2011                 udelay(10);
2012                 pm |= PWR_MGT_ON;
2013                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2014                 do {
2015                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2016                         mdelay(1);
2017                         if ((--timeout) == 0)
2018                                 break;
2019                 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2020         } else {
2021                 /* Wakeup */
2022                 pm &= ~PWR_MGT_ON;
2023                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2024                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2025                 udelay(10);
2026                 pm &= ~SUSPEND_NOW;
2027                 pm |= (PWR_BLON | AUTO_PWR_UP);
2028                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2029                 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2030                 udelay(10);
2031                 pm |= PWR_MGT_ON;
2032                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2033                 do {
2034                         pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2035                         mdelay(1);
2036                         if ((--timeout) == 0)
2037                                 break;
2038                 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2039         }
2040         mdelay(500);
2041
2042         return timeout ? 0 : -EIO;
2043 }
2044
2045 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2046 {
2047         struct fb_info *info = pci_get_drvdata(pdev);
2048         struct atyfb_par *par = (struct atyfb_par *) info->par;
2049
2050 #ifndef CONFIG_PPC_PMAC
2051         /* HACK ALERT ! Once I find a proper way to say to each driver
2052          * individually what will happen with it's PCI slot, I'll change
2053          * that. On laptops, the AGP slot is just unclocked, so D2 is
2054          * expected, while on desktops, the card is powered off
2055          */
2056         return 0;
2057 #endif /* CONFIG_PPC_PMAC */
2058
2059         if (state.event == pdev->dev.power.power_state.event)
2060                 return 0;
2061
2062         acquire_console_sem();
2063
2064         fb_set_suspend(info, 1);
2065
2066         /* Idle & reset engine */
2067         wait_for_idle(par);
2068         aty_reset_engine(par);
2069
2070         /* Blank display and LCD */
2071         atyfb_blank(FB_BLANK_POWERDOWN, info);
2072
2073         par->asleep = 1;
2074         par->lock_blank = 1;
2075
2076         /* Set chip to "suspend" mode */
2077         if (aty_power_mgmt(1, par)) {
2078                 par->asleep = 0;
2079                 par->lock_blank = 0;
2080                 atyfb_blank(FB_BLANK_UNBLANK, info);
2081                 fb_set_suspend(info, 0);
2082                 release_console_sem();
2083                 return -EIO;
2084         }
2085
2086         release_console_sem();
2087
2088         pdev->dev.power.power_state = state;
2089
2090         return 0;
2091 }
2092
2093 static int atyfb_pci_resume(struct pci_dev *pdev)
2094 {
2095         struct fb_info *info = pci_get_drvdata(pdev);
2096         struct atyfb_par *par = (struct atyfb_par *) info->par;
2097
2098         if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2099                 return 0;
2100
2101         acquire_console_sem();
2102
2103         if (pdev->dev.power.power_state.event == 2)
2104                 aty_power_mgmt(0, par);
2105         par->asleep = 0;
2106
2107         /* Restore display */
2108         atyfb_set_par(info);
2109
2110         /* Refresh */
2111         fb_set_suspend(info, 0);
2112
2113         /* Unblank */
2114         par->lock_blank = 0;
2115         atyfb_blank(FB_BLANK_UNBLANK, info);
2116
2117         release_console_sem();
2118
2119         pdev->dev.power.power_state = PMSG_ON;
2120
2121         return 0;
2122 }
2123
2124 #endif /*  defined(CONFIG_PM) && defined(CONFIG_PCI) */
2125
2126 /* Backlight */
2127 #ifdef CONFIG_FB_ATY_BACKLIGHT
2128 #define MAX_LEVEL 0xFF
2129
2130 static struct backlight_properties aty_bl_data;
2131
2132 static int aty_bl_get_level_brightness(struct atyfb_par *par, int level)
2133 {
2134         struct fb_info *info = pci_get_drvdata(par->pdev);
2135         int atylevel;
2136
2137         /* Get and convert the value */
2138         mutex_lock(&info->bl_mutex);
2139         atylevel = info->bl_curve[level] * FB_BACKLIGHT_MAX / MAX_LEVEL;
2140         mutex_unlock(&info->bl_mutex);
2141
2142         if (atylevel < 0)
2143                 atylevel = 0;
2144         else if (atylevel > MAX_LEVEL)
2145                 atylevel = MAX_LEVEL;
2146
2147         return atylevel;
2148 }
2149
2150 static int aty_bl_update_status(struct backlight_device *bd)
2151 {
2152         struct atyfb_par *par = class_get_devdata(&bd->class_dev);
2153         unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2154         int level;
2155
2156         if (bd->props->power != FB_BLANK_UNBLANK ||
2157             bd->props->fb_blank != FB_BLANK_UNBLANK)
2158                 level = 0;
2159         else
2160                 level = bd->props->brightness;
2161
2162         reg |= (BLMOD_EN | BIASMOD_EN);
2163         if (level > 0) {
2164                 reg &= ~BIAS_MOD_LEVEL_MASK;
2165                 reg |= (aty_bl_get_level_brightness(par, level) << BIAS_MOD_LEVEL_SHIFT);
2166         } else {
2167                 reg &= ~BIAS_MOD_LEVEL_MASK;
2168                 reg |= (aty_bl_get_level_brightness(par, 0) << BIAS_MOD_LEVEL_SHIFT);
2169         }
2170         aty_st_lcd(LCD_MISC_CNTL, reg, par);
2171
2172         return 0;
2173 }
2174
2175 static int aty_bl_get_brightness(struct backlight_device *bd)
2176 {
2177         return bd->props->brightness;
2178 }
2179
2180 static struct backlight_properties aty_bl_data = {
2181         .owner    = THIS_MODULE,
2182         .get_brightness = aty_bl_get_brightness,
2183         .update_status  = aty_bl_update_status,
2184         .max_brightness = (FB_BACKLIGHT_LEVELS - 1),
2185 };
2186
2187 static void aty_bl_init(struct atyfb_par *par)
2188 {
2189         struct fb_info *info = pci_get_drvdata(par->pdev);
2190         struct backlight_device *bd;
2191         char name[12];
2192
2193 #ifdef CONFIG_PMAC_BACKLIGHT
2194         if (!pmac_has_backlight_type("ati"))
2195                 return;
2196 #endif
2197
2198         snprintf(name, sizeof(name), "atybl%d", info->node);
2199
2200         bd = backlight_device_register(name, par, &aty_bl_data);
2201         if (IS_ERR(bd)) {
2202                 info->bl_dev = NULL;
2203                 printk("aty: Backlight registration failed\n");
2204                 goto error;
2205         }
2206
2207         mutex_lock(&info->bl_mutex);
2208         info->bl_dev = bd;
2209         fb_bl_default_curve(info, 0,
2210                 0x3F * FB_BACKLIGHT_MAX / MAX_LEVEL,
2211                 0xFF * FB_BACKLIGHT_MAX / MAX_LEVEL);
2212         mutex_unlock(&info->bl_mutex);
2213
2214         up(&bd->sem);
2215         bd->props->brightness = aty_bl_data.max_brightness;
2216         bd->props->power = FB_BLANK_UNBLANK;
2217         bd->props->update_status(bd);
2218         down(&bd->sem);
2219
2220 #ifdef CONFIG_PMAC_BACKLIGHT
2221         mutex_lock(&pmac_backlight_mutex);
2222         if (!pmac_backlight)
2223                 pmac_backlight = bd;
2224         mutex_unlock(&pmac_backlight_mutex);
2225 #endif
2226
2227         printk("aty: Backlight initialized (%s)\n", name);
2228
2229         return;
2230
2231 error:
2232         return;
2233 }
2234
2235 static void aty_bl_exit(struct atyfb_par *par)
2236 {
2237         struct fb_info *info = pci_get_drvdata(par->pdev);
2238
2239 #ifdef CONFIG_PMAC_BACKLIGHT
2240         mutex_lock(&pmac_backlight_mutex);
2241 #endif
2242
2243         mutex_lock(&info->bl_mutex);
2244         if (info->bl_dev) {
2245 #ifdef CONFIG_PMAC_BACKLIGHT
2246                 if (pmac_backlight == info->bl_dev)
2247                         pmac_backlight = NULL;
2248 #endif
2249
2250                 backlight_device_unregister(info->bl_dev);
2251
2252                 printk("aty: Backlight unloaded\n");
2253         }
2254         mutex_unlock(&info->bl_mutex);
2255
2256 #ifdef CONFIG_PMAC_BACKLIGHT
2257         mutex_unlock(&pmac_backlight_mutex);
2258 #endif
2259 }
2260
2261 #endif /* CONFIG_FB_ATY_BACKLIGHT */
2262
2263 static void __devinit aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2264 {
2265         const int ragepro_tbl[] = {
2266                 44, 50, 55, 66, 75, 80, 100
2267         };
2268         const int ragexl_tbl[] = {
2269                 50, 66, 75, 83, 90, 95, 100, 105,
2270                 110, 115, 120, 125, 133, 143, 166
2271         };
2272         const int *refresh_tbl;
2273         int i, size;
2274
2275         if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2276                 refresh_tbl = ragexl_tbl;
2277                 size = ARRAY_SIZE(ragexl_tbl);
2278         } else {
2279                 refresh_tbl = ragepro_tbl;
2280                 size = ARRAY_SIZE(ragepro_tbl);
2281         }
2282
2283         for (i=0; i < size; i++) {
2284                 if (xclk < refresh_tbl[i])
2285                 break;
2286         }
2287         par->mem_refresh_rate = i;
2288 }
2289
2290     /*
2291      *  Initialisation
2292      */
2293
2294 static struct fb_info *fb_list = NULL;
2295
2296 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2297 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2298                                                 struct fb_var_screeninfo *var)
2299 {
2300         int ret = -EINVAL;
2301
2302         if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2303                 *var = default_var;
2304                 var->xres = var->xres_virtual = par->lcd_hdisp;
2305                 var->right_margin = par->lcd_right_margin;
2306                 var->left_margin = par->lcd_hblank_len -
2307                         (par->lcd_right_margin + par->lcd_hsync_dly +
2308                          par->lcd_hsync_len);
2309                 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2310                 var->yres = var->yres_virtual = par->lcd_vdisp;
2311                 var->lower_margin = par->lcd_lower_margin;
2312                 var->upper_margin = par->lcd_vblank_len -
2313                         (par->lcd_lower_margin + par->lcd_vsync_len);
2314                 var->vsync_len = par->lcd_vsync_len;
2315                 var->pixclock = par->lcd_pixclock;
2316                 ret = 0;
2317         }
2318
2319         return ret;
2320 }
2321 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2322
2323 static int __devinit aty_init(struct fb_info *info, const char *name)
2324 {
2325         struct atyfb_par *par = (struct atyfb_par *) info->par;
2326         const char *ramname = NULL, *xtal;
2327         int gtb_memsize, has_var = 0;
2328         struct fb_var_screeninfo var;
2329         u8 pll_ref_div;
2330         u32 i;
2331 #if defined(CONFIG_PPC)
2332         int sense;
2333 #endif
2334
2335         init_waitqueue_head(&par->vblank.wait);
2336         spin_lock_init(&par->int_lock);
2337
2338         par->aty_cmap_regs =
2339             (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2340
2341 #ifdef CONFIG_PPC_PMAC
2342         /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2343          * and set the frequency manually. */
2344         if (machine_is_compatible("PowerBook2,1")) {
2345                 par->pll_limits.mclk = 70;
2346                 par->pll_limits.xclk = 53;
2347         }
2348 #endif
2349         if (pll)
2350                 par->pll_limits.pll_max = pll;
2351         if (mclk)
2352                 par->pll_limits.mclk = mclk;
2353         if (xclk)
2354                 par->pll_limits.xclk = xclk;
2355
2356         aty_calc_mem_refresh(par, par->pll_limits.xclk);
2357         par->pll_per = 1000000/par->pll_limits.pll_max;
2358         par->mclk_per = 1000000/par->pll_limits.mclk;
2359         par->xclk_per = 1000000/par->pll_limits.xclk;
2360
2361         par->ref_clk_per = 1000000000000ULL / 14318180;
2362         xtal = "14.31818";
2363
2364 #ifdef CONFIG_FB_ATY_GX
2365         if (!M64_HAS(INTEGRATED)) {
2366                 u32 stat0;
2367                 u8 dac_type, dac_subtype, clk_type;
2368                 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2369                 par->bus_type = (stat0 >> 0) & 0x07;
2370                 par->ram_type = (stat0 >> 3) & 0x07;
2371                 ramname = aty_gx_ram[par->ram_type];
2372                 /* FIXME: clockchip/RAMDAC probing? */
2373                 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2374 #ifdef CONFIG_ATARI
2375                 clk_type = CLK_ATI18818_1;
2376                 dac_type = (stat0 >> 9) & 0x07;
2377                 if (dac_type == 0x07)
2378                         dac_subtype = DAC_ATT20C408;
2379                 else
2380                         dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2381 #else
2382                 dac_type = DAC_IBMRGB514;
2383                 dac_subtype = DAC_IBMRGB514;
2384                 clk_type = CLK_IBMRGB514;
2385 #endif
2386                 switch (dac_subtype) {
2387                 case DAC_IBMRGB514:
2388                         par->dac_ops = &aty_dac_ibm514;
2389                         break;
2390                 case DAC_ATI68860_B:
2391                 case DAC_ATI68860_C:
2392                         par->dac_ops = &aty_dac_ati68860b;
2393                         break;
2394                 case DAC_ATT20C408:
2395                 case DAC_ATT21C498:
2396                         par->dac_ops = &aty_dac_att21c498;
2397                         break;
2398                 default:
2399                         PRINTKI("aty_init: DAC type not implemented yet!\n");
2400                         par->dac_ops = &aty_dac_unsupported;
2401                         break;
2402                 }
2403                 switch (clk_type) {
2404 #ifdef CONFIG_ATARI
2405                 case CLK_ATI18818_1:
2406                         par->pll_ops = &aty_pll_ati18818_1;
2407                         break;
2408 #else
2409                 case CLK_IBMRGB514:
2410                         par->pll_ops = &aty_pll_ibm514;
2411                         break;
2412 #endif
2413 #if 0 /* dead code */
2414                 case CLK_STG1703:
2415                         par->pll_ops = &aty_pll_stg1703;
2416                         break;
2417                 case CLK_CH8398:
2418                         par->pll_ops = &aty_pll_ch8398;
2419                         break;
2420                 case CLK_ATT20C408:
2421                         par->pll_ops = &aty_pll_att20c408;
2422                         break;
2423 #endif
2424                 default:
2425                         PRINTKI("aty_init: CLK type not implemented yet!");
2426                         par->pll_ops = &aty_pll_unsupported;
2427                         break;
2428                 }
2429         }
2430 #endif /* CONFIG_FB_ATY_GX */
2431 #ifdef CONFIG_FB_ATY_CT
2432         if (M64_HAS(INTEGRATED)) {
2433                 par->dac_ops = &aty_dac_ct;
2434                 par->pll_ops = &aty_pll_ct;
2435                 par->bus_type = PCI;
2436                 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2437                 ramname = aty_ct_ram[par->ram_type];
2438                 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2439                 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2440                         par->pll_limits.mclk = 63;
2441         }
2442
2443         if (M64_HAS(GTB_DSP)
2444             && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2445                 int diff1, diff2;
2446                 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2447                 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2448                 if (diff1 < 0)
2449                         diff1 = -diff1;
2450                 if (diff2 < 0)
2451                         diff2 = -diff2;
2452                 if (diff2 < diff1) {
2453                         par->ref_clk_per = 1000000000000ULL / 29498928;
2454                         xtal = "29.498928";
2455                 }
2456         }
2457 #endif /* CONFIG_FB_ATY_CT */
2458
2459         /* save previous video mode */
2460         aty_get_crtc(par, &saved_crtc);
2461         if(par->pll_ops->get_pll)
2462                 par->pll_ops->get_pll(info, &saved_pll);
2463
2464         i = aty_ld_le32(MEM_CNTL, par);
2465         gtb_memsize = M64_HAS(GTB_DSP);
2466         if (gtb_memsize)
2467                 switch (i & 0xF) {      /* 0xF used instead of MEM_SIZE_ALIAS */
2468                 case MEM_SIZE_512K:
2469                         info->fix.smem_len = 0x80000;
2470                         break;
2471                 case MEM_SIZE_1M:
2472                         info->fix.smem_len = 0x100000;
2473                         break;
2474                 case MEM_SIZE_2M_GTB:
2475                         info->fix.smem_len = 0x200000;
2476                         break;
2477                 case MEM_SIZE_4M_GTB:
2478                         info->fix.smem_len = 0x400000;
2479                         break;
2480                 case MEM_SIZE_6M_GTB:
2481                         info->fix.smem_len = 0x600000;
2482                         break;
2483                 case MEM_SIZE_8M_GTB:
2484                         info->fix.smem_len = 0x800000;
2485                         break;
2486                 default:
2487                         info->fix.smem_len = 0x80000;
2488         } else
2489                 switch (i & MEM_SIZE_ALIAS) {
2490                 case MEM_SIZE_512K:
2491                         info->fix.smem_len = 0x80000;
2492                         break;
2493                 case MEM_SIZE_1M:
2494                         info->fix.smem_len = 0x100000;
2495                         break;
2496                 case MEM_SIZE_2M:
2497                         info->fix.smem_len = 0x200000;
2498                         break;
2499                 case MEM_SIZE_4M:
2500                         info->fix.smem_len = 0x400000;
2501                         break;
2502                 case MEM_SIZE_6M:
2503                         info->fix.smem_len = 0x600000;
2504                         break;
2505                 case MEM_SIZE_8M:
2506                         info->fix.smem_len = 0x800000;
2507                         break;
2508                 default:
2509                         info->fix.smem_len = 0x80000;
2510                 }
2511
2512         if (M64_HAS(MAGIC_VRAM_SIZE)) {
2513                 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2514                         info->fix.smem_len += 0x400000;
2515         }
2516
2517         if (vram) {
2518                 info->fix.smem_len = vram * 1024;
2519                 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2520                 if (info->fix.smem_len <= 0x80000)
2521                         i |= MEM_SIZE_512K;
2522                 else if (info->fix.smem_len <= 0x100000)
2523                         i |= MEM_SIZE_1M;
2524                 else if (info->fix.smem_len <= 0x200000)
2525                         i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2526                 else if (info->fix.smem_len <= 0x400000)
2527                         i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2528                 else if (info->fix.smem_len <= 0x600000)
2529                         i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2530                 else
2531                         i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2532                 aty_st_le32(MEM_CNTL, i, par);
2533         }
2534
2535         /*
2536          *  Reg Block 0 (CT-compatible block) is at mmio_start
2537          *  Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2538          */
2539         if (M64_HAS(GX)) {
2540                 info->fix.mmio_len = 0x400;
2541                 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2542         } else if (M64_HAS(CT)) {
2543                 info->fix.mmio_len = 0x400;
2544                 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2545         } else if (M64_HAS(VT)) {
2546                 info->fix.mmio_start -= 0x400;
2547                 info->fix.mmio_len = 0x800;
2548                 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2549         } else {/* GT */
2550                 info->fix.mmio_start -= 0x400;
2551                 info->fix.mmio_len = 0x800;
2552                 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2553         }
2554
2555         PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2556                info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2557                info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2558                par->pll_limits.mclk, par->pll_limits.xclk);
2559
2560 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2561         if (M64_HAS(INTEGRATED)) {
2562                 int i;
2563                 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2564                        "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2565                        "debug atyfb: %08x %08x %08x %08x     %08x      %08x   %08x   %08x\n"
2566                        "debug atyfb: PLL",
2567                         aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2568                         aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2569                         aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2570                         aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2571                 for (i = 0; i < 40; i++)
2572                         printk(" %02x", aty_ld_pll_ct(i, par));
2573                 printk("\n");
2574         }
2575 #endif
2576         if(par->pll_ops->init_pll)
2577                 par->pll_ops->init_pll(info, &par->pll);
2578
2579         /*
2580          *  Last page of 8 MB (4 MB on ISA) aperture is MMIO
2581          *  FIXME: we should use the auxiliary aperture instead so we can access
2582          *  the full 8 MB of video RAM on 8 MB boards
2583          */
2584
2585         if (!par->aux_start &&
2586                 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2587                 info->fix.smem_len -= GUI_RESERVE;
2588
2589         /*
2590          *  Disable register access through the linear aperture
2591          *  if the auxiliary aperture is used so we can access
2592          *  the full 8 MB of video RAM on 8 MB boards.
2593          */
2594         if (par->aux_start)
2595                 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2596
2597 #ifdef CONFIG_MTRR
2598         par->mtrr_aper = -1;
2599         par->mtrr_reg = -1;
2600         if (!nomtrr) {
2601                 /* Cover the whole resource. */
2602                  par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2603                  if (par->mtrr_aper >= 0 && !par->aux_start) {
2604                         /* Make a hole for mmio. */
2605                         par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2606                                 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2607                         if (par->mtrr_reg < 0) {
2608                                 mtrr_del(par->mtrr_aper, 0, 0);
2609                                 par->mtrr_aper = -1;
2610                         }
2611                  }
2612         }
2613 #endif
2614
2615         info->fbops = &atyfb_ops;
2616         info->pseudo_palette = pseudo_palette;
2617         info->flags = FBINFO_DEFAULT           |
2618                       FBINFO_HWACCEL_IMAGEBLIT |
2619                       FBINFO_HWACCEL_FILLRECT  |
2620                       FBINFO_HWACCEL_COPYAREA  |
2621                       FBINFO_HWACCEL_YPAN;
2622
2623 #ifdef CONFIG_PMAC_BACKLIGHT
2624         if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2625                 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2626                 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2627                            | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2628         } else
2629 #endif
2630         if (M64_HAS(MOBIL_BUS)) {
2631 #ifdef CONFIG_FB_ATY_BACKLIGHT
2632                 aty_bl_init (par);
2633 #endif
2634         }
2635
2636         memset(&var, 0, sizeof(var));
2637 #ifdef CONFIG_PPC
2638         if (machine_is(powermac)) {
2639                 /*
2640                  *  FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2641                  *         applies to all Mac video cards
2642                  */
2643                 if (mode) {
2644                         if (mac_find_mode(&var, info, mode, 8))
2645                                 has_var = 1;
2646                 } else {
2647                         if (default_vmode == VMODE_CHOOSE) {
2648                                 if (M64_HAS(G3_PB_1024x768))
2649                                         /* G3 PowerBook with 1024x768 LCD */
2650                                         default_vmode = VMODE_1024_768_60;
2651                                 else if (machine_is_compatible("iMac"))
2652                                         default_vmode = VMODE_1024_768_75;
2653                                 else if (machine_is_compatible
2654                                          ("PowerBook2,1"))
2655                                         /* iBook with 800x600 LCD */
2656                                         default_vmode = VMODE_800_600_60;
2657                                 else
2658                                         default_vmode = VMODE_640_480_67;
2659                                 sense = read_aty_sense(par);
2660                                 PRINTKI("monitor sense=%x, mode %d\n",
2661                                         sense,  mac_map_monitor_sense(sense));
2662                         }
2663                         if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2664                                 default_vmode = VMODE_640_480_60;
2665                         if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2666                                 default_cmode = CMODE_8;
2667                         if (!mac_vmode_to_var(default_vmode, default_cmode,
2668                                                &var))
2669                                 has_var = 1;
2670                 }
2671         }
2672
2673 #endif /* !CONFIG_PPC */
2674
2675 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2676         if (!atyfb_get_timings_from_lcd(par, &var))
2677                 has_var = 1;
2678 #endif
2679
2680         if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2681                 has_var = 1;
2682
2683         if (!has_var)
2684                 var = default_var;
2685
2686         if (noaccel)
2687                 var.accel_flags &= ~FB_ACCELF_TEXT;
2688         else
2689                 var.accel_flags |= FB_ACCELF_TEXT;
2690
2691         if (comp_sync != -1) {
2692                 if (!comp_sync)
2693                         var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2694                 else
2695                         var.sync |= FB_SYNC_COMP_HIGH_ACT;
2696         }
2697
2698         if (var.yres == var.yres_virtual) {
2699                 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2700                 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2701                 if (var.yres_virtual < var.yres)
2702                         var.yres_virtual = var.yres;
2703         }
2704
2705         if (atyfb_check_var(&var, info)) {
2706                 PRINTKE("can't set default video mode\n");
2707                 goto aty_init_exit;
2708         }
2709
2710 #ifdef __sparc__
2711         atyfb_save_palette(par, 0);
2712 #endif
2713
2714 #ifdef CONFIG_FB_ATY_CT
2715         if (!noaccel && M64_HAS(INTEGRATED))
2716                 aty_init_cursor(info);
2717 #endif /* CONFIG_FB_ATY_CT */
2718         info->var = var;
2719
2720         fb_alloc_cmap(&info->cmap, 256, 0);
2721
2722         if (register_framebuffer(info) < 0)
2723                 goto aty_init_exit;
2724
2725         fb_list = info;
2726
2727         PRINTKI("fb%d: %s frame buffer device on %s\n",
2728                info->node, info->fix.id, name);
2729         return 0;
2730
2731 aty_init_exit:
2732         /* restore video mode */
2733         aty_set_crtc(par, &saved_crtc);
2734         par->pll_ops->set_pll(info, &saved_pll);
2735
2736 #ifdef CONFIG_MTRR
2737         if (par->mtrr_reg >= 0) {
2738             mtrr_del(par->mtrr_reg, 0, 0);
2739             par->mtrr_reg = -1;
2740         }
2741         if (par->mtrr_aper >= 0) {
2742             mtrr_del(par->mtrr_aper, 0, 0);
2743             par->mtrr_aper = -1;
2744         }
2745 #endif
2746         return -1;
2747 }
2748
2749 #ifdef CONFIG_ATARI
2750 static int __devinit store_video_par(char *video_str, unsigned char m64_num)
2751 {
2752         char *p;
2753         unsigned long vmembase, size, guiregbase;
2754
2755         PRINTKI("store_video_par() '%s' \n", video_str);
2756
2757         if (!(p = strsep(&video_str, ";")) || !*p)
2758                 goto mach64_invalid;
2759         vmembase = simple_strtoul(p, NULL, 0);
2760         if (!(p = strsep(&video_str, ";")) || !*p)
2761                 goto mach64_invalid;
2762         size = simple_strtoul(p, NULL, 0);
2763         if (!(p = strsep(&video_str, ";")) || !*p)
2764                 goto mach64_invalid;
2765         guiregbase = simple_strtoul(p, NULL, 0);
2766
2767         phys_vmembase[m64_num] = vmembase;
2768         phys_size[m64_num] = size;
2769         phys_guiregbase[m64_num] = guiregbase;
2770         PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2771                guiregbase);
2772         return 0;
2773
2774       mach64_invalid:
2775         phys_vmembase[m64_num] = 0;
2776         return -1;
2777 }
2778 #endif /* CONFIG_ATARI */
2779
2780     /*
2781      *  Blank the display.
2782      */
2783
2784 static int atyfb_blank(int blank, struct fb_info *info)
2785 {
2786         struct atyfb_par *par = (struct atyfb_par *) info->par;
2787         u32 gen_cntl;
2788
2789         if (par->lock_blank || par->asleep)
2790                 return 0;
2791
2792 #ifdef CONFIG_PMAC_BACKLIGHT
2793         if (machine_is(powermac) && blank > FB_BLANK_NORMAL) {
2794                 mutex_lock(&info->bl_mutex);
2795                 if (info->bl_dev) {
2796                         down(&info->bl_dev->sem);
2797                         info->bl_dev->props->power = FB_BLANK_POWERDOWN;
2798                         info->bl_dev->props->update_status(info->bl_dev);
2799                         up(&info->bl_dev->sem);
2800                 }
2801                 mutex_unlock(&info->bl_mutex);
2802         }
2803 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2804         if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2805             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2806                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2807                 pm &= ~PWR_BLON;
2808                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2809         }
2810 #endif
2811
2812         gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2813         switch (blank) {
2814                 case FB_BLANK_UNBLANK:
2815                         gen_cntl &= ~0x400004c;
2816                         break;
2817                 case FB_BLANK_NORMAL:
2818                         gen_cntl |= 0x4000040;
2819                         break;
2820                 case FB_BLANK_VSYNC_SUSPEND:
2821                         gen_cntl |= 0x4000048;
2822                         break;
2823                 case FB_BLANK_HSYNC_SUSPEND:
2824                         gen_cntl |= 0x4000044;
2825                         break;
2826                 case FB_BLANK_POWERDOWN:
2827                         gen_cntl |= 0x400004c;
2828                         break;
2829         }
2830         aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2831
2832 #ifdef CONFIG_PMAC_BACKLIGHT
2833         if (machine_is(powermac) && blank <= FB_BLANK_NORMAL) {
2834                 mutex_lock(&info->bl_mutex);
2835                 if (info->bl_dev) {
2836                         down(&info->bl_dev->sem);
2837                         info->bl_dev->props->power = FB_BLANK_UNBLANK;
2838                         info->bl_dev->props->update_status(info->bl_dev);
2839                         up(&info->bl_dev->sem);
2840                 }
2841                 mutex_unlock(&info->bl_mutex);
2842         }
2843 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2844         if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2845             (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2846                 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2847                 pm |= PWR_BLON;
2848                 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2849         }
2850 #endif
2851
2852         return 0;
2853 }
2854
2855 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2856                        const struct atyfb_par *par)
2857 {
2858 #ifdef CONFIG_ATARI
2859         out_8(&par->aty_cmap_regs->windex, regno);
2860         out_8(&par->aty_cmap_regs->lut, red);
2861         out_8(&par->aty_cmap_regs->lut, green);
2862         out_8(&par->aty_cmap_regs->lut, blue);
2863 #else
2864         writeb(regno, &par->aty_cmap_regs->windex);
2865         writeb(red, &par->aty_cmap_regs->lut);
2866         writeb(green, &par->aty_cmap_regs->lut);
2867         writeb(blue, &par->aty_cmap_regs->lut);
2868 #endif
2869 }
2870
2871     /*
2872      *  Set a single color register. The values supplied are already
2873      *  rounded down to the hardware's capabilities (according to the
2874      *  entries in the var structure). Return != 0 for invalid regno.
2875      *  !! 4 & 8 =  PSEUDO, > 8 = DIRECTCOLOR
2876      */
2877
2878 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2879         u_int transp, struct fb_info *info)
2880 {
2881         struct atyfb_par *par = (struct atyfb_par *) info->par;
2882         int i, depth;
2883         u32 *pal = info->pseudo_palette;
2884
2885         depth = info->var.bits_per_pixel;
2886         if (depth == 16)
2887                 depth = (info->var.green.length == 5) ? 15 : 16;
2888
2889         if (par->asleep)
2890                 return 0;
2891
2892         if (regno > 255 ||
2893             (depth == 16 && regno > 63) ||
2894             (depth == 15 && regno > 31))
2895                 return 1;
2896
2897         red >>= 8;
2898         green >>= 8;
2899         blue >>= 8;
2900
2901         par->palette[regno].red = red;
2902         par->palette[regno].green = green;
2903         par->palette[regno].blue = blue;
2904
2905         if (regno < 16) {
2906                 switch (depth) {
2907                 case 15:
2908                         pal[regno] = (regno << 10) | (regno << 5) | regno;
2909                         break;
2910                 case 16:
2911                         pal[regno] = (regno << 11) | (regno << 5) | regno;
2912                         break;
2913                 case 24:
2914                         pal[regno] = (regno << 16) | (regno << 8) | regno;
2915                         break;
2916                 case 32:
2917                         i = (regno << 8) | regno;
2918                         pal[regno] = (i << 16) | i;
2919                         break;
2920                 }
2921         }
2922
2923         i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2924         if (M64_HAS(EXTRA_BRIGHT))
2925                 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2926         aty_st_8(DAC_CNTL, i, par);
2927         aty_st_8(DAC_MASK, 0xff, par);
2928
2929         if (M64_HAS(INTEGRATED)) {
2930                 if (depth == 16) {
2931                         if (regno < 32)
2932                                 aty_st_pal(regno << 3, red,
2933                                            par->palette[regno<<1].green,
2934                                            blue, par);
2935                         red = par->palette[regno>>1].red;
2936                         blue = par->palette[regno>>1].blue;
2937                         regno <<= 2;
2938                 } else if (depth == 15) {
2939                         regno <<= 3;
2940                         for(i = 0; i < 8; i++) {
2941                             aty_st_pal(regno + i, red, green, blue, par);
2942                         }
2943                 }
2944         }
2945         aty_st_pal(regno, red, green, blue, par);
2946
2947         return 0;
2948 }
2949
2950 #ifdef CONFIG_PCI
2951
2952 #ifdef __sparc__
2953
2954 extern void (*prom_palette) (int);
2955
2956 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2957                         struct fb_info *info, unsigned long addr)
2958 {
2959         extern int con_is_present(void);
2960
2961         struct atyfb_par *par = info->par;
2962         struct pcidev_cookie *pcp;
2963         char prop[128];
2964         int node, len, i, j, ret;
2965         u32 mem, chip_id;
2966
2967         /* Do not attach when we have a serial console. */
2968         if (!con_is_present())
2969                 return -ENXIO;
2970
2971         /*
2972          * Map memory-mapped registers.
2973          */
2974         par->ati_regbase = (void *)addr + 0x7ffc00UL;
2975         info->fix.mmio_start = addr + 0x7ffc00UL;
2976
2977         /*
2978          * Map in big-endian aperture.
2979          */
2980         info->screen_base = (char *) (addr + 0x800000UL);
2981         info->fix.smem_start = addr + 0x800000UL;
2982
2983         /*
2984          * Figure mmap addresses from PCI config space.
2985          * Split Framebuffer in big- and little-endian halfs.
2986          */
2987         for (i = 0; i < 6 && pdev->resource[i].start; i++)
2988                 /* nothing */ ;
2989         j = i + 4;
2990
2991         par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2992         if (!par->mmap_map) {
2993                 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2994                 return -ENOMEM;
2995         }
2996         memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2997
2998         for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2999                 struct resource *rp = &pdev->resource[i];
3000                 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
3001                 unsigned long base;
3002                 u32 size, pbase;
3003
3004                 base = rp->start;
3005
3006                 io = (rp->flags & IORESOURCE_IO);
3007
3008                 size = rp->end - base + 1;
3009
3010                 pci_read_config_dword(pdev, breg, &pbase);
3011
3012                 if (io)
3013                         size &= ~1;
3014
3015                 /*
3016                  * Map the framebuffer a second time, this time without
3017                  * the braindead _PAGE_IE setting. This is used by the
3018                  * fixed Xserver, but we need to maintain the old mapping
3019                  * to stay compatible with older ones...
3020                  */
3021                 if (base == addr) {
3022                         par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
3023                         par->mmap_map[j].poff = base & PAGE_MASK;
3024                         par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3025                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3026                         par->mmap_map[j].prot_flag = _PAGE_E;
3027                         j++;
3028                 }
3029
3030                 /*
3031                  * Here comes the old framebuffer mapping with _PAGE_IE
3032                  * set for the big endian half of the framebuffer...
3033                  */
3034                 if (base == addr) {
3035                         par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
3036                         par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
3037                         par->mmap_map[j].size = 0x800000;
3038                         par->mmap_map[j].prot_mask = _PAGE_CACHE;
3039                         par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
3040                         size -= 0x800000;
3041                         j++;
3042                 }
3043
3044                 par->mmap_map[j].voff = pbase & PAGE_MASK;
3045                 par->mmap_map[j].poff = base & PAGE_MASK;
3046                 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
3047                 par->mmap_map[j].prot_mask = _PAGE_CACHE;
3048                 par->mmap_map[j].prot_flag = _PAGE_E;
3049                 j++;
3050         }
3051
3052         if((ret = correct_chipset(par)))
3053                 return ret;
3054
3055         if (IS_XL(pdev->device)) {
3056                 /*
3057                  * Fix PROMs idea of MEM_CNTL settings...
3058                  */
3059                 mem = aty_ld_le32(MEM_CNTL, par);
3060                 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
3061                 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
3062                         switch (mem & 0x0f) {
3063                         case 3:
3064                                 mem = (mem & ~(0x0f)) | 2;
3065                                 break;
3066                         case 7:
3067                                 mem = (mem & ~(0x0f)) | 3;
3068                                 break;
3069                         case 9:
3070                                 mem = (mem & ~(0x0f)) | 4;
3071                                 break;
3072                         case 11:
3073                                 mem = (mem & ~(0x0f)) | 5;
3074                                 break;
3075                         default:
3076                                 break;
3077                         }
3078                         if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
3079                                 mem &= ~(0x00700000);
3080                 }
3081                 mem &= ~(0xcf80e000);   /* Turn off all undocumented bits. */
3082                 aty_st_le32(MEM_CNTL, mem, par);
3083         }
3084
3085         /*
3086          * If this is the console device, we will set default video
3087          * settings to what the PROM left us with.
3088          */
3089         node = prom_getchild(prom_root_node);
3090         node = prom_searchsiblings(node, "aliases");
3091         if (node) {
3092                 len = prom_getproperty(node, "screen", prop, sizeof(prop));
3093                 if (len > 0) {
3094                         prop[len] = '\0';
3095                         node = prom_finddevice(prop);
3096                 } else
3097                         node = 0;
3098         }
3099
3100         pcp = pdev->sysdata;
3101         if (node == pcp->prom_node->node) {
3102                 struct fb_var_screeninfo *var = &default_var;
3103                 unsigned int N, P, Q, M, T, R;
3104                 u32 v_total, h_total;
3105                 struct crtc crtc;
3106                 u8 pll_regs[16];
3107                 u8 clock_cntl;
3108
3109                 crtc.vxres = prom_getintdefault(node, "width", 1024);
3110                 crtc.vyres = prom_getintdefault(node, "height", 768);
3111                 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
3112                 var->xoffset = var->yoffset = 0;
3113                 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
3114                 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
3115                 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
3116                 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
3117                 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
3118                 aty_crtc_to_var(&crtc, var);
3119
3120                 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
3121                 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
3122
3123                 /*
3124                  * Read the PLL to figure actual Refresh Rate.
3125                  */
3126                 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
3127                 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
3128                 for (i = 0; i < 16; i++)
3129                         pll_regs[i] = aty_ld_pll_ct(i, par);
3130
3131                 /*
3132                  * PLL Reference Divider M:
3133                  */
3134                 M = pll_regs[2];
3135
3136                 /*
3137                  * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3138                  */
3139                 N = pll_regs[7 + (clock_cntl & 3)];
3140
3141                 /*
3142                  * PLL Post Divider P (Dependant on CLOCK_CNTL):
3143                  */
3144                 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3145
3146                 /*
3147                  * PLL Divider Q:
3148                  */
3149                 Q = N / P;
3150
3151                 /*
3152                  * Target Frequency:
3153                  *
3154                  *      T * M
3155                  * Q = -------
3156                  *      2 * R
3157                  *
3158                  * where R is XTALIN (= 14318 or 29498 kHz).
3159                  */
3160                 if (IS_XL(pdev->device))
3161                         R = 29498;
3162                 else
3163                         R = 14318;
3164
3165                 T = 2 * Q * R / M;
3166
3167                 default_var.pixclock = 1000000000 / T;
3168         }
3169
3170         return 0;
3171 }
3172
3173 #else /* __sparc__ */
3174
3175 #ifdef __i386__
3176 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3177 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3178 {
3179         u32 driv_inf_tab, sig;
3180         u16 lcd_ofs;
3181
3182         /* To support an LCD panel, we should know it's dimensions and
3183          *  it's desired pixel clock.
3184          * There are two ways to do it:
3185          *  - Check the startup video mode and calculate the panel
3186          *    size from it. This is unreliable.
3187          *  - Read it from the driver information table in the video BIOS.
3188         */
3189         /* Address of driver information table is at offset 0x78. */
3190         driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3191
3192         /* Check for the driver information table signature. */
3193         sig = (*(u32 *)driv_inf_tab);
3194         if ((sig == 0x54504c24) || /* Rage LT pro */
3195                 (sig == 0x544d5224) || /* Rage mobility */
3196                 (sig == 0x54435824) || /* Rage XC */
3197                 (sig == 0x544c5824)) { /* Rage XL */
3198                 PRINTKI("BIOS contains driver information table.\n");
3199                 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3200                 par->lcd_table = 0;
3201                 if (lcd_ofs != 0) {
3202                         par->lcd_table = bios_base + lcd_ofs;
3203                 }
3204         }
3205
3206         if (par->lcd_table != 0) {
3207                 char model[24];
3208                 char strbuf[16];
3209                 char refresh_rates_buf[100];
3210                 int id, tech, f, i, m, default_refresh_rate;
3211                 char *txtcolour;
3212                 char *txtmonitor;
3213                 char *txtdual;
3214                 char *txtformat;
3215                 u16 width, height, panel_type, refresh_rates;
3216                 u16 *lcdmodeptr;
3217                 u32 format;
3218                 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3219                 /* The most important information is the panel size at
3220                  * offset 25 and 27, but there's some other nice information
3221                  * which we print to the screen.
3222                  */
3223                 id = *(u8 *)par->lcd_table;
3224                 strncpy(model,(char *)par->lcd_table+1,24);
3225                 model[23]=0;
3226
3227                 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3228                 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3229                 panel_type = *(u16 *)(par->lcd_table+29);
3230                 if (panel_type & 1)
3231                         txtcolour = "colour";
3232                 else
3233                         txtcolour = "monochrome";
3234                 if (panel_type & 2)
3235                         txtdual = "dual (split) ";
3236                 else
3237                         txtdual = "";
3238                 tech = (panel_type>>2) & 63;
3239                 switch (tech) {
3240                 case 0:
3241                         txtmonitor = "passive matrix";
3242                         break;
3243                 case 1:
3244                         txtmonitor = "active matrix";
3245                         break;
3246                 case 2:
3247                         txtmonitor = "active addressed STN";
3248                         break;
3249                 case 3:
3250                         txtmonitor = "EL";
3251                         break;
3252                 case 4:
3253                         txtmonitor = "plasma";
3254                         break;
3255                 default:
3256                         txtmonitor = "unknown";
3257                 }
3258                 format = *(u32 *)(par->lcd_table+57);
3259                 if (tech == 0 || tech == 2) {
3260                         switch (format & 7) {
3261                         case 0:
3262                                 txtformat = "12 bit interface";
3263                                 break;
3264                         case 1:
3265                                 txtformat = "16 bit interface";
3266                                 break;
3267                         case 2:
3268                                 txtformat = "24 bit interface";
3269                                 break;
3270                         default:
3271                                 txtformat = "unkown format";
3272                         }
3273                 } else {
3274                         switch (format & 7) {
3275                         case 0:
3276                                 txtformat = "8 colours";
3277                                 break;
3278                         case 1:
3279                                 txtformat = "512 colours";
3280                                 break;
3281                         case 2:
3282                                 txtformat = "4096 colours";
3283                                 break;
3284                         case 4:
3285                                 txtformat = "262144 colours (LT mode)";
3286                                 break;
3287                         case 5:
3288                                 txtformat = "16777216 colours";
3289                                 break;
3290                         case 6:
3291                                 txtformat = "262144 colours (FDPI-2 mode)";
3292                                 break;
3293                         default:
3294                                 txtformat = "unkown format";
3295                         }
3296                 }
3297                 PRINTKI("%s%s %s monitor detected: %s\n",
3298                         txtdual ,txtcolour, txtmonitor, model);
3299                 PRINTKI("       id=%d, %dx%d pixels, %s\n",
3300                         id, width, height, txtformat);
3301                 refresh_rates_buf[0] = 0;
3302                 refresh_rates = *(u16 *)(par->lcd_table+62);
3303                 m = 1;
3304                 f = 0;
3305                 for (i=0;i<16;i++) {
3306                         if (refresh_rates & m) {
3307                                 if (f == 0) {
3308                                         sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3309                                         f++;
3310                                 } else {
3311                                         sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3312                                 }
3313                                 strcat(refresh_rates_buf,strbuf);
3314                         }
3315                         m = m << 1;
3316                 }
3317                 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3318                 PRINTKI("       supports refresh rates [%s], default %d Hz\n",
3319                         refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3320                 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3321                 /* We now need to determine the crtc parameters for the
3322                  * LCD monitor. This is tricky, because they are not stored
3323                  * individually in the BIOS. Instead, the BIOS contains a
3324                  * table of display modes that work for this monitor.
3325                  *
3326                  * The idea is that we search for a mode of the same dimensions
3327                  * as the dimensions of the LCD monitor. Say our LCD monitor
3328                  * is 800x600 pixels, we search for a 800x600 monitor.
3329                  * The CRTC parameters we find here are the ones that we need
3330                  * to use to simulate other resolutions on the LCD screen.
3331                  */
3332                 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3333                 while (*lcdmodeptr != 0) {
3334                         u32 modeptr;
3335                         u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3336                         modeptr = bios_base + *lcdmodeptr;
3337
3338                         mwidth = *((u16 *)(modeptr+0));
3339                         mheight = *((u16 *)(modeptr+2));
3340
3341                         if (mwidth == width && mheight == height) {
3342                                 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3343                                 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3344                                 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3345                                 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3346                                 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3347                                 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3348
3349                                 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3350                                 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3351                                 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3352                                 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3353
3354                                 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3355                                 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3356                                 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3357                                 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3358
3359                                 par->lcd_vtotal++;
3360                                 par->lcd_vdisp++;
3361                                 lcd_vsync_start++;
3362
3363                                 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3364                                 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3365                                 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3366                                 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3367                                 break;
3368                         }
3369
3370                         lcdmodeptr++;
3371                 }
3372                 if (*lcdmodeptr == 0) {
3373                         PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3374                         /* To do: Switch to CRT if possible. */
3375                 } else {
3376                         PRINTKI("       LCD CRTC parameters: %d.%d  %d %d %d %d  %d %d %d %d\n",
3377                                 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3378                                 par->lcd_hdisp,
3379                                 par->lcd_hdisp + par->lcd_right_margin,
3380                                 par->lcd_hdisp + par->lcd_right_margin
3381                                         + par->lcd_hsync_dly + par->lcd_hsync_len,
3382                                 par->lcd_htotal,
3383                                 par->lcd_vdisp,
3384                                 par->lcd_vdisp + par->lcd_lower_margin,
3385                                 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3386                                 par->lcd_vtotal);
3387                         PRINTKI("                          : %d %d %d %d %d %d %d %d %d\n",
3388                                 par->lcd_pixclock,
3389                                 par->lcd_hblank_len - (par->lcd_right_margin +
3390                                         par->lcd_hsync_dly + par->lcd_hsync_len),
3391                                 par->lcd_hdisp,
3392                                 par->lcd_right_margin,
3393                                 par->lcd_hsync_len,
3394                                 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3395                                 par->lcd_vdisp,
3396                                 par->lcd_lower_margin,
3397                                 par->lcd_vsync_len);
3398                 }
3399         }
3400 }
3401 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3402
3403 static int __devinit init_from_bios(struct atyfb_par *par)
3404 {
3405         u32 bios_base, rom_addr;
3406         int ret;
3407
3408         rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3409         bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3410
3411         /* The BIOS starts with 0xaa55. */
3412         if (*((u16 *)bios_base) == 0xaa55) {
3413
3414                 u8 *bios_ptr;
3415                 u16 rom_table_offset, freq_table_offset;
3416                 PLL_BLOCK_MACH64 pll_block;
3417
3418                 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3419
3420                 /* check for frequncy table */
3421                 bios_ptr = (u8*)bios_base;
3422                 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3423                 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3424                 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3425
3426                 PRINTKI("BIOS frequency table:\n");
3427                 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3428                         pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3429                         pll_block.ref_freq, pll_block.ref_divider);
3430                 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3431                         pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3432                         pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3433
3434                 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3435                 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3436                 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3437                 par->pll_limits.ref_div = pll_block.ref_divider;
3438                 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3439                 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3440                 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3441                 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3442 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3443                 aty_init_lcd(par, bios_base);
3444 #endif
3445                 ret = 0;
3446         } else {
3447                 PRINTKE("no BIOS frequency table found, use parameters\n");
3448                 ret = -ENXIO;
3449         }
3450         iounmap((void* __iomem )bios_base);
3451
3452         return ret;
3453 }
3454 #endif /* __i386__ */
3455
3456 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3457 {
3458         struct atyfb_par *par = info->par;
3459         u16 tmp;
3460         unsigned long raddr;
3461         struct resource *rrp;
3462         int ret = 0;
3463
3464         raddr = addr + 0x7ff000UL;
3465         rrp = &pdev->resource[2];
3466         if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3467                 par->aux_start = rrp->start;
3468                 par->aux_size = rrp->end - rrp->start + 1;
3469                 raddr = rrp->start;
3470                 PRINTKI("using auxiliary register aperture\n");
3471         }
3472
3473         info->fix.mmio_start = raddr;
3474         par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3475         if (par->ati_regbase == 0)
3476                 return -ENOMEM;
3477
3478         info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3479         par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3480
3481         /*
3482          * Enable memory-space accesses using config-space
3483          * command register.
3484          */
3485         pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3486         if (!(tmp & PCI_COMMAND_MEMORY)) {
3487                 tmp |= PCI_COMMAND_MEMORY;
3488                 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3489         }
3490 #ifdef __BIG_ENDIAN
3491         /* Use the big-endian aperture */
3492         addr += 0x800000;
3493 #endif
3494
3495         /* Map in frame buffer */
3496         info->fix.smem_start = addr;
3497         info->screen_base = ioremap(addr, 0x800000);
3498         if (info->screen_base == NULL) {
3499                 ret = -ENOMEM;
3500                 goto atyfb_setup_generic_fail;
3501         }
3502
3503         if((ret = correct_chipset(par)))
3504                 goto atyfb_setup_generic_fail;
3505 #ifdef __i386__
3506         if((ret = init_from_bios(par)))
3507                 goto atyfb_setup_generic_fail;
3508 #endif
3509         if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3510                 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3511         else
3512                 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3513
3514         /* according to ATI, we should use clock 3 for acelerated mode */
3515         par->clk_wr_offset = 3;
3516
3517         return 0;
3518
3519 atyfb_setup_generic_fail:
3520         iounmap(par->ati_regbase);
3521         par->ati_regbase = NULL;
3522         return ret;
3523 }
3524
3525 #endif /* !__sparc__ */
3526
3527 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3528 {
3529         unsigned long addr, res_start, res_size;
3530         struct fb_info *info;
3531         struct resource *rp;
3532         struct atyfb_par *par;
3533         int i, rc = -ENOMEM;
3534
3535         for (i = ARRAY_SIZE(aty_chips) - 1; i >= 0; i--)
3536                 if (pdev->device == aty_chips[i].pci_id)
3537                         break;
3538
3539         if (i < 0)
3540                 return -ENODEV;
3541
3542         /* Enable device in PCI config */
3543         if (pci_enable_device(pdev)) {
3544                 PRINTKE("Cannot enable PCI device\n");
3545                 return -ENXIO;
3546         }
3547
3548         /* Find which resource to use */
3549         rp = &pdev->resource[0];
3550         if (rp->flags & IORESOURCE_IO)
3551                 rp = &pdev->resource[1];
3552         addr = rp->start;
3553         if (!addr)
3554                 return -ENXIO;
3555
3556         /* Reserve space */
3557         res_start = rp->start;
3558         res_size = rp->end - rp->start + 1;
3559         if (!request_mem_region (res_start, res_size, "atyfb"))
3560                 return -EBUSY;
3561
3562         /* Allocate framebuffer */
3563         info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3564         if (!info) {
3565                 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3566                 return -ENOMEM;
3567         }
3568         par = info->par;
3569         info->fix = atyfb_fix;
3570         info->device = &pdev->dev;
3571         par->pci_id = aty_chips[i].pci_id;
3572         par->res_start = res_start;
3573         par->res_size = res_size;
3574         par->irq = pdev->irq;
3575         par->pdev = pdev;
3576
3577         /* Setup "info" structure */
3578 #ifdef __sparc__
3579         rc = atyfb_setup_sparc(pdev, info, addr);
3580 #else
3581         rc = atyfb_setup_generic(pdev, info, addr);
3582 #endif
3583         if (rc)
3584                 goto err_release_mem;
3585
3586         pci_set_drvdata(pdev, info);
3587
3588         /* Init chip & register framebuffer */
3589         if (aty_init(info, "PCI"))
3590                 goto err_release_io;
3591
3592 #ifdef __sparc__
3593         if (!prom_palette)
3594                 prom_palette = atyfb_palette;
3595
3596         /*
3597          * Add /dev/fb mmap values.
3598          */
3599         par->mmap_map[0].voff = 0x8000000000000000UL;
3600         par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3601         par->mmap_map[0].size = info->fix.smem_len;
3602         par->mmap_map[0].prot_mask = _PAGE_CACHE;
3603         par->mmap_map[0].prot_flag = _PAGE_E;
3604         par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3605         par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3606         par->mmap_map[1].size = PAGE_SIZE;
3607         par->mmap_map[1].prot_mask = _PAGE_CACHE;
3608         par->mmap_map[1].prot_flag = _PAGE_E;
3609 #endif /* __sparc__ */
3610
3611         return 0;
3612
3613 err_release_io:
3614 #ifdef __sparc__
3615         kfree(par->mmap_map);
3616 #else
3617         if (par->ati_regbase)
3618                 iounmap(par->ati_regbase);
3619         if (info->screen_base)
3620                 iounmap(info->screen_base);
3621 #endif
3622 err_release_mem:
3623         if (par->aux_start)
3624                 release_mem_region(par->aux_start, par->aux_size);
3625
3626         release_mem_region(par->res_start, par->res_size);
3627         framebuffer_release(info);
3628
3629         return rc;
3630 }
3631
3632 #endif /* CONFIG_PCI */
3633
3634 #ifdef CONFIG_ATARI
3635
3636 static int __devinit atyfb_atari_probe(void)
3637 {
3638         struct atyfb_par *par;
3639         struct fb_info *info;
3640         int m64_num;
3641         u32 clock_r;
3642
3643         for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3644                 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3645                     !phys_guiregbase[m64_num]) {
3646                     PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3647                         continue;
3648                 }
3649
3650                 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3651                 if (!info) {
3652                         PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3653                         return -ENOMEM;
3654                 }
3655                 par = info->par;
3656
3657                 info->fix = atyfb_fix;
3658
3659                 par->irq = (unsigned int) -1; /* something invalid */
3660
3661                 /*
3662                  *  Map the video memory (physical address given) to somewhere in the
3663                  *  kernel address space.
3664                  */
3665                 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3666                 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3667                 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3668                                                 0xFC00ul;
3669                 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3670
3671                 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3672                 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3673
3674                 switch (clock_r & 0x003F) {
3675                 case 0x12:
3676                         par->clk_wr_offset = 3; /*  */
3677                         break;
3678                 case 0x34:
3679                         par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3680                         break;
3681                 case 0x16:
3682                         par->clk_wr_offset = 1; /*  */
3683                         break;
3684                 case 0x38:
3685                         par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3686                         break;
3687                 }
3688
3689                 if (aty_init(info, "ISA bus")) {
3690                         framebuffer_release(info);
3691                         /* This is insufficient! kernel_map has added two large chunks!! */
3692                         return -ENXIO;
3693                 }
3694         }
3695 }
3696
3697 #endif /* CONFIG_ATARI */
3698
3699 static void __devexit atyfb_remove(struct fb_info *info)
3700 {
3701         struct atyfb_par *par = (struct atyfb_par *) info->par;
3702
3703         /* restore video mode */
3704         aty_set_crtc(par, &saved_crtc);
3705         par->pll_ops->set_pll(info, &saved_pll);
3706
3707 #ifdef CONFIG_FB_ATY_BACKLIGHT
3708         if (M64_HAS(MOBIL_BUS))
3709                 aty_bl_exit(par);
3710 #endif
3711
3712         unregister_framebuffer(info);
3713
3714 #ifdef CONFIG_MTRR
3715         if (par->mtrr_reg >= 0) {
3716             mtrr_del(par->mtrr_reg, 0, 0);
3717             par->mtrr_reg = -1;
3718         }
3719         if (par->mtrr_aper >= 0) {
3720             mtrr_del(par->mtrr_aper, 0, 0);
3721             par->mtrr_aper = -1;
3722         }
3723 #endif
3724 #ifndef __sparc__
3725         if (par->ati_regbase)
3726                 iounmap(par->ati_regbase);
3727         if (info->screen_base)
3728                 iounmap(info->screen_base);
3729 #ifdef __BIG_ENDIAN
3730         if (info->sprite.addr)
3731                 iounmap(info->sprite.addr);
3732 #endif
3733 #endif
3734 #ifdef __sparc__
3735         kfree(par->mmap_map);
3736 #endif
3737         if (par->aux_start)
3738                 release_mem_region(par->aux_start, par->aux_size);
3739
3740         if (par->res_start)
3741                 release_mem_region(par->res_start, par->res_size);
3742
3743         framebuffer_release(info);
3744 }
3745
3746 #ifdef CONFIG_PCI
3747
3748 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3749 {
3750         struct fb_info *info = pci_get_drvdata(pdev);
3751
3752         atyfb_remove(info);
3753 }
3754
3755 /*
3756  * This driver uses its own matching table. That will be more difficult
3757  * to fix, so for now, we just match against any ATI ID and let the
3758  * probe() function find out what's up. That also mean we don't have
3759  * a module ID table though.
3760  */
3761 static struct pci_device_id atyfb_pci_tbl[] = {
3762         { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3763           PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3764         { 0, }
3765 };
3766
3767 static struct pci_driver atyfb_driver = {
3768         .name           = "atyfb",
3769         .id_table       = atyfb_pci_tbl,
3770         .probe          = atyfb_pci_probe,
3771         .remove         = __devexit_p(atyfb_pci_remove),
3772 #ifdef CONFIG_PM
3773         .suspend        = atyfb_pci_suspend,
3774         .resume         = atyfb_pci_resume,
3775 #endif /* CONFIG_PM */
3776 };
3777
3778 #endif /* CONFIG_PCI */
3779
3780 #ifndef MODULE
3781 static int __devinit atyfb_setup(char *options)
3782 {
3783         char *this_opt;
3784
3785         if (!options || !*options)
3786                 return 0;
3787
3788         while ((this_opt = strsep(&options, ",")) != NULL) {
3789                 if (!strncmp(this_opt, "noaccel", 7)) {
3790                         noaccel = 1;
3791 #ifdef CONFIG_MTRR
3792                 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3793                         nomtrr = 1;
3794 #endif
3795                 } else if (!strncmp(this_opt, "vram:", 5))
3796                         vram = simple_strtoul(this_opt + 5, NULL, 0);
3797                 else if (!strncmp(this_opt, "pll:", 4))
3798                         pll = simple_strtoul(this_opt + 4, NULL, 0);
3799                 else if (!strncmp(this_opt, "mclk:", 5))
3800                         mclk = simple_strtoul(this_opt + 5, NULL, 0);
3801                 else if (!strncmp(this_opt, "xclk:", 5))
3802                         xclk = simple_strtoul(this_opt+5, NULL, 0);
3803                 else if (!strncmp(this_opt, "comp_sync:", 10))
3804                         comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3805 #ifdef CONFIG_PPC
3806                 else if (!strncmp(this_opt, "vmode:", 6)) {
3807                         unsigned int vmode =
3808                             simple_strtoul(this_opt + 6, NULL, 0);
3809                         if (vmode > 0 && vmode <= VMODE_MAX)
3810                                 default_vmode = vmode;
3811                 } else if (!strncmp(this_opt, "cmode:", 6)) {
3812                         unsigned int cmode =
3813                             simple_strtoul(this_opt + 6, NULL, 0);
3814                         switch (cmode) {
3815                         case 0:
3816                         case 8:
3817                                 default_cmode = CMODE_8;
3818                                 break;
3819                         case 15:
3820                         case 16:
3821                                 default_cmode = CMODE_16;
3822                                 break;
3823                         case 24:
3824                         case 32:
3825                                 default_cmode = CMODE_32;
3826                                 break;
3827                         }
3828                 }
3829 #endif
3830 #ifdef CONFIG_ATARI
3831                 /*
3832                  * Why do we need this silly Mach64 argument?
3833                  * We are already here because of mach64= so its redundant.
3834                  */
3835                 else if (MACH_IS_ATARI
3836                          && (!strncmp(this_opt, "Mach64:", 7))) {
3837                         static unsigned char m64_num;
3838                         static char mach64_str[80];
3839                         strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3840                         if (!store_video_par(mach64_str, m64_num)) {
3841                                 m64_num++;
3842                                 mach64_count = m64_num;
3843                         }
3844                 }
3845 #endif
3846                 else
3847                         mode = this_opt;
3848         }
3849         return 0;
3850 }
3851 #endif  /*  MODULE  */
3852
3853 static int __devinit atyfb_init(void)
3854 {
3855 #ifndef MODULE
3856     char *option = NULL;
3857
3858     if (fb_get_options("atyfb", &option))
3859         return -ENODEV;
3860     atyfb_setup(option);
3861 #endif
3862
3863 #ifdef CONFIG_PCI
3864     pci_register_driver(&atyfb_driver);
3865 #endif
3866 #ifdef CONFIG_ATARI
3867     atyfb_atari_probe();
3868 #endif
3869     return 0;
3870 }
3871
3872 static void __exit atyfb_exit(void)
3873 {
3874 #ifdef CONFIG_PCI
3875         pci_unregister_driver(&atyfb_driver);
3876 #endif
3877 }
3878
3879 module_init(atyfb_init);
3880 module_exit(atyfb_exit);
3881
3882 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3883 MODULE_LICENSE("GPL");
3884 module_param(noaccel, bool, 0);
3885 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3886 module_param(vram, int, 0);
3887 MODULE_PARM_DESC(vram, "int: override size of video ram");
3888 module_param(pll, int, 0);
3889 MODULE_PARM_DESC(pll, "int: override video clock");
3890 module_param(mclk, int, 0);
3891 MODULE_PARM_DESC(mclk, "int: override memory clock");
3892 module_param(xclk, int, 0);
3893 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3894 module_param(comp_sync, int, 0);
3895 MODULE_PARM_DESC(comp_sync,
3896                  "Set composite sync signal to low (0) or high (1)");
3897 module_param(mode, charp, 0);
3898 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3899 #ifdef CONFIG_MTRR
3900 module_param(nomtrr, bool, 0);
3901 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");
3902 #endif