2 * ATI Frame Buffer Device Driver Core
4 * Copyright (C) 2004 Alex Kern <alex.kern@gmx.de>
5 * Copyright (C) 1997-2001 Geert Uytterhoeven
6 * Copyright (C) 1998 Bernd Harries
7 * Copyright (C) 1998 Eddie C. Dost (ecd@skynet.be)
9 * This driver supports the following ATI graphics chips:
12 * To do: add support for
13 * - ATI Rage128 (from aty128fb.c)
14 * - ATI Radeon (from radeonfb.c)
16 * This driver is partly based on the PowerMac console driver:
18 * Copyright (C) 1996 Paul Mackerras
20 * and on the PowerMac ATI/mach64 display driver:
22 * Copyright (C) 1997 Michael AK Tesch
24 * with work by Jon Howell
26 * Anthony Tong <atong@uiuc.edu>
28 * Generic LCD support written by Daniel Mantione, ported from 2.4.20 by Alex Kern
29 * Many Thanks to Ville Syrjälä for patches and fixing nasting 16 bit color bug.
31 * This file is subject to the terms and conditions of the GNU General Public
32 * License. See the file COPYING in the main directory of this archive for
35 * Many thanks to Nitya from ATI devrel for support and patience !
38 /******************************************************************************
42 - cursor support on all cards and all ramdacs.
43 - cursor parameters controlable via ioctl()s.
44 - guess PLL and MCLK based on the original PLL register values initialized
45 by Open Firmware (if they are initialized). BIOS is done
47 (Anyone with Mac to help with this?)
49 ******************************************************************************/
52 #include <linux/config.h>
53 #include <linux/module.h>
54 #include <linux/moduleparam.h>
55 #include <linux/kernel.h>
56 #include <linux/errno.h>
57 #include <linux/string.h>
59 #include <linux/slab.h>
60 #include <linux/vmalloc.h>
61 #include <linux/delay.h>
62 #include <linux/console.h>
64 #include <linux/init.h>
65 #include <linux/pci.h>
66 #include <linux/interrupt.h>
67 #include <linux/spinlock.h>
68 #include <linux/wait.h>
71 #include <asm/uaccess.h>
73 #include <video/mach64.h>
79 #include "../macmodes.h"
87 #include <linux/adb.h>
88 #include <linux/pmu.h>
90 #ifdef CONFIG_BOOTX_TEXT
91 #include <asm/btext.h>
93 #ifdef CONFIG_PMAC_BACKLIGHT
94 #include <asm/backlight.h>
106 /* Make sure n * PAGE_SIZE is protected at end of Aperture for GUI-regs */
107 /* - must be large enough to catch all GUI-Regs */
108 /* - must be aligned to a PAGE boundary */
109 #define GUI_RESERVE (1 * PAGE_SIZE)
111 /* FIXME: remove the FAIL definition */
112 #define FAIL(msg) do { \
113 if (!(var->activate & FB_ACTIVATE_TEST)) \
114 printk(KERN_CRIT "atyfb: " msg "\n"); \
117 #define FAIL_MAX(msg, x, _max_) do { \
119 if (!(var->activate & FB_ACTIVATE_TEST)) \
120 printk(KERN_CRIT "atyfb: " msg " %x(%x)\n", x, _max_); \
125 #define DPRINTK(fmt, args...) printk(KERN_DEBUG "atyfb: " fmt, ## args)
127 #define DPRINTK(fmt, args...)
130 #define PRINTKI(fmt, args...) printk(KERN_INFO "atyfb: " fmt, ## args)
131 #define PRINTKE(fmt, args...) printk(KERN_ERR "atyfb: " fmt, ## args)
133 #if defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD)
134 static const u32 lt_lcd_regs[] = {
141 0, /* EXT_VERT_STRETCH */
146 void aty_st_lcd(int index, u32 val, const struct atyfb_par *par)
148 if (M64_HAS(LT_LCD_REGS)) {
149 aty_st_le32(lt_lcd_regs[index], val, par);
153 /* write addr byte */
154 temp = aty_ld_le32(LCD_INDEX, par);
155 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
156 /* write the register value */
157 aty_st_le32(LCD_DATA, val, par);
161 u32 aty_ld_lcd(int index, const struct atyfb_par *par)
163 if (M64_HAS(LT_LCD_REGS)) {
164 return aty_ld_le32(lt_lcd_regs[index], par);
168 /* write addr byte */
169 temp = aty_ld_le32(LCD_INDEX, par);
170 aty_st_le32(LCD_INDEX, (temp & ~LCD_INDEX_MASK) | index, par);
171 /* read the register value */
172 return aty_ld_le32(LCD_DATA, par);
175 #endif /* defined(CONFIG_PM) || defined(CONFIG_PMAC_BACKLIGHT) || defined (CONFIG_FB_ATY_GENERIC_LCD) */
177 #ifdef CONFIG_FB_ATY_GENERIC_LCD
181 * Reduce a fraction by factoring out the largest common divider of the
182 * fraction's numerator and denominator.
184 static void ATIReduceRatio(int *Numerator, int *Denominator)
186 int Multiplier, Divider, Remainder;
188 Multiplier = *Numerator;
189 Divider = *Denominator;
191 while ((Remainder = Multiplier % Divider))
193 Multiplier = Divider;
197 *Numerator /= Divider;
198 *Denominator /= Divider;
202 * The Hardware parameters for each card
205 struct aty_cmap_regs {
213 struct pci_mmap_map {
217 unsigned long prot_flag;
218 unsigned long prot_mask;
221 static struct fb_fix_screeninfo atyfb_fix __devinitdata = {
223 .type = FB_TYPE_PACKED_PIXELS,
224 .visual = FB_VISUAL_PSEUDOCOLOR,
230 * Frame buffer device API
233 static int atyfb_open(struct fb_info *info, int user);
234 static int atyfb_release(struct fb_info *info, int user);
235 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info);
236 static int atyfb_set_par(struct fb_info *info);
237 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
238 u_int transp, struct fb_info *info);
239 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info);
240 static int atyfb_blank(int blank, struct fb_info *info);
241 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
242 u_long arg, struct fb_info *info);
243 extern void atyfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
244 extern void atyfb_copyarea(struct fb_info *info, const struct fb_copyarea *area);
245 extern void atyfb_imageblit(struct fb_info *info, const struct fb_image *image);
247 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma);
249 static int atyfb_sync(struct fb_info *info);
255 static int aty_init(struct fb_info *info, const char *name);
257 static int store_video_par(char *videopar, unsigned char m64_num);
260 static struct crtc saved_crtc;
261 static union aty_pll saved_pll;
262 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc);
264 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc);
265 static int aty_var_to_crtc(const struct fb_info *info, const struct fb_var_screeninfo *var, struct crtc *crtc);
266 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var);
267 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info);
269 static int read_aty_sense(const struct atyfb_par *par);
274 * Interface used by the world
277 static struct fb_var_screeninfo default_var = {
278 /* 640x480, 60 Hz, Non-Interlaced (25.175 MHz dotclock) */
279 640, 480, 640, 480, 0, 0, 8, 0,
280 {0, 8, 0}, {0, 8, 0}, {0, 8, 0}, {0, 0, 0},
281 0, 0, -1, -1, 0, 39722, 48, 16, 33, 10, 96, 2,
282 0, FB_VMODE_NONINTERLACED
285 static struct fb_videomode defmode = {
286 /* 640x480 @ 60 Hz, 31.5 kHz hsync */
287 NULL, 60, 640, 480, 39721, 40, 24, 32, 11, 96, 2,
288 0, FB_VMODE_NONINTERLACED
291 static struct fb_ops atyfb_ops = {
292 .owner = THIS_MODULE,
293 .fb_open = atyfb_open,
294 .fb_release = atyfb_release,
295 .fb_check_var = atyfb_check_var,
296 .fb_set_par = atyfb_set_par,
297 .fb_setcolreg = atyfb_setcolreg,
298 .fb_pan_display = atyfb_pan_display,
299 .fb_blank = atyfb_blank,
300 .fb_ioctl = atyfb_ioctl,
301 .fb_fillrect = atyfb_fillrect,
302 .fb_copyarea = atyfb_copyarea,
303 .fb_imageblit = atyfb_imageblit,
305 .fb_mmap = atyfb_mmap,
307 .fb_sync = atyfb_sync,
318 static int comp_sync __initdata = -1;
322 static int default_vmode __initdata = VMODE_CHOOSE;
323 static int default_cmode __initdata = CMODE_CHOOSE;
325 module_param_named(vmode, default_vmode, int, 0);
326 MODULE_PARM_DESC(vmode, "int: video mode for mac");
327 module_param_named(cmode, default_cmode, int, 0);
328 MODULE_PARM_DESC(cmode, "int: color mode for mac");
332 static unsigned int mach64_count __initdata = 0;
333 static unsigned long phys_vmembase[FB_MAX] __initdata = { 0, };
334 static unsigned long phys_size[FB_MAX] __initdata = { 0, };
335 static unsigned long phys_guiregbase[FB_MAX] __initdata = { 0, };
338 /* top -> down is an evolution of mach64 chipset, any corrections? */
339 #define ATI_CHIP_88800GX (M64F_GX)
340 #define ATI_CHIP_88800CX (M64F_GX)
342 #define ATI_CHIP_264CT (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
343 #define ATI_CHIP_264ET (M64F_CT | M64F_INTEGRATED | M64F_CT_BUS | M64F_MAGIC_FIFO)
345 #define ATI_CHIP_264VT (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_MAGIC_FIFO)
346 #define ATI_CHIP_264GT (M64F_GT | M64F_INTEGRATED | M64F_MAGIC_FIFO | M64F_EXTRA_BRIGHT)
348 #define ATI_CHIP_264VTB (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP)
349 #define ATI_CHIP_264VT3 (M64F_VT | M64F_INTEGRATED | M64F_VT_BUS | M64F_GTB_DSP | M64F_SDRAM_MAGIC_PLL)
350 #define ATI_CHIP_264VT4 (M64F_VT | M64F_INTEGRATED | M64F_GTB_DSP)
352 #define ATI_CHIP_264LT (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP)
354 /* make sets shorter */
355 #define ATI_MODERN_SET (M64F_GT | M64F_INTEGRATED | M64F_GTB_DSP | M64F_EXTRA_BRIGHT)
357 #define ATI_CHIP_264GTB (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
358 /*#define ATI_CHIP_264GTDVD ?*/
359 #define ATI_CHIP_264LTG (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL)
361 #define ATI_CHIP_264GT2C (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE)
362 #define ATI_CHIP_264GTPRO (ATI_MODERN_SET | M64F_SDRAM_MAGIC_PLL | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
363 #define ATI_CHIP_264LTPRO (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D)
365 #define ATI_CHIP_264XL (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4)
366 #define ATI_CHIP_MOBILITY (ATI_MODERN_SET | M64F_HW_TRIPLE | M64F_FIFO_32 | M64F_RESET_3D | M64F_XL_DLL | M64F_MFB_FORCE_4 | M64F_MOBIL_BUS)
371 int pll, mclk, xclk, ecp_max;
373 } aty_chips[] __devinitdata = {
374 #ifdef CONFIG_FB_ATY_GX
376 { PCI_CHIP_MACH64GX, "ATI888GX00 (Mach64 GX)", 135, 50, 50, 0, ATI_CHIP_88800GX },
377 { PCI_CHIP_MACH64CX, "ATI888CX00 (Mach64 CX)", 135, 50, 50, 0, ATI_CHIP_88800CX },
378 #endif /* CONFIG_FB_ATY_GX */
380 #ifdef CONFIG_FB_ATY_CT
381 { PCI_CHIP_MACH64CT, "ATI264CT (Mach64 CT)", 135, 60, 60, 0, ATI_CHIP_264CT },
382 { PCI_CHIP_MACH64ET, "ATI264ET (Mach64 ET)", 135, 60, 60, 0, ATI_CHIP_264ET },
384 { PCI_CHIP_MACH64VT, "ATI264VT (Mach64 VT)", 170, 67, 67, 80, ATI_CHIP_264VT },
385 { PCI_CHIP_MACH64GT, "3D RAGE (Mach64 GT)", 135, 63, 63, 80, ATI_CHIP_264GT },
387 { PCI_CHIP_MACH64VU, "ATI264VT3 (Mach64 VU)", 200, 67, 67, 80, ATI_CHIP_264VT3 },
388 { PCI_CHIP_MACH64GU, "3D RAGE II+ (Mach64 GU)", 200, 67, 67, 100, ATI_CHIP_264GTB },
390 { PCI_CHIP_MACH64LT, "3D RAGE LT (Mach64 LT)", 135, 63, 63, 0, ATI_CHIP_264LT },
391 /* FIXME chipset maybe ATI_CHIP_264LTPRO ? */
392 { PCI_CHIP_MACH64LG, "3D RAGE LT-G (Mach64 LG)", 230, 63, 63, 100, ATI_CHIP_264LTG | M64F_LT_LCD_REGS | M64F_G3_PB_1024x768 },
394 { PCI_CHIP_MACH64VV, "ATI264VT4 (Mach64 VV)", 230, 83, 83, 100, ATI_CHIP_264VT4 },
396 { PCI_CHIP_MACH64GV, "3D RAGE IIC (Mach64 GV, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
397 { PCI_CHIP_MACH64GW, "3D RAGE IIC (Mach64 GW, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
398 { PCI_CHIP_MACH64GY, "3D RAGE IIC (Mach64 GY, PCI)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
399 { PCI_CHIP_MACH64GZ, "3D RAGE IIC (Mach64 GZ, AGP)", 230, 83, 83, 100, ATI_CHIP_264GT2C },
401 { PCI_CHIP_MACH64GB, "3D RAGE PRO (Mach64 GB, BGA, AGP)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
402 { PCI_CHIP_MACH64GD, "3D RAGE PRO (Mach64 GD, BGA, AGP 1x)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
403 { PCI_CHIP_MACH64GI, "3D RAGE PRO (Mach64 GI, BGA, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO | M64F_MAGIC_VRAM_SIZE },
404 { PCI_CHIP_MACH64GP, "3D RAGE PRO (Mach64 GP, PQFP, PCI)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
405 { PCI_CHIP_MACH64GQ, "3D RAGE PRO (Mach64 GQ, PQFP, PCI, limited 3D)", 230, 100, 100, 125, ATI_CHIP_264GTPRO },
407 { PCI_CHIP_MACH64LB, "3D RAGE LT PRO (Mach64 LB, AGP)", 236, 75, 100, 135, ATI_CHIP_264LTPRO },
408 { PCI_CHIP_MACH64LD, "3D RAGE LT PRO (Mach64 LD, AGP)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
409 { PCI_CHIP_MACH64LI, "3D RAGE LT PRO (Mach64 LI, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO | M64F_G3_PB_1_1 | M64F_G3_PB_1024x768 },
410 { PCI_CHIP_MACH64LP, "3D RAGE LT PRO (Mach64 LP, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
411 { PCI_CHIP_MACH64LQ, "3D RAGE LT PRO (Mach64 LQ, PCI)", 230, 100, 100, 135, ATI_CHIP_264LTPRO },
413 { PCI_CHIP_MACH64GM, "3D RAGE XL (Mach64 GM, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
414 { PCI_CHIP_MACH64GN, "3D RAGE XC (Mach64 GN, AGP 2x)", 230, 83, 63, 135, ATI_CHIP_264XL },
415 { PCI_CHIP_MACH64GO, "3D RAGE XL (Mach64 GO, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
416 { PCI_CHIP_MACH64GL, "3D RAGE XC (Mach64 GL, PCI-66)", 230, 83, 63, 135, ATI_CHIP_264XL },
417 { PCI_CHIP_MACH64GR, "3D RAGE XL (Mach64 GR, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL | M64F_SDRAM_MAGIC_PLL },
418 { PCI_CHIP_MACH64GS, "3D RAGE XC (Mach64 GS, PCI-33)", 230, 83, 63, 135, ATI_CHIP_264XL },
420 { PCI_CHIP_MACH64LM, "3D RAGE Mobility P/M (Mach64 LM, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
421 { PCI_CHIP_MACH64LN, "3D RAGE Mobility L (Mach64 LN, AGP 2x)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
422 { PCI_CHIP_MACH64LR, "3D RAGE Mobility P/M (Mach64 LR, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
423 { PCI_CHIP_MACH64LS, "3D RAGE Mobility L (Mach64 LS, PCI)", 230, 83, 125, 135, ATI_CHIP_MOBILITY },
424 #endif /* CONFIG_FB_ATY_CT */
428 static int __devinit correct_chipset(struct atyfb_par *par)
436 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
437 if (par->pci_id == aty_chips[i].pci_id)
440 name = aty_chips[i].name;
441 par->pll_limits.pll_max = aty_chips[i].pll;
442 par->pll_limits.mclk = aty_chips[i].mclk;
443 par->pll_limits.xclk = aty_chips[i].xclk;
444 par->pll_limits.ecp_max = aty_chips[i].ecp_max;
445 par->features = aty_chips[i].features;
447 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
448 type = chip_id & CFG_CHIP_TYPE;
449 rev = (chip_id & CFG_CHIP_REV) >> 24;
451 switch(par->pci_id) {
452 #ifdef CONFIG_FB_ATY_GX
453 case PCI_CHIP_MACH64GX:
457 case PCI_CHIP_MACH64CX:
462 #ifdef CONFIG_FB_ATY_CT
463 case PCI_CHIP_MACH64VT:
464 switch (rev & 0x07) {
466 switch (rev & 0xc0) {
468 name = "ATI264VT (A3) (Mach64 VT)";
469 par->pll_limits.pll_max = 170;
470 par->pll_limits.mclk = 67;
471 par->pll_limits.xclk = 67;
472 par->pll_limits.ecp_max = 80;
473 par->features = ATI_CHIP_264VT;
476 name = "ATI264VT2 (A4) (Mach64 VT)";
477 par->pll_limits.pll_max = 200;
478 par->pll_limits.mclk = 67;
479 par->pll_limits.xclk = 67;
480 par->pll_limits.ecp_max = 80;
481 par->features = ATI_CHIP_264VT | M64F_MAGIC_POSTDIV;
486 name = "ATI264VT3 (B1) (Mach64 VT)";
487 par->pll_limits.pll_max = 200;
488 par->pll_limits.mclk = 67;
489 par->pll_limits.xclk = 67;
490 par->pll_limits.ecp_max = 80;
491 par->features = ATI_CHIP_264VTB;
494 name = "ATI264VT3 (B2) (Mach64 VT)";
495 par->pll_limits.pll_max = 200;
496 par->pll_limits.mclk = 67;
497 par->pll_limits.xclk = 67;
498 par->pll_limits.ecp_max = 80;
499 par->features = ATI_CHIP_264VT3;
503 case PCI_CHIP_MACH64GT:
504 switch (rev & 0x07) {
506 name = "3D RAGE II (Mach64 GT)";
507 par->pll_limits.pll_max = 170;
508 par->pll_limits.mclk = 67;
509 par->pll_limits.xclk = 67;
510 par->pll_limits.ecp_max = 80;
511 par->features = ATI_CHIP_264GTB;
514 name = "3D RAGE II+ (Mach64 GT)";
515 par->pll_limits.pll_max = 200;
516 par->pll_limits.mclk = 67;
517 par->pll_limits.xclk = 67;
518 par->pll_limits.ecp_max = 100;
519 par->features = ATI_CHIP_264GTB;
526 PRINTKI("%s [0x%04x rev 0x%02x]\n", name, type, rev);
530 static char ram_dram[] __devinitdata = "DRAM";
531 static char ram_resv[] __devinitdata = "RESV";
532 #ifdef CONFIG_FB_ATY_GX
533 static char ram_vram[] __devinitdata = "VRAM";
534 #endif /* CONFIG_FB_ATY_GX */
535 #ifdef CONFIG_FB_ATY_CT
536 static char ram_edo[] __devinitdata = "EDO";
537 static char ram_sdram[] __devinitdata = "SDRAM (1:1)";
538 static char ram_sgram[] __devinitdata = "SGRAM (1:1)";
539 static char ram_sdram32[] __devinitdata = "SDRAM (2:1) (32-bit)";
540 static char ram_off[] __devinitdata = "OFF";
541 #endif /* CONFIG_FB_ATY_CT */
544 static u32 pseudo_palette[17];
546 #ifdef CONFIG_FB_ATY_GX
547 static char *aty_gx_ram[8] __devinitdata = {
548 ram_dram, ram_vram, ram_vram, ram_dram,
549 ram_dram, ram_vram, ram_vram, ram_resv
551 #endif /* CONFIG_FB_ATY_GX */
553 #ifdef CONFIG_FB_ATY_CT
554 static char *aty_ct_ram[8] __devinitdata = {
555 ram_off, ram_dram, ram_edo, ram_edo,
556 ram_sdram, ram_sgram, ram_sdram32, ram_resv
558 #endif /* CONFIG_FB_ATY_CT */
560 static u32 atyfb_get_pixclock(struct fb_var_screeninfo *var, struct atyfb_par *par)
562 u32 pixclock = var->pixclock;
563 #ifdef CONFIG_FB_ATY_GENERIC_LCD
565 par->pll.ct.xres = 0;
566 if (par->lcd_table != 0) {
567 lcd_on_off = aty_ld_lcd(LCD_GEN_CNTL, par);
568 if(lcd_on_off & LCD_ON) {
569 par->pll.ct.xres = var->xres;
570 pixclock = par->lcd_pixclock;
577 #if defined(CONFIG_PPC)
580 * Apple monitor sense
583 static int __init read_aty_sense(const struct atyfb_par *par)
587 aty_st_le32(GP_IO, 0x31003100, par); /* drive outputs high */
589 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
591 i = aty_ld_le32(GP_IO, par); /* get primary sense value */
592 sense = ((i & 0x3000) >> 3) | (i & 0x100);
594 /* drive each sense line low in turn and collect the other 2 */
595 aty_st_le32(GP_IO, 0x20000000, par); /* drive A low */
597 i = aty_ld_le32(GP_IO, par);
598 sense |= ((i & 0x1000) >> 7) | ((i & 0x100) >> 4);
599 aty_st_le32(GP_IO, 0x20002000, par); /* drive A high again */
602 aty_st_le32(GP_IO, 0x10000000, par); /* drive B low */
604 i = aty_ld_le32(GP_IO, par);
605 sense |= ((i & 0x2000) >> 10) | ((i & 0x100) >> 6);
606 aty_st_le32(GP_IO, 0x10001000, par); /* drive B high again */
609 aty_st_le32(GP_IO, 0x01000000, par); /* drive C low */
611 sense |= (aty_ld_le32(GP_IO, par) & 0x3000) >> 12;
612 aty_st_le32(GP_IO, 0, par); /* turn off outputs */
616 #endif /* defined(CONFIG_PPC) */
618 /* ------------------------------------------------------------------------- */
624 static void aty_get_crtc(const struct atyfb_par *par, struct crtc *crtc)
626 #ifdef CONFIG_FB_ATY_GENERIC_LCD
627 if (par->lcd_table != 0) {
628 if(!M64_HAS(LT_LCD_REGS)) {
629 crtc->lcd_index = aty_ld_le32(LCD_INDEX, par);
630 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
632 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par);
633 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par);
636 /* switch to non shadow registers */
637 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
638 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
640 /* save stretching */
641 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
642 crtc->vert_stretching = aty_ld_lcd(VERT_STRETCHING, par);
643 if (!M64_HAS(LT_LCD_REGS))
644 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par);
647 crtc->h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
648 crtc->h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
649 crtc->v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
650 crtc->v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
651 crtc->vline_crnt_vline = aty_ld_le32(CRTC_VLINE_CRNT_VLINE, par);
652 crtc->off_pitch = aty_ld_le32(CRTC_OFF_PITCH, par);
653 crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
655 #ifdef CONFIG_FB_ATY_GENERIC_LCD
656 if (par->lcd_table != 0) {
657 /* switch to shadow registers */
658 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
659 SHADOW_EN | SHADOW_RW_EN, par);
661 crtc->shadow_h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
662 crtc->shadow_h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
663 crtc->shadow_v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
664 crtc->shadow_v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
666 aty_st_le32(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
668 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
671 static void aty_set_crtc(const struct atyfb_par *par, const struct crtc *crtc)
673 #ifdef CONFIG_FB_ATY_GENERIC_LCD
674 if (par->lcd_table != 0) {
676 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~(CRTC_EXT_DISP_EN | CRTC_EN), par);
678 /* update non-shadow registers first */
679 aty_st_lcd(CONFIG_PANEL, crtc->lcd_config_panel, par);
680 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl &
681 ~(CRTC_RW_SELECT | SHADOW_EN | SHADOW_RW_EN), par);
683 /* temporarily disable stretching */
684 aty_st_lcd(HORZ_STRETCHING,
685 crtc->horz_stretching &
686 ~(HORZ_STRETCH_MODE | HORZ_STRETCH_EN), par);
687 aty_st_lcd(VERT_STRETCHING,
688 crtc->vert_stretching &
689 ~(VERT_STRETCH_RATIO1 | VERT_STRETCH_RATIO2 |
690 VERT_STRETCH_USE0 | VERT_STRETCH_EN), par);
694 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl & ~CRTC_EN, par);
696 DPRINTK("setting up CRTC\n");
697 DPRINTK("set primary CRT to %ix%i %c%c composite %c\n",
698 ((((crtc->h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->v_tot_disp>>16) & 0x7ff) + 1),
699 (crtc->h_sync_strt_wid & 0x200000)?'N':'P', (crtc->v_sync_strt_wid & 0x200000)?'N':'P',
700 (crtc->gen_cntl & CRTC_CSYNC_EN)?'P':'N');
702 DPRINTK("CRTC_H_TOTAL_DISP: %x\n",crtc->h_tot_disp);
703 DPRINTK("CRTC_H_SYNC_STRT_WID: %x\n",crtc->h_sync_strt_wid);
704 DPRINTK("CRTC_V_TOTAL_DISP: %x\n",crtc->v_tot_disp);
705 DPRINTK("CRTC_V_SYNC_STRT_WID: %x\n",crtc->v_sync_strt_wid);
706 DPRINTK("CRTC_OFF_PITCH: %x\n", crtc->off_pitch);
707 DPRINTK("CRTC_VLINE_CRNT_VLINE: %x\n", crtc->vline_crnt_vline);
708 DPRINTK("CRTC_GEN_CNTL: %x\n",crtc->gen_cntl);
710 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->h_tot_disp, par);
711 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->h_sync_strt_wid, par);
712 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->v_tot_disp, par);
713 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->v_sync_strt_wid, par);
714 aty_st_le32(CRTC_OFF_PITCH, crtc->off_pitch, par);
715 aty_st_le32(CRTC_VLINE_CRNT_VLINE, crtc->vline_crnt_vline, par);
717 aty_st_le32(CRTC_GEN_CNTL, crtc->gen_cntl, par);
720 if (par->accel_flags & FB_ACCELF_TEXT)
721 aty_init_engine(par, info);
723 #ifdef CONFIG_FB_ATY_GENERIC_LCD
724 /* after setting the CRTC registers we should set the LCD registers. */
725 if (par->lcd_table != 0) {
726 /* switch to shadow registers */
727 aty_st_lcd(LCD_GEN_CNTL, (crtc->lcd_gen_cntl & ~CRTC_RW_SELECT) |
728 (SHADOW_EN | SHADOW_RW_EN), par);
730 DPRINTK("set shadow CRT to %ix%i %c%c\n",
731 ((((crtc->shadow_h_tot_disp>>16) & 0xff) + 1)<<3), (((crtc->shadow_v_tot_disp>>16) & 0x7ff) + 1),
732 (crtc->shadow_h_sync_strt_wid & 0x200000)?'N':'P', (crtc->shadow_v_sync_strt_wid & 0x200000)?'N':'P');
734 DPRINTK("SHADOW CRTC_H_TOTAL_DISP: %x\n", crtc->shadow_h_tot_disp);
735 DPRINTK("SHADOW CRTC_H_SYNC_STRT_WID: %x\n", crtc->shadow_h_sync_strt_wid);
736 DPRINTK("SHADOW CRTC_V_TOTAL_DISP: %x\n", crtc->shadow_v_tot_disp);
737 DPRINTK("SHADOW CRTC_V_SYNC_STRT_WID: %x\n", crtc->shadow_v_sync_strt_wid);
739 aty_st_le32(CRTC_H_TOTAL_DISP, crtc->shadow_h_tot_disp, par);
740 aty_st_le32(CRTC_H_SYNC_STRT_WID, crtc->shadow_h_sync_strt_wid, par);
741 aty_st_le32(CRTC_V_TOTAL_DISP, crtc->shadow_v_tot_disp, par);
742 aty_st_le32(CRTC_V_SYNC_STRT_WID, crtc->shadow_v_sync_strt_wid, par);
744 /* restore CRTC selection & shadow state and enable stretching */
745 DPRINTK("LCD_GEN_CNTL: %x\n", crtc->lcd_gen_cntl);
746 DPRINTK("HORZ_STRETCHING: %x\n", crtc->horz_stretching);
747 DPRINTK("VERT_STRETCHING: %x\n", crtc->vert_stretching);
748 if(!M64_HAS(LT_LCD_REGS))
749 DPRINTK("EXT_VERT_STRETCH: %x\n", crtc->ext_vert_stretch);
751 aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);
752 aty_st_lcd(HORZ_STRETCHING, crtc->horz_stretching, par);
753 aty_st_lcd(VERT_STRETCHING, crtc->vert_stretching, par);
754 if(!M64_HAS(LT_LCD_REGS)) {
755 aty_st_lcd(EXT_VERT_STRETCH, crtc->ext_vert_stretch, par);
756 aty_ld_le32(LCD_INDEX, par);
757 aty_st_le32(LCD_INDEX, crtc->lcd_index, par);
760 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
763 static int aty_var_to_crtc(const struct fb_info *info,
764 const struct fb_var_screeninfo *var, struct crtc *crtc)
766 struct atyfb_par *par = (struct atyfb_par *) info->par;
767 u32 xres, yres, vxres, vyres, xoffset, yoffset, bpp;
768 u32 sync, vmode, vdisplay;
769 u32 h_total, h_disp, h_sync_strt, h_sync_end, h_sync_dly, h_sync_wid, h_sync_pol;
770 u32 v_total, v_disp, v_sync_strt, v_sync_end, v_sync_wid, v_sync_pol, c_sync;
771 u32 pix_width, dp_pix_width, dp_chain_mask;
776 vxres = var->xres_virtual;
777 vyres = var->yres_virtual;
778 xoffset = var->xoffset;
779 yoffset = var->yoffset;
780 bpp = var->bits_per_pixel;
782 bpp = (var->green.length == 5) ? 15 : 16;
786 /* convert (and round up) and validate */
787 if (vxres < xres + xoffset)
788 vxres = xres + xoffset;
791 if (vyres < yres + yoffset)
792 vyres = yres + yoffset;
797 pix_width = CRTC_PIX_WIDTH_8BPP;
799 HOST_8BPP | SRC_8BPP | DST_8BPP |
800 BYTE_ORDER_LSB_TO_MSB;
801 dp_chain_mask = DP_CHAIN_8BPP;
802 } else if (bpp <= 15) {
804 pix_width = CRTC_PIX_WIDTH_15BPP;
805 dp_pix_width = HOST_15BPP | SRC_15BPP | DST_15BPP |
806 BYTE_ORDER_LSB_TO_MSB;
807 dp_chain_mask = DP_CHAIN_15BPP;
808 } else if (bpp <= 16) {
810 pix_width = CRTC_PIX_WIDTH_16BPP;
811 dp_pix_width = HOST_16BPP | SRC_16BPP | DST_16BPP |
812 BYTE_ORDER_LSB_TO_MSB;
813 dp_chain_mask = DP_CHAIN_16BPP;
814 } else if (bpp <= 24 && M64_HAS(INTEGRATED)) {
816 pix_width = CRTC_PIX_WIDTH_24BPP;
818 HOST_8BPP | SRC_8BPP | DST_8BPP |
819 BYTE_ORDER_LSB_TO_MSB;
820 dp_chain_mask = DP_CHAIN_24BPP;
821 } else if (bpp <= 32) {
823 pix_width = CRTC_PIX_WIDTH_32BPP;
824 dp_pix_width = HOST_32BPP | SRC_32BPP | DST_32BPP |
825 BYTE_ORDER_LSB_TO_MSB;
826 dp_chain_mask = DP_CHAIN_32BPP;
830 if (vxres * vyres * bpp / 8 > info->fix.smem_len)
831 FAIL("not enough video RAM");
833 h_sync_pol = sync & FB_SYNC_HOR_HIGH_ACT ? 0 : 1;
834 v_sync_pol = sync & FB_SYNC_VERT_HIGH_ACT ? 0 : 1;
836 if((xres > 1600) || (yres > 1200)) {
837 FAIL("MACH64 chips are designed for max 1600x1200\n"
838 "select anoter resolution.");
840 h_sync_strt = h_disp + var->right_margin;
841 h_sync_end = h_sync_strt + var->hsync_len;
842 h_sync_dly = var->right_margin & 7;
843 h_total = h_sync_end + h_sync_dly + var->left_margin;
845 v_sync_strt = v_disp + var->lower_margin;
846 v_sync_end = v_sync_strt + var->vsync_len;
847 v_total = v_sync_end + var->upper_margin;
849 #ifdef CONFIG_FB_ATY_GENERIC_LCD
850 if (par->lcd_table != 0) {
851 if(!M64_HAS(LT_LCD_REGS)) {
852 u32 lcd_index = aty_ld_le32(LCD_INDEX, par);
853 crtc->lcd_index = lcd_index &
854 ~(LCD_INDEX_MASK | LCD_DISPLAY_DIS | LCD_SRC_SEL | CRTC2_DISPLAY_DIS);
855 aty_st_le32(LCD_INDEX, lcd_index, par);
858 if (!M64_HAS(MOBIL_BUS))
859 crtc->lcd_index |= CRTC2_DISPLAY_DIS;
861 crtc->lcd_config_panel = aty_ld_lcd(CONFIG_PANEL, par) | 0x4000;
862 crtc->lcd_gen_cntl = aty_ld_lcd(LCD_GEN_CNTL, par) & ~CRTC_RW_SELECT;
864 crtc->lcd_gen_cntl &=
865 ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 | TVCLK_PM_EN |
866 /*VCLK_DAC_PM_EN | USE_SHADOWED_VEND |*/
867 USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
868 crtc->lcd_gen_cntl |= DONT_SHADOW_VPAR | LOCK_8DOT;
870 if((crtc->lcd_gen_cntl & LCD_ON) &&
871 ((xres > par->lcd_width) || (yres > par->lcd_height))) {
872 /* We cannot display the mode on the LCD. If the CRT is enabled
873 we can turn off the LCD.
874 If the CRT is off, it isn't a good idea to switch it on; we don't
875 know if one is connected. So it's better to fail then.
877 if (crtc->lcd_gen_cntl & CRT_ON) {
878 if (!(var->activate & FB_ACTIVATE_TEST))
879 PRINTKI("Disable LCD panel, because video mode does not fit.\n");
880 crtc->lcd_gen_cntl &= ~LCD_ON;
881 /*aty_st_lcd(LCD_GEN_CNTL, crtc->lcd_gen_cntl, par);*/
883 if (!(var->activate & FB_ACTIVATE_TEST))
884 PRINTKE("Video mode exceeds size of LCD panel.\nConnect this computer to a conventional monitor if you really need this mode.\n");
890 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON)) {
892 /* bpp -> bytespp, 1,4 -> 0; 8 -> 2; 15,16 -> 1; 24 -> 6; 32 -> 5
893 const u8 DFP_h_sync_dly_LT[] = { 0, 2, 1, 6, 5 };
894 const u8 ADD_to_strt_wid_and_dly_LT_DAC[] = { 0, 5, 6, 9, 9, 12, 12 }; */
896 vmode &= ~(FB_VMODE_DOUBLE | FB_VMODE_INTERLACED);
898 /* This is horror! When we simulate, say 640x480 on an 800x600
899 LCD monitor, the CRTC should be programmed 800x600 values for
900 the non visible part, but 640x480 for the visible part.
901 This code has been tested on a laptop with it's 1400x1050 LCD
902 monitor and a conventional monitor both switched on.
903 Tested modes: 1280x1024, 1152x864, 1024x768, 800x600,
904 works with little glitches also with DOUBLESCAN modes
906 if (yres < par->lcd_height) {
907 VScan = par->lcd_height / yres;
910 vmode |= FB_VMODE_DOUBLE;
914 h_sync_strt = h_disp + par->lcd_right_margin;
915 h_sync_end = h_sync_strt + par->lcd_hsync_len;
916 h_sync_dly = /*DFP_h_sync_dly[ ( bpp + 1 ) / 3 ]; */par->lcd_hsync_dly;
917 h_total = h_disp + par->lcd_hblank_len;
919 v_sync_strt = v_disp + par->lcd_lower_margin / VScan;
920 v_sync_end = v_sync_strt + par->lcd_vsync_len / VScan;
921 v_total = v_disp + par->lcd_vblank_len / VScan;
923 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
925 h_disp = (h_disp >> 3) - 1;
926 h_sync_strt = (h_sync_strt >> 3) - 1;
927 h_sync_end = (h_sync_end >> 3) - 1;
928 h_total = (h_total >> 3) - 1;
929 h_sync_wid = h_sync_end - h_sync_strt;
931 FAIL_MAX("h_disp too large", h_disp, 0xff);
932 FAIL_MAX("h_sync_strt too large", h_sync_strt, 0x1ff);
933 /*FAIL_MAX("h_sync_wid too large", h_sync_wid, 0x1f);*/
934 if(h_sync_wid > 0x1f)
936 FAIL_MAX("h_total too large", h_total, 0x1ff);
938 if (vmode & FB_VMODE_DOUBLE) {
946 #ifdef CONFIG_FB_ATY_GENERIC_LCD
947 if ((par->lcd_table != 0) && (crtc->lcd_gen_cntl & LCD_ON))
948 vdisplay = par->lcd_height;
955 v_sync_wid = v_sync_end - v_sync_strt;
957 FAIL_MAX("v_disp too large", v_disp, 0x7ff);
958 FAIL_MAX("v_sync_stsrt too large", v_sync_strt, 0x7ff);
959 /*FAIL_MAX("v_sync_wid too large", v_sync_wid, 0x1f);*/
960 if(v_sync_wid > 0x1f)
962 FAIL_MAX("v_total too large", v_total, 0x7ff);
964 c_sync = sync & FB_SYNC_COMP_HIGH_ACT ? CRTC_CSYNC_EN : 0;
969 crtc->xoffset = xoffset;
970 crtc->yoffset = yoffset;
972 crtc->off_pitch = ((yoffset*vxres+xoffset)*bpp/64) | (vxres<<19);
973 crtc->vline_crnt_vline = 0;
975 crtc->h_tot_disp = h_total | (h_disp<<16);
976 crtc->h_sync_strt_wid = (h_sync_strt & 0xff) | (h_sync_dly<<8) |
977 ((h_sync_strt & 0x100)<<4) | (h_sync_wid<<16) | (h_sync_pol<<21);
978 crtc->v_tot_disp = v_total | (v_disp<<16);
979 crtc->v_sync_strt_wid = v_sync_strt | (v_sync_wid<<16) | (v_sync_pol<<21);
981 /* crtc->gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_PRESERVED_MASK; */
982 crtc->gen_cntl = CRTC_EXT_DISP_EN | CRTC_EN | pix_width | c_sync;
983 crtc->gen_cntl |= CRTC_VGA_LINEAR;
985 /* Enable doublescan mode if requested */
986 if (vmode & FB_VMODE_DOUBLE)
987 crtc->gen_cntl |= CRTC_DBL_SCAN_EN;
988 /* Enable interlaced mode if requested */
989 if (vmode & FB_VMODE_INTERLACED)
990 crtc->gen_cntl |= CRTC_INTERLACE_EN;
991 #ifdef CONFIG_FB_ATY_GENERIC_LCD
992 if (par->lcd_table != 0) {
994 if(vmode & FB_VMODE_DOUBLE)
996 crtc->gen_cntl &= ~(CRTC2_EN | CRTC2_PIX_WIDTH);
997 crtc->lcd_gen_cntl &= ~(HORZ_DIVBY2_EN | DIS_HOR_CRT_DIVBY2 |
998 /*TVCLK_PM_EN | VCLK_DAC_PM_EN |*/
999 USE_SHADOWED_VEND | USE_SHADOWED_ROWCUR | SHADOW_EN | SHADOW_RW_EN);
1000 crtc->lcd_gen_cntl |= (DONT_SHADOW_VPAR/* | LOCK_8DOT*/);
1002 /* MOBILITY M1 tested, FIXME: LT */
1003 crtc->horz_stretching = aty_ld_lcd(HORZ_STRETCHING, par);
1004 if (!M64_HAS(LT_LCD_REGS))
1005 crtc->ext_vert_stretch = aty_ld_lcd(EXT_VERT_STRETCH, par) &
1006 ~(AUTO_VERT_RATIO | VERT_STRETCH_MODE | VERT_STRETCH_RATIO3);
1008 crtc->horz_stretching &=
1009 ~(HORZ_STRETCH_RATIO | HORZ_STRETCH_LOOP | AUTO_HORZ_RATIO |
1010 HORZ_STRETCH_MODE | HORZ_STRETCH_EN);
1011 if (xres < par->lcd_width && crtc->lcd_gen_cntl & LCD_ON) {
1014 * The horizontal blender misbehaves when HDisplay is less than a
1015 * a certain threshold (440 for a 1024-wide panel). It doesn't
1016 * stretch such modes enough. Use pixel replication instead of
1017 * blending to stretch modes that can be made to exactly fit the
1018 * panel width. The undocumented "NoLCDBlend" option allows the
1019 * pixel-replicated mode to be slightly wider or narrower than the
1020 * panel width. It also causes a mode that is exactly half as wide
1021 * as the panel to be pixel-replicated, rather than blended.
1023 int HDisplay = xres & ~7;
1024 int nStretch = par->lcd_width / HDisplay;
1025 int Remainder = par->lcd_width % HDisplay;
1027 if ((!Remainder && ((nStretch > 2))) ||
1028 (((HDisplay * 16) / par->lcd_width) < 7)) {
1029 static const char StretchLoops[] = {10, 12, 13, 15, 16};
1030 int horz_stretch_loop = -1, BestRemainder;
1031 int Numerator = HDisplay, Denominator = par->lcd_width;
1033 ATIReduceRatio(&Numerator, &Denominator);
1035 BestRemainder = (Numerator * 16) / Denominator;
1036 while (--Index >= 0) {
1037 Remainder = ((Denominator - Numerator) * StretchLoops[Index]) %
1039 if (Remainder < BestRemainder) {
1040 horz_stretch_loop = Index;
1041 if (!(BestRemainder = Remainder))
1046 if ((horz_stretch_loop >= 0) && !BestRemainder) {
1047 int horz_stretch_ratio = 0, Accumulator = 0;
1048 int reuse_previous = 1;
1050 Index = StretchLoops[horz_stretch_loop];
1052 while (--Index >= 0) {
1053 if (Accumulator > 0)
1054 horz_stretch_ratio |= reuse_previous;
1056 Accumulator += Denominator;
1057 Accumulator -= Numerator;
1058 reuse_previous <<= 1;
1061 crtc->horz_stretching |= (HORZ_STRETCH_EN |
1062 ((horz_stretch_loop & HORZ_STRETCH_LOOP) << 16) |
1063 (horz_stretch_ratio & HORZ_STRETCH_RATIO));
1064 break; /* Out of the do { ... } while (0) */
1068 crtc->horz_stretching |= (HORZ_STRETCH_MODE | HORZ_STRETCH_EN |
1069 (((HDisplay * (HORZ_STRETCH_BLEND + 1)) / par->lcd_width) & HORZ_STRETCH_BLEND));
1073 if (vdisplay < par->lcd_height && crtc->lcd_gen_cntl & LCD_ON) {
1074 crtc->vert_stretching = (VERT_STRETCH_USE0 | VERT_STRETCH_EN |
1075 (((vdisplay * (VERT_STRETCH_RATIO0 + 1)) / par->lcd_height) & VERT_STRETCH_RATIO0));
1077 if (!M64_HAS(LT_LCD_REGS) &&
1078 xres <= (M64_HAS(MOBIL_BUS)?1024:800))
1079 crtc->ext_vert_stretch |= VERT_STRETCH_MODE;
1082 * Don't use vertical blending if the mode is too wide or not
1083 * vertically stretched.
1085 crtc->vert_stretching = 0;
1087 /* copy to shadow crtc */
1088 crtc->shadow_h_tot_disp = crtc->h_tot_disp;
1089 crtc->shadow_h_sync_strt_wid = crtc->h_sync_strt_wid;
1090 crtc->shadow_v_tot_disp = crtc->v_tot_disp;
1091 crtc->shadow_v_sync_strt_wid = crtc->v_sync_strt_wid;
1093 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1095 if (M64_HAS(MAGIC_FIFO)) {
1096 /* FIXME: display FIFO low watermark values */
1097 crtc->gen_cntl |= (aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_FIFO_LWM);
1099 crtc->dp_pix_width = dp_pix_width;
1100 crtc->dp_chain_mask = dp_chain_mask;
1105 static int aty_crtc_to_var(const struct crtc *crtc, struct fb_var_screeninfo *var)
1107 u32 xres, yres, bpp, left, right, upper, lower, hslen, vslen, sync;
1108 u32 h_total, h_disp, h_sync_strt, h_sync_dly, h_sync_wid,
1110 u32 v_total, v_disp, v_sync_strt, v_sync_wid, v_sync_pol, c_sync;
1112 u32 double_scan, interlace;
1115 h_total = crtc->h_tot_disp & 0x1ff;
1116 h_disp = (crtc->h_tot_disp >> 16) & 0xff;
1117 h_sync_strt = (crtc->h_sync_strt_wid & 0xff) | ((crtc->h_sync_strt_wid >> 4) & 0x100);
1118 h_sync_dly = (crtc->h_sync_strt_wid >> 8) & 0x7;
1119 h_sync_wid = (crtc->h_sync_strt_wid >> 16) & 0x1f;
1120 h_sync_pol = (crtc->h_sync_strt_wid >> 21) & 0x1;
1121 v_total = crtc->v_tot_disp & 0x7ff;
1122 v_disp = (crtc->v_tot_disp >> 16) & 0x7ff;
1123 v_sync_strt = crtc->v_sync_strt_wid & 0x7ff;
1124 v_sync_wid = (crtc->v_sync_strt_wid >> 16) & 0x1f;
1125 v_sync_pol = (crtc->v_sync_strt_wid >> 21) & 0x1;
1126 c_sync = crtc->gen_cntl & CRTC_CSYNC_EN ? 1 : 0;
1127 pix_width = crtc->gen_cntl & CRTC_PIX_WIDTH_MASK;
1128 double_scan = crtc->gen_cntl & CRTC_DBL_SCAN_EN;
1129 interlace = crtc->gen_cntl & CRTC_INTERLACE_EN;
1132 xres = (h_disp + 1) * 8;
1134 left = (h_total - h_sync_strt - h_sync_wid) * 8 - h_sync_dly;
1135 right = (h_sync_strt - h_disp) * 8 + h_sync_dly;
1136 hslen = h_sync_wid * 8;
1137 upper = v_total - v_sync_strt - v_sync_wid;
1138 lower = v_sync_strt - v_disp;
1140 sync = (h_sync_pol ? 0 : FB_SYNC_HOR_HIGH_ACT) |
1141 (v_sync_pol ? 0 : FB_SYNC_VERT_HIGH_ACT) |
1142 (c_sync ? FB_SYNC_COMP_HIGH_ACT : 0);
1144 switch (pix_width) {
1146 case CRTC_PIX_WIDTH_4BPP:
1148 var->red.offset = 0;
1149 var->red.length = 8;
1150 var->green.offset = 0;
1151 var->green.length = 8;
1152 var->blue.offset = 0;
1153 var->blue.length = 8;
1154 var->transp.offset = 0;
1155 var->transp.length = 0;
1158 case CRTC_PIX_WIDTH_8BPP:
1160 var->red.offset = 0;
1161 var->red.length = 8;
1162 var->green.offset = 0;
1163 var->green.length = 8;
1164 var->blue.offset = 0;
1165 var->blue.length = 8;
1166 var->transp.offset = 0;
1167 var->transp.length = 0;
1169 case CRTC_PIX_WIDTH_15BPP: /* RGB 555 */
1171 var->red.offset = 10;
1172 var->red.length = 5;
1173 var->green.offset = 5;
1174 var->green.length = 5;
1175 var->blue.offset = 0;
1176 var->blue.length = 5;
1177 var->transp.offset = 0;
1178 var->transp.length = 0;
1180 case CRTC_PIX_WIDTH_16BPP: /* RGB 565 */
1182 var->red.offset = 11;
1183 var->red.length = 5;
1184 var->green.offset = 5;
1185 var->green.length = 6;
1186 var->blue.offset = 0;
1187 var->blue.length = 5;
1188 var->transp.offset = 0;
1189 var->transp.length = 0;
1191 case CRTC_PIX_WIDTH_24BPP: /* RGB 888 */
1193 var->red.offset = 16;
1194 var->red.length = 8;
1195 var->green.offset = 8;
1196 var->green.length = 8;
1197 var->blue.offset = 0;
1198 var->blue.length = 8;
1199 var->transp.offset = 0;
1200 var->transp.length = 0;
1202 case CRTC_PIX_WIDTH_32BPP: /* ARGB 8888 */
1204 var->red.offset = 16;
1205 var->red.length = 8;
1206 var->green.offset = 8;
1207 var->green.length = 8;
1208 var->blue.offset = 0;
1209 var->blue.length = 8;
1210 var->transp.offset = 24;
1211 var->transp.length = 8;
1214 PRINTKE("Invalid pixel width\n");
1221 var->xres_virtual = crtc->vxres;
1222 var->yres_virtual = crtc->vyres;
1223 var->bits_per_pixel = bpp;
1224 var->left_margin = left;
1225 var->right_margin = right;
1226 var->upper_margin = upper;
1227 var->lower_margin = lower;
1228 var->hsync_len = hslen;
1229 var->vsync_len = vslen;
1231 var->vmode = FB_VMODE_NONINTERLACED;
1232 /* In double scan mode, the vertical parameters are doubled, so we need to
1233 half them to get the right values.
1234 In interlaced mode the values are already correct, so no correction is
1238 var->vmode = FB_VMODE_INTERLACED;
1241 var->vmode = FB_VMODE_DOUBLE;
1243 var->upper_margin>>=1;
1244 var->lower_margin>>=1;
1251 /* ------------------------------------------------------------------------- */
1253 static int atyfb_set_par(struct fb_info *info)
1255 struct atyfb_par *par = (struct atyfb_par *) info->par;
1256 struct fb_var_screeninfo *var = &info->var;
1260 struct fb_var_screeninfo debug;
1266 if ((err = aty_var_to_crtc(info, var, &par->crtc)))
1269 pixclock = atyfb_get_pixclock(var, par);
1271 if (pixclock == 0) {
1272 PRINTKE("Invalid pixclock\n");
1275 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &par->pll)))
1279 par->accel_flags = var->accel_flags; /* hack */
1281 if (par->blitter_may_be_busy)
1284 aty_set_crtc(par, &par->crtc);
1285 par->dac_ops->set_dac(info, &par->pll, var->bits_per_pixel, par->accel_flags);
1286 par->pll_ops->set_pll(info, &par->pll);
1289 if(par->pll_ops && par->pll_ops->pll_to_var)
1290 pixclock_in_ps = par->pll_ops->pll_to_var(info, &(par->pll));
1294 if(0 == pixclock_in_ps) {
1295 PRINTKE("ALERT ops->pll_to_var get 0\n");
1296 pixclock_in_ps = pixclock;
1299 memset(&debug, 0, sizeof(debug));
1300 if(!aty_crtc_to_var(&(par->crtc), &debug)) {
1301 u32 hSync, vRefresh;
1302 u32 h_disp, h_sync_strt, h_sync_end, h_total;
1303 u32 v_disp, v_sync_strt, v_sync_end, v_total;
1305 h_disp = debug.xres;
1306 h_sync_strt = h_disp + debug.right_margin;
1307 h_sync_end = h_sync_strt + debug.hsync_len;
1308 h_total = h_sync_end + debug.left_margin;
1309 v_disp = debug.yres;
1310 v_sync_strt = v_disp + debug.lower_margin;
1311 v_sync_end = v_sync_strt + debug.vsync_len;
1312 v_total = v_sync_end + debug.upper_margin;
1314 hSync = 1000000000 / (pixclock_in_ps * h_total);
1315 vRefresh = (hSync * 1000) / v_total;
1316 if (par->crtc.gen_cntl & CRTC_INTERLACE_EN)
1318 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1321 DPRINTK("atyfb_set_par\n");
1322 DPRINTK(" Set Visible Mode to %ix%i-%i\n", var->xres, var->yres, var->bits_per_pixel);
1323 DPRINTK(" Virtual resolution %ix%i, pixclock_in_ps %i (calculated %i)\n",
1324 var->xres_virtual, var->yres_virtual, pixclock, pixclock_in_ps);
1325 DPRINTK(" Dot clock: %i MHz\n", 1000000 / pixclock_in_ps);
1326 DPRINTK(" Horizontal sync: %i kHz\n", hSync);
1327 DPRINTK(" Vertical refresh: %i Hz\n", vRefresh);
1328 DPRINTK(" x style: %i.%03i %i %i %i %i %i %i %i %i\n",
1329 1000000 / pixclock_in_ps, 1000000 % pixclock_in_ps,
1330 h_disp, h_sync_strt, h_sync_end, h_total,
1331 v_disp, v_sync_strt, v_sync_end, v_total);
1332 DPRINTK(" fb style: %i %i %i %i %i %i %i %i %i\n",
1334 debug.left_margin, h_disp, debug.right_margin, debug.hsync_len,
1335 debug.upper_margin, v_disp, debug.lower_margin, debug.vsync_len);
1339 if (!M64_HAS(INTEGRATED)) {
1340 /* Don't forget MEM_CNTL */
1341 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf0ffffff;
1342 switch (var->bits_per_pixel) {
1353 aty_st_le32(MEM_CNTL, tmp, par);
1355 tmp = aty_ld_le32(MEM_CNTL, par) & 0xf00fffff;
1356 if (!M64_HAS(MAGIC_POSTDIV))
1357 tmp |= par->mem_refresh_rate << 20;
1358 switch (var->bits_per_pixel) {
1370 if (M64_HAS(CT_BUS)) {
1371 aty_st_le32(DAC_CNTL, 0x87010184, par);
1372 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1373 } else if (M64_HAS(VT_BUS)) {
1374 aty_st_le32(DAC_CNTL, 0x87010184, par);
1375 aty_st_le32(BUS_CNTL, 0x680000f9, par);
1376 } else if (M64_HAS(MOBIL_BUS)) {
1377 aty_st_le32(DAC_CNTL, 0x80010102, par);
1378 aty_st_le32(BUS_CNTL, 0x7b33a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1381 aty_st_le32(DAC_CNTL, 0x86010102, par);
1382 aty_st_le32(BUS_CNTL, 0x7b23a040 | (par->aux_start ? BUS_APER_REG_DIS : 0), par);
1383 aty_st_le32(EXT_MEM_CNTL, aty_ld_le32(EXT_MEM_CNTL, par) | 0x5000001, par);
1385 aty_st_le32(MEM_CNTL, tmp, par);
1387 aty_st_8(DAC_MASK, 0xff, par);
1389 info->fix.line_length = var->xres_virtual * var->bits_per_pixel/8;
1390 info->fix.visual = var->bits_per_pixel <= 8 ?
1391 FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_DIRECTCOLOR;
1393 /* Initialize the graphics engine */
1394 if (par->accel_flags & FB_ACCELF_TEXT)
1395 aty_init_engine(par, info);
1397 #ifdef CONFIG_BOOTX_TEXT
1398 btext_update_display(info->fix.smem_start,
1399 (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8,
1400 ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1,
1401 var->bits_per_pixel,
1402 par->crtc.vxres * var->bits_per_pixel / 8);
1403 #endif /* CONFIG_BOOTX_TEXT */
1405 /* switch to accelerator mode */
1406 if (!(par->crtc.gen_cntl & CRTC_EXT_DISP_EN))
1407 aty_st_le32(CRTC_GEN_CNTL, par->crtc.gen_cntl | CRTC_EXT_DISP_EN, par);
1411 /* dump non shadow CRTC, pll, LCD registers */
1414 /* CRTC registers */
1416 printk("debug atyfb: Mach64 non-shadow register values:");
1417 for (i = 0; i < 256; i = i+4) {
1418 if(i%16 == 0) printk("\ndebug atyfb: 0x%04X: ", base + i);
1419 printk(" %08X", aty_ld_le32(i, par));
1423 #ifdef CONFIG_FB_ATY_CT
1426 printk("debug atyfb: Mach64 PLL register values:");
1427 for (i = 0; i < 64; i++) {
1428 if(i%16 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1429 if(i%4 == 0) printk(" ");
1430 printk("%02X", aty_ld_pll_ct(i, par));
1433 #endif /* CONFIG_FB_ATY_CT */
1435 #ifdef CONFIG_FB_ATY_GENERIC_LCD
1436 if (par->lcd_table != 0) {
1439 printk("debug atyfb: LCD register values:");
1440 if(M64_HAS(LT_LCD_REGS)) {
1441 for(i = 0; i <= POWER_MANAGEMENT; i++) {
1442 if(i == EXT_VERT_STRETCH)
1444 printk("\ndebug atyfb: 0x%04X: ", lt_lcd_regs[i]);
1445 printk(" %08X", aty_ld_lcd(i, par));
1449 for (i = 0; i < 64; i++) {
1450 if(i%4 == 0) printk("\ndebug atyfb: 0x%02X: ", base + i);
1451 printk(" %08X", aty_ld_lcd(i, par));
1456 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
1462 static int atyfb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
1464 struct atyfb_par *par = (struct atyfb_par *) info->par;
1470 memcpy(&pll, &(par->pll), sizeof(pll));
1472 if((err = aty_var_to_crtc(info, var, &crtc)))
1475 pixclock = atyfb_get_pixclock(var, par);
1477 if (pixclock == 0) {
1478 if (!(var->activate & FB_ACTIVATE_TEST))
1479 PRINTKE("Invalid pixclock\n");
1482 if((err = par->pll_ops->var_to_pll(info, pixclock, var->bits_per_pixel, &pll)))
1486 if (var->accel_flags & FB_ACCELF_TEXT)
1487 info->var.accel_flags = FB_ACCELF_TEXT;
1489 info->var.accel_flags = 0;
1491 #if 0 /* fbmon is not done. uncomment for 2.5.x -brad */
1492 if (!fbmon_valid_timings(pixclock, htotal, vtotal, info))
1495 aty_crtc_to_var(&crtc, var);
1496 var->pixclock = par->pll_ops->pll_to_var(info, &pll);
1500 static void set_off_pitch(struct atyfb_par *par, const struct fb_info *info)
1502 u32 xoffset = info->var.xoffset;
1503 u32 yoffset = info->var.yoffset;
1504 u32 vxres = par->crtc.vxres;
1505 u32 bpp = info->var.bits_per_pixel;
1507 par->crtc.off_pitch = ((yoffset * vxres + xoffset) * bpp / 64) | (vxres << 19);
1512 * Open/Release the frame buffer device
1515 static int atyfb_open(struct fb_info *info, int user)
1517 struct atyfb_par *par = (struct atyfb_par *) info->par;
1528 static irqreturn_t aty_irq(int irq, void *dev_id, struct pt_regs *fp)
1530 struct atyfb_par *par = dev_id;
1534 spin_lock(&par->int_lock);
1536 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par);
1538 if (int_cntl & CRTC_VBLANK_INT) {
1539 /* clear interrupt */
1540 aty_st_le32(CRTC_INT_CNTL, (int_cntl & CRTC_INT_EN_MASK) | CRTC_VBLANK_INT_AK, par);
1541 par->vblank.count++;
1542 if (par->vblank.pan_display) {
1543 par->vblank.pan_display = 0;
1544 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1546 wake_up_interruptible(&par->vblank.wait);
1550 spin_unlock(&par->int_lock);
1552 return IRQ_RETVAL(handled);
1555 static int aty_enable_irq(struct atyfb_par *par, int reenable)
1559 if (!test_and_set_bit(0, &par->irq_flags)) {
1560 if (request_irq(par->irq, aty_irq, SA_SHIRQ, "atyfb", par)) {
1561 clear_bit(0, &par->irq_flags);
1564 spin_lock_irq(&par->int_lock);
1565 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1566 /* clear interrupt */
1567 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_AK, par);
1568 /* enable interrupt */
1569 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par);
1570 spin_unlock_irq(&par->int_lock);
1571 } else if (reenable) {
1572 spin_lock_irq(&par->int_lock);
1573 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1574 if (!(int_cntl & CRTC_VBLANK_INT_EN)) {
1575 printk("atyfb: someone disabled IRQ [%08x]\n", int_cntl);
1576 /* re-enable interrupt */
1577 aty_st_le32(CRTC_INT_CNTL, int_cntl | CRTC_VBLANK_INT_EN, par );
1579 spin_unlock_irq(&par->int_lock);
1585 static int aty_disable_irq(struct atyfb_par *par)
1589 if (test_and_clear_bit(0, &par->irq_flags)) {
1590 if (par->vblank.pan_display) {
1591 par->vblank.pan_display = 0;
1592 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1594 spin_lock_irq(&par->int_lock);
1595 int_cntl = aty_ld_le32(CRTC_INT_CNTL, par) & CRTC_INT_EN_MASK;
1596 /* disable interrupt */
1597 aty_st_le32(CRTC_INT_CNTL, int_cntl & ~CRTC_VBLANK_INT_EN, par );
1598 spin_unlock_irq(&par->int_lock);
1599 free_irq(par->irq, par);
1605 static int atyfb_release(struct fb_info *info, int user)
1607 struct atyfb_par *par = (struct atyfb_par *) info->par;
1614 int was_mmaped = par->mmaped;
1619 struct fb_var_screeninfo var;
1621 /* Now reset the default display config, we have no
1622 * idea what the program(s) which mmap'd the chip did
1623 * to the configuration, nor whether it restored it
1628 var.accel_flags &= ~FB_ACCELF_TEXT;
1630 var.accel_flags |= FB_ACCELF_TEXT;
1631 if (var.yres == var.yres_virtual) {
1632 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
1633 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
1634 if (var.yres_virtual < var.yres)
1635 var.yres_virtual = var.yres;
1639 aty_disable_irq(par);
1646 * Pan or Wrap the Display
1648 * This call looks only at xoffset, yoffset and the FB_VMODE_YWRAP flag
1651 static int atyfb_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
1653 struct atyfb_par *par = (struct atyfb_par *) info->par;
1654 u32 xres, yres, xoffset, yoffset;
1656 xres = (((par->crtc.h_tot_disp >> 16) & 0xff) + 1) * 8;
1657 yres = ((par->crtc.v_tot_disp >> 16) & 0x7ff) + 1;
1658 if (par->crtc.gen_cntl & CRTC_DBL_SCAN_EN)
1660 xoffset = (var->xoffset + 7) & ~7;
1661 yoffset = var->yoffset;
1662 if (xoffset + xres > par->crtc.vxres || yoffset + yres > par->crtc.vyres)
1664 info->var.xoffset = xoffset;
1665 info->var.yoffset = yoffset;
1669 set_off_pitch(par, info);
1670 if ((var->activate & FB_ACTIVATE_VBL) && !aty_enable_irq(par, 0)) {
1671 par->vblank.pan_display = 1;
1673 par->vblank.pan_display = 0;
1674 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1680 static int aty_waitforvblank(struct atyfb_par *par, u32 crtc)
1682 struct aty_interrupt *vbl;
1694 ret = aty_enable_irq(par, 0);
1699 ret = wait_event_interruptible_timeout(vbl->wait, count != vbl->count, HZ/10);
1704 aty_enable_irq(par, 1);
1713 #define ATYIO_CLKR 0x41545900 /* ATY\00 */
1714 #define ATYIO_CLKW 0x41545901 /* ATY\01 */
1720 u8 mclk_post_div; /* 1,2,3,4,8 */
1721 u8 mclk_fb_mult; /* 2 or 4 */
1722 u8 xclk_post_div; /* 1,2,3,4,8 */
1724 u8 vclk_post_div; /* 1,2,3,4,6,8,12 */
1725 u32 dsp_xclks_per_row; /* 0-16383 */
1726 u32 dsp_loop_latency; /* 0-15 */
1727 u32 dsp_precision; /* 0-7 */
1728 u32 dsp_on; /* 0-2047 */
1729 u32 dsp_off; /* 0-2047 */
1732 #define ATYIO_FEATR 0x41545902 /* ATY\02 */
1733 #define ATYIO_FEATW 0x41545903 /* ATY\03 */
1736 #ifndef FBIO_WAITFORVSYNC
1737 #define FBIO_WAITFORVSYNC _IOW('F', 0x20, __u32)
1740 static int atyfb_ioctl(struct inode *inode, struct file *file, u_int cmd,
1741 u_long arg, struct fb_info *info)
1743 struct atyfb_par *par = (struct atyfb_par *) info->par;
1745 struct fbtype fbtyp;
1751 fbtyp.fb_type = FBTYPE_PCI_GENERIC;
1752 fbtyp.fb_width = par->crtc.vxres;
1753 fbtyp.fb_height = par->crtc.vyres;
1754 fbtyp.fb_depth = info->var.bits_per_pixel;
1755 fbtyp.fb_cmsize = info->cmap.len;
1756 fbtyp.fb_size = info->fix.smem_len;
1757 if (copy_to_user((struct fbtype __user *) arg, &fbtyp, sizeof(fbtyp)))
1760 #endif /* __sparc__ */
1762 case FBIO_WAITFORVSYNC:
1766 if (get_user(crtc, (__u32 __user *) arg))
1769 return aty_waitforvblank(par, crtc);
1773 #if defined(DEBUG) && defined(CONFIG_FB_ATY_CT)
1775 if (M64_HAS(INTEGRATED)) {
1777 union aty_pll *pll = &(par->pll);
1778 u32 dsp_config = pll->ct.dsp_config;
1779 u32 dsp_on_off = pll->ct.dsp_on_off;
1780 clk.ref_clk_per = par->ref_clk_per;
1781 clk.pll_ref_div = pll->ct.pll_ref_div;
1782 clk.mclk_fb_div = pll->ct.mclk_fb_div;
1783 clk.mclk_post_div = pll->ct.mclk_post_div_real;
1784 clk.mclk_fb_mult = pll->ct.mclk_fb_mult;
1785 clk.xclk_post_div = pll->ct.xclk_post_div_real;
1786 clk.vclk_fb_div = pll->ct.vclk_fb_div;
1787 clk.vclk_post_div = pll->ct.vclk_post_div_real;
1788 clk.dsp_xclks_per_row = dsp_config & 0x3fff;
1789 clk.dsp_loop_latency = (dsp_config >> 16) & 0xf;
1790 clk.dsp_precision = (dsp_config >> 20) & 7;
1791 clk.dsp_off = dsp_on_off & 0x7ff;
1792 clk.dsp_on = (dsp_on_off >> 16) & 0x7ff;
1793 if (copy_to_user((struct atyclk __user *) arg, &clk,
1800 if (M64_HAS(INTEGRATED)) {
1802 union aty_pll *pll = &(par->pll);
1803 if (copy_from_user(&clk, (struct atyclk __user *) arg, sizeof(clk)))
1805 par->ref_clk_per = clk.ref_clk_per;
1806 pll->ct.pll_ref_div = clk.pll_ref_div;
1807 pll->ct.mclk_fb_div = clk.mclk_fb_div;
1808 pll->ct.mclk_post_div_real = clk.mclk_post_div;
1809 pll->ct.mclk_fb_mult = clk.mclk_fb_mult;
1810 pll->ct.xclk_post_div_real = clk.xclk_post_div;
1811 pll->ct.vclk_fb_div = clk.vclk_fb_div;
1812 pll->ct.vclk_post_div_real = clk.vclk_post_div;
1813 pll->ct.dsp_config = (clk.dsp_xclks_per_row & 0x3fff) |
1814 ((clk.dsp_loop_latency & 0xf)<<16)| ((clk.dsp_precision & 7)<<20);
1815 pll->ct.dsp_on_off = (clk.dsp_off & 0x7ff) | ((clk.dsp_on & 0x7ff)<<16);
1816 /*aty_calc_pll_ct(info, &pll->ct);*/
1817 aty_set_pll_ct(info, pll);
1822 if (get_user(par->features, (u32 __user *) arg))
1826 if (put_user(par->features, (u32 __user *) arg))
1829 #endif /* DEBUG && CONFIG_FB_ATY_CT */
1836 static int atyfb_sync(struct fb_info *info)
1838 struct atyfb_par *par = (struct atyfb_par *) info->par;
1840 if (par->blitter_may_be_busy)
1846 static int atyfb_mmap(struct fb_info *info, struct file *file, struct vm_area_struct *vma)
1848 struct atyfb_par *par = (struct atyfb_par *) info->par;
1849 unsigned int size, page, map_size = 0;
1850 unsigned long map_offset = 0;
1857 if (vma->vm_pgoff > (~0UL >> PAGE_SHIFT))
1860 off = vma->vm_pgoff << PAGE_SHIFT;
1861 size = vma->vm_end - vma->vm_start;
1863 /* To stop the swapper from even considering these pages. */
1864 vma->vm_flags |= (VM_IO | VM_RESERVED);
1866 if (((vma->vm_pgoff == 0) && (size == info->fix.smem_len)) ||
1867 ((off == info->fix.smem_len) && (size == PAGE_SIZE)))
1868 off += 0x8000000000000000UL;
1870 vma->vm_pgoff = off >> PAGE_SHIFT; /* propagate off changes */
1872 /* Each page, see which map applies */
1873 for (page = 0; page < size;) {
1875 for (i = 0; par->mmap_map[i].size; i++) {
1876 unsigned long start = par->mmap_map[i].voff;
1877 unsigned long end = start + par->mmap_map[i].size;
1878 unsigned long offset = off + page;
1885 map_size = par->mmap_map[i].size - (offset - start);
1887 par->mmap_map[i].poff + (offset - start);
1894 if (page + map_size > size)
1895 map_size = size - page;
1897 pgprot_val(vma->vm_page_prot) &=
1898 ~(par->mmap_map[i].prot_mask);
1899 pgprot_val(vma->vm_page_prot) |= par->mmap_map[i].prot_flag;
1901 if (remap_pfn_range(vma, vma->vm_start + page,
1902 map_offset >> PAGE_SHIFT, map_size, vma->vm_page_prot))
1923 static void atyfb_save_palette(struct atyfb_par *par, int enter)
1927 for (i = 0; i < 256; i++) {
1928 tmp = aty_ld_8(DAC_CNTL, par) & 0xfc;
1929 if (M64_HAS(EXTRA_BRIGHT))
1931 aty_st_8(DAC_CNTL, tmp, par);
1932 aty_st_8(DAC_MASK, 0xff, par);
1934 writeb(i, &par->aty_cmap_regs->rindex);
1935 atyfb_save.r[enter][i] = readb(&par->aty_cmap_regs->lut);
1936 atyfb_save.g[enter][i] = readb(&par->aty_cmap_regs->lut);
1937 atyfb_save.b[enter][i] = readb(&par->aty_cmap_regs->lut);
1938 writeb(i, &par->aty_cmap_regs->windex);
1939 writeb(atyfb_save.r[1 - enter][i],
1940 &par->aty_cmap_regs->lut);
1941 writeb(atyfb_save.g[1 - enter][i],
1942 &par->aty_cmap_regs->lut);
1943 writeb(atyfb_save.b[1 - enter][i],
1944 &par->aty_cmap_regs->lut);
1948 static void atyfb_palette(int enter)
1950 struct atyfb_par *par;
1951 struct fb_info *info;
1954 for (i = 0; i < FB_MAX; i++) {
1955 info = registered_fb[i];
1956 if (info && info->fbops == &atyfb_ops) {
1957 par = (struct atyfb_par *) info->par;
1959 atyfb_save_palette(par, enter);
1961 atyfb_save.yoffset = info->var.yoffset;
1962 info->var.yoffset = 0;
1963 set_off_pitch(par, info);
1965 info->var.yoffset = atyfb_save.yoffset;
1966 set_off_pitch(par, info);
1968 aty_st_le32(CRTC_OFF_PITCH, par->crtc.off_pitch, par);
1973 #endif /* __sparc__ */
1977 #if defined(CONFIG_PM) && defined(CONFIG_PCI)
1979 /* Power management routines. Those are used for PowerBook sleep.
1981 static int aty_power_mgmt(int sleep, struct atyfb_par *par)
1986 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1987 pm = (pm & ~PWR_MGT_MODE_MASK) | PWR_MGT_MODE_REG;
1988 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1989 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1995 aty_st_lcd(POWER_MANAGEMENT, pm, par);
1996 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
1998 pm &= ~(PWR_BLON | AUTO_PWR_UP);
2000 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2001 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2004 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2006 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2008 if ((--timeout) == 0)
2010 } while ((pm & PWR_MGT_STATUS_MASK) != PWR_MGT_STATUS_SUSPEND);
2014 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2015 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2018 pm |= (PWR_BLON | AUTO_PWR_UP);
2019 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2020 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2023 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2025 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2027 if ((--timeout) == 0)
2029 } while ((pm & PWR_MGT_STATUS_MASK) != 0);
2033 return timeout ? 0 : -EIO;
2036 static int atyfb_pci_suspend(struct pci_dev *pdev, pm_message_t state)
2038 struct fb_info *info = pci_get_drvdata(pdev);
2039 struct atyfb_par *par = (struct atyfb_par *) info->par;
2041 #ifndef CONFIG_PPC_PMAC
2042 /* HACK ALERT ! Once I find a proper way to say to each driver
2043 * individually what will happen with it's PCI slot, I'll change
2044 * that. On laptops, the AGP slot is just unclocked, so D2 is
2045 * expected, while on desktops, the card is powered off
2048 #endif /* CONFIG_PPC_PMAC */
2050 if (state.event == pdev->dev.power.power_state.event)
2053 acquire_console_sem();
2055 fb_set_suspend(info, 1);
2057 /* Idle & reset engine */
2059 aty_reset_engine(par);
2061 /* Blank display and LCD */
2062 atyfb_blank(FB_BLANK_POWERDOWN, info);
2065 par->lock_blank = 1;
2067 /* Set chip to "suspend" mode */
2068 if (aty_power_mgmt(1, par)) {
2070 par->lock_blank = 0;
2071 atyfb_blank(FB_BLANK_UNBLANK, info);
2072 fb_set_suspend(info, 0);
2073 release_console_sem();
2077 release_console_sem();
2079 pdev->dev.power.power_state = state;
2084 static int atyfb_pci_resume(struct pci_dev *pdev)
2086 struct fb_info *info = pci_get_drvdata(pdev);
2087 struct atyfb_par *par = (struct atyfb_par *) info->par;
2089 if (pdev->dev.power.power_state.event == PM_EVENT_ON)
2092 acquire_console_sem();
2094 if (pdev->dev.power.power_state.event == 2)
2095 aty_power_mgmt(0, par);
2098 /* Restore display */
2099 atyfb_set_par(info);
2102 fb_set_suspend(info, 0);
2105 par->lock_blank = 0;
2106 atyfb_blank(FB_BLANK_UNBLANK, info);
2108 release_console_sem();
2110 pdev->dev.power.power_state = PMSG_ON;
2115 #endif /* defined(CONFIG_PM) && defined(CONFIG_PCI) */
2117 #ifdef CONFIG_PMAC_BACKLIGHT
2120 * LCD backlight control
2123 static int backlight_conv[] = {
2124 0x00, 0x3f, 0x4c, 0x59, 0x66, 0x73, 0x80, 0x8d,
2125 0x9a, 0xa7, 0xb4, 0xc1, 0xcf, 0xdc, 0xe9, 0xff
2128 static int aty_set_backlight_enable(int on, int level, void *data)
2130 struct fb_info *info = (struct fb_info *) data;
2131 struct atyfb_par *par = (struct atyfb_par *) info->par;
2132 unsigned int reg = aty_ld_lcd(LCD_MISC_CNTL, par);
2134 reg |= (BLMOD_EN | BIASMOD_EN);
2135 if (on && level > BACKLIGHT_OFF) {
2136 reg &= ~BIAS_MOD_LEVEL_MASK;
2137 reg |= (backlight_conv[level] << BIAS_MOD_LEVEL_SHIFT);
2139 reg &= ~BIAS_MOD_LEVEL_MASK;
2140 reg |= (backlight_conv[0] << BIAS_MOD_LEVEL_SHIFT);
2142 aty_st_lcd(LCD_MISC_CNTL, reg, par);
2146 static int aty_set_backlight_level(int level, void *data)
2148 return aty_set_backlight_enable(1, level, data);
2151 static struct backlight_controller aty_backlight_controller = {
2152 aty_set_backlight_enable,
2153 aty_set_backlight_level
2155 #endif /* CONFIG_PMAC_BACKLIGHT */
2157 static void __init aty_calc_mem_refresh(struct atyfb_par *par, int xclk)
2159 const int ragepro_tbl[] = {
2160 44, 50, 55, 66, 75, 80, 100
2162 const int ragexl_tbl[] = {
2163 50, 66, 75, 83, 90, 95, 100, 105,
2164 110, 115, 120, 125, 133, 143, 166
2166 const int *refresh_tbl;
2169 if (IS_XL(par->pci_id) || IS_MOBILITY(par->pci_id)) {
2170 refresh_tbl = ragexl_tbl;
2171 size = sizeof(ragexl_tbl)/sizeof(int);
2173 refresh_tbl = ragepro_tbl;
2174 size = sizeof(ragepro_tbl)/sizeof(int);
2177 for (i=0; i < size; i++) {
2178 if (xclk < refresh_tbl[i])
2181 par->mem_refresh_rate = i;
2188 static struct fb_info *fb_list = NULL;
2190 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2191 static int __devinit atyfb_get_timings_from_lcd(struct atyfb_par *par,
2192 struct fb_var_screeninfo *var)
2196 if (par->lcd_table != 0 && (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2198 var->xres = var->xres_virtual = par->lcd_hdisp;
2199 var->right_margin = par->lcd_right_margin;
2200 var->left_margin = par->lcd_hblank_len -
2201 (par->lcd_right_margin + par->lcd_hsync_dly +
2202 par->lcd_hsync_len);
2203 var->hsync_len = par->lcd_hsync_len + par->lcd_hsync_dly;
2204 var->yres = var->yres_virtual = par->lcd_vdisp;
2205 var->lower_margin = par->lcd_lower_margin;
2206 var->upper_margin = par->lcd_vblank_len -
2207 (par->lcd_lower_margin + par->lcd_vsync_len);
2208 var->vsync_len = par->lcd_vsync_len;
2209 var->pixclock = par->lcd_pixclock;
2215 #endif /* defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD) */
2217 static int __init aty_init(struct fb_info *info, const char *name)
2219 struct atyfb_par *par = (struct atyfb_par *) info->par;
2220 const char *ramname = NULL, *xtal;
2221 int gtb_memsize, has_var = 0;
2222 struct fb_var_screeninfo var;
2225 #if defined(CONFIG_PPC)
2229 init_waitqueue_head(&par->vblank.wait);
2230 spin_lock_init(&par->int_lock);
2232 par->aty_cmap_regs =
2233 (struct aty_cmap_regs __iomem *) (par->ati_regbase + 0xc0);
2235 #ifdef CONFIG_PPC_PMAC
2236 /* The Apple iBook1 uses non-standard memory frequencies. We detect it
2237 * and set the frequency manually. */
2238 if (machine_is_compatible("PowerBook2,1")) {
2239 par->pll_limits.mclk = 70;
2240 par->pll_limits.xclk = 53;
2244 par->pll_limits.pll_max = pll;
2246 par->pll_limits.mclk = mclk;
2248 par->pll_limits.xclk = xclk;
2250 aty_calc_mem_refresh(par, par->pll_limits.xclk);
2251 par->pll_per = 1000000/par->pll_limits.pll_max;
2252 par->mclk_per = 1000000/par->pll_limits.mclk;
2253 par->xclk_per = 1000000/par->pll_limits.xclk;
2255 par->ref_clk_per = 1000000000000ULL / 14318180;
2258 #ifdef CONFIG_FB_ATY_GX
2259 if (!M64_HAS(INTEGRATED)) {
2261 u8 dac_type, dac_subtype, clk_type;
2262 stat0 = aty_ld_le32(CONFIG_STAT0, par);
2263 par->bus_type = (stat0 >> 0) & 0x07;
2264 par->ram_type = (stat0 >> 3) & 0x07;
2265 ramname = aty_gx_ram[par->ram_type];
2266 /* FIXME: clockchip/RAMDAC probing? */
2267 dac_type = (aty_ld_le32(DAC_CNTL, par) >> 16) & 0x07;
2269 clk_type = CLK_ATI18818_1;
2270 dac_type = (stat0 >> 9) & 0x07;
2271 if (dac_type == 0x07)
2272 dac_subtype = DAC_ATT20C408;
2274 dac_subtype = (aty_ld_8(SCRATCH_REG1 + 1, par) & 0xF0) | dac_type;
2276 dac_type = DAC_IBMRGB514;
2277 dac_subtype = DAC_IBMRGB514;
2278 clk_type = CLK_IBMRGB514;
2280 switch (dac_subtype) {
2282 par->dac_ops = &aty_dac_ibm514;
2284 case DAC_ATI68860_B:
2285 case DAC_ATI68860_C:
2286 par->dac_ops = &aty_dac_ati68860b;
2290 par->dac_ops = &aty_dac_att21c498;
2293 PRINTKI("aty_init: DAC type not implemented yet!\n");
2294 par->dac_ops = &aty_dac_unsupported;
2298 case CLK_ATI18818_1:
2299 par->pll_ops = &aty_pll_ati18818_1;
2302 par->pll_ops = &aty_pll_stg1703;
2305 par->pll_ops = &aty_pll_ch8398;
2308 par->pll_ops = &aty_pll_att20c408;
2311 par->pll_ops = &aty_pll_ibm514;
2314 PRINTKI("aty_init: CLK type not implemented yet!");
2315 par->pll_ops = &aty_pll_unsupported;
2319 #endif /* CONFIG_FB_ATY_GX */
2320 #ifdef CONFIG_FB_ATY_CT
2321 if (M64_HAS(INTEGRATED)) {
2322 par->dac_ops = &aty_dac_ct;
2323 par->pll_ops = &aty_pll_ct;
2324 par->bus_type = PCI;
2325 par->ram_type = (aty_ld_le32(CONFIG_STAT0, par) & 0x07);
2326 ramname = aty_ct_ram[par->ram_type];
2327 /* for many chips, the mclk is 67 MHz for SDRAM, 63 MHz otherwise */
2328 if (par->pll_limits.mclk == 67 && par->ram_type < SDRAM)
2329 par->pll_limits.mclk = 63;
2332 if (M64_HAS(GTB_DSP)
2333 && (pll_ref_div = aty_ld_pll_ct(PLL_REF_DIV, par))) {
2335 diff1 = 510 * 14 / pll_ref_div - par->pll_limits.pll_max;
2336 diff2 = 510 * 29 / pll_ref_div - par->pll_limits.pll_max;
2341 if (diff2 < diff1) {
2342 par->ref_clk_per = 1000000000000ULL / 29498928;
2346 #endif /* CONFIG_FB_ATY_CT */
2348 /* save previous video mode */
2349 aty_get_crtc(par, &saved_crtc);
2350 if(par->pll_ops->get_pll)
2351 par->pll_ops->get_pll(info, &saved_pll);
2353 i = aty_ld_le32(MEM_CNTL, par);
2354 gtb_memsize = M64_HAS(GTB_DSP);
2356 switch (i & 0xF) { /* 0xF used instead of MEM_SIZE_ALIAS */
2358 info->fix.smem_len = 0x80000;
2361 info->fix.smem_len = 0x100000;
2363 case MEM_SIZE_2M_GTB:
2364 info->fix.smem_len = 0x200000;
2366 case MEM_SIZE_4M_GTB:
2367 info->fix.smem_len = 0x400000;
2369 case MEM_SIZE_6M_GTB:
2370 info->fix.smem_len = 0x600000;
2372 case MEM_SIZE_8M_GTB:
2373 info->fix.smem_len = 0x800000;
2376 info->fix.smem_len = 0x80000;
2378 switch (i & MEM_SIZE_ALIAS) {
2380 info->fix.smem_len = 0x80000;
2383 info->fix.smem_len = 0x100000;
2386 info->fix.smem_len = 0x200000;
2389 info->fix.smem_len = 0x400000;
2392 info->fix.smem_len = 0x600000;
2395 info->fix.smem_len = 0x800000;
2398 info->fix.smem_len = 0x80000;
2401 if (M64_HAS(MAGIC_VRAM_SIZE)) {
2402 if (aty_ld_le32(CONFIG_STAT1, par) & 0x40000000)
2403 info->fix.smem_len += 0x400000;
2407 info->fix.smem_len = vram * 1024;
2408 i = i & ~(gtb_memsize ? 0xF : MEM_SIZE_ALIAS);
2409 if (info->fix.smem_len <= 0x80000)
2411 else if (info->fix.smem_len <= 0x100000)
2413 else if (info->fix.smem_len <= 0x200000)
2414 i |= gtb_memsize ? MEM_SIZE_2M_GTB : MEM_SIZE_2M;
2415 else if (info->fix.smem_len <= 0x400000)
2416 i |= gtb_memsize ? MEM_SIZE_4M_GTB : MEM_SIZE_4M;
2417 else if (info->fix.smem_len <= 0x600000)
2418 i |= gtb_memsize ? MEM_SIZE_6M_GTB : MEM_SIZE_6M;
2420 i |= gtb_memsize ? MEM_SIZE_8M_GTB : MEM_SIZE_8M;
2421 aty_st_le32(MEM_CNTL, i, par);
2425 * Reg Block 0 (CT-compatible block) is at mmio_start
2426 * Reg Block 1 (multimedia extensions) is at mmio_start - 0x400
2429 info->fix.mmio_len = 0x400;
2430 info->fix.accel = FB_ACCEL_ATI_MACH64GX;
2431 } else if (M64_HAS(CT)) {
2432 info->fix.mmio_len = 0x400;
2433 info->fix.accel = FB_ACCEL_ATI_MACH64CT;
2434 } else if (M64_HAS(VT)) {
2435 info->fix.mmio_start -= 0x400;
2436 info->fix.mmio_len = 0x800;
2437 info->fix.accel = FB_ACCEL_ATI_MACH64VT;
2439 info->fix.mmio_start -= 0x400;
2440 info->fix.mmio_len = 0x800;
2441 info->fix.accel = FB_ACCEL_ATI_MACH64GT;
2444 PRINTKI("%d%c %s, %s MHz XTAL, %d MHz PLL, %d Mhz MCLK, %d MHz XCLK\n",
2445 info->fix.smem_len == 0x80000 ? 512 : (info->fix.smem_len >> 20),
2446 info->fix.smem_len == 0x80000 ? 'K' : 'M', ramname, xtal, par->pll_limits.pll_max,
2447 par->pll_limits.mclk, par->pll_limits.xclk);
2449 #if defined(DEBUG) && defined(CONFIG_ATY_CT)
2450 if (M64_HAS(INTEGRATED)) {
2452 printk("debug atyfb: BUS_CNTL DAC_CNTL MEM_CNTL EXT_MEM_CNTL CRTC_GEN_CNTL "
2453 "DSP_CONFIG DSP_ON_OFF CLOCK_CNTL\n"
2454 "debug atyfb: %08x %08x %08x %08x %08x %08x %08x %08x\n"
2456 aty_ld_le32(BUS_CNTL, par), aty_ld_le32(DAC_CNTL, par),
2457 aty_ld_le32(MEM_CNTL, par), aty_ld_le32(EXT_MEM_CNTL, par),
2458 aty_ld_le32(CRTC_GEN_CNTL, par), aty_ld_le32(DSP_CONFIG, par),
2459 aty_ld_le32(DSP_ON_OFF, par), aty_ld_le32(CLOCK_CNTL, par));
2460 for (i = 0; i < 40; i++)
2461 printk(" %02x", aty_ld_pll_ct(i, par));
2465 if(par->pll_ops->init_pll)
2466 par->pll_ops->init_pll(info, &par->pll);
2469 * Last page of 8 MB (4 MB on ISA) aperture is MMIO
2470 * FIXME: we should use the auxiliary aperture instead so we can access
2471 * the full 8 MB of video RAM on 8 MB boards
2474 if (!par->aux_start &&
2475 (info->fix.smem_len == 0x800000 || (par->bus_type == ISA && info->fix.smem_len == 0x400000)))
2476 info->fix.smem_len -= GUI_RESERVE;
2479 * Disable register access through the linear aperture
2480 * if the auxiliary aperture is used so we can access
2481 * the full 8 MB of video RAM on 8 MB boards.
2484 aty_st_le32(BUS_CNTL, aty_ld_le32(BUS_CNTL, par) | BUS_APER_REG_DIS, par);
2487 par->mtrr_aper = -1;
2490 /* Cover the whole resource. */
2491 par->mtrr_aper = mtrr_add(par->res_start, par->res_size, MTRR_TYPE_WRCOMB, 1);
2492 if (par->mtrr_aper >= 0 && !par->aux_start) {
2493 /* Make a hole for mmio. */
2494 par->mtrr_reg = mtrr_add(par->res_start + 0x800000 - GUI_RESERVE,
2495 GUI_RESERVE, MTRR_TYPE_UNCACHABLE, 1);
2496 if (par->mtrr_reg < 0) {
2497 mtrr_del(par->mtrr_aper, 0, 0);
2498 par->mtrr_aper = -1;
2504 info->fbops = &atyfb_ops;
2505 info->pseudo_palette = pseudo_palette;
2506 info->flags = FBINFO_FLAG_DEFAULT;
2508 #ifdef CONFIG_PMAC_BACKLIGHT
2509 if (M64_HAS(G3_PB_1_1) && machine_is_compatible("PowerBook1,1")) {
2510 /* these bits let the 101 powerbook wake up from sleep -- paulus */
2511 aty_st_lcd(POWER_MANAGEMENT, aty_ld_lcd(POWER_MANAGEMENT, par)
2512 | (USE_F32KHZ | TRISTATE_MEM_EN), par);
2513 } else if (M64_HAS(MOBIL_BUS))
2514 register_backlight_controller(&aty_backlight_controller, info, "ati");
2515 #endif /* CONFIG_PMAC_BACKLIGHT */
2517 memset(&var, 0, sizeof(var));
2519 if (_machine == _MACH_Pmac) {
2521 * FIXME: The NVRAM stuff should be put in a Mac-specific file, as it
2522 * applies to all Mac video cards
2525 if (mac_find_mode(&var, info, mode, 8))
2528 if (default_vmode == VMODE_CHOOSE) {
2529 if (M64_HAS(G3_PB_1024x768))
2530 /* G3 PowerBook with 1024x768 LCD */
2531 default_vmode = VMODE_1024_768_60;
2532 else if (machine_is_compatible("iMac"))
2533 default_vmode = VMODE_1024_768_75;
2534 else if (machine_is_compatible
2536 /* iBook with 800x600 LCD */
2537 default_vmode = VMODE_800_600_60;
2539 default_vmode = VMODE_640_480_67;
2540 sense = read_aty_sense(par);
2541 PRINTKI("monitor sense=%x, mode %d\n",
2542 sense, mac_map_monitor_sense(sense));
2544 if (default_vmode <= 0 || default_vmode > VMODE_MAX)
2545 default_vmode = VMODE_640_480_60;
2546 if (default_cmode < CMODE_8 || default_cmode > CMODE_32)
2547 default_cmode = CMODE_8;
2548 if (!mac_vmode_to_var(default_vmode, default_cmode,
2554 #endif /* !CONFIG_PPC */
2556 #if defined(__i386__) && defined(CONFIG_FB_ATY_GENERIC_LCD)
2557 if (!atyfb_get_timings_from_lcd(par, &var))
2561 if (mode && fb_find_mode(&var, info, mode, NULL, 0, &defmode, 8))
2568 var.accel_flags &= ~FB_ACCELF_TEXT;
2570 var.accel_flags |= FB_ACCELF_TEXT;
2572 if (comp_sync != -1) {
2574 var.sync &= ~FB_SYNC_COMP_HIGH_ACT;
2576 var.sync |= FB_SYNC_COMP_HIGH_ACT;
2579 if (var.yres == var.yres_virtual) {
2580 u32 videoram = (info->fix.smem_len - (PAGE_SIZE << 2));
2581 var.yres_virtual = ((videoram * 8) / var.bits_per_pixel) / var.xres_virtual;
2582 if (var.yres_virtual < var.yres)
2583 var.yres_virtual = var.yres;
2586 if (atyfb_check_var(&var, info)) {
2587 PRINTKE("can't set default video mode\n");
2592 atyfb_save_palette(par, 0);
2595 #ifdef CONFIG_FB_ATY_CT
2596 if (!noaccel && M64_HAS(INTEGRATED))
2597 aty_init_cursor(info);
2598 #endif /* CONFIG_FB_ATY_CT */
2601 fb_alloc_cmap(&info->cmap, 256, 0);
2603 if (register_framebuffer(info) < 0)
2608 PRINTKI("fb%d: %s frame buffer device on %s\n",
2609 info->node, info->fix.id, name);
2613 /* restore video mode */
2614 aty_set_crtc(par, &saved_crtc);
2615 par->pll_ops->set_pll(info, &saved_pll);
2618 if (par->mtrr_reg >= 0) {
2619 mtrr_del(par->mtrr_reg, 0, 0);
2622 if (par->mtrr_aper >= 0) {
2623 mtrr_del(par->mtrr_aper, 0, 0);
2624 par->mtrr_aper = -1;
2631 static int __init store_video_par(char *video_str, unsigned char m64_num)
2634 unsigned long vmembase, size, guiregbase;
2636 PRINTKI("store_video_par() '%s' \n", video_str);
2638 if (!(p = strsep(&video_str, ";")) || !*p)
2639 goto mach64_invalid;
2640 vmembase = simple_strtoul(p, NULL, 0);
2641 if (!(p = strsep(&video_str, ";")) || !*p)
2642 goto mach64_invalid;
2643 size = simple_strtoul(p, NULL, 0);
2644 if (!(p = strsep(&video_str, ";")) || !*p)
2645 goto mach64_invalid;
2646 guiregbase = simple_strtoul(p, NULL, 0);
2648 phys_vmembase[m64_num] = vmembase;
2649 phys_size[m64_num] = size;
2650 phys_guiregbase[m64_num] = guiregbase;
2651 PRINTKI("stored them all: $%08lX $%08lX $%08lX \n", vmembase, size,
2656 phys_vmembase[m64_num] = 0;
2659 #endif /* CONFIG_ATARI */
2662 * Blank the display.
2665 static int atyfb_blank(int blank, struct fb_info *info)
2667 struct atyfb_par *par = (struct atyfb_par *) info->par;
2670 if (par->lock_blank || par->asleep)
2673 #ifdef CONFIG_PMAC_BACKLIGHT
2674 if ((_machine == _MACH_Pmac) && blank > FB_BLANK_NORMAL)
2675 set_backlight_enable(0);
2676 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2677 if (par->lcd_table && blank > FB_BLANK_NORMAL &&
2678 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2679 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2681 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2685 gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2687 case FB_BLANK_UNBLANK:
2688 gen_cntl &= ~0x400004c;
2690 case FB_BLANK_NORMAL:
2691 gen_cntl |= 0x4000040;
2693 case FB_BLANK_VSYNC_SUSPEND:
2694 gen_cntl |= 0x4000048;
2696 case FB_BLANK_HSYNC_SUSPEND:
2697 gen_cntl |= 0x4000044;
2699 case FB_BLANK_POWERDOWN:
2700 gen_cntl |= 0x400004c;
2703 aty_st_le32(CRTC_GEN_CNTL, gen_cntl, par);
2705 #ifdef CONFIG_PMAC_BACKLIGHT
2706 if ((_machine == _MACH_Pmac) && blank <= FB_BLANK_NORMAL)
2707 set_backlight_enable(1);
2708 #elif defined(CONFIG_FB_ATY_GENERIC_LCD)
2709 if (par->lcd_table && blank <= FB_BLANK_NORMAL &&
2710 (aty_ld_lcd(LCD_GEN_CNTL, par) & LCD_ON)) {
2711 u32 pm = aty_ld_lcd(POWER_MANAGEMENT, par);
2713 aty_st_lcd(POWER_MANAGEMENT, pm, par);
2720 static void aty_st_pal(u_int regno, u_int red, u_int green, u_int blue,
2721 const struct atyfb_par *par)
2724 out_8(&par->aty_cmap_regs->windex, regno);
2725 out_8(&par->aty_cmap_regs->lut, red);
2726 out_8(&par->aty_cmap_regs->lut, green);
2727 out_8(&par->aty_cmap_regs->lut, blue);
2729 writeb(regno, &par->aty_cmap_regs->windex);
2730 writeb(red, &par->aty_cmap_regs->lut);
2731 writeb(green, &par->aty_cmap_regs->lut);
2732 writeb(blue, &par->aty_cmap_regs->lut);
2737 * Set a single color register. The values supplied are already
2738 * rounded down to the hardware's capabilities (according to the
2739 * entries in the var structure). Return != 0 for invalid regno.
2740 * !! 4 & 8 = PSEUDO, > 8 = DIRECTCOLOR
2743 static int atyfb_setcolreg(u_int regno, u_int red, u_int green, u_int blue,
2744 u_int transp, struct fb_info *info)
2746 struct atyfb_par *par = (struct atyfb_par *) info->par;
2748 u32 *pal = info->pseudo_palette;
2750 depth = info->var.bits_per_pixel;
2752 depth = (info->var.green.length == 5) ? 15 : 16;
2758 (depth == 16 && regno > 63) ||
2759 (depth == 15 && regno > 31))
2766 par->palette[regno].red = red;
2767 par->palette[regno].green = green;
2768 par->palette[regno].blue = blue;
2773 pal[regno] = (regno << 10) | (regno << 5) | regno;
2776 pal[regno] = (regno << 11) | (regno << 5) | regno;
2779 pal[regno] = (regno << 16) | (regno << 8) | regno;
2782 i = (regno << 8) | regno;
2783 pal[regno] = (i << 16) | i;
2788 i = aty_ld_8(DAC_CNTL, par) & 0xfc;
2789 if (M64_HAS(EXTRA_BRIGHT))
2790 i |= 0x2; /* DAC_CNTL | 0x2 turns off the extra brightness for gt */
2791 aty_st_8(DAC_CNTL, i, par);
2792 aty_st_8(DAC_MASK, 0xff, par);
2794 if (M64_HAS(INTEGRATED)) {
2797 aty_st_pal(regno << 3, red,
2798 par->palette[regno<<1].green,
2800 red = par->palette[regno>>1].red;
2801 blue = par->palette[regno>>1].blue;
2803 } else if (depth == 15) {
2805 for(i = 0; i < 8; i++) {
2806 aty_st_pal(regno + i, red, green, blue, par);
2810 aty_st_pal(regno, red, green, blue, par);
2819 extern void (*prom_palette) (int);
2821 static int __devinit atyfb_setup_sparc(struct pci_dev *pdev,
2822 struct fb_info *info, unsigned long addr)
2824 extern int con_is_present(void);
2826 struct atyfb_par *par = info->par;
2827 struct pcidev_cookie *pcp;
2829 int node, len, i, j, ret;
2832 /* Do not attach when we have a serial console. */
2833 if (!con_is_present())
2837 * Map memory-mapped registers.
2839 par->ati_regbase = (void *)addr + 0x7ffc00UL;
2840 info->fix.mmio_start = addr + 0x7ffc00UL;
2843 * Map in big-endian aperture.
2845 info->screen_base = (char *) (addr + 0x800000UL);
2846 info->fix.smem_start = addr + 0x800000UL;
2849 * Figure mmap addresses from PCI config space.
2850 * Split Framebuffer in big- and little-endian halfs.
2852 for (i = 0; i < 6 && pdev->resource[i].start; i++)
2856 par->mmap_map = kmalloc(j * sizeof(*par->mmap_map), GFP_ATOMIC);
2857 if (!par->mmap_map) {
2858 PRINTKE("atyfb_setup_sparc() can't alloc mmap_map\n");
2861 memset(par->mmap_map, 0, j * sizeof(*par->mmap_map));
2863 for (i = 0, j = 2; i < 6 && pdev->resource[i].start; i++) {
2864 struct resource *rp = &pdev->resource[i];
2865 int io, breg = PCI_BASE_ADDRESS_0 + (i << 2);
2871 io = (rp->flags & IORESOURCE_IO);
2873 size = rp->end - base + 1;
2875 pci_read_config_dword(pdev, breg, &pbase);
2881 * Map the framebuffer a second time, this time without
2882 * the braindead _PAGE_IE setting. This is used by the
2883 * fixed Xserver, but we need to maintain the old mapping
2884 * to stay compatible with older ones...
2887 par->mmap_map[j].voff = (pbase + 0x10000000) & PAGE_MASK;
2888 par->mmap_map[j].poff = base & PAGE_MASK;
2889 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2890 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2891 par->mmap_map[j].prot_flag = _PAGE_E;
2896 * Here comes the old framebuffer mapping with _PAGE_IE
2897 * set for the big endian half of the framebuffer...
2900 par->mmap_map[j].voff = (pbase + 0x800000) & PAGE_MASK;
2901 par->mmap_map[j].poff = (base + 0x800000) & PAGE_MASK;
2902 par->mmap_map[j].size = 0x800000;
2903 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2904 par->mmap_map[j].prot_flag = _PAGE_E | _PAGE_IE;
2909 par->mmap_map[j].voff = pbase & PAGE_MASK;
2910 par->mmap_map[j].poff = base & PAGE_MASK;
2911 par->mmap_map[j].size = (size + ~PAGE_MASK) & PAGE_MASK;
2912 par->mmap_map[j].prot_mask = _PAGE_CACHE;
2913 par->mmap_map[j].prot_flag = _PAGE_E;
2917 if((ret = correct_chipset(par)))
2920 if (IS_XL(pdev->device)) {
2922 * Fix PROMs idea of MEM_CNTL settings...
2924 mem = aty_ld_le32(MEM_CNTL, par);
2925 chip_id = aty_ld_le32(CONFIG_CHIP_ID, par);
2926 if (((chip_id & CFG_CHIP_TYPE) == VT_CHIP_ID) && !((chip_id >> 24) & 1)) {
2927 switch (mem & 0x0f) {
2929 mem = (mem & ~(0x0f)) | 2;
2932 mem = (mem & ~(0x0f)) | 3;
2935 mem = (mem & ~(0x0f)) | 4;
2938 mem = (mem & ~(0x0f)) | 5;
2943 if ((aty_ld_le32(CONFIG_STAT0, par) & 7) >= SDRAM)
2944 mem &= ~(0x00700000);
2946 mem &= ~(0xcf80e000); /* Turn off all undocumented bits. */
2947 aty_st_le32(MEM_CNTL, mem, par);
2951 * If this is the console device, we will set default video
2952 * settings to what the PROM left us with.
2954 node = prom_getchild(prom_root_node);
2955 node = prom_searchsiblings(node, "aliases");
2957 len = prom_getproperty(node, "screen", prop, sizeof(prop));
2960 node = prom_finddevice(prop);
2965 pcp = pdev->sysdata;
2966 if (node == pcp->prom_node) {
2967 struct fb_var_screeninfo *var = &default_var;
2968 unsigned int N, P, Q, M, T, R;
2969 u32 v_total, h_total;
2974 crtc.vxres = prom_getintdefault(node, "width", 1024);
2975 crtc.vyres = prom_getintdefault(node, "height", 768);
2976 var->bits_per_pixel = prom_getintdefault(node, "depth", 8);
2977 var->xoffset = var->yoffset = 0;
2978 crtc.h_tot_disp = aty_ld_le32(CRTC_H_TOTAL_DISP, par);
2979 crtc.h_sync_strt_wid = aty_ld_le32(CRTC_H_SYNC_STRT_WID, par);
2980 crtc.v_tot_disp = aty_ld_le32(CRTC_V_TOTAL_DISP, par);
2981 crtc.v_sync_strt_wid = aty_ld_le32(CRTC_V_SYNC_STRT_WID, par);
2982 crtc.gen_cntl = aty_ld_le32(CRTC_GEN_CNTL, par);
2983 aty_crtc_to_var(&crtc, var);
2985 h_total = var->xres + var->right_margin + var->hsync_len + var->left_margin;
2986 v_total = var->yres + var->lower_margin + var->vsync_len + var->upper_margin;
2989 * Read the PLL to figure actual Refresh Rate.
2991 clock_cntl = aty_ld_8(CLOCK_CNTL, par);
2992 /* DPRINTK("CLOCK_CNTL %02x\n", clock_cntl); */
2993 for (i = 0; i < 16; i++)
2994 pll_regs[i] = aty_ld_pll_ct(i, par);
2997 * PLL Reference Divider M:
3002 * PLL Feedback Divider N (Dependant on CLOCK_CNTL):
3004 N = pll_regs[7 + (clock_cntl & 3)];
3007 * PLL Post Divider P (Dependant on CLOCK_CNTL):
3009 P = 1 << (pll_regs[6] >> ((clock_cntl & 3) << 1));
3023 * where R is XTALIN (= 14318 or 29498 kHz).
3025 if (IS_XL(pdev->device))
3032 default_var.pixclock = 1000000000 / T;
3038 #else /* __sparc__ */
3041 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3042 static void aty_init_lcd(struct atyfb_par *par, u32 bios_base)
3044 u32 driv_inf_tab, sig;
3047 /* To support an LCD panel, we should know it's dimensions and
3048 * it's desired pixel clock.
3049 * There are two ways to do it:
3050 * - Check the startup video mode and calculate the panel
3051 * size from it. This is unreliable.
3052 * - Read it from the driver information table in the video BIOS.
3054 /* Address of driver information table is at offset 0x78. */
3055 driv_inf_tab = bios_base + *((u16 *)(bios_base+0x78));
3057 /* Check for the driver information table signature. */
3058 sig = (*(u32 *)driv_inf_tab);
3059 if ((sig == 0x54504c24) || /* Rage LT pro */
3060 (sig == 0x544d5224) || /* Rage mobility */
3061 (sig == 0x54435824) || /* Rage XC */
3062 (sig == 0x544c5824)) { /* Rage XL */
3063 PRINTKI("BIOS contains driver information table.\n");
3064 lcd_ofs = (*(u16 *)(driv_inf_tab + 10));
3067 par->lcd_table = bios_base + lcd_ofs;
3071 if (par->lcd_table != 0) {
3074 char refresh_rates_buf[100];
3075 int id, tech, f, i, m, default_refresh_rate;
3080 u16 width, height, panel_type, refresh_rates;
3083 u8 lcd_refresh_rates[16] = {50,56,60,67,70,72,75,76,85,90,100,120,140,150,160,200};
3084 /* The most important information is the panel size at
3085 * offset 25 and 27, but there's some other nice information
3086 * which we print to the screen.
3088 id = *(u8 *)par->lcd_table;
3089 strncpy(model,(char *)par->lcd_table+1,24);
3092 width = par->lcd_width = *(u16 *)(par->lcd_table+25);
3093 height = par->lcd_height = *(u16 *)(par->lcd_table+27);
3094 panel_type = *(u16 *)(par->lcd_table+29);
3096 txtcolour = "colour";
3098 txtcolour = "monochrome";
3100 txtdual = "dual (split) ";
3103 tech = (panel_type>>2) & 63;
3106 txtmonitor = "passive matrix";
3109 txtmonitor = "active matrix";
3112 txtmonitor = "active addressed STN";
3118 txtmonitor = "plasma";
3121 txtmonitor = "unknown";
3123 format = *(u32 *)(par->lcd_table+57);
3124 if (tech == 0 || tech == 2) {
3125 switch (format & 7) {
3127 txtformat = "12 bit interface";
3130 txtformat = "16 bit interface";
3133 txtformat = "24 bit interface";
3136 txtformat = "unkown format";
3139 switch (format & 7) {
3141 txtformat = "8 colours";
3144 txtformat = "512 colours";
3147 txtformat = "4096 colours";
3150 txtformat = "262144 colours (LT mode)";
3153 txtformat = "16777216 colours";
3156 txtformat = "262144 colours (FDPI-2 mode)";
3159 txtformat = "unkown format";
3162 PRINTKI("%s%s %s monitor detected: %s\n",
3163 txtdual ,txtcolour, txtmonitor, model);
3164 PRINTKI(" id=%d, %dx%d pixels, %s\n",
3165 id, width, height, txtformat);
3166 refresh_rates_buf[0] = 0;
3167 refresh_rates = *(u16 *)(par->lcd_table+62);
3170 for (i=0;i<16;i++) {
3171 if (refresh_rates & m) {
3173 sprintf(strbuf, "%d", lcd_refresh_rates[i]);
3176 sprintf(strbuf, ",%d", lcd_refresh_rates[i]);
3178 strcat(refresh_rates_buf,strbuf);
3182 default_refresh_rate = (*(u8 *)(par->lcd_table+61) & 0xf0) >> 4;
3183 PRINTKI(" supports refresh rates [%s], default %d Hz\n",
3184 refresh_rates_buf, lcd_refresh_rates[default_refresh_rate]);
3185 par->lcd_refreshrate = lcd_refresh_rates[default_refresh_rate];
3186 /* We now need to determine the crtc parameters for the
3187 * LCD monitor. This is tricky, because they are not stored
3188 * individually in the BIOS. Instead, the BIOS contains a
3189 * table of display modes that work for this monitor.
3191 * The idea is that we search for a mode of the same dimensions
3192 * as the dimensions of the LCD monitor. Say our LCD monitor
3193 * is 800x600 pixels, we search for a 800x600 monitor.
3194 * The CRTC parameters we find here are the ones that we need
3195 * to use to simulate other resolutions on the LCD screen.
3197 lcdmodeptr = (u16 *)(par->lcd_table + 64);
3198 while (*lcdmodeptr != 0) {
3200 u16 mwidth, mheight, lcd_hsync_start, lcd_vsync_start;
3201 modeptr = bios_base + *lcdmodeptr;
3203 mwidth = *((u16 *)(modeptr+0));
3204 mheight = *((u16 *)(modeptr+2));
3206 if (mwidth == width && mheight == height) {
3207 par->lcd_pixclock = 100000000 / *((u16 *)(modeptr+9));
3208 par->lcd_htotal = *((u16 *)(modeptr+17)) & 511;
3209 par->lcd_hdisp = *((u16 *)(modeptr+19)) & 511;
3210 lcd_hsync_start = *((u16 *)(modeptr+21)) & 511;
3211 par->lcd_hsync_dly = (*((u16 *)(modeptr+21)) >> 9) & 7;
3212 par->lcd_hsync_len = *((u8 *)(modeptr+23)) & 63;
3214 par->lcd_vtotal = *((u16 *)(modeptr+24)) & 2047;
3215 par->lcd_vdisp = *((u16 *)(modeptr+26)) & 2047;
3216 lcd_vsync_start = *((u16 *)(modeptr+28)) & 2047;
3217 par->lcd_vsync_len = (*((u16 *)(modeptr+28)) >> 11) & 31;
3219 par->lcd_htotal = (par->lcd_htotal + 1) * 8;
3220 par->lcd_hdisp = (par->lcd_hdisp + 1) * 8;
3221 lcd_hsync_start = (lcd_hsync_start + 1) * 8;
3222 par->lcd_hsync_len = par->lcd_hsync_len * 8;
3228 par->lcd_right_margin = lcd_hsync_start - par->lcd_hdisp;
3229 par->lcd_lower_margin = lcd_vsync_start - par->lcd_vdisp;
3230 par->lcd_hblank_len = par->lcd_htotal - par->lcd_hdisp;
3231 par->lcd_vblank_len = par->lcd_vtotal - par->lcd_vdisp;
3237 if (*lcdmodeptr == 0) {
3238 PRINTKE("LCD monitor CRTC parameters not found!!!\n");
3239 /* To do: Switch to CRT if possible. */
3241 PRINTKI(" LCD CRTC parameters: %d.%d %d %d %d %d %d %d %d %d\n",
3242 1000000 / par->lcd_pixclock, 1000000 % par->lcd_pixclock,
3244 par->lcd_hdisp + par->lcd_right_margin,
3245 par->lcd_hdisp + par->lcd_right_margin
3246 + par->lcd_hsync_dly + par->lcd_hsync_len,
3249 par->lcd_vdisp + par->lcd_lower_margin,
3250 par->lcd_vdisp + par->lcd_lower_margin + par->lcd_vsync_len,
3252 PRINTKI(" : %d %d %d %d %d %d %d %d %d\n",
3254 par->lcd_hblank_len - (par->lcd_right_margin +
3255 par->lcd_hsync_dly + par->lcd_hsync_len),
3257 par->lcd_right_margin,
3259 par->lcd_vblank_len - (par->lcd_lower_margin + par->lcd_vsync_len),
3261 par->lcd_lower_margin,
3262 par->lcd_vsync_len);
3266 #endif /* CONFIG_FB_ATY_GENERIC_LCD */
3268 static int __devinit init_from_bios(struct atyfb_par *par)
3270 u32 bios_base, rom_addr;
3273 rom_addr = 0xc0000 + ((aty_ld_le32(SCRATCH_REG1, par) & 0x7f) << 11);
3274 bios_base = (unsigned long)ioremap(rom_addr, 0x10000);
3276 /* The BIOS starts with 0xaa55. */
3277 if (*((u16 *)bios_base) == 0xaa55) {
3280 u16 rom_table_offset, freq_table_offset;
3281 PLL_BLOCK_MACH64 pll_block;
3283 PRINTKI("Mach64 BIOS is located at %x, mapped at %x.\n", rom_addr, bios_base);
3285 /* check for frequncy table */
3286 bios_ptr = (u8*)bios_base;
3287 rom_table_offset = (u16)(bios_ptr[0x48] | (bios_ptr[0x49] << 8));
3288 freq_table_offset = bios_ptr[rom_table_offset + 16] | (bios_ptr[rom_table_offset + 17] << 8);
3289 memcpy(&pll_block, bios_ptr + freq_table_offset, sizeof(PLL_BLOCK_MACH64));
3291 PRINTKI("BIOS frequency table:\n");
3292 PRINTKI("PCLK_min_freq %d, PCLK_max_freq %d, ref_freq %d, ref_divider %d\n",
3293 pll_block.PCLK_min_freq, pll_block.PCLK_max_freq,
3294 pll_block.ref_freq, pll_block.ref_divider);
3295 PRINTKI("MCLK_pwd %d, MCLK_max_freq %d, XCLK_max_freq %d, SCLK_freq %d\n",
3296 pll_block.MCLK_pwd, pll_block.MCLK_max_freq,
3297 pll_block.XCLK_max_freq, pll_block.SCLK_freq);
3299 par->pll_limits.pll_min = pll_block.PCLK_min_freq/100;
3300 par->pll_limits.pll_max = pll_block.PCLK_max_freq/100;
3301 par->pll_limits.ref_clk = pll_block.ref_freq/100;
3302 par->pll_limits.ref_div = pll_block.ref_divider;
3303 par->pll_limits.sclk = pll_block.SCLK_freq/100;
3304 par->pll_limits.mclk = pll_block.MCLK_max_freq/100;
3305 par->pll_limits.mclk_pm = pll_block.MCLK_pwd/100;
3306 par->pll_limits.xclk = pll_block.XCLK_max_freq/100;
3307 #ifdef CONFIG_FB_ATY_GENERIC_LCD
3308 aty_init_lcd(par, bios_base);
3312 PRINTKE("no BIOS frequency table found, use parameters\n");
3315 iounmap((void* __iomem )bios_base);
3319 #endif /* __i386__ */
3321 static int __devinit atyfb_setup_generic(struct pci_dev *pdev, struct fb_info *info, unsigned long addr)
3323 struct atyfb_par *par = info->par;
3325 unsigned long raddr;
3326 struct resource *rrp;
3329 raddr = addr + 0x7ff000UL;
3330 rrp = &pdev->resource[2];
3331 if ((rrp->flags & IORESOURCE_MEM) && request_mem_region(rrp->start, rrp->end - rrp->start + 1, "atyfb")) {
3332 par->aux_start = rrp->start;
3333 par->aux_size = rrp->end - rrp->start + 1;
3335 PRINTKI("using auxiliary register aperture\n");
3338 info->fix.mmio_start = raddr;
3339 par->ati_regbase = ioremap(info->fix.mmio_start, 0x1000);
3340 if (par->ati_regbase == 0)
3343 info->fix.mmio_start += par->aux_start ? 0x400 : 0xc00;
3344 par->ati_regbase += par->aux_start ? 0x400 : 0xc00;
3347 * Enable memory-space accesses using config-space
3350 pci_read_config_word(pdev, PCI_COMMAND, &tmp);
3351 if (!(tmp & PCI_COMMAND_MEMORY)) {
3352 tmp |= PCI_COMMAND_MEMORY;
3353 pci_write_config_word(pdev, PCI_COMMAND, tmp);
3356 /* Use the big-endian aperture */
3360 /* Map in frame buffer */
3361 info->fix.smem_start = addr;
3362 info->screen_base = ioremap(addr, 0x800000);
3363 if (info->screen_base == NULL) {
3365 goto atyfb_setup_generic_fail;
3368 if((ret = correct_chipset(par)))
3369 goto atyfb_setup_generic_fail;
3371 if((ret = init_from_bios(par)))
3372 goto atyfb_setup_generic_fail;
3374 if (!(aty_ld_le32(CRTC_GEN_CNTL, par) & CRTC_EXT_DISP_EN))
3375 par->clk_wr_offset = (inb(R_GENMO) & 0x0CU) >> 2;
3377 par->clk_wr_offset = aty_ld_8(CLOCK_CNTL, par) & 0x03U;
3379 /* according to ATI, we should use clock 3 for acelerated mode */
3380 par->clk_wr_offset = 3;
3384 atyfb_setup_generic_fail:
3385 iounmap(par->ati_regbase);
3386 par->ati_regbase = NULL;
3390 #endif /* !__sparc__ */
3392 static int __devinit atyfb_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
3394 unsigned long addr, res_start, res_size;
3395 struct fb_info *info;
3396 struct resource *rp;
3397 struct atyfb_par *par;
3398 int i, rc = -ENOMEM;
3400 for (i = sizeof(aty_chips) / sizeof(*aty_chips) - 1; i >= 0; i--)
3401 if (pdev->device == aty_chips[i].pci_id)
3407 /* Enable device in PCI config */
3408 if (pci_enable_device(pdev)) {
3409 PRINTKE("Cannot enable PCI device\n");
3413 /* Find which resource to use */
3414 rp = &pdev->resource[0];
3415 if (rp->flags & IORESOURCE_IO)
3416 rp = &pdev->resource[1];
3422 res_start = rp->start;
3423 res_size = rp->end - rp->start + 1;
3424 if (!request_mem_region (res_start, res_size, "atyfb"))
3427 /* Allocate framebuffer */
3428 info = framebuffer_alloc(sizeof(struct atyfb_par), &pdev->dev);
3430 PRINTKE("atyfb_pci_probe() can't alloc fb_info\n");
3434 info->fix = atyfb_fix;
3435 info->device = &pdev->dev;
3436 par->pci_id = aty_chips[i].pci_id;
3437 par->res_start = res_start;
3438 par->res_size = res_size;
3439 par->irq = pdev->irq;
3441 /* Setup "info" structure */
3443 rc = atyfb_setup_sparc(pdev, info, addr);
3445 rc = atyfb_setup_generic(pdev, info, addr);
3448 goto err_release_mem;
3450 pci_set_drvdata(pdev, info);
3452 /* Init chip & register framebuffer */
3453 if (aty_init(info, "PCI"))
3454 goto err_release_io;
3458 prom_palette = atyfb_palette;
3461 * Add /dev/fb mmap values.
3463 par->mmap_map[0].voff = 0x8000000000000000UL;
3464 par->mmap_map[0].poff = (unsigned long) info->screen_base & PAGE_MASK;
3465 par->mmap_map[0].size = info->fix.smem_len;
3466 par->mmap_map[0].prot_mask = _PAGE_CACHE;
3467 par->mmap_map[0].prot_flag = _PAGE_E;
3468 par->mmap_map[1].voff = par->mmap_map[0].voff + info->fix.smem_len;
3469 par->mmap_map[1].poff = (long)par->ati_regbase & PAGE_MASK;
3470 par->mmap_map[1].size = PAGE_SIZE;
3471 par->mmap_map[1].prot_mask = _PAGE_CACHE;
3472 par->mmap_map[1].prot_flag = _PAGE_E;
3473 #endif /* __sparc__ */
3479 kfree(par->mmap_map);
3481 if (par->ati_regbase)
3482 iounmap(par->ati_regbase);
3483 if (info->screen_base)
3484 iounmap(info->screen_base);
3488 release_mem_region(par->aux_start, par->aux_size);
3490 release_mem_region(par->res_start, par->res_size);
3491 framebuffer_release(info);
3496 #endif /* CONFIG_PCI */
3500 static int __devinit atyfb_atari_probe(void)
3502 struct aty_par *par;
3503 struct fb_info *info;
3507 for (m64_num = 0; m64_num < mach64_count; m64_num++) {
3508 if (!phys_vmembase[m64_num] || !phys_size[m64_num] ||
3509 !phys_guiregbase[m64_num]) {
3510 PRINTKI("phys_*[%d] parameters not set => returning early. \n", m64_num);
3514 info = framebuffer_alloc(sizeof(struct atyfb_par), NULL);
3516 PRINTKE("atyfb_atari_probe() can't alloc fb_info\n");
3521 info->fix = atyfb_fix;
3523 par->irq = (unsigned int) -1; /* something invalid */
3526 * Map the video memory (physical address given) to somewhere in the
3527 * kernel address space.
3529 info->screen_base = ioremap(phys_vmembase[m64_num], phys_size[m64_num]);
3530 info->fix.smem_start = (unsigned long)info->screen_base; /* Fake! */
3531 par->ati_regbase = ioremap(phys_guiregbase[m64_num], 0x10000) +
3533 info->fix.mmio_start = (unsigned long)par->ati_regbase; /* Fake! */
3535 aty_st_le32(CLOCK_CNTL, 0x12345678, par);
3536 clock_r = aty_ld_le32(CLOCK_CNTL, par);
3538 switch (clock_r & 0x003F) {
3540 par->clk_wr_offset = 3; /* */
3543 par->clk_wr_offset = 2; /* Medusa ST-IO ISA Adapter etc. */
3546 par->clk_wr_offset = 1; /* */
3549 par->clk_wr_offset = 0; /* Panther 1 ISA Adapter (Gerald) */
3553 if (aty_init(info, "ISA bus")) {
3554 framebuffer_release(info);
3555 /* This is insufficient! kernel_map has added two large chunks!! */
3561 #endif /* CONFIG_ATARI */
3563 static void __devexit atyfb_remove(struct fb_info *info)
3565 struct atyfb_par *par = (struct atyfb_par *) info->par;
3567 /* restore video mode */
3568 aty_set_crtc(par, &saved_crtc);
3569 par->pll_ops->set_pll(info, &saved_pll);
3571 unregister_framebuffer(info);
3574 if (par->mtrr_reg >= 0) {
3575 mtrr_del(par->mtrr_reg, 0, 0);
3578 if (par->mtrr_aper >= 0) {
3579 mtrr_del(par->mtrr_aper, 0, 0);
3580 par->mtrr_aper = -1;
3584 if (par->ati_regbase)
3585 iounmap(par->ati_regbase);
3586 if (info->screen_base)
3587 iounmap(info->screen_base);
3589 if (info->sprite.addr)
3590 iounmap(info->sprite.addr);
3594 kfree(par->mmap_map);
3597 release_mem_region(par->aux_start, par->aux_size);
3600 release_mem_region(par->res_start, par->res_size);
3602 framebuffer_release(info);
3607 static void __devexit atyfb_pci_remove(struct pci_dev *pdev)
3609 struct fb_info *info = pci_get_drvdata(pdev);
3615 * This driver uses its own matching table. That will be more difficult
3616 * to fix, so for now, we just match against any ATI ID and let the
3617 * probe() function find out what's up. That also mean we don't have
3618 * a module ID table though.
3620 static struct pci_device_id atyfb_pci_tbl[] = {
3621 { PCI_VENDOR_ID_ATI, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
3622 PCI_BASE_CLASS_DISPLAY << 16, 0xff0000, 0 },
3626 static struct pci_driver atyfb_driver = {
3628 .id_table = atyfb_pci_tbl,
3629 .probe = atyfb_pci_probe,
3630 .remove = __devexit_p(atyfb_pci_remove),
3632 .suspend = atyfb_pci_suspend,
3633 .resume = atyfb_pci_resume,
3634 #endif /* CONFIG_PM */
3637 #endif /* CONFIG_PCI */
3640 static int __init atyfb_setup(char *options)
3644 if (!options || !*options)
3647 while ((this_opt = strsep(&options, ",")) != NULL) {
3648 if (!strncmp(this_opt, "noaccel", 7)) {
3651 } else if (!strncmp(this_opt, "nomtrr", 6)) {
3654 } else if (!strncmp(this_opt, "vram:", 5))
3655 vram = simple_strtoul(this_opt + 5, NULL, 0);
3656 else if (!strncmp(this_opt, "pll:", 4))
3657 pll = simple_strtoul(this_opt + 4, NULL, 0);
3658 else if (!strncmp(this_opt, "mclk:", 5))
3659 mclk = simple_strtoul(this_opt + 5, NULL, 0);
3660 else if (!strncmp(this_opt, "xclk:", 5))
3661 xclk = simple_strtoul(this_opt+5, NULL, 0);
3662 else if (!strncmp(this_opt, "comp_sync:", 10))
3663 comp_sync = simple_strtoul(this_opt+10, NULL, 0);
3665 else if (!strncmp(this_opt, "vmode:", 6)) {
3666 unsigned int vmode =
3667 simple_strtoul(this_opt + 6, NULL, 0);
3668 if (vmode > 0 && vmode <= VMODE_MAX)
3669 default_vmode = vmode;
3670 } else if (!strncmp(this_opt, "cmode:", 6)) {
3671 unsigned int cmode =
3672 simple_strtoul(this_opt + 6, NULL, 0);
3676 default_cmode = CMODE_8;
3680 default_cmode = CMODE_16;
3684 default_cmode = CMODE_32;
3691 * Why do we need this silly Mach64 argument?
3692 * We are already here because of mach64= so its redundant.
3694 else if (MACH_IS_ATARI
3695 && (!strncmp(this_opt, "Mach64:", 7))) {
3696 static unsigned char m64_num;
3697 static char mach64_str[80];
3698 strlcpy(mach64_str, this_opt + 7, sizeof(mach64_str));
3699 if (!store_video_par(mach64_str, m64_num)) {
3701 mach64_count = m64_num;
3712 static int __init atyfb_init(void)
3715 char *option = NULL;
3717 if (fb_get_options("atyfb", &option))
3719 atyfb_setup(option);
3722 pci_register_driver(&atyfb_driver);
3724 atyfb_atari_probe();
3729 static void __exit atyfb_exit(void)
3731 pci_unregister_driver(&atyfb_driver);
3734 module_init(atyfb_init);
3735 module_exit(atyfb_exit);
3737 MODULE_DESCRIPTION("FBDev driver for ATI Mach64 cards");
3738 MODULE_LICENSE("GPL");
3739 module_param(noaccel, bool, 0);
3740 MODULE_PARM_DESC(noaccel, "bool: disable acceleration");
3741 module_param(vram, int, 0);
3742 MODULE_PARM_DESC(vram, "int: override size of video ram");
3743 module_param(pll, int, 0);
3744 MODULE_PARM_DESC(pll, "int: override video clock");
3745 module_param(mclk, int, 0);
3746 MODULE_PARM_DESC(mclk, "int: override memory clock");
3747 module_param(xclk, int, 0);
3748 MODULE_PARM_DESC(xclk, "int: override accelerated engine clock");
3749 module_param(comp_sync, int, 0);
3750 MODULE_PARM_DESC(comp_sync,
3751 "Set composite sync signal to low (0) or high (1)");
3752 module_param(mode, charp, 0);
3753 MODULE_PARM_DESC(mode, "Specify resolution as \"<xres>x<yres>[-<bpp>][@<refresh>]\" ");
3755 module_param(nomtrr, bool, 0);
3756 MODULE_PARM_DESC(nomtrr, "bool: disable use of MTRR registers");