SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8192su/r8192S_rtl6052.c

   1 /******************************************************************************
   2  *
   3  *     (c) Copyright  2008, RealTEK Technologies Inc. All Rights Reserved.
   4  *
   5  * Module:      HalRf6052.c     ( Source C File)
   6  *
   7  * Note:        Provide RF 6052 series relative API.
   8  *
   9  * Function:
  10  *
  11  * Export:
  12  *
  13  * Abbrev:
  14  *
  15  * History:
  16  * Data                 Who             Remark
  17  *
  18  * 09/25/2008   MHC             Create initial version.
  19  * 11/05/2008   MHC             Add API for tw power setting.
  20  *
  21  *
  22 ******************************************************************************/
  23 #include "r8192U.h"
  24 #include "r8192S_rtl6052.h"
  25
  26 #include "r8192S_hw.h"
  27 #include "r8192S_phyreg.h"
  28 #include "r8192S_phy.h"
  29
  30
  31 /*---------------------------Define Local Constant---------------------------*/
  32 // Define local structure for debug!!!!!
  33 typedef struct RF_Shadow_Compare_Map {
  34         // Shadow register value
  35         u32             Value;
  36         // Compare or not flag
  37         u8              Compare;
  38         // Record If it had ever modified unpredicted
  39         u8              ErrorOrNot;
  40         // Recorver Flag
  41         u8              Recorver;
  42         //
  43         u8              Driver_Write;
  44 }RF_SHADOW_T;
  45 /*---------------------------Define Local Constant---------------------------*/
  46
  47
  48 /*------------------------Define global variable-----------------------------*/
  49 /*------------------------Define global variable-----------------------------*/
  50
  51
  52
  53
  54 /*---------------------Define local function prototype-----------------------*/
  55 void phy_RF6052_Config_HardCode(struct net_device* dev);
  56
  57 RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev);
  58 /*---------------------Define local function prototype-----------------------*/
  59
  60 /*------------------------Define function prototype--------------------------*/
  61 extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate);
  62
  63 /*------------------------Define function prototype--------------------------*/
  64
  65 /*------------------------Define local variable------------------------------*/
  66 // 2008/11/20 MH For Debug only, RF
  67 static  RF_SHADOW_T     RF_Shadow[RF6052_MAX_PATH][RF6052_MAX_REG];// = {{0}};//FIXLZM
  68 /*------------------------Define local variable------------------------------*/
  69
  70 /*------------------------Define function prototype--------------------------*/
  71 /*-----------------------------------------------------------------------------
  72  * Function:    RF_ChangeTxPath
  73  *
  74  * Overview:    For RL6052, we must change some RF settign for 1T or 2T.
  75  *
  76  * Input:               u16 DataRate            // 0x80-8f, 0x90-9f
  77  *
  78  * Output:      NONE
  79  *
  80  * Return:      NONE
  81  *
  82  * Revised History:
  83  * When                 Who             Remark
  84  * 09/25/2008   MHC             Create Version 0.
  85  *                                              Firmwaer support the utility later.
  86  *
  87  *---------------------------------------------------------------------------*/
  88 extern void RF_ChangeTxPath(struct net_device* dev,  u16 DataRate)
  89 {
  90 }       /* RF_ChangeTxPath */
  91
  92
  93 /*-----------------------------------------------------------------------------
  94  * Function:    PHY_RF6052SetBandwidth()
  95  *
  96  * Overview:    This function is called by SetBWModeCallback8190Pci() only
  97  *
  98  * Input:       PADAPTER                                Adapter
  99  *                      WIRELESS_BANDWIDTH_E    Bandwidth       //20M or 40M
 100  *
 101  * Output:      NONE
 102  *
 103  * Return:      NONE
 104  *
 105  * Note:                For RF type 0222D
 106  *---------------------------------------------------------------------------*/
 107 void PHY_RF6052SetBandwidth(struct net_device* dev, HT_CHANNEL_WIDTH Bandwidth) //20M or 40M
 108 {
 109         //u8                            eRFPath;
 110         //struct r8192_priv     *priv = ieee80211_priv(dev);
 111
 112
 113         //if (priv->card_8192 == NIC_8192SE)
 114         {
 115                 switch(Bandwidth)
 116                 {
 117                         case HT_CHANNEL_WIDTH_20:
 118                                 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
 119                                 //      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x58);
 120
 121                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x01);
 122                                 break;
 123                         case HT_CHANNEL_WIDTH_20_40:
 124                                 //if (priv->card_8192_version >= VERSION_8192S_BCUT)
 125                                 //      rtl8192_setBBreg(dev, rFPGA0_AnalogParameter2, 0xff, 0x18);
 126
 127                                 rtl8192_phy_SetRFReg(dev, (RF90_RADIO_PATH_E)RF90_PATH_A, RF_CHNLBW, BIT10|BIT11, 0x00);
 128                                 break;
 129                         default:
 130                                 RT_TRACE(COMP_DBG, "PHY_SetRF6052Bandwidth(): unknown Bandwidth: %#X\n",Bandwidth);
 131                                 break;
 132                 }
 133         }
 134 //      else
 135 }
 136
 137
 138 /*-----------------------------------------------------------------------------
 139  * Function:    PHY_RF6052SetCckTxPower
 140  *
 141  * Overview:
 142  *
 143  * Input:       NONE
 144  *
 145  * Output:      NONE
 146  *
 147  * Return:      NONE
 148  *
 149  * Revised History:
 150  * When                 Who             Remark
 151  * 11/05/2008   MHC             Simulate 8192series..
 152  *
 153  *---------------------------------------------------------------------------*/
 154 extern void PHY_RF6052SetCckTxPower(struct net_device* dev, u8  powerlevel)
 155 {
 156         struct r8192_priv *priv = ieee80211_priv(dev);
 157         u32                             TxAGC=0;
 158
 159         if(priv->ieee80211->scanning == 1)
 160                 TxAGC = 0x3f;
 161         else if(priv->bDynamicTxLowPower == true)//cosa 04282008 for cck long range
 162                 TxAGC = 0x22;
 163         else
 164                 TxAGC = powerlevel;
 165
 166         //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
 167         if(priv->bIgnoreDiffRateTxPowerOffset)
 168                 TxAGC = powerlevel;
 169
 170         if(TxAGC > RF6052_MAX_TX_PWR)
 171                 TxAGC = RF6052_MAX_TX_PWR;
 172
 173         //printk("CCK PWR= %x\n", TxAGC);
 174         rtl8192_setBBreg(dev, rTxAGC_CCK_Mcs32, bTxAGCRateCCK, TxAGC);
 175
 176 }       /* PHY_RF6052SetCckTxPower */
 177
 178
 179
 180 /*-----------------------------------------------------------------------------
 181  * Function:    PHY_RF6052SetOFDMTxPower
 182  *
 183  * Overview:    For legacy and HY OFDM, we must read EEPROM TX power index for
 184  *                      different channel and read original value in TX power register area from
 185  *                      0xe00. We increase offset and original value to be correct tx pwr.
 186  *
 187  * Input:       NONE
 188  *
 189  * Output:      NONE
 190  *
 191  * Return:      NONE
 192  *
 193  * Revised History:
 194  * When                 Who             Remark
 195  * 11/05/2008   MHC             Simulate 8192 series method.
 196 * 01/06/2009    MHC             1. Prevent Path B tx power overflow or underflow dure to
 197  *                                              A/B pwr difference or legacy/HT pwr diff.
 198  *                                              2. We concern with path B legacy/HT OFDM difference.
 199  * 01/22/2009   MHC             Support new EPRO format from SD3.
 200  *---------------------------------------------------------------------------*/
 201  #if 1
 202 extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
 203 {
 204         struct r8192_priv *priv = ieee80211_priv(dev);
 205         u32     writeVal, powerBase0, powerBase1;
 206         u8      index = 0;
 207         u16     RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 208         //u8    byte0, byte1, byte2, byte3;
 209         u8    Channel = priv->ieee80211->current_network.channel;
 210         u8      rfa_pwr[4];
 211         u8      rfa_lower_bound = 0, rfa_upper_bound = 0 /*, rfa_htpwr, rfa_legacypwr*/;
 212         u8      i;
 213         u8      rf_pwr_diff = 0;
 214         u8      Legacy_pwrdiff=0, HT20_pwrdiff=0, BandEdge_Pwrdiff=0;
 215         u8      ofdm_bandedge_chnl_low=0, ofdm_bandedge_chnl_high=0;
 216
 217
 218         // We only care about the path A for legacy.
 219         if (priv->EEPROMVersion != 2)
 220         powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
 221         else if (priv->EEPROMVersion == 2)      // Defined by SD1 Jong
 222         {
 223                 //
 224                 // 2009/01/21 MH Support new EEPROM format from SD3 requirement
 225                 //
 226                 Legacy_pwrdiff = priv->TxPwrLegacyHtDiff[RF90_PATH_A][Channel-1];
 227                 // For legacy OFDM, tx pwr always > HT OFDM pwr. We do not care Path B
 228                 // legacy OFDM pwr diff. NO BB register to notify HW.
 229                 powerBase0 = powerlevel + Legacy_pwrdiff;
 230                 //RTPRINT(FPHY, PHY_TXPWR, (" [LagacyToHT40 pwr diff = %d]\n", Legacy_pwrdiff));
 231
 232                 // Band Edge scheme is enabled for FCC mode
 233                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
 234                 {
 235                         ofdm_bandedge_chnl_low = 1;
 236                         ofdm_bandedge_chnl_high = 11;
 237                         BandEdge_Pwrdiff = 0;
 238                         if (Channel <= ofdm_bandedge_chnl_low)
 239                                 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][0];
 240                         else if (Channel >= ofdm_bandedge_chnl_high)
 241                         {
 242                                 BandEdge_Pwrdiff = priv->TxPwrbandEdgeLegacyOfdm[RF90_PATH_A][1];
 243                         }
 244                         powerBase0 -= BandEdge_Pwrdiff;
 245                         if (Channel <= ofdm_bandedge_chnl_low || Channel >= ofdm_bandedge_chnl_high)
 246                         {
 247                                 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM band-edge channel = %d, pwr diff = %d]\n",
 248                                 //Channel, BandEdge_Pwrdiff));
 249                         }
 250                 }
 251                 //RTPRINT(FPHY, PHY_TXPWR, (" [OFDM power base index = 0x%x]\n", powerBase0));
 252         }
 253         powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
 254
 255         //MCS rates
 256         if(priv->EEPROMVersion == 2)
 257         {
 258                 //Cosa add for new EEPROM content. 02102009
 259
 260                 //Check HT20 to HT40 diff
 261                 if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 262                 {
 263                         // HT 20<->40 pwr diff
 264                         HT20_pwrdiff = priv->TxPwrHt20Diff[RF90_PATH_A][Channel-1];
 265
 266                         // Calculate Antenna pwr diff
 267                         if (HT20_pwrdiff < 8)   // 0~+7
 268                                 powerlevel += HT20_pwrdiff;
 269                         else                            // index8-15=-8~-1
 270                                 powerlevel -= (16-HT20_pwrdiff);
 271
 272                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 to HT40 pwrdiff = %d]\n", HT20_pwrdiff));
 273                         //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
 274                 }
 275
 276                 // Band Edge scheme is enabled for FCC mode
 277                 if (priv->TxPwrbandEdgeFlag == 1/* && pHalData->ChannelPlan == 0*/)
 278                 {
 279                         BandEdge_Pwrdiff = 0;
 280                         if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20_40)
 281                         {
 282                                 if (Channel <= 3)
 283                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][0];
 284                                 else if (Channel >= 9)
 285                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt40[RF90_PATH_A][1];
 286                                 if (Channel <= 3 || Channel >= 9)
 287                                 {
 288                                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT40 band-edge channel = %d, pwr diff = %d]\n",
 289                                         //Channel, BandEdge_Pwrdiff));
 290                                 }
 291                         }
 292                         else if (priv->CurrentChannelBW == HT_CHANNEL_WIDTH_20)
 293                         {
 294                                 if (Channel <= 1)
 295                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][0];
 296                                 else if (Channel >= 11)
 297                                         BandEdge_Pwrdiff = priv->TxPwrbandEdgeHt20[RF90_PATH_A][1];
 298                                 if (Channel <= 1 || Channel >= 11)
 299                                 {
 300                                         //RTPRINT(FPHY, PHY_TXPWR, (" [HT20 band-edge channel = %d, pwr diff = %d]\n",
 301                                         //Channel, BandEdge_Pwrdiff));
 302                                 }
 303                         }
 304                         powerlevel -= BandEdge_Pwrdiff;
 305                         //RTPRINT(FPHY, PHY_TXPWR, (" [MCS power base index = 0x%x]\n", powerlevel));
 306                 }
 307         }
 308         powerBase1 = powerlevel;
 309         powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
 310
 311         //RTPRINT(FPHY, PHY_TXPWR, (" [Legacy/HT power index= %x/%x]\n", powerBase0, powerBase1));
 312
 313         for(index=0; index<6; index++)
 314         {
 315                 //
 316                 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
 317                 //
 318                 //cosa add for lenovo, to pass the safety spec, don't increase power index for different rates.
 319                 if(priv->bIgnoreDiffRateTxPowerOffset)
 320                         writeVal = ((index<2)?powerBase0:powerBase1);
 321                 else
 322                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] + ((index<2)?powerBase0:powerBase1);
 323
 324                 //RTPRINT(FPHY, PHY_TXPWR, ("Reg 0x%x, Original=%x writeVal=%x\n",
 325                 //RegOffset[index], priv->MCSTxPowerLevelOriginalOffset[index], writeVal));
 326
 327                 //
 328                 // If path A and Path B coexist, we must limit Path A tx power.
 329                 // Protect Path B pwr over or under flow. We need to calculate upper and
 330                 // lower bound of path A tx power.
 331                 //
 332                 if (priv->rf_type == RF_2T2R)
 333                 {
 334                         rf_pwr_diff = priv->AntennaTxPwDiff[0];
 335                         //RTPRINT(FPHY, PHY_TXPWR, ("2T2R RF-B to RF-A PWR DIFF=%d\n", rf_pwr_diff));
 336
 337                         if (rf_pwr_diff >= 8)           // Diff=-8~-1
 338                         {       // Prevent underflow!!
 339                                 rfa_lower_bound = 0x10-rf_pwr_diff;
 340                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_lower_bound= %d\n", rfa_lower_bound));
 341                         }
 342                         else if (rf_pwr_diff >= 0)      // Diff = 0-7
 343                         {
 344                                 rfa_upper_bound = RF6052_MAX_TX_PWR-rf_pwr_diff;
 345                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_upper_bound= %d\n", rfa_upper_bound));
 346                         }
 347                 }
 348
 349                 for (i=  0; i <4; i++)
 350                 {
 351                         rfa_pwr[i] = (u8)((writeVal & (0x7f<<(i*8)))>>(i*8));
 352                         if (rfa_pwr[i]  > RF6052_MAX_TX_PWR)
 353                                 rfa_pwr[i]  = RF6052_MAX_TX_PWR;
 354
 355                         //
 356                         // If path A and Path B coexist, we must limit Path A tx power.
 357                         // Protect Path B pwr over or under flow. We need to calculate upper and
 358                         // lower bound of path A tx power.
 359                         //
 360                         if (priv->rf_type == RF_2T2R)
 361                         {
 362                                 if (rf_pwr_diff >= 8)           // Diff=-8~-1
 363                                 {       // Prevent underflow!!
 364                                         if (rfa_pwr[i] <rfa_lower_bound)
 365                                         {
 366                                                 //RTPRINT(FPHY, PHY_TXPWR, ("Underflow"));
 367                                                 rfa_pwr[i] = rfa_lower_bound;
 368                                         }
 369                                 }
 370                                 else if (rf_pwr_diff >= 1)      // Diff = 0-7
 371                                 {       // Prevent overflow
 372                                         if (rfa_pwr[i] > rfa_upper_bound)
 373                                         {
 374                                                 //RTPRINT(FPHY, PHY_TXPWR, ("Overflow"));
 375                                                 rfa_pwr[i] = rfa_upper_bound;
 376                                         }
 377                                 }
 378                                 //RTPRINT(FPHY, PHY_TXPWR, ("rfa_pwr[%d]=%x\n", i, rfa_pwr[i]));
 379                         }
 380
 381                 }
 382
 383                 //
 384                 // Add description: PWDB > threshold!!!High power issue!!
 385                 // We must decrease tx power !! Why is the value ???
 386                 //
 387                 if(priv->bDynamicTxHighPower == TRUE)
 388                 {
 389                         // For MCS rate
 390                         if(index > 1)
 391                         {
 392                                 writeVal = 0x03030303;
 393                         }
 394                         // For Legacy rate
 395                         else
 396                         {
 397                                 writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
 398                         }
 399                         //RTPRINT(FPHY, PHY_TXPWR, ("HighPower=%08x\n", writeVal));
 400                 }
 401                 else
 402                 {
 403                         writeVal = (rfa_pwr[3]<<24) | (rfa_pwr[2]<<16) |(rfa_pwr[1]<<8) |rfa_pwr[0];
 404                         //RTPRINT(FPHY, PHY_TXPWR, ("NormalPower=%08x\n", writeVal));
 405                 }
 406
 407                 //
 408                 // Write different rate set tx power index.
 409                 //
 410                 //if (DCMD_Test_Flag == 0)
 411                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 412         }
 413
 414 }       /* PHY_RF6052SetOFDMTxPower */
 415 #else
 416 extern void PHY_RF6052SetOFDMTxPower(struct net_device* dev, u8 powerlevel)
 417 {
 418         struct r8192_priv *priv = ieee80211_priv(dev);
 419         u32     writeVal, powerBase0, powerBase1;
 420         u8      index = 0;
 421         u16     RegOffset[6] = {0xe00, 0xe04, 0xe10, 0xe14, 0xe18, 0xe1c};
 422         u8      byte0, byte1, byte2, byte3;
 423         u8    channel = priv->ieee80211->current_network.channel;
 424
 425         //Legacy OFDM rates
 426         powerBase0 = powerlevel + (priv->LegacyHTTxPowerDiff & 0xf);
 427         powerBase0 = (powerBase0<<24) | (powerBase0<<16) |(powerBase0<<8) |powerBase0;
 428
 429         //MCS rates HT OFDM
 430         powerBase1 = powerlevel;
 431         powerBase1 = (powerBase1<<24) | (powerBase1<<16) |(powerBase1<<8) |powerBase1;
 432
 433         //printk("Legacy/HT PWR= %x/%x\n", powerBase0, powerBase1);
 434
 435         for(index=0; index<6; index++)
 436         {
 437                 //
 438                 // Index 0 & 1= legacy OFDM, 2-5=HT_MCS rate
 439                 //
 440                 writeVal = priv->MCSTxPowerLevelOriginalOffset[index] +  ((index<2)?powerBase0:powerBase1);
 441
 442                 //printk("Index = %d Original=%x writeVal=%x\n", index, priv->MCSTxPowerLevelOriginalOffset[index], writeVal);
 443
 444                 byte0 = (u8)(writeVal & 0x7f);
 445                 byte1 = (u8)((writeVal & 0x7f00)>>8);
 446                 byte2 = (u8)((writeVal & 0x7f0000)>>16);
 447                 byte3 = (u8)((writeVal & 0x7f000000)>>24);
 448
 449                 // Max power index = 0x3F Range = 0-0x3F
 450                 if(byte0 > RF6052_MAX_TX_PWR)
 451                         byte0 = RF6052_MAX_TX_PWR;
 452                 if(byte1 > RF6052_MAX_TX_PWR)
 453                         byte1 = RF6052_MAX_TX_PWR;
 454                 if(byte2 > RF6052_MAX_TX_PWR)
 455                         byte2 = RF6052_MAX_TX_PWR;
 456                 if(byte3 > RF6052_MAX_TX_PWR)
 457                         byte3 = RF6052_MAX_TX_PWR;
 458
 459                 //
 460                 // Add description: PWDB > threshold!!!High power issue!!
 461                 // We must decrease tx power !! Why is the value ???
 462                 //
 463                 if(priv->bDynamicTxHighPower == true)
 464                 {
 465                         // For MCS rate
 466                         if(index > 1)
 467                         {
 468                                 writeVal = 0x03030303;
 469                         }
 470                         // For Legacy rate
 471                         else
 472                         {
 473                                 writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 474                         }
 475                 }
 476                 else
 477                 {
 478                         writeVal = (byte3<<24) | (byte2<<16) |(byte1<<8) |byte0;
 479                 }
 480
 481                 //
 482                 // Write different rate set tx power index.
 483                 //
 484                 rtl8192_setBBreg(dev, RegOffset[index], 0x7f7f7f7f, writeVal);
 485         }
 486
 487 }       /* PHY_RF6052SetOFDMTxPower */
 488 #endif
 489
 490 RT_STATUS PHY_RF6052_Config(struct net_device* dev)
 491 {
 492         struct r8192_priv                       *priv = ieee80211_priv(dev);
 493         RT_STATUS                               rtStatus = RT_STATUS_SUCCESS;
 494         //RF90_RADIO_PATH_E             eRFPath;
 495         //BB_REGISTER_DEFINITION_T      *pPhyReg;
 496         //u32                                           OrgStoreRFIntSW[RF90_PATH_D+1];
 497
 498         //
 499         // Initialize general global value
 500         //
 501         // TODO: Extend RF_PATH_C and RF_PATH_D in the future
 502         if(priv->rf_type == RF_1T1R)
 503                 priv->NumTotalRFPath = 1;
 504         else
 505                 priv->NumTotalRFPath = 2;
 506
 507         //
 508         // Config BB and RF
 509         //
 510 //      switch( priv->bRegHwParaFile )
 511 //      {
 512 //              case 0:
 513 //                      phy_RF6052_Config_HardCode(dev);
 514 //                      break;
 515
 516 //              case 1:
 517                         rtStatus = phy_RF6052_Config_ParaFile(dev);
 518 //                      break;
 519
 520 //              case 2:
 521                         // Partial Modify.
 522 //                      phy_RF6052_Config_HardCode(dev);
 523 //                      phy_RF6052_Config_ParaFile(dev);
 524 //                      break;
 525
 526 //              default:
 527 //                      phy_RF6052_Config_HardCode(dev);
 528 //                      break;
 529 //      }
 530         return rtStatus;
 531
 532 }
 533
 534 void phy_RF6052_Config_HardCode(struct net_device* dev)
 535 {
 536
 537         // Set Default Bandwidth to 20M
 538         //Adapter->HalFunc      .SetBWModeHandler(Adapter, HT_CHANNEL_WIDTH_20);
 539
 540         // TODO: Set Default Channel to channel one for RTL8225
 541
 542 }
 543
 544 RT_STATUS phy_RF6052_Config_ParaFile(struct net_device* dev)
 545 {
 546         u32                     u4RegValue = 0;
 547         //static s1Byte         szRadioAFile[] = RTL819X_PHY_RADIO_A;
 548         //static s1Byte         szRadioBFile[] = RTL819X_PHY_RADIO_B;
 549         //static s1Byte         szRadioBGMFile[] = RTL819X_PHY_RADIO_B_GM;
 550         u8                      eRFPath;
 551         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
 552         struct r8192_priv       *priv = ieee80211_priv(dev);
 553         BB_REGISTER_DEFINITION_T        *pPhyReg;
 554         //u8                    eCheckItem;
 555
 556
 557         //3//-----------------------------------------------------------------
 558         //3// <2> Initialize RF
 559         //3//-----------------------------------------------------------------
 560         //for(eRFPath = RF90_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
 561         for(eRFPath = 0; eRFPath <priv->NumTotalRFPath; eRFPath++)
 562         {
 563
 564                 pPhyReg = &priv->PHYRegDef[eRFPath];
 565
 566                 /*----Store original RFENV control type----*/
 567                 switch(eRFPath)
 568                 {
 569                 case RF90_PATH_A:
 570                 case RF90_PATH_C:
 571                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV);
 572                         break;
 573                 case RF90_PATH_B :
 574                 case RF90_PATH_D:
 575                         u4RegValue = rtl8192_QueryBBReg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16);
 576                         break;
 577                 }
 578
 579                 /*----Set RF_ENV enable----*/
 580                 rtl8192_setBBreg(dev, pPhyReg->rfintfe, bRFSI_RFENV<<16, 0x1);
 581
 582                 /*----Set RF_ENV output high----*/
 583                 rtl8192_setBBreg(dev, pPhyReg->rfintfo, bRFSI_RFENV, 0x1);
 584
 585                 /* Set bit number of Address and Data for RF register */
 586                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireAddressLength, 0x0);  // Set 1 to 4 bits for 8255
 587                 rtl8192_setBBreg(dev, pPhyReg->rfHSSIPara2, b3WireDataLength, 0x0);     // Set 0 to 12  bits for 8255
 588
 589
 590                 /*----Initialize RF fom connfiguration file----*/
 591                 switch(eRFPath)
 592                 {
 593                 case RF90_PATH_A:
 594                         rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
 595                         break;
 596                 case RF90_PATH_B:
 597                         rtStatus= rtl8192_phy_ConfigRFWithHeaderFile(dev,(RF90_RADIO_PATH_E)eRFPath);
 598                         break;
 599                 case RF90_PATH_C:
 600                         break;
 601                 case RF90_PATH_D:
 602                         break;
 603                 }
 604
 605                 /*----Restore RFENV control type----*/;
 606                 switch(eRFPath)
 607                 {
 608                 case RF90_PATH_A:
 609                 case RF90_PATH_C:
 610                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV, u4RegValue);
 611                         break;
 612                 case RF90_PATH_B :
 613                 case RF90_PATH_D:
 614                         rtl8192_setBBreg(dev, pPhyReg->rfintfs, bRFSI_RFENV<<16, u4RegValue);
 615                         break;
 616                 }
 617
 618                 if(rtStatus != RT_STATUS_SUCCESS){
 619                         printk("phy_RF6052_Config_ParaFile():Radio[%d] Fail!!", eRFPath);
 620                         goto phy_RF6052_Config_ParaFile_Fail;
 621                 }
 622
 623         }
 624
 625         RT_TRACE(COMP_INIT, "<---phy_RF6052_Config_ParaFile()\n");
 626         return rtStatus;
 627
 628 phy_RF6052_Config_ParaFile_Fail:
 629         return rtStatus;
 630 }
 631
 632
 633 //
 634 // ==> RF shadow Operation API Code Section!!!
 635 //
 636 /*-----------------------------------------------------------------------------
 637  * Function:    PHY_RFShadowRead
 638  *                              PHY_RFShadowWrite
 639  *                              PHY_RFShadowCompare
 640  *                              PHY_RFShadowRecorver
 641  *                              PHY_RFShadowCompareAll
 642  *                              PHY_RFShadowRecorverAll
 643  *                              PHY_RFShadowCompareFlagSet
 644  *                              PHY_RFShadowRecorverFlagSet
 645  *
 646  * Overview:    When we set RF register, we must write shadow at first.
 647  *                      When we are running, we must compare shadow abd locate error addr.
 648  *                      Decide to recorver or not.
 649  *
 650  * Input:       NONE
 651  *
 652  * Output:      NONE
 653  *
 654  * Return:      NONE
 655  *
 656  * Revised History:
 657  * When                 Who             Remark
 658  * 11/20/2008   MHC             Create Version 0.
 659  *
 660  *---------------------------------------------------------------------------*/
 661 extern u32 PHY_RFShadowRead(
 662         struct net_device               * dev,
 663         RF90_RADIO_PATH_E       eRFPath,
 664         u32                                     Offset)
 665 {
 666         return  RF_Shadow[eRFPath][Offset].Value;
 667
 668 }       /* PHY_RFShadowRead */
 669
 670
 671 extern void PHY_RFShadowWrite(
 672         struct net_device               * dev,
 673         u32     eRFPath,
 674         u32                                     Offset,
 675         u32                                     Data)
 676 {
 677         //RF_Shadow[eRFPath][Offset].Value = (Data & bMask20Bits);
 678         RF_Shadow[eRFPath][Offset].Value = (Data & bRFRegOffsetMask);
 679         RF_Shadow[eRFPath][Offset].Driver_Write = true;
 680
 681 }       /* PHY_RFShadowWrite */
 682
 683
 684 extern void PHY_RFShadowCompare(
 685         struct net_device               * dev,
 686         RF90_RADIO_PATH_E       eRFPath,
 687         u32                                     Offset)
 688 {
 689         u32     reg;
 690
 691         // Check if we need to check the register
 692         if (RF_Shadow[eRFPath][Offset].Compare == true)
 693         {
 694                 reg = rtl8192_phy_QueryRFReg(dev, eRFPath, Offset, bRFRegOffsetMask);
 695                 // Compare shadow and real rf register for 20bits!!
 696                 if (RF_Shadow[eRFPath][Offset].Value != reg)
 697                 {
 698                         // Locate error position.
 699                         RF_Shadow[eRFPath][Offset].ErrorOrNot = true;
 700                         RT_TRACE(COMP_INIT, "PHY_RFShadowCompare RF-%d Addr%02xErr = %05x", eRFPath, Offset, reg);
 701                 }
 702         }
 703
 704 }       /* PHY_RFShadowCompare */
 705
 706 extern void PHY_RFShadowRecorver(
 707         struct net_device               * dev,
 708         RF90_RADIO_PATH_E       eRFPath,
 709         u32                                     Offset)
 710 {
 711         // Check if the address is error
 712         if (RF_Shadow[eRFPath][Offset].ErrorOrNot == true)
 713         {
 714                 // Check if we need to recorver the register.
 715                 if (RF_Shadow[eRFPath][Offset].Recorver == true)
 716                 {
 717                         rtl8192_phy_SetRFReg(dev, eRFPath, Offset, bRFRegOffsetMask, RF_Shadow[eRFPath][Offset].Value);
 718                         RT_TRACE(COMP_INIT, "PHY_RFShadowRecorver RF-%d Addr%02x=%05x",
 719                         eRFPath, Offset, RF_Shadow[eRFPath][Offset].Value);
 720                 }
 721         }
 722
 723 }       /* PHY_RFShadowRecorver */
 724
 725
 726 extern void PHY_RFShadowCompareAll(struct net_device * dev)
 727 {
 728         u32             eRFPath;
 729         u32             Offset;
 730
 731         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 732         {
 733                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 734                 {
 735                         PHY_RFShadowCompare(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
 736                 }
 737         }
 738
 739 }       /* PHY_RFShadowCompareAll */
 740
 741
 742 extern void PHY_RFShadowRecorverAll(struct net_device * dev)
 743 {
 744         u32             eRFPath;
 745         u32             Offset;
 746
 747         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 748         {
 749                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 750                 {
 751                         PHY_RFShadowRecorver(dev, (RF90_RADIO_PATH_E)eRFPath, Offset);
 752                 }
 753         }
 754
 755 }       /* PHY_RFShadowRecorverAll */
 756
 757
 758 extern void PHY_RFShadowCompareFlagSet(
 759         struct net_device               * dev,
 760         RF90_RADIO_PATH_E       eRFPath,
 761         u32                                     Offset,
 762         u8                                      Type)
 763 {
 764         // Set True or False!!!
 765         RF_Shadow[eRFPath][Offset].Compare = Type;
 766
 767 }       /* PHY_RFShadowCompareFlagSet */
 768
 769
 770 extern void PHY_RFShadowRecorverFlagSet(
 771         struct net_device               * dev,
 772         RF90_RADIO_PATH_E       eRFPath,
 773         u32                                     Offset,
 774         u8                                      Type)
 775 {
 776         // Set True or False!!!
 777         RF_Shadow[eRFPath][Offset].Recorver= Type;
 778
 779 }       /* PHY_RFShadowRecorverFlagSet */
 780
 781
 782 extern void PHY_RFShadowCompareFlagSetAll(struct net_device  * dev)
 783 {
 784         u32             eRFPath;
 785         u32             Offset;
 786
 787         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 788         {
 789                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 790                 {
 791                         // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
 792                         if (Offset != 0x26 && Offset != 0x27)
 793                                 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
 794                         else
 795                                 PHY_RFShadowCompareFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
 796                 }
 797         }
 798
 799 }       /* PHY_RFShadowCompareFlagSetAll */
 800
 801
 802 extern void PHY_RFShadowRecorverFlagSetAll(struct net_device  * dev)
 803 {
 804         u32             eRFPath;
 805         u32             Offset;
 806
 807         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 808         {
 809                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 810                 {
 811                         // 2008/11/20 MH For S3S4 test, we only check reg 26/27 now!!!!
 812                         if (Offset != 0x26 && Offset != 0x27)
 813                                 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, FALSE);
 814                         else
 815                                 PHY_RFShadowRecorverFlagSet(dev, (RF90_RADIO_PATH_E)eRFPath, Offset, TRUE);
 816                 }
 817         }
 818
 819 }       /* PHY_RFShadowCompareFlagSetAll */
 820
 821
 822
 823 extern void PHY_RFShadowRefresh(struct net_device  * dev)
 824 {
 825         u32             eRFPath;
 826         u32             Offset;
 827
 828         for (eRFPath = 0; eRFPath < RF6052_MAX_PATH; eRFPath++)
 829         {
 830                 for (Offset = 0; Offset <= RF6052_MAX_REG; Offset++)
 831                 {
 832                         RF_Shadow[eRFPath][Offset].Value = 0;
 833                         RF_Shadow[eRFPath][Offset].Compare = false;
 834                         RF_Shadow[eRFPath][Offset].Recorver  = false;
 835                         RF_Shadow[eRFPath][Offset].ErrorOrNot = false;
 836                         RF_Shadow[eRFPath][Offset].Driver_Write = false;
 837                 }
 838         }
 839
 840 }       /* PHY_RFShadowRead */
 841
 842 /* End of HalRf6052.c */