SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8185b_init.c

   1 /*++
   2 Copyright (c) Realtek Semiconductor Corp. All rights reserved.
   3
   4 Module Name:
   5         r8185b_init.c
   6
   7 Abstract:
   8         Hardware Initialization and Hardware IO for RTL8185B
   9
  10 Major Change History:
  11         When        Who      What
  12         ----------    ---------------   -------------------------------
  13         2006-11-15    Xiong             Created
  14
  15 Notes:
  16         This file is ported from RTL8185B Windows driver.
  17
  18
  19 --*/
  20
  21 /*--------------------------Include File------------------------------------*/
  22 #include <linux/spinlock.h>
  23 #include "r8180_hw.h"
  24 #include "r8180.h"
  25 #include "r8180_rtl8225.h" /* RTL8225 Radio frontend */
  26 #include "r8180_93cx6.h"   /* Card EEPROM */
  27 #include "r8180_wx.h"
  28
  29 #include "ieee80211/dot11d.h"
  30
  31
  32 //#define CONFIG_RTL8180_IO_MAP
  33
  34 #define TC_3W_POLL_MAX_TRY_CNT 5
  35 static u8 MAC_REG_TABLE[][2]={
  36                         //PAGA 0:
  37                         // 0x34(BRSR), 0xBE(RATE_FALLBACK_CTL), 0x1E0(ARFR) would set in HwConfigureRTL8185()
  38                         // 0x272(RFSW_CTRL), 0x1CE(AESMSK_QC) set in InitializeAdapter8185().
  39                         // 0x1F0~0x1F8  set in MacConfig_85BASIC()
  40                         {0x08, 0xae}, {0x0a, 0x72}, {0x5b, 0x42},
  41                         {0x84, 0x88}, {0x85, 0x24}, {0x88, 0x54}, {0x8b, 0xb8}, {0x8c, 0x03},
  42                         {0x8d, 0x40}, {0x8e, 0x00}, {0x8f, 0x00}, {0x5b, 0x18}, {0x91, 0x03},
  43                         {0x94, 0x0F}, {0x95, 0x32},
  44                         {0x96, 0x00}, {0x97, 0x07}, {0xb4, 0x22}, {0xdb, 0x00},
  45                         {0xf0, 0x32}, {0xf1, 0x32}, {0xf2, 0x00}, {0xf3, 0x00}, {0xf4, 0x32},
  46                         {0xf5, 0x43}, {0xf6, 0x00}, {0xf7, 0x00}, {0xf8, 0x46}, {0xf9, 0xa4},
  47                         {0xfa, 0x00}, {0xfb, 0x00}, {0xfc, 0x96}, {0xfd, 0xa4}, {0xfe, 0x00},
  48                         {0xff, 0x00},
  49
  50                         //PAGE 1:
  51                         // For Flextronics system Logo PCIHCT failure:
  52                         // 0x1C4~0x1CD set no-zero value to avoid PCI configuration space 0x45[7]=1
  53                         {0x5e, 0x01},
  54                         {0x58, 0x00}, {0x59, 0x00}, {0x5a, 0x04}, {0x5b, 0x00}, {0x60, 0x24},
  55                         {0x61, 0x97}, {0x62, 0xF0}, {0x63, 0x09}, {0x80, 0x0F}, {0x81, 0xFF},
  56                         {0x82, 0xFF}, {0x83, 0x03},
  57                         {0xC4, 0x22}, {0xC5, 0x22}, {0xC6, 0x22}, {0xC7, 0x22}, {0xC8, 0x22}, //lzm add 080826
  58                         {0xC9, 0x22}, {0xCA, 0x22}, {0xCB, 0x22}, {0xCC, 0x22}, {0xCD, 0x22},//lzm add 080826
  59                         {0xe2, 0x00},
  60
  61
  62                         //PAGE 2:
  63                         {0x5e, 0x02},
  64                         {0x0c, 0x04}, {0x4c, 0x30}, {0x4d, 0x08}, {0x50, 0x05}, {0x51, 0xf5},
  65                         {0x52, 0x04}, {0x53, 0xa0}, {0x54, 0xff}, {0x55, 0xff}, {0x56, 0xff},
  66                         {0x57, 0xff}, {0x58, 0x08}, {0x59, 0x08}, {0x5a, 0x08}, {0x5b, 0x08},
  67                         {0x60, 0x08}, {0x61, 0x08}, {0x62, 0x08}, {0x63, 0x08}, {0x64, 0x2f},
  68                         {0x8c, 0x3f}, {0x8d, 0x3f}, {0x8e, 0x3f},
  69                         {0x8f, 0x3f}, {0xc4, 0xff}, {0xc5, 0xff}, {0xc6, 0xff}, {0xc7, 0xff},
  70                         {0xc8, 0x00}, {0xc9, 0x00}, {0xca, 0x80}, {0xcb, 0x00},
  71
  72                         //PAGA 0:
  73                         {0x5e, 0x00},{0x9f, 0x03}
  74                 };
  75
  76
  77 static u8  ZEBRA_AGC[]={
  78                         0,
  79                         0x7E,0x7E,0x7E,0x7E,0x7D,0x7C,0x7B,0x7A,0x79,0x78,0x77,0x76,0x75,0x74,0x73,0x72,
  80                         0x71,0x70,0x6F,0x6E,0x6D,0x6C,0x6B,0x6A,0x69,0x68,0x67,0x66,0x65,0x64,0x63,0x62,
  81                         0x48,0x47,0x46,0x45,0x44,0x29,0x28,0x27,0x26,0x25,0x24,0x23,0x22,0x21,0x08,0x07,
  82                         0x06,0x05,0x04,0x03,0x02,0x01,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,0x00,
  83                         0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x0f,0x10,0x11,0x12,0x13,0x15,0x16,
  84                         0x17,0x17,0x18,0x18,0x19,0x1a,0x1a,0x1b,0x1b,0x1c,0x1c,0x1d,0x1d,0x1d,0x1e,0x1e,
  85                         0x1f,0x1f,0x1f,0x20,0x20,0x20,0x20,0x21,0x21,0x21,0x22,0x22,0x22,0x23,0x23,0x24,
  86                         0x24,0x25,0x25,0x25,0x26,0x26,0x27,0x27,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F,0x2F
  87                         };
  88
  89 static u32 ZEBRA_RF_RX_GAIN_TABLE[]={
  90                         0x0096,0x0076,0x0056,0x0036,0x0016,0x01f6,0x01d6,0x01b6,
  91                         0x0196,0x0176,0x00F7,0x00D7,0x00B7,0x0097,0x0077,0x0057,
  92                         0x0037,0x00FB,0x00DB,0x00BB,0x00FF,0x00E3,0x00C3,0x00A3,
  93                         0x0083,0x0063,0x0043,0x0023,0x0003,0x01E3,0x01C3,0x01A3,
  94                         0x0183,0x0163,0x0143,0x0123,0x0103
  95         };
  96
  97 static u8 OFDM_CONFIG[]={
  98                         // OFDM reg0x06[7:0]=0xFF: Enable power saving mode in RX
  99                         // OFDM reg0x3C[4]=1'b1: Enable RX power saving mode
 100                         // ofdm 0x3a = 0x7b ,(original : 0xfb) For ECS shielding room TP test
 101
 102                         // 0x00
 103                         0x10, 0x0F, 0x0A, 0x0C, 0x14, 0xFA, 0xFF, 0x50,
 104                         0x00, 0x50, 0x00, 0x00, 0x00, 0x5C, 0x00, 0x00,
 105                         // 0x10
 106                         0x40, 0x00, 0x40, 0x00, 0x00, 0x00, 0xA8, 0x26,
 107                         0x32, 0x33, 0x06, 0xA5, 0x6F, 0x55, 0xC8, 0xBB,
 108                         // 0x20
 109                         0x0A, 0xE1, 0x2C, 0x4A, 0x86, 0x83, 0x34, 0x00,
 110                         0x4F, 0x24, 0x6F, 0xC2, 0x03, 0x40, 0x80, 0x00,
 111                         // 0x30
 112                         0xC0, 0xC1, 0x58, 0xF1, 0x00, 0xC4, 0x90, 0x3e,
 113                         0xD8, 0x3C, 0x7B, 0x10, 0x10
 114                 };
 115
 116 /*---------------------------------------------------------------
 117   * Hardware IO
 118   * the code is ported from Windows source code
 119   ----------------------------------------------------------------*/
 120
 121 void
 122 PlatformIOWrite1Byte(
 123         struct net_device *dev,
 124         u32             offset,
 125         u8              data
 126         )
 127 {
 128         write_nic_byte(dev, offset, data);
 129         read_nic_byte(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 130
 131 }
 132
 133 void
 134 PlatformIOWrite2Byte(
 135         struct net_device *dev,
 136         u32             offset,
 137         u16             data
 138         )
 139 {
 140         write_nic_word(dev, offset, data);
 141         read_nic_word(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 142
 143
 144 }
 145 u8 PlatformIORead1Byte(struct net_device *dev, u32 offset);
 146
 147 void
 148 PlatformIOWrite4Byte(
 149         struct net_device *dev,
 150         u32             offset,
 151         u32             data
 152         )
 153 {
 154 //{by amy 080312
 155 if (offset == PhyAddr)
 156         {//For Base Band configuration.
 157                 unsigned char   cmdByte;
 158                 unsigned long   dataBytes;
 159                 unsigned char   idx;
 160                 u8      u1bTmp;
 161
 162                 cmdByte = (u8)(data & 0x000000ff);
 163                 dataBytes = data>>8;
 164
 165                 //
 166                 // 071010, rcnjko:
 167                 // The critical section is only BB read/write race condition.
 168                 // Assumption:
 169                 // 1. We assume NO one will access BB at DIRQL, otherwise, system will crash for
 170                 // acquiring the spinlock in such context.
 171                 // 2. PlatformIOWrite4Byte() MUST NOT be recursive.
 172                 //
 173 //              NdisAcquireSpinLock( &(pDevice->IoSpinLock) );
 174
 175                 for(idx = 0; idx < 30; idx++)
 176                 { // Make sure command bit is clear before access it.
 177                         u1bTmp = PlatformIORead1Byte(dev, PhyAddr);
 178                         if((u1bTmp & BIT7) == 0)
 179                                 break;
 180                         else
 181                                 mdelay(10);
 182                 }
 183
 184                 for(idx=0; idx < 3; idx++)
 185                 {
 186                         PlatformIOWrite1Byte(dev,offset+1+idx,((u8*)&dataBytes)[idx] );
 187                 }
 188                 write_nic_byte(dev, offset, cmdByte);
 189
 190 //              NdisReleaseSpinLock( &(pDevice->IoSpinLock) );
 191         }
 192 //by amy 080312}
 193         else{
 194                 write_nic_dword(dev, offset, data);
 195                 read_nic_dword(dev, offset); // To make sure write operation is completed, 2005.11.09, by rcnjko.
 196         }
 197 }
 198
 199 u8
 200 PlatformIORead1Byte(
 201         struct net_device *dev,
 202         u32             offset
 203         )
 204 {
 205         u8      data = 0;
 206
 207         data = read_nic_byte(dev, offset);
 208
 209
 210         return data;
 211 }
 212
 213 u16
 214 PlatformIORead2Byte(
 215         struct net_device *dev,
 216         u32             offset
 217         )
 218 {
 219         u16     data = 0;
 220
 221         data = read_nic_word(dev, offset);
 222
 223
 224         return data;
 225 }
 226
 227 u32
 228 PlatformIORead4Byte(
 229         struct net_device *dev,
 230         u32             offset
 231         )
 232 {
 233         u32     data = 0;
 234
 235         data = read_nic_dword(dev, offset);
 236
 237
 238         return data;
 239 }
 240
 241 void
 242 SetOutputEnableOfRfPins(
 243         struct net_device *dev
 244         )
 245 {
 246         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 247
 248         switch(priv->rf_chip)
 249         {
 250         case RFCHIPID_RTL8225:
 251         case RF_ZEBRA2:
 252         case RF_ZEBRA4:
 253                 write_nic_word(dev, RFPinsEnable, 0x1bff);
 254                 //write_nic_word(dev, RFPinsEnable, 0x1fff);
 255                 break;
 256         }
 257 }
 258
 259 void
 260 ZEBRA_RFSerialWrite(
 261         struct net_device *dev,
 262         u32                     data2Write,
 263         u8                      totalLength,
 264         u8                      low2high
 265         )
 266 {
 267         ThreeWireReg            twreg;
 268         int                             i;
 269         u16                             oval,oval2,oval3;
 270         u32                             mask;
 271         u16                             UshortBuffer;
 272
 273         u8                      u1bTmp;
 274         // RTL8187S HSSI Read/Write Function
 275         u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 276         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 277         write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 278         UshortBuffer = read_nic_word(dev, RFPinsOutput);
 279         oval = UshortBuffer & 0xfff8; // We shall clear bit0, 1, 2 first, 2005.10.28, by rcnjko.
 280
 281         oval2 = read_nic_word(dev, RFPinsEnable);
 282         oval3 = read_nic_word(dev, RFPinsSelect);
 283
 284         // <RJ_NOTE> 3-wire should be controled by HW when we finish SW 3-wire programming. 2005.08.10, by rcnjko.
 285         oval3 &= 0xfff8;
 286
 287         write_nic_word(dev, RFPinsEnable, (oval2|0x0007)); // Set To Output Enable
 288         write_nic_word(dev, RFPinsSelect, (oval3|0x0007)); // Set To SW Switch
 289         udelay(10);
 290
 291         // Add this to avoid hardware and software 3-wire conflict.
 292         // 2005.03.01, by rcnjko.
 293         twreg.longData = 0;
 294         twreg.struc.enableB = 1;
 295         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Set SI_EN (RFLE)
 296         udelay(2);
 297         twreg.struc.enableB = 0;
 298         write_nic_word(dev, RFPinsOutput, (twreg.longData|oval)); // Clear SI_EN (RFLE)
 299         udelay(10);
 300
 301         mask = (low2high)?0x01:((u32)0x01<<(totalLength-1));
 302
 303         for(i=0; i<totalLength/2; i++)
 304         {
 305                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 306                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 307                 twreg.struc.clk = 1;
 308                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 309                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 310
 311                 mask = (low2high)?(mask<<1):(mask>>1);
 312                 twreg.struc.data = ((data2Write&mask)!=0) ? 1 : 0;
 313                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 314                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 315                 twreg.struc.clk = 0;
 316                 write_nic_word(dev, RFPinsOutput, (twreg.longData|oval));
 317                 mask = (low2high)?(mask<<1):(mask>>1);
 318         }
 319
 320         twreg.struc.enableB = 1;
 321         twreg.struc.clk = 0;
 322         twreg.struc.data = 0;
 323         write_nic_word(dev, RFPinsOutput, twreg.longData|oval);
 324         udelay(10);
 325
 326         write_nic_word(dev, RFPinsOutput, oval|0x0004);
 327         write_nic_word(dev, RFPinsSelect, oval3|0x0000);
 328
 329         SetOutputEnableOfRfPins(dev);
 330 }
 331 //by amy
 332
 333
 334 int
 335 HwHSSIThreeWire(
 336         struct net_device *dev,
 337         u8                      *pDataBuf,
 338         u8                      nDataBufBitCnt,
 339         int                     bSI,
 340         int                     bWrite
 341         )
 342 {
 343         int     bResult = 1;
 344         u8      TryCnt;
 345         u8      u1bTmp;
 346
 347         do
 348         {
 349                 // Check if WE and RE are cleared.
 350                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 351                 {
 352                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 353                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 354                         {
 355                                 break;
 356                         }
 357                         udelay(10);
 358                 }
 359                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 360                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 361
 362                 // RTL8187S HSSI Read/Write Function
 363                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 364
 365                 if(bSI)
 366                 {
 367                         u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 368                 }else
 369                 {
 370                         u1bTmp &= ~RF_SW_CFG_SI;  //reg08[1]=0 Parallel Interface(PI)
 371                 }
 372
 373                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 374
 375                 if(bSI)
 376                 {
 377                         // jong: HW SI read must set reg84[3]=0.
 378                         u1bTmp = read_nic_byte(dev, RFPinsSelect);
 379                         u1bTmp &= ~BIT3;
 380                         write_nic_byte(dev, RFPinsSelect, u1bTmp );
 381                 }
 382                 // Fill up data buffer for write operation.
 383
 384                 if(bWrite)
 385                 {
 386                         if(nDataBufBitCnt == 16)
 387                         {
 388                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf));
 389                         }
 390                         else if(nDataBufBitCnt == 64)  // RTL8187S shouldn't enter this case
 391                         {
 392                                 write_nic_dword(dev, SW_3W_DB0, *((u32*)pDataBuf));
 393                                 write_nic_dword(dev, SW_3W_DB1, *((u32*)(pDataBuf + 4)));
 394                         }
 395                         else
 396                         {
 397                                 int idx;
 398                                 int ByteCnt = nDataBufBitCnt / 8;
 399                                 //printk("%d\n",nDataBufBitCnt);
 400                                 if ((nDataBufBitCnt % 8) != 0)
 401                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 402                                 nDataBufBitCnt);
 403
 404                                if (nDataBufBitCnt > 64)
 405                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 406                                 nDataBufBitCnt);
 407
 408                                 for(idx = 0; idx < ByteCnt; idx++)
 409                                 {
 410                                         write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 411                                 }
 412                         }
 413                 }
 414                 else            //read
 415                 {
 416                         if(bSI)
 417                         {
 418                                 // SI - reg274[3:0] : RF register's Address
 419                                 write_nic_word(dev, SW_3W_DB0, *((u16*)pDataBuf) );
 420                         }
 421                         else
 422                         {
 423                                 // PI - reg274[15:12] : RF register's Address
 424                                 write_nic_word(dev, SW_3W_DB0, (*((u16*)pDataBuf)) << 12);
 425                         }
 426                 }
 427
 428                 // Set up command: WE or RE.
 429                 if(bWrite)
 430                 {
 431                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 432                 }
 433                 else
 434                 {
 435                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 436                 }
 437
 438                 // Check if DONE is set.
 439                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 440                 {
 441                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 442                         if(  (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 443                         {
 444                                 break;
 445                         }
 446                         udelay(10);
 447                 }
 448
 449                 write_nic_byte(dev, SW_3W_CMD1, 0);
 450
 451                 // Read back data for read operation.
 452                 if(bWrite == 0)
 453                 {
 454                         if(bSI)
 455                         {
 456                                 //Serial Interface : reg363_362[11:0]
 457                                 *((u16*)pDataBuf) = read_nic_word(dev, SI_DATA_READ) ;
 458                         }
 459                         else
 460                         {
 461                                 //Parallel Interface : reg361_360[11:0]
 462                                 *((u16*)pDataBuf) = read_nic_word(dev, PI_DATA_READ);
 463                         }
 464
 465                         *((u16*)pDataBuf) &= 0x0FFF;
 466                 }
 467
 468         }while(0);
 469
 470         return bResult;
 471 }
 472 //by amy
 473
 474 int
 475 HwThreeWire(
 476         struct net_device *dev,
 477         u8                      *pDataBuf,
 478         u8                      nDataBufBitCnt,
 479         int                     bHold,
 480         int                     bWrite
 481         )
 482 {
 483         int     bResult = 1;
 484         u8      TryCnt;
 485         u8      u1bTmp;
 486
 487         do
 488         {
 489                 // Check if WE and RE are cleared.
 490                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 491                 {
 492                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 493                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 )
 494                         {
 495                                 break;
 496                         }
 497                         udelay(10);
 498                 }
 499                 if (TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 500                         panic("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear!!\n", u1bTmp);
 501
 502                 // Fill up data buffer for write operation.
 503                 if(nDataBufBitCnt == 16)
 504                 {
 505                         write_nic_word(dev, SW_3W_DB0, *((u16 *)pDataBuf));
 506                 }
 507                 else if(nDataBufBitCnt == 64)
 508                 {
 509                         write_nic_dword(dev, SW_3W_DB0, *((u32 *)pDataBuf));
 510                         write_nic_dword(dev, SW_3W_DB1, *((u32 *)(pDataBuf + 4)));
 511                 }
 512                 else
 513                 {
 514                         int idx;
 515                         int ByteCnt = nDataBufBitCnt / 8;
 516
 517                         if ((nDataBufBitCnt % 8) != 0)
 518                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 519                                 nDataBufBitCnt);
 520
 521                         if (nDataBufBitCnt > 64)
 522                                 panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 523                                 nDataBufBitCnt);
 524
 525                         for(idx = 0; idx < ByteCnt; idx++)
 526                         {
 527                                 write_nic_byte(dev, (SW_3W_DB0+idx), *(pDataBuf+idx));
 528                         }
 529                 }
 530
 531                 // Fill up length field.
 532                 u1bTmp = (u8)(nDataBufBitCnt - 1); // Number of bits - 1.
 533                 if(bHold)
 534                         u1bTmp |= SW_3W_CMD0_HOLD;
 535                 write_nic_byte(dev, SW_3W_CMD0, u1bTmp);
 536
 537                 // Set up command: WE or RE.
 538                 if(bWrite)
 539                 {
 540                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_WE);
 541                 }
 542                 else
 543                 {
 544                         write_nic_byte(dev, SW_3W_CMD1, SW_3W_CMD1_RE);
 545                 }
 546
 547                 // Check if WE and RE are cleared and DONE is set.
 548                 for(TryCnt = 0; TryCnt < TC_3W_POLL_MAX_TRY_CNT; TryCnt++)
 549                 {
 550                         u1bTmp = read_nic_byte(dev, SW_3W_CMD1);
 551                         if( (u1bTmp & (SW_3W_CMD1_RE|SW_3W_CMD1_WE)) == 0 &&
 552                                 (u1bTmp & SW_3W_CMD1_DONE) != 0 )
 553                         {
 554                                 break;
 555                         }
 556                         udelay(10);
 557                 }
 558                 if(TryCnt == TC_3W_POLL_MAX_TRY_CNT)
 559                 {
 560                         //RT_ASSERT(TryCnt != TC_3W_POLL_MAX_TRY_CNT,
 561                         //      ("HwThreeWire(): CmdReg: %#X RE|WE bits are not clear or DONE is not set!!\n", u1bTmp));
 562                         // Workaround suggested by wcchu: clear WE here. 2006.07.07, by rcnjko.
 563                         write_nic_byte(dev, SW_3W_CMD1, 0);
 564                 }
 565
 566                 // Read back data for read operation.
 567                 // <RJ_TODO> I am not sure if this is correct output format of a read operation.
 568                 if(bWrite == 0)
 569                 {
 570                         if(nDataBufBitCnt == 16)
 571                         {
 572                                 *((u16 *)pDataBuf) = read_nic_word(dev, SW_3W_DB0);
 573                         }
 574                         else if(nDataBufBitCnt == 64)
 575                         {
 576                                 *((u32 *)pDataBuf) = read_nic_dword(dev, SW_3W_DB0);
 577                                 *((u32 *)(pDataBuf + 4)) = read_nic_dword(dev, SW_3W_DB1);
 578                         }
 579                         else
 580                         {
 581                                 int idx;
 582                                 int ByteCnt = nDataBufBitCnt / 8;
 583
 584                                 if ((nDataBufBitCnt % 8) != 0)
 585                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should be multiple of 8!!!\n",
 586                                         nDataBufBitCnt);
 587
 588                                 if (nDataBufBitCnt > 64)
 589                                         panic("HwThreeWire(): nDataBufBitCnt(%d) should <= 64!!!\n",
 590                                         nDataBufBitCnt);
 591
 592                                 for(idx = 0; idx < ByteCnt; idx++)
 593                                 {
 594                                         *(pDataBuf+idx) = read_nic_byte(dev, (SW_3W_DB0+idx));
 595                                 }
 596                         }
 597                 }
 598
 599         }while(0);
 600
 601         return bResult;
 602 }
 603
 604
 605 void
 606 RF_WriteReg(
 607         struct net_device *dev,
 608         u8              offset,
 609         u32             data
 610         )
 611 {
 612         //RFReg                 reg;
 613         u32                     data2Write;
 614         u8                      len;
 615         u8                      low2high;
 616         //u32                   RF_Read = 0;
 617         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 618
 619
 620         switch(priv->rf_chip)
 621         {
 622         case RFCHIPID_RTL8225:
 623         case RF_ZEBRA2:         // Annie 2006-05-12.
 624         case RF_ZEBRA4:        //by amy
 625                 switch(priv->RegThreeWireMode)
 626                 {
 627                 case SW_THREE_WIRE:
 628                         { // Perform SW 3-wire programming by driver.
 629                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 630                                 len = 16;
 631                                 low2high = 0;
 632                                 ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 633                         }
 634                         break;
 635
 636                 case HW_THREE_WIRE:
 637                         { // Pure HW 3-wire.
 638                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 639                                 len = 16;
 640                                 HwThreeWire(
 641                                         dev,
 642                                         (u8 *)(&data2Write),    // pDataBuf,
 643                                         len,                            // nDataBufBitCnt,
 644                                         0,                                      // bHold,
 645                                         1);                                     // bWrite
 646                         }
 647                         break;
 648                         case HW_THREE_WIRE_PI: //Parallel Interface
 649                         { // Pure HW 3-wire.
 650                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 651                                 len = 16;
 652                                         HwHSSIThreeWire(
 653                                                 dev,
 654                                                 (u8*)(&data2Write),     // pDataBuf,
 655                                                 len,                                            // nDataBufBitCnt,
 656                                                 0,                                      // bSI
 657                                                 1);                                     // bWrite
 658
 659                                 //printk("33333\n");
 660                         }
 661                         break;
 662
 663                         case HW_THREE_WIRE_SI: //Serial Interface
 664                         { // Pure HW 3-wire.
 665                                 data2Write = (data << 4) | (u32)(offset & 0x0f);
 666                                 len = 16;
 667 //                                printk(" enter  ZEBRA_RFSerialWrite\n ");
 668 //                                low2high = 0;
 669 //                                ZEBRA_RFSerialWrite(dev, data2Write, len, low2high);
 670
 671                                 HwHSSIThreeWire(
 672                                         dev,
 673                                         (u8*)(&data2Write),     // pDataBuf,
 674                                         len,                                            // nDataBufBitCnt,
 675                                         1,                                      // bSI
 676                                         1);                                     // bWrite
 677
 678 //                                 printk(" exit ZEBRA_RFSerialWrite\n ");
 679                         }
 680                         break;
 681
 682
 683                 default:
 684                         DMESGE("RF_WriteReg(): invalid RegThreeWireMode(%d) !!!", priv->RegThreeWireMode);
 685                         break;
 686                 }
 687                 break;
 688
 689         default:
 690                 DMESGE("RF_WriteReg(): unknown RFChipID: %#X", priv->rf_chip);
 691                 break;
 692         }
 693 }
 694
 695
 696 void
 697 ZEBRA_RFSerialRead(
 698         struct net_device *dev,
 699         u32             data2Write,
 700         u8              wLength,
 701         u32             *data2Read,
 702         u8              rLength,
 703         u8              low2high
 704         )
 705 {
 706         ThreeWireReg    twreg;
 707         int                             i;
 708         u16                     oval,oval2,oval3,tmp, wReg80;
 709         u32                     mask;
 710         u8                      u1bTmp;
 711         ThreeWireReg    tdata;
 712         //PHAL_DATA_8187        pHalData = GetHalData8187(pAdapter);
 713         { // RTL8187S HSSI Read/Write Function
 714                 u1bTmp = read_nic_byte(dev, RF_SW_CONFIG);
 715                 u1bTmp |=   RF_SW_CFG_SI;   //reg08[1]=1 Serial Interface(SI)
 716                 write_nic_byte(dev, RF_SW_CONFIG, u1bTmp);
 717         }
 718
 719         wReg80 = oval = read_nic_word(dev, RFPinsOutput);
 720         oval2 = read_nic_word(dev, RFPinsEnable);
 721         oval3 = read_nic_word(dev, RFPinsSelect);
 722
 723         write_nic_word(dev, RFPinsEnable, oval2|0xf);
 724         write_nic_word(dev, RFPinsSelect, oval3|0xf);
 725
 726         *data2Read = 0;
 727
 728         // We must clear BIT0-3 here, otherwise,
 729         // SW_Enalbe will be true when we first call ZEBRA_RFSerialRead() after 8187MPVC open,
 730         // which will cause the value read become 0. 2005.04.11, by rcnjko.
 731         oval &= ~0xf;
 732
 733         // Avoid collision with hardware three-wire.
 734         twreg.longData = 0;
 735         twreg.struc.enableB = 1;
 736         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(4);
 737
 738         twreg.longData = 0;
 739         twreg.struc.enableB = 0;
 740         twreg.struc.clk = 0;
 741         twreg.struc.read_write = 0;
 742         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(5);
 743
 744         mask = (low2high) ? 0x01 : ((u32)0x01<<(32-1));
 745         for(i = 0; i < wLength/2; i++)
 746         {
 747                 twreg.struc.data = ((data2Write&mask) != 0) ? 1 : 0;
 748                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 749                 twreg.struc.clk = 1;
 750                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 751                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 752
 753                 mask = (low2high) ? (mask<<1): (mask>>1);
 754
 755                 if(i == 2)
 756                 {
 757                         // Commented out by Jackie, 2004.08.26. <RJ_NOTE> We must comment out the following two lines for we cannot pull down VCOPDN during RF Serail Read.
 758                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0xe);     // turn off data enable
 759                         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0xe);
 760
 761                         twreg.struc.read_write=1;
 762                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 763                         twreg.struc.clk = 0;
 764                         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 765                         break;
 766                 }
 767                 twreg.struc.data = ((data2Write&mask) != 0) ? 1: 0;
 768                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 769                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 770
 771                 twreg.struc.clk = 0;
 772                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 773
 774                 mask = (low2high) ? (mask<<1) : (mask>>1);
 775         }
 776
 777         twreg.struc.clk = 0;
 778         twreg.struc.data = 0;
 779         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 780         mask = (low2high) ? 0x01 : ((u32)0x01 << (12-1));
 781
 782         //
 783         // 061016, by rcnjko:
 784         // We must set data pin to HW controled, otherwise RF can't driver it and
 785         // value RF register won't be able to read back properly.
 786         //
 787         write_nic_word(dev, RFPinsEnable, ( ((oval2|0x0E) & (~0x01))) );
 788
 789         for(i = 0; i < rLength; i++)
 790         {
 791                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(1);
 792                 twreg.struc.clk = 1;
 793                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 794                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 795                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 796                 tmp = read_nic_word(dev, RFPinsInput);
 797                 tdata.longData = tmp;
 798                 *data2Read |= tdata.struc.clk ? mask : 0;
 799
 800                 twreg.struc.clk = 0;
 801                 write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 802
 803                 mask = (low2high) ? (mask<<1) : (mask>>1);
 804         }
 805         twreg.struc.enableB = 1;
 806         twreg.struc.clk = 0;
 807         twreg.struc.data = 0;
 808         twreg.struc.read_write = 1;
 809         write_nic_word(dev, RFPinsOutput, twreg.longData|oval); udelay(2);
 810
 811         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, oval2|0x8);   // Set To Output Enable
 812         write_nic_word(dev, RFPinsEnable, oval2);   // Set To Output Enable, <RJ_NOTE> We cannot enable BIT3 here, otherwise, we will failed to switch channel. 2005.04.12.
 813         //PlatformEFIOWrite2Byte(pAdapter, RFPinsEnable, 0x1bff);
 814         write_nic_word(dev, RFPinsSelect, oval3);   // Set To SW Switch
 815         //PlatformEFIOWrite2Byte(pAdapter, RFPinsSelect, 0x0488);
 816         write_nic_word(dev, RFPinsOutput, 0x3a0);
 817         //PlatformEFIOWrite2Byte(pAdapter, RFPinsOutput, 0x0480);
 818 }
 819
 820
 821 u32
 822 RF_ReadReg(
 823         struct net_device *dev,
 824         u8              offset
 825         )
 826 {
 827         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 828         u32                     data2Write;
 829         u8                      wlen;
 830         u8                      rlen;
 831         u8                      low2high;
 832         u32                     dataRead;
 833
 834         switch(priv->rf_chip)
 835         {
 836         case RFCHIPID_RTL8225:
 837         case RF_ZEBRA2:
 838         case RF_ZEBRA4:
 839                 switch(priv->RegThreeWireMode)
 840                 {
 841                         case HW_THREE_WIRE_PI: // For 87S  Parallel Interface.
 842                         {
 843                                 data2Write = ((u32)(offset&0x0f));
 844                                 wlen=16;
 845                                 HwHSSIThreeWire(
 846                                         dev,
 847                                         (u8*)(&data2Write),     // pDataBuf,
 848                                         wlen,                                   // nDataBufBitCnt,
 849                                         0,                                      // bSI
 850                                         0);                                     // bWrite
 851                                 dataRead= data2Write;
 852                         }
 853                         break;
 854
 855                         case HW_THREE_WIRE_SI: // For 87S Serial Interface.
 856                         {
 857                                 data2Write = ((u32)(offset&0x0f)) ;
 858                                 wlen=16;
 859                                 HwHSSIThreeWire(
 860                                         dev,
 861                                         (u8*)(&data2Write),     // pDataBuf,
 862                                         wlen,                                   // nDataBufBitCnt,
 863                                         1,                                      // bSI
 864                                         0                                       // bWrite
 865                                         );
 866                                 dataRead= data2Write;
 867                         }
 868                         break;
 869
 870                         // Perform SW 3-wire programming by driver.
 871                         default:
 872                         {
 873                                 data2Write = ((u32)(offset&0x1f)) << 27; // For Zebra E-cut. 2005.04.11, by rcnjko.
 874                                 wlen = 6;
 875                                 rlen = 12;
 876                                 low2high = 0;
 877                                 ZEBRA_RFSerialRead(dev, data2Write, wlen,&dataRead,rlen, low2high);
 878                         }
 879                         break;
 880                 }
 881                 break;
 882         default:
 883                 dataRead = 0;
 884                 break;
 885         }
 886
 887         return dataRead;
 888 }
 889
 890
 891 // by Owen on 04/07/14 for writing BB register successfully
 892 void
 893 WriteBBPortUchar(
 894         struct net_device *dev,
 895         u32             Data
 896         )
 897 {
 898         //u8    TimeoutCounter;
 899         u8      RegisterContent;
 900         u8      UCharData;
 901
 902         UCharData = (u8)((Data & 0x0000ff00) >> 8);
 903         PlatformIOWrite4Byte(dev, PhyAddr, Data);
 904         //for(TimeoutCounter = 10; TimeoutCounter > 0; TimeoutCounter--)
 905         {
 906                 PlatformIOWrite4Byte(dev, PhyAddr, Data & 0xffffff7f);
 907                 RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 908                 //if(UCharData == RegisterContent)
 909                 //      break;
 910         }
 911 }
 912
 913 u8
 914 ReadBBPortUchar(
 915         struct net_device *dev,
 916         u32             addr
 917         )
 918 {
 919         //u8    TimeoutCounter;
 920         u8      RegisterContent;
 921
 922         PlatformIOWrite4Byte(dev, PhyAddr, addr & 0xffffff7f);
 923         RegisterContent = PlatformIORead1Byte(dev, PhyDataR);
 924
 925         return RegisterContent;
 926 }
 927 //{by amy 080312
 928 //
 929 //      Description:
 930 //              Perform Antenna settings with antenna diversity on 87SE.
 931 //    Created by Roger, 2008.01.25.
 932 //
 933 bool
 934 SetAntennaConfig87SE(
 935         struct net_device *dev,
 936         u8                      DefaultAnt,             // 0: Main, 1: Aux.
 937         bool            bAntDiversity   // 1:Enable, 0: Disable.
 938 )
 939 {
 940         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
 941         bool   bAntennaSwitched = true;
 942
 943         //printk("SetAntennaConfig87SE(): DefaultAnt(%d), bAntDiversity(%d)\n", DefaultAnt, bAntDiversity);
 944
 945         // Threshold for antenna diversity.
 946         write_phy_cck(dev, 0x0c, 0x09); // Reg0c : 09
 947
 948         if( bAntDiversity )  //  Enable Antenna Diversity.
 949         {
 950                 if( DefaultAnt == 1 )  // aux antenna
 951                 {
 952                         // Mac register, aux antenna
 953                         write_nic_byte(dev, ANTSEL, 0x00);
 954
 955                         // Config CCK RX antenna.
 956                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 957                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 958
 959                         // Config OFDM RX antenna.
 960                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 961                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 962                 }
 963                 else //  use main antenna
 964                 {
 965                         // Mac register, main antenna
 966                         write_nic_byte(dev, ANTSEL, 0x03);
 967                         //base band
 968                         // Config CCK RX antenna.
 969                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 970                         write_phy_cck(dev, 0x01, 0xc7); // Reg01 : c7
 971
 972                         // Config OFDM RX antenna.
 973                         write_phy_ofdm(dev, 0x0d, 0x5c);   // Reg0d : 5c
 974                         write_phy_ofdm(dev, 0x18, 0xb2);  // Reg18 : b2
 975                 }
 976         }
 977         else   // Disable Antenna Diversity.
 978         {
 979                 if( DefaultAnt == 1 ) // aux Antenna
 980                 {
 981                         // Mac register, aux antenna
 982                         write_nic_byte(dev, ANTSEL, 0x00);
 983
 984                         // Config CCK RX antenna.
 985                         write_phy_cck(dev, 0x11, 0xbb); // Reg11 : bb
 986                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
 987
 988                         // Config OFDM RX antenna.
 989                         write_phy_ofdm(dev, 0x0D, 0x54);   // Reg0d : 54
 990                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
 991                 }
 992                 else // main Antenna
 993                 {
 994                         // Mac register, main antenna
 995                         write_nic_byte(dev, ANTSEL, 0x03);
 996
 997                         // Config CCK RX antenna.
 998                         write_phy_cck(dev, 0x11, 0x9b); // Reg11 : 9b
 999                         write_phy_cck(dev, 0x01, 0x47); // Reg01 : 47
1000
1001                         // Config OFDM RX antenna.
1002                         write_phy_ofdm(dev, 0x0D, 0x5c);   // Reg0d : 5c
1003                         write_phy_ofdm(dev, 0x18, 0x32);  // Reg18 : 32
1004                 }
1005         }
1006         priv->CurrAntennaIndex = DefaultAnt; // Update default settings.
1007         return  bAntennaSwitched;
1008 }
1009 //by amy 080312
1010 /*---------------------------------------------------------------
1011   * Hardware Initialization.
1012   * the code is ported from Windows source code
1013   ----------------------------------------------------------------*/
1014
1015 void
1016 ZEBRA_Config_85BASIC_HardCode(
1017         struct net_device *dev
1018         )
1019 {
1020
1021         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1022         u32                     i;
1023         u32     addr,data;
1024         u32     u4bRegOffset, u4bRegValue, u4bRF23, u4bRF24;
1025        u8                       u1b24E;
1026
1027
1028         //=============================================================================
1029         // 87S_PCIE :: RADIOCFG.TXT
1030         //=============================================================================
1031
1032
1033         // Page1 : reg16-reg30
1034         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1); // switch to page1
1035         u4bRF23= RF_ReadReg(dev, 0x08);                 mdelay(1);
1036         u4bRF24= RF_ReadReg(dev, 0x09);                 mdelay(1);
1037
1038         if (u4bRF23==0x818 && u4bRF24==0x70C && priv->card_8185 == VERSION_8187S_C)
1039                 priv->card_8185 = VERSION_8187S_D;
1040
1041         // Page0 : reg0-reg15
1042
1043 //      RF_WriteReg(dev, 0x00, 0x003f);                 mdelay(1);//1
1044         RF_WriteReg(dev, 0x00, 0x009f);         mdelay(1);// 1
1045
1046         RF_WriteReg(dev, 0x01, 0x06e0);                 mdelay(1);
1047
1048 //      RF_WriteReg(dev, 0x02, 0x004c);                 mdelay(1);//2
1049         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1);// 2
1050
1051 //      RF_WriteReg(dev, 0x03, 0x0000);                 mdelay(1);//3
1052         RF_WriteReg(dev, 0x03, 0x07f1);                 mdelay(1);// 3
1053
1054         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1);
1055         RF_WriteReg(dev, 0x05, 0x0c72);                 mdelay(1);
1056         RF_WriteReg(dev, 0x06, 0x0ae6);                 mdelay(1);
1057         RF_WriteReg(dev, 0x07, 0x00ca);                 mdelay(1);
1058         RF_WriteReg(dev, 0x08, 0x0e1c);                 mdelay(1);
1059         RF_WriteReg(dev, 0x09, 0x02f0);                 mdelay(1);
1060         RF_WriteReg(dev, 0x0a, 0x09d0);                 mdelay(1);
1061         RF_WriteReg(dev, 0x0b, 0x01ba);                 mdelay(1);
1062         RF_WriteReg(dev, 0x0c, 0x0640);                 mdelay(1);
1063         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1);
1064         RF_WriteReg(dev, 0x0e, 0x0020);                 mdelay(1);
1065         RF_WriteReg(dev, 0x0f, 0x0990);                 mdelay(1);
1066
1067
1068         // Page1 : reg16-reg30
1069         RF_WriteReg(dev, 0x00, 0x013f);                 mdelay(1);
1070
1071         RF_WriteReg(dev, 0x03, 0x0806);                 mdelay(1);
1072
1073         if(priv->card_8185 < VERSION_8187S_C)
1074         {
1075                 RF_WriteReg(dev, 0x04, 0x03f7);                 mdelay(1);
1076                 RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1);
1077                 RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1078         }
1079         else
1080         {
1081                 RF_WriteReg(dev, 0x04, 0x03a7);                 mdelay(1);
1082                 RF_WriteReg(dev, 0x05, 0x059b);                 mdelay(1);
1083                 RF_WriteReg(dev, 0x06, 0x0081);                 mdelay(1);
1084         }
1085
1086
1087         RF_WriteReg(dev, 0x07, 0x01A0);                 mdelay(1);
1088 // Don't write RF23/RF24 to make a difference between 87S C cut and D cut. asked by SD3 stevenl.
1089 //      RF_WriteReg(dev, 0x08, 0x0597);                 mdelay(1);
1090 //      RF_WriteReg(dev, 0x09, 0x050a);                 mdelay(1);
1091         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1092         RF_WriteReg(dev, 0x0b, 0x0418);                 mdelay(1);
1093
1094         if(priv->card_8185 == VERSION_8187S_D)
1095         {
1096                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1097                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1098                 RF_WriteReg(dev, 0x0e, 0x0807);                 mdelay(1); // RX LO buffer
1099         }
1100         else
1101         {
1102                 RF_WriteReg(dev, 0x0c, 0x0fbe);                 mdelay(1);
1103                 RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);
1104                 RF_WriteReg(dev, 0x0e, 0x0806);                 mdelay(1); // RX LO buffer
1105         }
1106
1107         RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1108
1109 //      RF_WriteReg(dev, 0x00, 0x017f);                 mdelay(1);//6
1110         RF_WriteReg(dev, 0x00, 0x01d7);                 mdelay(1);// 6
1111
1112         RF_WriteReg(dev, 0x03, 0x0e00);                 mdelay(1);
1113         RF_WriteReg(dev, 0x04, 0x0e50);                 mdelay(1);
1114         for(i=0;i<=36;i++)
1115         {
1116                 RF_WriteReg(dev, 0x01, i);                     mdelay(1);
1117                 RF_WriteReg(dev, 0x02, ZEBRA_RF_RX_GAIN_TABLE[i]); mdelay(1);
1118                 //DbgPrint("RF - 0x%x = 0x%x", i, ZEBRA_RF_RX_GAIN_TABLE[i]);
1119         }
1120
1121         RF_WriteReg(dev, 0x05, 0x0203);                 mdelay(1);      /// 203, 343
1122         //RF_WriteReg(dev, 0x06, 0x0300);                       mdelay(1);      // 400
1123         RF_WriteReg(dev, 0x06, 0x0200);                 mdelay(1);      // 400
1124
1125         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30, and HSSI disable 137
1126         mdelay(10);     // Deay 10 ms. //0xfd
1127
1128 //      RF_WriteReg(dev, 0x0c, 0x09be);                 mdelay(1);      // 7
1129         //RF_WriteReg(dev, 0x0c, 0x07be);                       mdelay(1);
1130         //mdelay(10);   // Deay 10 ms. //0xfd
1131
1132         RF_WriteReg(dev, 0x0d, 0x0008);                 mdelay(1);      // Z4 synthesizer loop filter setting, 392
1133         mdelay(10);     // Deay 10 ms. //0xfd
1134
1135         RF_WriteReg(dev, 0x00, 0x0037);                 mdelay(1);      // switch to reg0-reg15, and HSSI disable
1136         mdelay(10);     // Deay 10 ms. //0xfd
1137
1138         RF_WriteReg(dev, 0x04, 0x0160);                 mdelay(1);      // CBC on, Tx Rx disable, High gain
1139         mdelay(10);     // Deay 10 ms. //0xfd
1140
1141         RF_WriteReg(dev, 0x07, 0x0080);                 mdelay(1);      // Z4 setted channel 1
1142         mdelay(10);     // Deay 10 ms. //0xfd
1143
1144         RF_WriteReg(dev, 0x02, 0x088D);                 mdelay(1);      // LC calibration
1145         mdelay(200);    // Deay 200 ms. //0xfd
1146         mdelay(10);     // Deay 10 ms. //0xfd
1147         mdelay(10);     // Deay 10 ms. //0xfd
1148
1149         RF_WriteReg(dev, 0x00, 0x0137);                 mdelay(1);      // switch to reg16-reg30 137, and HSSI disable 137
1150         mdelay(10);     // Deay 10 ms. //0xfd
1151
1152         RF_WriteReg(dev, 0x07, 0x0000);                 mdelay(1);
1153         RF_WriteReg(dev, 0x07, 0x0180);                 mdelay(1);
1154         RF_WriteReg(dev, 0x07, 0x0220);                 mdelay(1);
1155         RF_WriteReg(dev, 0x07, 0x03E0);                 mdelay(1);
1156
1157         // DAC calibration off 20070702
1158         RF_WriteReg(dev, 0x06, 0x00c1);                 mdelay(1);
1159         RF_WriteReg(dev, 0x0a, 0x0001);                 mdelay(1);
1160 //{by amy 080312
1161         // For crystal calibration, added by Roger, 2007.12.11.
1162         if( priv->bXtalCalibration ) // reg 30.
1163         { // enable crystal calibration.
1164                 // RF Reg[30], (1)Xin:[12:9], Xout:[8:5],  addr[4:0].
1165                 // (2)PA Pwr delay timer[15:14], default: 2.4us, set BIT15=0
1166                 // (3)RF signal on/off when calibration[13], default: on, set BIT13=0.
1167                 // So we should minus 4 BITs offset.
1168                 RF_WriteReg(dev, 0x0f, (priv->XtalCal_Xin<<5)|(priv->XtalCal_Xout<<1)|BIT11|BIT9);                      mdelay(1);
1169                 printk("ZEBRA_Config_85BASIC_HardCode(): (%02x)\n",
1170                                 (priv->XtalCal_Xin<<5) | (priv->XtalCal_Xout<<1) | BIT11| BIT9);
1171         }
1172         else
1173         { // using default value. Xin=6, Xout=6.
1174                 RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);
1175         }
1176 //by amy 080312
1177 //      RF_WriteReg(dev, 0x0f, 0x0acc);                 mdelay(1);  //-by amy 080312
1178
1179         RF_WriteReg(dev, 0x00, 0x00bf);                 mdelay(1); // switch to reg0-reg15, and HSSI enable
1180 //      RF_WriteReg(dev, 0x0d, 0x009f);                 mdelay(1); // Rx BB start calibration, 00c//-edward
1181         RF_WriteReg(dev, 0x0d, 0x08df);                 mdelay(1); // Rx BB start calibration, 00c//+edward
1182         RF_WriteReg(dev, 0x02, 0x004d);                 mdelay(1); // temperature meter off
1183         RF_WriteReg(dev, 0x04, 0x0975);                 mdelay(1); // Rx mode
1184         mdelay(10);     // Deay 10 ms. //0xfe
1185         mdelay(10);     // Deay 10 ms. //0xfe
1186         mdelay(10);     // Deay 10 ms. //0xfe
1187         RF_WriteReg(dev, 0x00, 0x0197);                 mdelay(1); // Rx mode//+edward
1188         RF_WriteReg(dev, 0x05, 0x05ab);                 mdelay(1); // Rx mode//+edward
1189         RF_WriteReg(dev, 0x00, 0x009f);                 mdelay(1); // Rx mode//+edward
1190
1191         RF_WriteReg(dev, 0x01, 0x0000);                 mdelay(1); // Rx mode//+edward
1192         RF_WriteReg(dev, 0x02, 0x0000);                 mdelay(1); // Rx mode//+edward
1193         //power save parameters.
1194         u1b24E = read_nic_byte(dev, 0x24E);
1195         write_nic_byte(dev, 0x24E, (u1b24E & (~(BIT5|BIT6))));
1196
1197         //=============================================================================
1198
1199         //=============================================================================
1200         // CCKCONF.TXT
1201         //=============================================================================
1202
1203         /*      [POWER SAVE] Power Saving Parameters by jong. 2007-11-27
1204                 CCK reg0x00[7]=1'b1 :power saving for TX (default)
1205                 CCK reg0x00[6]=1'b1: power saving for RX (default)
1206                 CCK reg0x06[4]=1'b1: turn off channel estimation related circuits if not doing channel estimation.
1207                 CCK reg0x06[3]=1'b1: turn off unused circuits before cca = 1
1208                 CCK reg0x06[2]=1'b1: turn off cck's circuit if macrst =0
1209         */
1210
1211         write_phy_cck(dev,0x00,0xc8);
1212         write_phy_cck(dev,0x06,0x1c);
1213         write_phy_cck(dev,0x10,0x78);
1214         write_phy_cck(dev,0x2e,0xd0);
1215         write_phy_cck(dev,0x2f,0x06);
1216         write_phy_cck(dev,0x01,0x46);
1217
1218         // power control
1219         write_nic_byte(dev, CCK_TXAGC, 0x10);
1220         write_nic_byte(dev, OFDM_TXAGC, 0x1B);
1221         write_nic_byte(dev, ANTSEL, 0x03);
1222
1223
1224
1225         //=============================================================================
1226         // AGC.txt
1227         //=============================================================================
1228
1229 //      PlatformIOWrite4Byte( dev, PhyAddr, 0x00001280);        // Annie, 2006-05-05
1230         write_phy_ofdm(dev, 0x00, 0x12);
1231         //WriteBBPortUchar(dev, 0x00001280);
1232
1233         for (i=0; i<128; i++)
1234         {
1235                 //DbgPrint("AGC - [%x+1] = 0x%x\n", i, ZEBRA_AGC[i+1]);
1236
1237                 data = ZEBRA_AGC[i+1];
1238                 data = data << 8;
1239                 data = data | 0x0000008F;
1240
1241                 addr = i + 0x80; //enable writing AGC table
1242                 addr = addr << 8;
1243                 addr = addr | 0x0000008E;
1244
1245                 WriteBBPortUchar(dev, data);
1246                 WriteBBPortUchar(dev, addr);
1247                 WriteBBPortUchar(dev, 0x0000008E);
1248         }
1249
1250         PlatformIOWrite4Byte( dev, PhyAddr, 0x00001080);        // Annie, 2006-05-05
1251         //WriteBBPortUchar(dev, 0x00001080);
1252
1253         //=============================================================================
1254
1255         //=============================================================================
1256         // OFDMCONF.TXT
1257         //=============================================================================
1258
1259         for(i=0; i<60; i++)
1260         {
1261                 u4bRegOffset=i;
1262                 u4bRegValue=OFDM_CONFIG[i];
1263
1264                 //DbgPrint("OFDM - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1265
1266                 WriteBBPortUchar(dev,
1267                                                 (0x00000080 |
1268                                                 (u4bRegOffset & 0x7f) |
1269                                                 ((u4bRegValue & 0xff) << 8)));
1270         }
1271
1272         //=============================================================================
1273 //by amy for antenna
1274         //=============================================================================
1275 //{by amy 080312
1276         // Config Sw/Hw  Combinational Antenna Diversity. Added by Roger, 2008.02.26.
1277         SetAntennaConfig87SE(dev, priv->bDefaultAntenna1, priv->bSwAntennaDiverity);
1278 //by amy 080312}
1279 //by amy for antenna
1280 }
1281
1282
1283 void
1284 UpdateInitialGain(
1285         struct net_device *dev
1286         )
1287 {
1288         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1289         //unsigned char* IGTable;
1290         //u8                    DIG_CurrentInitialGain = 4;
1291         //unsigned char u1Tmp;
1292
1293         //lzm add 080826
1294         if(priv->eRFPowerState != eRfOn)
1295         {
1296                 //Don't access BB/RF under disable PLL situation.
1297                 //RT_TRACE(COMP_DIG, DBG_LOUD, ("UpdateInitialGain - pHalData->eRFPowerState!=eRfOn\n"));
1298                 // Back to the original state
1299                 priv->InitialGain= priv->InitialGainBackUp;
1300                 return;
1301         }
1302
1303         switch(priv->rf_chip)
1304         {
1305         case RF_ZEBRA4:
1306                 // Dynamic set initial gain, follow 87B
1307                 switch(priv->InitialGain)
1308                 {
1309                         case 1: //m861dBm
1310                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm \n");
1311                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1312                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1313                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1314                                 break;
1315
1316                         case 2: //m862dBm
1317                                 //DMESG("RTL8187 + 8225 Initial Gain State 2: -82 dBm \n");
1318                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1319                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1320                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1321                                 break;
1322
1323                         case 3: //m863dBm
1324                                 //DMESG("RTL8187 + 8225 Initial Gain State 3: -82 dBm \n");
1325                                 write_phy_ofdm(dev, 0x17, 0x36);        mdelay(1);
1326                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1327                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1328                                 break;
1329
1330                         case 4: //m864dBm
1331                                 //DMESG("RTL8187 + 8225 Initial Gain State 4: -78 dBm \n");
1332                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1333                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1334                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1335                                 break;
1336
1337                         case 5: //m82dBm
1338                                 //DMESG("RTL8187 + 8225 Initial Gain State 5: -74 dBm \n");
1339                                 write_phy_ofdm(dev, 0x17, 0x46);        mdelay(1);
1340                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1341                                 write_phy_ofdm(dev, 0x05, 0xfb);        mdelay(1);
1342                                 break;
1343
1344                         case 6: //m78dBm
1345                                 //DMESG ("RTL8187 + 8225 Initial Gain State 6: -70 dBm \n");
1346                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1347                                 write_phy_ofdm(dev, 0x24, 0x96);        mdelay(1);
1348                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1349                                 break;
1350
1351                         case 7: //m74dBm
1352                                 //DMESG("RTL8187 + 8225 Initial Gain State 7: -66 dBm \n");
1353                                 write_phy_ofdm(dev, 0x17, 0x56);        mdelay(1);
1354                                 write_phy_ofdm(dev, 0x24, 0xa6);        mdelay(1);
1355                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1356                                 break;
1357
1358                         case 8:
1359                                 //DMESG("RTL8187 + 8225 Initial Gain State 8:\n");
1360                                 write_phy_ofdm(dev, 0x17, 0x66);        mdelay(1);
1361                                 write_phy_ofdm(dev, 0x24, 0xb6);        mdelay(1);
1362                                 write_phy_ofdm(dev, 0x05, 0xfc);        mdelay(1);
1363                                 break;
1364
1365
1366                         default:        //MP
1367                                 //DMESG("RTL8187 + 8225 Initial Gain State 1: -82 dBm (default)\n");
1368                                 write_phy_ofdm(dev, 0x17, 0x26);        mdelay(1);
1369                                 write_phy_ofdm(dev, 0x24, 0x86);        mdelay(1);
1370                                 write_phy_ofdm(dev, 0x05, 0xfa);        mdelay(1);
1371                                 break;
1372                 }
1373                 break;
1374
1375
1376         default:
1377                 DMESG("UpdateInitialGain(): unknown RFChipID: %#X\n", priv->rf_chip);
1378                 break;
1379         }
1380 }
1381 //
1382 //      Description:
1383 //              Tx Power tracking mechanism routine on 87SE.
1384 //      Created by Roger, 2007.12.11.
1385 //
1386 void
1387 InitTxPwrTracking87SE(
1388         struct net_device *dev
1389 )
1390 {
1391         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1392         u32     u4bRfReg;
1393
1394         u4bRfReg = RF_ReadReg(dev, 0x02);
1395
1396         // Enable Thermal meter indication.
1397         //printk("InitTxPwrTracking87SE(): Enable thermal meter indication, Write RF[0x02] = %#x", u4bRfReg|PWR_METER_EN);
1398         RF_WriteReg(dev, 0x02, u4bRfReg|PWR_METER_EN);                  mdelay(1);
1399 }
1400
1401 void
1402 PhyConfig8185(
1403         struct net_device *dev
1404         )
1405 {
1406         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1407        write_nic_dword(dev, RCR, priv->ReceiveConfig);
1408            priv->RFProgType = read_nic_byte(dev, CONFIG4) & 0x03;
1409         // RF config
1410         switch(priv->rf_chip)
1411         {
1412         case RF_ZEBRA2:
1413         case RF_ZEBRA4:
1414                 ZEBRA_Config_85BASIC_HardCode( dev);
1415                 break;
1416         }
1417 //{by amy 080312
1418         // Set default initial gain state to 4, approved by SD3 DZ, by Bruce, 2007-06-06.
1419         if(priv->bDigMechanism)
1420         {
1421                 if(priv->InitialGain == 0)
1422                         priv->InitialGain = 4;
1423                 //printk("PhyConfig8185(): DIG is enabled, set default initial gain index to %d\n", priv->InitialGain);
1424         }
1425
1426         //
1427         // Enable thermal meter indication to implement TxPower tracking on 87SE.
1428         // We initialize thermal meter here to avoid unsuccessful configuration.
1429         // Added by Roger, 2007.12.11.
1430         //
1431         if(priv->bTxPowerTrack)
1432                 InitTxPwrTracking87SE(dev);
1433
1434 //by amy 080312}
1435         priv->InitialGainBackUp= priv->InitialGain;
1436         UpdateInitialGain(dev);
1437
1438         return;
1439 }
1440
1441
1442
1443
1444 void
1445 HwConfigureRTL8185(
1446                 struct net_device *dev
1447                 )
1448 {
1449         //RTL8185_TODO: Determine Retrylimit, TxAGC, AutoRateFallback control.
1450 //      u8              bUNIVERSAL_CONTROL_RL = 1;
1451         u8              bUNIVERSAL_CONTROL_RL = 0;
1452
1453         u8              bUNIVERSAL_CONTROL_AGC = 1;
1454         u8              bUNIVERSAL_CONTROL_ANT = 1;
1455         u8              bAUTO_RATE_FALLBACK_CTL = 1;
1456         u8              val8;
1457         //struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1458         //struct ieee80211_device *ieee = priv->ieee80211;
1459         //if(IS_WIRELESS_MODE_A(dev) || IS_WIRELESS_MODE_G(dev))
1460 //{by amy 080312        if((ieee->mode == IEEE_G)||(ieee->mode == IEEE_A))
1461 //      {
1462 //              write_nic_word(dev, BRSR, 0xffff);
1463 //      }
1464 //      else
1465 //      {
1466 //              write_nic_word(dev, BRSR, 0x000f);
1467 //      }
1468 //by amy 080312}
1469         write_nic_word(dev, BRSR, 0x0fff);
1470         // Retry limit
1471         val8 = read_nic_byte(dev, CW_CONF);
1472
1473         if(bUNIVERSAL_CONTROL_RL)
1474                 val8 = val8 & 0xfd;
1475         else
1476                 val8 = val8 | 0x02;
1477
1478         write_nic_byte(dev, CW_CONF, val8);
1479
1480         // Tx AGC
1481         val8 = read_nic_byte(dev, TXAGC_CTL);
1482         if(bUNIVERSAL_CONTROL_AGC)
1483         {
1484                 write_nic_byte(dev, CCK_TXAGC, 128);
1485                 write_nic_byte(dev, OFDM_TXAGC, 128);
1486                 val8 = val8 & 0xfe;
1487         }
1488         else
1489         {
1490                 val8 = val8 | 0x01 ;
1491         }
1492
1493
1494         write_nic_byte(dev, TXAGC_CTL, val8);
1495
1496         // Tx Antenna including Feedback control
1497         val8 = read_nic_byte(dev, TXAGC_CTL );
1498
1499         if(bUNIVERSAL_CONTROL_ANT)
1500         {
1501                 write_nic_byte(dev, ANTSEL, 0x00);
1502                 val8 = val8 & 0xfd;
1503         }
1504         else
1505         {
1506                 val8 = val8 & (val8|0x02); //xiong-2006-11-15
1507         }
1508
1509         write_nic_byte(dev, TXAGC_CTL, val8);
1510
1511         // Auto Rate fallback control
1512         val8 = read_nic_byte(dev, RATE_FALLBACK);
1513         val8 &= 0x7c;
1514         if( bAUTO_RATE_FALLBACK_CTL )
1515         {
1516                 val8 |= RATE_FALLBACK_CTL_ENABLE | RATE_FALLBACK_CTL_AUTO_STEP1;
1517
1518                 // <RJ_TODO_8185B> We shall set up the ARFR according to user's setting.
1519                 //write_nic_word(dev, ARFR, 0x0fff); // set 1M ~ 54M
1520 //by amy
1521                 // Aadded by Roger, 2007.11.15.
1522                 PlatformIOWrite2Byte(dev, ARFR, 0x0fff); //set 1M ~ 54Mbps.
1523 //by amy
1524         }
1525         else
1526         {
1527         }
1528         write_nic_byte(dev, RATE_FALLBACK, val8);
1529 }
1530
1531
1532
1533 static void
1534 MacConfig_85BASIC_HardCode(
1535         struct net_device *dev)
1536 {
1537         //============================================================================
1538         // MACREG.TXT
1539         //============================================================================
1540         int                     nLinesRead = 0;
1541
1542         u32     u4bRegOffset, u4bRegValue,u4bPageIndex = 0;
1543         int     i;
1544
1545         nLinesRead=sizeof(MAC_REG_TABLE)/2;
1546
1547         for(i = 0; i < nLinesRead; i++)  //nLinesRead=101
1548         {
1549                 u4bRegOffset=MAC_REG_TABLE[i][0];
1550                 u4bRegValue=MAC_REG_TABLE[i][1];
1551
1552                 if(u4bRegOffset == 0x5e)
1553                 {
1554                     u4bPageIndex = u4bRegValue;
1555                 }
1556                 else
1557                 {
1558                     u4bRegOffset |= (u4bPageIndex << 8);
1559                 }
1560                 //DbgPrint("MAC - 0x%x = 0x%x\n", u4bRegOffset, u4bRegValue);
1561                 write_nic_byte(dev, u4bRegOffset, (u8)u4bRegValue);
1562         }
1563         //============================================================================
1564 }
1565
1566
1567
1568 static void
1569 MacConfig_85BASIC(
1570         struct net_device *dev)
1571 {
1572
1573        u8                       u1DA;
1574         MacConfig_85BASIC_HardCode(dev);
1575
1576         //============================================================================
1577
1578         // Follow TID_AC_MAP of WMac.
1579         write_nic_word(dev, TID_AC_MAP, 0xfa50);
1580
1581         // Interrupt Migration, Jong suggested we use set 0x0000 first, 2005.12.14, by rcnjko.
1582         write_nic_word(dev, IntMig, 0x0000);
1583
1584         // Prevent TPC to cause CRC error. Added by Annie, 2006-06-10.
1585         PlatformIOWrite4Byte(dev, 0x1F0, 0x00000000);
1586         PlatformIOWrite4Byte(dev, 0x1F4, 0x00000000);
1587         PlatformIOWrite1Byte(dev, 0x1F8, 0x00);
1588
1589         // Asked for by SD3 CM Lin, 2006.06.27, by rcnjko.
1590         //PlatformIOWrite4Byte(dev, RFTiming, 0x00004001);
1591 //by amy
1592         // power save parameter based on "87SE power save parameters 20071127.doc", as follow.
1593
1594         //Enable DA10 TX power saving
1595         u1DA = read_nic_byte(dev, PHYPR);
1596         write_nic_byte(dev, PHYPR, (u1DA | BIT2) );
1597
1598         //POWER:
1599         write_nic_word(dev, 0x360, 0x1000);
1600         write_nic_word(dev, 0x362, 0x1000);
1601
1602         // AFE.
1603         write_nic_word(dev, 0x370, 0x0560);
1604         write_nic_word(dev, 0x372, 0x0560);
1605         write_nic_word(dev, 0x374, 0x0DA4);
1606         write_nic_word(dev, 0x376, 0x0DA4);
1607         write_nic_word(dev, 0x378, 0x0560);
1608         write_nic_word(dev, 0x37A, 0x0560);
1609         write_nic_word(dev, 0x37C, 0x00EC);
1610 //      write_nic_word(dev, 0x37E, 0x00FE);//-edward
1611         write_nic_word(dev, 0x37E, 0x00EC);//+edward
1612        write_nic_byte(dev, 0x24E,0x01);
1613 //by amy
1614
1615 }
1616
1617
1618
1619
1620 u8
1621 GetSupportedWirelessMode8185(
1622         struct net_device *dev
1623 )
1624 {
1625         u8                      btSupportedWirelessMode = 0;
1626         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1627
1628         switch(priv->rf_chip)
1629         {
1630         case RF_ZEBRA2:
1631         case RF_ZEBRA4:
1632                 btSupportedWirelessMode = (WIRELESS_MODE_B | WIRELESS_MODE_G);
1633                 break;
1634         default:
1635                 btSupportedWirelessMode = WIRELESS_MODE_B;
1636                 break;
1637         }
1638
1639         return btSupportedWirelessMode;
1640 }
1641
1642 void
1643 ActUpdateChannelAccessSetting(
1644         struct net_device *dev,
1645         WIRELESS_MODE                   WirelessMode,
1646         PCHANNEL_ACCESS_SETTING ChnlAccessSetting
1647         )
1648 {
1649         struct r8180_priv *priv = ieee80211_priv(dev);
1650         struct ieee80211_device *ieee = priv->ieee80211;
1651         AC_CODING       eACI;
1652         AC_PARAM        AcParam;
1653         //PSTA_QOS      pStaQos = Adapter->MgntInfo.pStaQos;
1654         u8      bFollowLegacySetting = 0;
1655         u8   u1bAIFS;
1656
1657         //
1658         // <RJ_TODO_8185B>
1659         // TODO: We still don't know how to set up these registers, just follow WMAC to
1660         // verify 8185B FPAG.
1661         //
1662         // <RJ_TODO_8185B>
1663         // Jong said CWmin/CWmax register are not functional in 8185B,
1664         // so we shall fill channel access realted register into AC parameter registers,
1665         // even in nQBss.
1666         //
1667         ChnlAccessSetting->SIFS_Timer = 0x22; // Suggested by Jong, 2005.12.08.
1668         ChnlAccessSetting->DIFS_Timer = 0x1C; // 2006.06.02, by rcnjko.
1669         ChnlAccessSetting->SlotTimeTimer = 9; // 2006.06.02, by rcnjko.
1670         ChnlAccessSetting->EIFS_Timer = 0x5B; // Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1671         ChnlAccessSetting->CWminIndex = 3; // 2006.06.02, by rcnjko.
1672         ChnlAccessSetting->CWmaxIndex = 7; // 2006.06.02, by rcnjko.
1673
1674         write_nic_byte(dev, SIFS, ChnlAccessSetting->SIFS_Timer);
1675         //Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_SLOT_TIME, &ChnlAccessSetting->SlotTimeTimer );     // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1676         write_nic_byte(dev, SLOT, ChnlAccessSetting->SlotTimeTimer);    // Rewrited from directly use PlatformEFIOWrite1Byte(), by Annie, 2006-03-29.
1677
1678         u1bAIFS = aSifsTime + (2 * ChnlAccessSetting->SlotTimeTimer );
1679
1680         //write_nic_byte(dev, AC_VO_PARAM, u1bAIFS);
1681         //write_nic_byte(dev, AC_VI_PARAM, u1bAIFS);
1682         //write_nic_byte(dev, AC_BE_PARAM, u1bAIFS);
1683         //write_nic_byte(dev, AC_BK_PARAM, u1bAIFS);
1684
1685         write_nic_byte(dev, EIFS, ChnlAccessSetting->EIFS_Timer);
1686
1687         write_nic_byte(dev, AckTimeOutReg, 0x5B); // <RJ_EXPR_QOS> Suggested by wcchu, it is the default value of EIFS register, 2005.12.08.
1688
1689 #ifdef TODO
1690         // <RJ_TODO_NOW_8185B> Update ECWmin/ECWmax, AIFS, TXOP Limit of each AC to the value defined by SPEC.
1691         if( pStaQos->CurrentQosMode > QOS_DISABLE )
1692         { // QoS mode.
1693                 if(pStaQos->QBssWirelessMode == WirelessMode)
1694                 {
1695                         // Follow AC Parameters of the QBSS.
1696                         for(eACI = 0; eACI < AC_MAX; eACI++)
1697                         {
1698                                 Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, (pu1Byte)(&(pStaQos->WMMParamEle.AcParam[eACI])) );
1699                         }
1700                 }
1701                 else
1702                 {
1703                         // Follow Default WMM AC Parameters.
1704                         bFollowLegacySetting = 1;
1705                 }
1706         }
1707         else
1708 #endif
1709         { // Legacy 802.11.
1710                 bFollowLegacySetting = 1;
1711
1712         }
1713
1714         // this setting is copied from rtl8187B.  xiong-2006-11-13
1715         if(bFollowLegacySetting)
1716         {
1717
1718
1719                 //
1720                 // Follow 802.11 seeting to AC parameter, all AC shall use the same parameter.
1721                 // 2005.12.01, by rcnjko.
1722                 //
1723                 AcParam.longData = 0;
1724                 AcParam.f.AciAifsn.f.AIFSN = 2; // Follow 802.11 DIFS.
1725                 AcParam.f.AciAifsn.f.ACM = 0;
1726                 AcParam.f.Ecw.f.ECWmin = ChnlAccessSetting->CWminIndex; // Follow 802.11 CWmin.
1727                 AcParam.f.Ecw.f.ECWmax = ChnlAccessSetting->CWmaxIndex; // Follow 802.11 CWmax.
1728                 AcParam.f.TXOPLimit = 0;
1729
1730                 //lzm reserved 080826
1731 #if 1
1732                 // For turbo mode setting. port from 87B by Isaiah 2008-08-01
1733                 if( ieee->current_network.Turbo_Enable == 1 )
1734                         AcParam.f.TXOPLimit = 0x01FF;
1735                 // For 87SE with Intel 4965  Ad-Hoc mode have poor throughput (19MB)
1736                 if (ieee->iw_mode == IW_MODE_ADHOC)
1737                         AcParam.f.TXOPLimit = 0x0020;
1738 #endif
1739
1740                 for(eACI = 0; eACI < AC_MAX; eACI++)
1741                 {
1742                         AcParam.f.AciAifsn.f.ACI = (u8)eACI;
1743                         {
1744                                 PAC_PARAM       pAcParam = (PAC_PARAM)(&AcParam);
1745                                 AC_CODING       eACI;
1746                                 u8              u1bAIFS;
1747                                 u32             u4bAcParam;
1748
1749                                 // Retrive paramters to udpate.
1750                                 eACI = pAcParam->f.AciAifsn.f.ACI;
1751                                 u1bAIFS = pAcParam->f.AciAifsn.f.AIFSN * ChnlAccessSetting->SlotTimeTimer + aSifsTime;
1752                                 u4bAcParam = (  (((u32)(pAcParam->f.TXOPLimit)) << AC_PARAM_TXOP_LIMIT_OFFSET)  |
1753                                                 (((u32)(pAcParam->f.Ecw.f.ECWmax)) << AC_PARAM_ECW_MAX_OFFSET)  |
1754                                                 (((u32)(pAcParam->f.Ecw.f.ECWmin)) << AC_PARAM_ECW_MIN_OFFSET)  |
1755                                                 (((u32)u1bAIFS) << AC_PARAM_AIFS_OFFSET));
1756
1757                                 switch(eACI)
1758                                 {
1759                                         case AC1_BK:
1760                                                 //write_nic_dword(dev, AC_BK_PARAM, u4bAcParam);
1761                                                 break;
1762
1763                                         case AC0_BE:
1764                                                 //write_nic_dword(dev, AC_BE_PARAM, u4bAcParam);
1765                                                 break;
1766
1767                                         case AC2_VI:
1768                                                 //write_nic_dword(dev, AC_VI_PARAM, u4bAcParam);
1769                                                 break;
1770
1771                                         case AC3_VO:
1772                                                 //write_nic_dword(dev, AC_VO_PARAM, u4bAcParam);
1773                                                 break;
1774
1775                                         default:
1776                                                 DMESGW( "SetHwReg8185(): invalid ACI: %d !\n", eACI);
1777                                                 break;
1778                                 }
1779
1780                                 // Cehck ACM bit.
1781                                 // If it is set, immediately set ACM control bit to downgrading AC for passing WMM testplan. Annie, 2005-12-13.
1782                                 //write_nic_byte(dev, ACM_CONTROL, pAcParam->f.AciAifsn);
1783                                 {
1784                                         PACI_AIFSN      pAciAifsn = (PACI_AIFSN)(&pAcParam->f.AciAifsn);
1785                                         AC_CODING       eACI = pAciAifsn->f.ACI;
1786
1787                                         //modified Joseph
1788                                         //for 8187B AsynIORead issue
1789 #ifdef TODO
1790                                         u8      AcmCtrl = pHalData->AcmControl;
1791 #else
1792                                         u8      AcmCtrl = 0;
1793 #endif
1794                                         if( pAciAifsn->f.ACM )
1795                                         { // ACM bit is 1.
1796                                                 switch(eACI)
1797                                                 {
1798                                                         case AC0_BE:
1799                                                                 AcmCtrl |= (BEQ_ACM_EN|BEQ_ACM_CTL|ACM_HW_EN);  // or 0x21
1800                                                                 break;
1801
1802                                                         case AC2_VI:
1803                                                                 AcmCtrl |= (VIQ_ACM_EN|VIQ_ACM_CTL|ACM_HW_EN);  // or 0x42
1804                                                                 break;
1805
1806                                                         case AC3_VO:
1807                                                                 AcmCtrl |= (VOQ_ACM_EN|VOQ_ACM_CTL|ACM_HW_EN);  // or 0x84
1808                                                                 break;
1809
1810                                                         default:
1811                                                                 DMESGW("SetHwReg8185(): [HW_VAR_ACM_CTRL] ACM set failed: eACI is %d\n", eACI );
1812                                                                 break;
1813                                                 }
1814                                         }
1815                                         else
1816                                         { // ACM bit is 0.
1817                                                 switch(eACI)
1818                                                 {
1819                                                         case AC0_BE:
1820                                                                 AcmCtrl &= ( (~BEQ_ACM_EN) & (~BEQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xDE
1821                                                                 break;
1822
1823                                                         case AC2_VI:
1824                                                                 AcmCtrl &= ( (~VIQ_ACM_EN) & (~VIQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0xBD
1825                                                                 break;
1826
1827                                                         case AC3_VO:
1828                                                                 AcmCtrl &= ( (~VOQ_ACM_EN) & (~VOQ_ACM_CTL) & (~ACM_HW_EN) );   // and 0x7B
1829                                                                 break;
1830
1831                                                         default:
1832                                                                 break;
1833                                                 }
1834                                         }
1835
1836                                         //printk(KERN_WARNING "SetHwReg8185(): [HW_VAR_ACM_CTRL] Write 0x%X\n", AcmCtrl);
1837
1838 #ifdef TO_DO
1839                                         pHalData->AcmControl = AcmCtrl;
1840 #endif
1841                                         //write_nic_byte(dev, ACM_CONTROL, AcmCtrl);
1842                                         write_nic_byte(dev, ACM_CONTROL, 0);
1843                                 }
1844                         }
1845                 }
1846
1847
1848         }
1849 }
1850
1851 void
1852 ActSetWirelessMode8185(
1853         struct net_device *dev,
1854         u8                              btWirelessMode
1855         )
1856 {
1857         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1858         struct ieee80211_device *ieee = priv->ieee80211;
1859         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
1860         u8      btSupportedWirelessMode = GetSupportedWirelessMode8185(dev);
1861
1862         if( (btWirelessMode & btSupportedWirelessMode) == 0 )
1863         { // Don't switch to unsupported wireless mode, 2006.02.15, by rcnjko.
1864                 DMESGW("ActSetWirelessMode8185(): WirelessMode(%d) is not supported (%d)!\n",
1865                         btWirelessMode, btSupportedWirelessMode);
1866                 return;
1867         }
1868
1869         // 1. Assign wireless mode to swtich if necessary.
1870         if (btWirelessMode == WIRELESS_MODE_AUTO)
1871         {
1872                 if((btSupportedWirelessMode & WIRELESS_MODE_A))
1873                 {
1874                         btWirelessMode = WIRELESS_MODE_A;
1875                 }
1876                 else if((btSupportedWirelessMode & WIRELESS_MODE_G))
1877                 {
1878                         btWirelessMode = WIRELESS_MODE_G;
1879                 }
1880                 else if((btSupportedWirelessMode & WIRELESS_MODE_B))
1881                 {
1882                         btWirelessMode = WIRELESS_MODE_B;
1883                 }
1884                 else
1885                 {
1886                         DMESGW("ActSetWirelessMode8185(): No valid wireless mode supported, btSupportedWirelessMode(%x)!!!\n",
1887                                          btSupportedWirelessMode);
1888                         btWirelessMode = WIRELESS_MODE_B;
1889                 }
1890         }
1891
1892
1893         // 2. Swtich band: RF or BB specific actions,
1894         // for example, refresh tables in omc8255, or change initial gain if necessary.
1895         switch(priv->rf_chip)
1896         {
1897         case RF_ZEBRA2:
1898         case RF_ZEBRA4:
1899                 {
1900                         // Nothing to do for Zebra to switch band.
1901                         // Update current wireless mode if we swtich to specified band successfully.
1902                         ieee->mode = (WIRELESS_MODE)btWirelessMode;
1903                 }
1904                 break;
1905
1906         default:
1907                 DMESGW("ActSetWirelessMode8185(): unsupported RF: 0x%X !!!\n", priv->rf_chip);
1908                 break;
1909         }
1910
1911         // 3. Change related setting.
1912         if( ieee->mode == WIRELESS_MODE_A ){
1913                 DMESG("WIRELESS_MODE_A\n");
1914         }
1915         else if( ieee->mode == WIRELESS_MODE_B ){
1916                 DMESG("WIRELESS_MODE_B\n");
1917         }
1918         else if( ieee->mode == WIRELESS_MODE_G ){
1919                 DMESG("WIRELESS_MODE_G\n");
1920         }
1921
1922         ActUpdateChannelAccessSetting( dev, ieee->mode, &priv->ChannelAccessSetting);
1923 }
1924
1925 void rtl8185b_irq_enable(struct net_device *dev)
1926 {
1927         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1928
1929         priv->irq_enabled = 1;
1930         write_nic_dword(dev, IMR, priv->IntrMask);
1931 }
1932 //by amy for power save
1933 void
1934 DrvIFIndicateDisassociation(
1935         struct net_device *dev,
1936         u16                     reason
1937         )
1938 {
1939         //printk("==> DrvIFIndicateDisassociation()\n");
1940
1941         // nothing is needed after disassociation request.
1942
1943         //printk("<== DrvIFIndicateDisassociation()\n");
1944 }
1945 void
1946 MgntDisconnectIBSS(
1947         struct net_device *dev
1948 )
1949 {
1950         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1951         u8                      i;
1952
1953         //printk("XXXXXXXXXX MgntDisconnect IBSS\n");
1954
1955         DrvIFIndicateDisassociation(dev, unspec_reason);
1956
1957 //      PlatformZeroMemory( pMgntInfo->Bssid, 6 );
1958         for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x55;
1959
1960         priv->ieee80211->state = IEEE80211_NOLINK;
1961
1962         //Stop Beacon.
1963
1964         // Vista add a Adhoc profile, HW radio off untill OID_DOT11_RESET_REQUEST
1965         // Driver would set MSR=NO_LINK, then HW Radio ON, MgntQueue Stuck.
1966         // Because Bcn DMA isn't complete, mgnt queue would stuck until Bcn packet send.
1967
1968         // Disable Beacon Queue Own bit, suggested by jong
1969 //      Adapter->HalFunc.SetTxDescOWNHandler(Adapter, BEACON_QUEUE, 0, 0);
1970         ieee80211_stop_send_beacons(priv->ieee80211);
1971
1972         priv->ieee80211->link_change(dev);
1973         notify_wx_assoc_event(priv->ieee80211);
1974
1975         // Stop SW Beacon.Use hw beacon so do not need to do so.by amy
1976
1977 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE );
1978
1979 }
1980 void
1981 MlmeDisassociateRequest(
1982         struct net_device *dev,
1983         u8*                     asSta,
1984         u8                      asRsn
1985         )
1986 {
1987         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
1988         u8 i;
1989
1990         SendDisassociation(priv->ieee80211, asSta, asRsn );
1991
1992         if( memcmp(priv->ieee80211->current_network.bssid, asSta, 6 ) == 0 ){
1993                 //ShuChen TODO: change media status.
1994                 //ShuChen TODO: What to do when disassociate.
1995                 DrvIFIndicateDisassociation(dev, unspec_reason);
1996
1997
1998         //      pMgntInfo->AsocTimestamp = 0;
1999                 for(i=0;i<6;i++)  priv->ieee80211->current_network.bssid[i] = 0x22;
2000 //              pMgntInfo->mBrates.Length = 0;
2001 //              Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
2002
2003                 ieee80211_disassociate(priv->ieee80211);
2004
2005
2006         }
2007
2008 }
2009
2010 void
2011 MgntDisconnectAP(
2012         struct net_device *dev,
2013         u8                      asRsn
2014 )
2015 {
2016         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2017
2018 //
2019 // Commented out by rcnjko, 2005.01.27:
2020 // I move SecClearAllKeys() to MgntActSet_802_11_DISASSOCIATE().
2021 //
2022 //      //2004/09/15, kcwu, the key should be cleared, or the new handshaking will not success
2023 //      SecClearAllKeys(Adapter);
2024
2025         // In WPA WPA2 need to Clear all key ... because new key will set after new handshaking.
2026 #ifdef TODO
2027         if(   pMgntInfo->SecurityInfo.AuthMode > RT_802_11AuthModeAutoSwitch ||
2028                 (pMgntInfo->bAPSuportCCKM && pMgntInfo->bCCX8021xenable) )  // In CCKM mode will Clear key
2029         {
2030                 SecClearAllKeys(Adapter);
2031                 RT_TRACE(COMP_SEC, DBG_LOUD,("======>CCKM clear key..."))
2032         }
2033 #endif
2034         // 2004.10.11, by rcnjko.
2035         //MlmeDisassociateRequest( Adapter, pMgntInfo->Bssid, disas_lv_ss );
2036         MlmeDisassociateRequest( dev, priv->ieee80211->current_network.bssid, asRsn );
2037
2038         priv->ieee80211->state = IEEE80211_NOLINK;
2039 //      pMgntInfo->AsocTimestamp = 0;
2040 }
2041 bool
2042 MgntDisconnect(
2043         struct net_device *dev,
2044         u8                      asRsn
2045 )
2046 {
2047         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2048         //
2049         // Schedule an workitem to wake up for ps mode, 070109, by rcnjko.
2050         //
2051 #ifdef TODO
2052         if(pMgntInfo->mPss != eAwake)
2053         {
2054                 //
2055                 // Using AwkaeTimer to prevent mismatch ps state.
2056                 // In the timer the state will be changed according to the RF is being awoke or not. By Bruce, 2007-10-31.
2057                 //
2058                 // PlatformScheduleWorkItem( &(pMgntInfo->AwakeWorkItem) );
2059                 PlatformSetTimer( Adapter, &(pMgntInfo->AwakeTimer), 0 );
2060         }
2061 #endif
2062
2063         // Indication of disassociation event.
2064         //DrvIFIndicateDisassociation(Adapter, asRsn);
2065         if(IS_DOT11D_ENABLE(priv->ieee80211))
2066                 Dot11d_Reset(priv->ieee80211);
2067         // In adhoc mode, update beacon frame.
2068         if( priv->ieee80211->state == IEEE80211_LINKED )
2069         {
2070                 if( priv->ieee80211->iw_mode == IW_MODE_ADHOC )
2071                 {
2072 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectIBSS\n"));
2073                         //printk("MgntDisconnect() ===> MgntDisconnectIBSS\n");
2074                         MgntDisconnectIBSS(dev);
2075                 }
2076                 if( priv->ieee80211->iw_mode == IW_MODE_INFRA )
2077                 {
2078                         // We clear key here instead of MgntDisconnectAP() because that
2079                         // MgntActSet_802_11_DISASSOCIATE() is an interface called by OS,
2080                         // e.g. OID_802_11_DISASSOCIATE in Windows while as MgntDisconnectAP() is
2081                         // used to handle disassociation related things to AP, e.g. send Disassoc
2082                         // frame to AP.  2005.01.27, by rcnjko.
2083 //                      SecClearAllKeys(Adapter);
2084
2085 //                      RT_TRACE(COMP_MLME, DBG_LOUD, ("MgntDisconnect() ===> MgntDisconnectAP\n"));
2086                         //printk("MgntDisconnect() ===> MgntDisconnectAP\n");
2087                         MgntDisconnectAP(dev, asRsn);
2088                 }
2089
2090                 // Inidicate Disconnect, 2005.02.23, by rcnjko.
2091 //              MgntIndicateMediaStatus( Adapter, RT_MEDIA_DISCONNECT, GENERAL_INDICATE);
2092         }
2093
2094         return true;
2095 }
2096 //
2097 //      Description:
2098 //              Chang RF Power State.
2099 //              Note that, only MgntActSet_RF_State() is allowed to set HW_VAR_RF_STATE.
2100 //
2101 //      Assumption:
2102 //              PASSIVE LEVEL.
2103 //
2104 bool
2105 SetRFPowerState(
2106         struct net_device *dev,
2107         RT_RF_POWER_STATE       eRFPowerState
2108         )
2109 {
2110         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2111         bool                    bResult = false;
2112
2113 //      printk("---------> SetRFPowerState(): eRFPowerState(%d)\n", eRFPowerState);
2114         if(eRFPowerState == priv->eRFPowerState)
2115         {
2116 //              printk("<--------- SetRFPowerState(): discard the request for eRFPowerState(%d) is the same.\n", eRFPowerState);
2117                 return bResult;
2118         }
2119
2120         switch(priv->rf_chip)
2121         {
2122                 case RF_ZEBRA2:
2123                 case RF_ZEBRA4:
2124                          bResult = SetZebraRFPowerState8185(dev, eRFPowerState);
2125                         break;
2126
2127                 default:
2128                         printk("SetRFPowerState8185(): unknown RFChipID: 0x%X!!!\n", priv->rf_chip);
2129                         break;;
2130 }
2131 //      printk("<--------- SetRFPowerState(): bResult(%d)\n", bResult);
2132
2133         return bResult;
2134 }
2135 void
2136 HalEnableRx8185Dummy(
2137         struct net_device *dev
2138         )
2139 {
2140 }
2141 void
2142 HalDisableRx8185Dummy(
2143         struct net_device *dev
2144         )
2145 {
2146 }
2147
2148 bool
2149 MgntActSet_RF_State(
2150         struct net_device *dev,
2151         RT_RF_POWER_STATE       StateToSet,
2152         u32     ChangeSource
2153         )
2154 {
2155         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2156         bool                            bActionAllowed = false;
2157         bool                            bConnectBySSID = false;
2158         RT_RF_POWER_STATE       rtState;
2159         u16                             RFWaitCounter = 0;
2160         unsigned long flag;
2161 //       printk("===>MgntActSet_RF_State(): StateToSet(%d), ChangeSource(0x%x)\n",StateToSet, ChangeSource);
2162         //
2163         // Prevent the race condition of RF state change. By Bruce, 2007-11-28.
2164         // Only one thread can change the RF state at one time, and others should wait to be executed.
2165         //
2166 #if 1
2167         while(true)
2168         {
2169 //              down(&priv->rf_state);
2170                 spin_lock_irqsave(&priv->rf_ps_lock,flag);
2171                 if(priv->RFChangeInProgress)
2172                 {
2173 //                      printk("====================>haha111111111\n");
2174 //                      up(&priv->rf_state);
2175 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): RF Change in progress! Wait to set..StateToSet(%d).\n", StateToSet));
2176                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2177                         // Set RF after the previous action is done.
2178                         while(priv->RFChangeInProgress)
2179                         {
2180                                 RFWaitCounter ++;
2181 //                              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Wait 1 ms (%d times)...\n", RFWaitCounter));
2182                                 udelay(1000); // 1 ms
2183
2184                                 // Wait too long, return FALSE to avoid to be stuck here.
2185                                 if(RFWaitCounter > 1000) // 1sec
2186                                 {
2187 //                                      RT_ASSERT(FALSE, ("MgntActSet_RF_State(): Wait too logn to set RF\n"));
2188                                         printk("MgntActSet_RF_State(): Wait too long to set RF\n");
2189                                         // TODO: Reset RF state?
2190                                         return false;
2191                                 }
2192                         }
2193                 }
2194                 else
2195                 {
2196 //                      printk("========================>haha2\n");
2197                         priv->RFChangeInProgress = true;
2198 //                      up(&priv->rf_state);
2199                         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2200                         break;
2201                 }
2202         }
2203 #endif
2204         rtState = priv->eRFPowerState;
2205
2206
2207         switch(StateToSet)
2208         {
2209         case eRfOn:
2210                 //
2211                 // Turn On RF no matter the IPS setting because we need to update the RF state to Ndis under Vista, or
2212                 // the Windows does not allow the driver to perform site survey any more. By Bruce, 2007-10-02.
2213                 //
2214                 priv->RfOffReason &= (~ChangeSource);
2215
2216                 if(! priv->RfOffReason)
2217                 {
2218                         priv->RfOffReason = 0;
2219                         bActionAllowed = true;
2220
2221                         if(rtState == eRfOff && ChangeSource >=RF_CHANGE_BY_HW && !priv->bInHctTest)
2222                         {
2223                                 bConnectBySSID = true;
2224                         }
2225                 }
2226                 else
2227 //                      RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State - eRfon reject pMgntInfo->RfOffReason= 0x%x, ChangeSource=0x%X\n", pMgntInfo->RfOffReason, ChangeSource));
2228                         ;
2229                 break;
2230
2231         case eRfOff:
2232                  // 070125, rcnjko: we always keep connected in AP mode.
2233
2234                         if (priv->RfOffReason > RF_CHANGE_BY_IPS)
2235                         {
2236                                 //
2237                                 // 060808, Annie:
2238                                 // Disconnect to current BSS when radio off. Asked by QuanTa.
2239                                 //
2240
2241                                 //
2242                                 // Calling MgntDisconnect() instead of MgntActSet_802_11_DISASSOCIATE(),
2243                                 // because we do NOT need to set ssid to dummy ones.
2244                                 // Revised by Roger, 2007.12.04.
2245                                 //
2246                                 MgntDisconnect( dev, disas_lv_ss );
2247
2248                                 // Clear content of bssDesc[] and bssDesc4Query[] to avoid reporting old bss to UI.
2249                                 // 2007.05.28, by shien chang.
2250 //                              PlatformZeroMemory( pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2251 //                              pMgntInfo->NumBssDesc = 0;
2252 //                              PlatformZeroMemory( pMgntInfo->bssDesc4Query, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC );
2253 //                              pMgntInfo->NumBssDesc4Query = 0;
2254                         }
2255
2256
2257
2258                 priv->RfOffReason |= ChangeSource;
2259                 bActionAllowed = true;
2260                 break;
2261
2262         case eRfSleep:
2263                 priv->RfOffReason |= ChangeSource;
2264                 bActionAllowed = true;
2265                 break;
2266
2267         default:
2268                 break;
2269         }
2270
2271         if(bActionAllowed)
2272         {
2273 //              RT_TRACE(COMP_RF, DBG_LOUD, ("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, pMgntInfo->RfOffReason));
2274                 // Config HW to the specified mode.
2275 //              printk("MgntActSet_RF_State(): Action is allowed.... StateToSet(%d), RfOffReason(%#X)\n", StateToSet, priv->RfOffReason);
2276                 SetRFPowerState(dev, StateToSet);
2277
2278                 // Turn on RF.
2279                 if(StateToSet == eRfOn)
2280                 {
2281                         HalEnableRx8185Dummy(dev);
2282                         if(bConnectBySSID)
2283                         {
2284                         // by amy not supported
2285 //                              MgntActSet_802_11_SSID(Adapter, Adapter->MgntInfo.Ssid.Octet, Adapter->MgntInfo.Ssid.Length, TRUE );
2286                         }
2287                 }
2288                 // Turn off RF.
2289                 else if(StateToSet == eRfOff)
2290                 {
2291                         HalDisableRx8185Dummy(dev);
2292                 }
2293         }
2294         else
2295         {
2296         //      printk("MgntActSet_RF_State(): Action is rejected.... StateToSet(%d), ChangeSource(%#X), RfOffReason(%#X)\n", StateToSet, ChangeSource, priv->RfOffReason);
2297         }
2298
2299         // Release RF spinlock
2300 //      down(&priv->rf_state);
2301         spin_lock_irqsave(&priv->rf_ps_lock,flag);
2302         priv->RFChangeInProgress = false;
2303 //      up(&priv->rf_state);
2304         spin_unlock_irqrestore(&priv->rf_ps_lock,flag);
2305 //      printk("<===MgntActSet_RF_State()\n");
2306         return bActionAllowed;
2307 }
2308 void
2309 InactivePowerSave(
2310         struct net_device *dev
2311         )
2312 {
2313         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2314         //u8 index = 0;
2315
2316         //
2317         // This flag "bSwRfProcessing", indicates the status of IPS procedure, should be set if the IPS workitem
2318         // is really scheduled.
2319         // The old code, sets this flag before scheduling the IPS workitem and however, at the same time the
2320         // previous IPS workitem did not end yet, fails to schedule the current workitem. Thus, bSwRfProcessing
2321         // blocks the IPS procedure of switching RF.
2322         // By Bruce, 2007-12-25.
2323         //
2324         priv->bSwRfProcessing = true;
2325
2326         MgntActSet_RF_State(dev, priv->eInactivePowerState, RF_CHANGE_BY_IPS);
2327
2328         //
2329         // To solve CAM values miss in RF OFF, rewrite CAM values after RF ON. By Bruce, 2007-09-20.
2330         //
2331
2332         priv->bSwRfProcessing = false;
2333 }
2334
2335 //
2336 //      Description:
2337 //              Enter the inactive power save mode. RF will be off
2338 //      2007.08.17, by shien chang.
2339 //
2340 void
2341 IPSEnter(
2342         struct net_device *dev
2343         )
2344 {
2345         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2346         RT_RF_POWER_STATE rtState;
2347         //printk("==============================>enter IPS\n");
2348         if (priv->bInactivePs)
2349         {
2350                 rtState = priv->eRFPowerState;
2351
2352                 //
2353                 // Added by Bruce, 2007-12-25.
2354                 // Do not enter IPS in the following conditions:
2355                 // (1) RF is already OFF or Sleep
2356                 // (2) bSwRfProcessing (indicates the IPS is still under going)
2357                 // (3) Connectted (only disconnected can trigger IPS)
2358                 // (4) IBSS (send Beacon)
2359                 // (5) AP mode (send Beacon)
2360                 //
2361                 if (rtState == eRfOn && !priv->bSwRfProcessing
2362                         && (priv->ieee80211->state != IEEE80211_LINKED ))
2363                 {
2364         //              printk("IPSEnter(): Turn off RF.\n");
2365                         priv->eInactivePowerState = eRfOff;
2366                         InactivePowerSave(dev);
2367                 }
2368         }
2369 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2370 }
2371 void
2372 IPSLeave(
2373         struct net_device *dev
2374         )
2375 {
2376         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2377         RT_RF_POWER_STATE rtState;
2378         //printk("===================================>leave IPS\n");
2379         if (priv->bInactivePs)
2380         {
2381                 rtState = priv->eRFPowerState;
2382                 if ((rtState == eRfOff || rtState == eRfSleep) && (!priv->bSwRfProcessing) && priv->RfOffReason <= RF_CHANGE_BY_IPS)
2383                 {
2384 //                      printk("IPSLeave(): Turn on RF.\n");
2385                         priv->eInactivePowerState = eRfOn;
2386                         InactivePowerSave(dev);
2387                 }
2388         }
2389 //      printk("priv->eRFPowerState is %d\n",priv->eRFPowerState);
2390 }
2391 //by amy for power save
2392 void rtl8185b_adapter_start(struct net_device *dev)
2393 {
2394       struct r8180_priv *priv = ieee80211_priv(dev);
2395         struct ieee80211_device *ieee = priv->ieee80211;
2396
2397         u8 SupportedWirelessMode;
2398         u8                      InitWirelessMode;
2399         u8                      bInvalidWirelessMode = 0;
2400         //int i;
2401         u8 tmpu8;
2402         //u8 u1tmp,u2tmp;
2403         u8 btCR9346;
2404         u8 TmpU1b;
2405         u8 btPSR;
2406
2407         //rtl8180_rtx_disable(dev);
2408 //{by amy 080312
2409         write_nic_byte(dev,0x24e, (BIT5|BIT6|BIT0));
2410 //by amy 080312}
2411         rtl8180_reset(dev);
2412
2413         priv->dma_poll_mask = 0;
2414         priv->dma_poll_stop_mask = 0;
2415
2416         //rtl8180_beacon_tx_disable(dev);
2417
2418         HwConfigureRTL8185(dev);
2419
2420         write_nic_dword(dev, MAC0, ((u32*)dev->dev_addr)[0]);
2421         write_nic_word(dev, MAC4, ((u32*)dev->dev_addr)[1] & 0xffff );
2422
2423         write_nic_byte(dev, MSR, read_nic_byte(dev, MSR) & 0xf3);       // default network type to 'No  Link'
2424
2425         //write_nic_byte(dev, BRSR, 0x0);               // Set BRSR= 1M
2426
2427         write_nic_word(dev, BcnItv, 100);
2428         write_nic_word(dev, AtimWnd, 2);
2429
2430         //PlatformEFIOWrite2Byte(dev, FEMR, 0xFFFF);
2431         PlatformIOWrite2Byte(dev, FEMR, 0xFFFF);
2432
2433         write_nic_byte(dev, WPA_CONFIG, 0);
2434
2435         MacConfig_85BASIC(dev);
2436
2437         // Override the RFSW_CTRL (MAC offset 0x272-0x273), 2006.06.07, by rcnjko.
2438         // BT_DEMO_BOARD type
2439         PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x569a);
2440 //by amy
2441 //#ifdef CONFIG_RTL818X_S
2442                 // for jong required
2443 //      PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2444 //#endif
2445 //by amy
2446         //BT_QA_BOARD
2447         //PlatformIOWrite2Byte(dev, RFSW_CTRL, 0x9a56);
2448
2449         //-----------------------------------------------------------------------------
2450         // Set up PHY related.
2451         //-----------------------------------------------------------------------------
2452         // Enable Config3.PARAM_En to revise AnaaParm.
2453         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2454 //by amy
2455         tmpu8 = read_nic_byte(dev, CONFIG3);
2456         write_nic_byte(dev, CONFIG3, (tmpu8 |CONFIG3_PARM_En) );
2457 //by amy
2458         // Turn on Analog power.
2459         // Asked for by William, otherwise, MAC 3-wire can't work, 2006.06.27, by rcnjko.
2460         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2461         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2462 //by amy
2463         write_nic_word(dev, ANAPARAM3, 0x0010);
2464 //by amy
2465
2466         write_nic_byte(dev, CONFIG3, tmpu8);
2467         write_nic_byte(dev, CR9346, 0x00);
2468 //{by amy 080312 for led
2469         // enable EEM0 and EEM1 in 9346CR
2470         btCR9346 = read_nic_byte(dev, CR9346);
2471         write_nic_byte(dev, CR9346, (btCR9346|0xC0) );
2472
2473         // B cut use LED1 to control HW RF on/off
2474         TmpU1b = read_nic_byte(dev, CONFIG5);
2475         TmpU1b = TmpU1b & ~BIT3;
2476         write_nic_byte(dev,CONFIG5, TmpU1b);
2477
2478         // disable EEM0 and EEM1 in 9346CR
2479         btCR9346 &= ~(0xC0);
2480         write_nic_byte(dev, CR9346, btCR9346);
2481
2482         //Enable Led (suggested by Jong)
2483         // B-cut RF Radio on/off  5e[3]=0
2484         btPSR = read_nic_byte(dev, PSR);
2485         write_nic_byte(dev, PSR, (btPSR | BIT3));
2486 //by amy 080312 for led}
2487         // setup initial timing for RFE.
2488         write_nic_word(dev, RFPinsOutput, 0x0480);
2489         SetOutputEnableOfRfPins(dev);
2490         write_nic_word(dev, RFPinsSelect, 0x2488);
2491
2492         // PHY config.
2493         PhyConfig8185(dev);
2494
2495         // We assume RegWirelessMode has already been initialized before,
2496         // however, we has to validate the wireless mode here and provide a
2497         // reasonable initialized value if necessary. 2005.01.13, by rcnjko.
2498         SupportedWirelessMode = GetSupportedWirelessMode8185(dev);
2499         if(     (ieee->mode != WIRELESS_MODE_B) &&
2500                 (ieee->mode != WIRELESS_MODE_G) &&
2501                 (ieee->mode != WIRELESS_MODE_A) &&
2502                 (ieee->mode != WIRELESS_MODE_AUTO))
2503         { // It should be one of B, G, A, or AUTO.
2504                 bInvalidWirelessMode = 1;
2505         }
2506         else
2507         { // One of B, G, A, or AUTO.
2508                 // Check if the wireless mode is supported by RF.
2509                 if( (ieee->mode != WIRELESS_MODE_AUTO) &&
2510                         (ieee->mode & SupportedWirelessMode) == 0 )
2511                 {
2512                         bInvalidWirelessMode = 1;
2513                 }
2514         }
2515
2516         if(bInvalidWirelessMode || ieee->mode==WIRELESS_MODE_AUTO)
2517         { // Auto or other invalid value.
2518                 // Assigne a wireless mode to initialize.
2519                 if((SupportedWirelessMode & WIRELESS_MODE_A))
2520                 {
2521                         InitWirelessMode = WIRELESS_MODE_A;
2522                 }
2523                 else if((SupportedWirelessMode & WIRELESS_MODE_G))
2524                 {
2525                         InitWirelessMode = WIRELESS_MODE_G;
2526                 }
2527                 else if((SupportedWirelessMode & WIRELESS_MODE_B))
2528                 {
2529                         InitWirelessMode = WIRELESS_MODE_B;
2530                 }
2531                 else
2532                 {
2533                         DMESGW("InitializeAdapter8185(): No valid wireless mode supported, SupportedWirelessMode(%x)!!!\n",
2534                                  SupportedWirelessMode);
2535                         InitWirelessMode = WIRELESS_MODE_B;
2536                 }
2537
2538                 // Initialize RegWirelessMode if it is not a valid one.
2539                 if(bInvalidWirelessMode)
2540                 {
2541                         ieee->mode = (WIRELESS_MODE)InitWirelessMode;
2542                 }
2543         }
2544         else
2545         { // One of B, G, A.
2546                 InitWirelessMode = ieee->mode;
2547         }
2548 //by amy for power save
2549 //      printk("initialize ENABLE_IPS\n");
2550         priv->eRFPowerState = eRfOff;
2551         priv->RfOffReason = 0;
2552         {
2553         //      u32 tmp2;
2554         //      u32 tmp = jiffies;
2555                 MgntActSet_RF_State(dev, eRfOn, 0);
2556         //      tmp2 = jiffies;
2557         //      printk("rf on cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2558         }
2559 //      DrvIFIndicateCurrentPhyStatus(priv);
2560                 //
2561                 // If inactive power mode is enabled, disable rf while in disconnected state.
2562                 // 2007.07.16, by shien chang.
2563                 //
2564         if (priv->bInactivePs)
2565         {
2566         //      u32 tmp2;
2567         //      u32 tmp = jiffies;
2568                 MgntActSet_RF_State(dev,eRfOff, RF_CHANGE_BY_IPS);
2569         //      tmp2 = jiffies;
2570         //      printk("rf off cost jiffies:%lx\n", (tmp2-tmp)*1000/HZ);
2571
2572         }
2573 //      IPSEnter(dev);
2574 //by amy for power save
2575 #ifdef TODO
2576         // Turn off RF if necessary. 2005.08.23, by rcnjko.
2577         // We shall turn off RF after setting CMDR, otherwise,
2578         // RF will be turnned on after we enable MAC Tx/Rx.
2579         if(Adapter->MgntInfo.RegRfOff == TRUE)
2580         {
2581                 SetRFPowerState8185(Adapter, RF_OFF);
2582         }
2583         else
2584         {
2585                 SetRFPowerState8185(Adapter, RF_ON);
2586         }
2587 #endif
2588
2589 /*   //these is equal with above TODO.
2590         write_nic_byte(dev, CR9346, 0xc0);      // enable config register write
2591         write_nic_byte(dev, CONFIG3, read_nic_byte(dev, CONFIG3) | CONFIG3_PARM_En);
2592         RF_WriteReg(dev, 0x4, 0x9FF);
2593         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ASIC_ON);
2594         write_nic_dword(dev, ANAPARAM, ANAPARM_ASIC_ON);
2595         write_nic_byte(dev, CONFIG3, (read_nic_byte(dev, CONFIG3)&(~CONFIG3_PARM_En)));
2596         write_nic_byte(dev, CR9346, 0x00);
2597 */
2598
2599         ActSetWirelessMode8185(dev, (u8)(InitWirelessMode));
2600
2601         //-----------------------------------------------------------------------------
2602
2603         rtl8185b_irq_enable(dev);
2604
2605         netif_start_queue(dev);
2606
2607  }
2608
2609
2610 void rtl8185b_rx_enable(struct net_device *dev)
2611 {
2612         u8 cmd;
2613         //u32 rxconf;
2614         /* for now we accept data, management & ctl frame*/
2615         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2616
2617         if (dev->flags & IFF_PROMISC) DMESG ("NIC in promisc mode");
2618
2619         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR || \
2620            dev->flags & IFF_PROMISC){
2621                 priv->ReceiveConfig = priv->ReceiveConfig & (~RCR_APM);
2622                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_AAP;
2623         }
2624
2625         /*if(priv->ieee80211->iw_mode == IW_MODE_MASTER){
2626                 rxconf = rxconf | (1<<ACCEPT_ALLMAC_FRAME_SHIFT);
2627                 rxconf = rxconf | (1<<RX_CHECK_BSSID_SHIFT);
2628         }*/
2629
2630         if(priv->ieee80211->iw_mode == IW_MODE_MONITOR){
2631                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACF | RCR_APWRMGT | RCR_AICV;
2632         }
2633
2634         if( priv->crcmon == 1 && priv->ieee80211->iw_mode == IW_MODE_MONITOR)
2635                 priv->ReceiveConfig = priv->ReceiveConfig | RCR_ACRC32;
2636
2637         write_nic_dword(dev, RCR, priv->ReceiveConfig);
2638
2639         fix_rx_fifo(dev);
2640
2641 #ifdef DEBUG_RX
2642         DMESG("rxconf: %x %x",priv->ReceiveConfig ,read_nic_dword(dev,RCR));
2643 #endif
2644         cmd=read_nic_byte(dev,CMD);
2645         write_nic_byte(dev,CMD,cmd | (1<<CMD_RX_ENABLE_SHIFT));
2646
2647 }
2648
2649 void rtl8185b_tx_enable(struct net_device *dev)
2650 {
2651         u8 cmd;
2652         //u8 tx_agc_ctl;
2653         u8 byte;
2654         //u32 txconf;
2655         struct r8180_priv *priv = (struct r8180_priv *)ieee80211_priv(dev);
2656
2657         write_nic_dword(dev, TCR, priv->TransmitConfig);
2658         byte = read_nic_byte(dev, MSR);
2659         byte |= MSR_LINK_ENEDCA;
2660         write_nic_byte(dev, MSR, byte);
2661
2662         fix_tx_fifo(dev);
2663
2664 #ifdef DEBUG_TX
2665         DMESG("txconf: %x %x",priv->TransmitConfig,read_nic_dword(dev,TCR));
2666 #endif
2667
2668         cmd=read_nic_byte(dev,CMD);
2669         write_nic_byte(dev,CMD,cmd | (1<<CMD_TX_ENABLE_SHIFT));
2670
2671         //write_nic_dword(dev,TX_CONF,txconf);
2672
2673
2674 /*
2675         rtl8180_set_mode(dev,EPROM_CMD_CONFIG);
2676         write_nic_byte(dev, TX_DMA_POLLING, priv->dma_poll_mask);
2677         rtl8180_set_mode(dev,EPROM_CMD_NORMAL);
2678         */
2679 }
2680
2681