SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/staging/rtl8187se/r8180_rtl8225z2.c

   1 /*
   2   This is part of the rtl8180-sa2400 driver
   3   released under the GPL (See file COPYING for details).
   4   Copyright (c) 2005 Andrea Merello <andreamrl@tiscali.it>
   5
   6   This files contains programming code for the rtl8225
   7   radio frontend.
   8
   9   *Many* thanks to Realtek Corp. for their great support!
  10
  11 */
  12
  13 #include "r8180_hw.h"
  14 #include "r8180_rtl8225.h"
  15 #include "r8180_93cx6.h"
  16
  17 #include "ieee80211/dot11d.h"
  18
  19
  20 static void write_rtl8225(struct net_device *dev, u8 adr, u16 data)
  21 {
  22         int i;
  23         u16 out, select;
  24         u8 bit;
  25         u32 bangdata = (data << 4) | (adr & 0xf);
  26         struct r8180_priv *priv = ieee80211_priv(dev);
  27
  28         out = read_nic_word(dev, RFPinsOutput) & 0xfff3;
  29
  30         write_nic_word(dev, RFPinsEnable,
  31                 (read_nic_word(dev, RFPinsEnable) | 0x7));
  32
  33         select = read_nic_word(dev, RFPinsSelect);
  34
  35         write_nic_word(dev, RFPinsSelect, select | 0x7 |
  36                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  37
  38         force_pci_posting(dev);
  39         udelay(10);
  40
  41         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  42
  43         force_pci_posting(dev);
  44         udelay(2);
  45
  46         write_nic_word(dev, RFPinsOutput, out);
  47
  48         force_pci_posting(dev);
  49         udelay(10);
  50
  51         for (i = 15; i >= 0; i--) {
  52                 bit = (bangdata & (1 << i)) >> i;
  53
  54                 write_nic_word(dev, RFPinsOutput, bit | out);
  55
  56                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  57                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  58
  59                 i--;
  60                 bit = (bangdata & (1 << i)) >> i;
  61
  62                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  63                 write_nic_word(dev, RFPinsOutput, bit | out | BB_HOST_BANG_CLK);
  64
  65                 write_nic_word(dev, RFPinsOutput, bit | out);
  66
  67         }
  68
  69         write_nic_word(dev, RFPinsOutput, out | BB_HOST_BANG_EN);
  70
  71         force_pci_posting(dev);
  72         udelay(10);
  73
  74         write_nic_word(dev, RFPinsOutput, out |
  75                 ((priv->card_type == USB) ? 4 : BB_HOST_BANG_EN));
  76
  77         write_nic_word(dev, RFPinsSelect, select |
  78                 ((priv->card_type == USB) ? 0 : SW_CONTROL_GPIO));
  79
  80         if (priv->card_type == USB)
  81                 mdelay(2);
  82         else
  83                 rtl8185_rf_pins_enable(dev);
  84 }
  85
  86 static const u16 rtl8225bcd_rxgain[] = {
  87         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
  88         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
  89         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
  90         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
  91         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
  92         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
  93         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
  94         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
  95         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
  96         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
  97         0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
  98         0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
  99
 100 };
 101
 102 static const u8 rtl8225_agc[] = {
 103         0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e,
 104         0x9d, 0x9c, 0x9b, 0x9a, 0x99, 0x98, 0x97, 0x96,
 105         0x95, 0x94, 0x93, 0x92, 0x91, 0x90, 0x8f, 0x8e,
 106         0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86,
 107         0x85, 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e,
 108         0x3d, 0x3c, 0x3b, 0x3a, 0x39, 0x38, 0x37, 0x36,
 109         0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f, 0x2e,
 110         0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26,
 111         0x25, 0x24, 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e,
 112         0x1d, 0x1c, 0x1b, 0x1a, 0x19, 0x18, 0x17, 0x16,
 113         0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
 114         0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06,
 115         0x05, 0x04, 0x03, 0x02, 0x01, 0x01, 0x01, 0x01,
 116         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 117         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 118         0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
 119 };
 120
 121 static const u8 rtl8225_gain[] = {
 122         0x23, 0x88, 0x7c, 0xa5, /* -82dBm */
 123         0x23, 0x88, 0x7c, 0xb5, /* -82dBm */
 124         0x23, 0x88, 0x7c, 0xc5, /* -82dBm */
 125         0x33, 0x80, 0x79, 0xc5, /* -78dBm */
 126         0x43, 0x78, 0x76, 0xc5, /* -74dBm */
 127         0x53, 0x60, 0x73, 0xc5, /* -70dBm */
 128         0x63, 0x58, 0x70, 0xc5, /* -66dBm */
 129 };
 130
 131 static const u8 rtl8225_tx_gain_cck_ofdm[] = {
 132         0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
 133 };
 134
 135 static const u8 rtl8225_tx_power_cck[] = {
 136         0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
 137         0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
 138         0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
 139         0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
 140         0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
 141         0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
 142 };
 143
 144 static const u8 rtl8225_tx_power_cck_ch14[] = {
 145         0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
 146         0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
 147         0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
 148         0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
 149         0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
 150         0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
 151 };
 152
 153 static const u8 rtl8225_tx_power_ofdm[] = {
 154         0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
 155 };
 156
 157 static const u32 rtl8225_chan[] = {
 158         0,
 159         0x0080, 0x0100, 0x0180, 0x0200, 0x0280, 0x0300, 0x0380,
 160         0x0400, 0x0480, 0x0500, 0x0580, 0x0600, 0x0680, 0x074A,
 161 };
 162
 163 static void rtl8225_SetTXPowerLevel(struct net_device *dev, short ch)
 164 {
 165         struct r8180_priv *priv = ieee80211_priv(dev);
 166         int GainIdx;
 167         int GainSetting;
 168         int i;
 169         u8 power;
 170         const u8 *cck_power_table;
 171         u8 max_cck_power_level;
 172         u8 max_ofdm_power_level;
 173         u8 min_ofdm_power_level;
 174         u8 cck_power_level = 0xff & priv->chtxpwr[ch];
 175         u8 ofdm_power_level = 0xff & priv->chtxpwr_ofdm[ch];
 176
 177         if (priv->card_type == USB) {
 178                 max_cck_power_level = 11;
 179                 max_ofdm_power_level = 25;
 180                 min_ofdm_power_level = 10;
 181         } else {
 182                 max_cck_power_level = 35;
 183                 max_ofdm_power_level = 35;
 184                 min_ofdm_power_level = 0;
 185         }
 186
 187         if (cck_power_level > max_cck_power_level)
 188                 cck_power_level = max_cck_power_level;
 189
 190         GainIdx = cck_power_level % 6;
 191         GainSetting = cck_power_level / 6;
 192
 193         if (ch == 14)
 194                 cck_power_table = rtl8225_tx_power_cck_ch14;
 195         else
 196                 cck_power_table = rtl8225_tx_power_cck;
 197
 198         write_nic_byte(dev, TX_GAIN_CCK,
 199                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 200
 201         for (i = 0; i < 8; i++) {
 202                 power = cck_power_table[GainIdx * 8 + i];
 203                 write_phy_cck(dev, 0x44 + i, power);
 204         }
 205
 206         /* FIXME Is this delay really needeed ? */
 207         force_pci_posting(dev);
 208         mdelay(1);
 209
 210         if (ofdm_power_level > (max_ofdm_power_level - min_ofdm_power_level))
 211                 ofdm_power_level = max_ofdm_power_level;
 212         else
 213                 ofdm_power_level += min_ofdm_power_level;
 214
 215         if (ofdm_power_level > 35)
 216                 ofdm_power_level = 35;
 217
 218         GainIdx = ofdm_power_level % 6;
 219         GainSetting = ofdm_power_level / 6;
 220
 221         rtl8185_set_anaparam2(dev, RTL8225_ANAPARAM2_ON);
 222
 223         write_phy_ofdm(dev, 2, 0x42);
 224         write_phy_ofdm(dev, 6, 0x00);
 225         write_phy_ofdm(dev, 8, 0x00);
 226
 227         write_nic_byte(dev, TX_GAIN_OFDM,
 228                        rtl8225_tx_gain_cck_ofdm[GainSetting] >> 1);
 229
 230         power = rtl8225_tx_power_ofdm[GainIdx];
 231
 232         write_phy_ofdm(dev, 5, power);
 233         write_phy_ofdm(dev, 7, power);
 234
 235         force_pci_posting(dev);
 236         mdelay(1);
 237 }
 238
 239 static const u8 rtl8225z2_threshold[] = {
 240         0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
 241 };
 242
 243 static const u8 rtl8225z2_gain_bg[] = {
 244         0x23, 0x15, 0xa5, /* -82-1dBm */
 245         0x23, 0x15, 0xb5, /* -82-2dBm */
 246         0x23, 0x15, 0xc5, /* -82-3dBm */
 247         0x33, 0x15, 0xc5, /* -78dBm */
 248         0x43, 0x15, 0xc5, /* -74dBm */
 249         0x53, 0x15, 0xc5, /* -70dBm */
 250         0x63, 0x15, 0xc5, /* -66dBm */
 251 };
 252
 253 static const u8 rtl8225z2_gain_a[] = {
 254         0x13, 0x27, 0x5a, /* -82dBm */
 255         0x23, 0x23, 0x58, /* -82dBm */
 256         0x33, 0x1f, 0x56, /* -82dBm */
 257         0x43, 0x1b, 0x54, /* -78dBm */
 258         0x53, 0x17, 0x51, /* -74dBm */
 259         0x63, 0x24, 0x4f, /* -70dBm */
 260         0x73, 0x0f, 0x4c, /* -66dBm */
 261 };
 262
 263 static const u16 rtl8225z2_rxgain[] = {
 264         0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
 265         0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
 266         0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
 267         0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
 268         0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
 269         0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
 270         0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
 271         0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
 272         0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
 273         0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
 274         0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
 275         0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
 276
 277 };
 278
 279 static const u8 ZEBRA2_CCK_OFDM_GAIN_SETTING[] = {
 280         0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
 281         0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
 282         0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
 283         0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
 284         0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
 285         0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
 286 };
 287
 288 static const u8 rtl8225z2_tx_power_ofdm[] = {
 289         0x42, 0x00, 0x40, 0x00, 0x40
 290 };
 291
 292 static const u8 rtl8225z2_tx_power_cck_ch14[] = {
 293         0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
 294 };
 295
 296 static const u8 rtl8225z2_tx_power_cck[] = {
 297         0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
 298 };
 299
 300 void rtl8225z2_set_gain(struct net_device *dev, short gain)
 301 {
 302         const u8 *rtl8225_gain;
 303         struct r8180_priv *priv = ieee80211_priv(dev);
 304         u8 mode = priv->ieee80211->mode;
 305
 306         if (mode == IEEE_B || mode == IEEE_G)
 307                 rtl8225_gain = rtl8225z2_gain_bg;
 308         else
 309                 rtl8225_gain = rtl8225z2_gain_a;
 310
 311         write_phy_ofdm(dev, 0x0b, rtl8225_gain[gain * 3]);
 312         write_phy_ofdm(dev, 0x1b, rtl8225_gain[gain * 3 + 1]);
 313         write_phy_ofdm(dev, 0x1d, rtl8225_gain[gain * 3 + 2]);
 314         write_phy_ofdm(dev, 0x21, 0x37);
 315 }
 316
 317 static u32 read_rtl8225(struct net_device *dev, u8 adr)
 318 {
 319         u32 data2Write = ((u32)(adr & 0x1f)) << 27;
 320         u32 dataRead;
 321         u32 mask;
 322         u16 oval,oval2,oval3,tmp;
 323         int i;
 324         short bit, rw;
 325         u8 wLength = 6;
 326         u8 rLength = 12;
 327         u8 low2high = 0;
 328
 329         oval = read_nic_word(dev, RFPinsOutput);
 330         oval2 = read_nic_word(dev, RFPinsEnable);
 331         oval3 = read_nic_word(dev, RFPinsSelect);
 332
 333         write_nic_word(dev, RFPinsEnable, (oval2|0xf));
 334         write_nic_word(dev, RFPinsSelect, (oval3|0xf));
 335
 336         dataRead = 0;
 337
 338         oval &= ~0xf;
 339
 340         write_nic_word(dev, RFPinsOutput, oval | BB_HOST_BANG_EN ); udelay(4);
 341
 342         write_nic_word(dev, RFPinsOutput, oval ); udelay(5);
 343
 344         rw = 0;
 345
 346         mask = (low2high) ? 0x01 : (((u32)0x01)<<(32-1));
 347
 348         for (i = 0; i < wLength/2; i++) {
 349                 bit = ((data2Write&mask) != 0) ? 1 : 0;
 350                 write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(1);
 351
 352                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 353                 write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 354
 355                 mask = (low2high) ? (mask<<1): (mask>>1);
 356
 357                 if (i == 2) {
 358                         rw = BB_HOST_BANG_RW;
 359                         write_nic_word(dev, RFPinsOutput, bit|oval | BB_HOST_BANG_CLK | rw); udelay(2);
 360                         write_nic_word(dev, RFPinsOutput, bit|oval | rw); udelay(2);
 361                         break;
 362                 }
 363
 364                 bit = ((data2Write&mask) != 0) ? 1: 0;
 365
 366                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 367                 write_nic_word(dev, RFPinsOutput, oval|bit|rw| BB_HOST_BANG_CLK); udelay(2);
 368
 369                 write_nic_word(dev, RFPinsOutput, oval| bit |rw); udelay(1);
 370
 371                 mask = (low2high) ? (mask<<1) : (mask>>1);
 372         }
 373
 374         write_nic_word(dev, RFPinsOutput, rw|oval); udelay(2);
 375         mask = (low2high) ? 0x01 : (((u32)0x01) << (12-1));
 376
 377         /*
 378          * We must set data pin to HW controled, otherwise RF can't driver it
 379          * and value RF register won't be able to read back properly.
 380          */
 381         write_nic_word(dev, RFPinsEnable, (oval2 & (~0x01)));
 382
 383         for (i = 0; i < rLength; i++) {
 384                 write_nic_word(dev, RFPinsOutput, rw|oval); udelay(1);
 385
 386                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 387                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 388                 write_nic_word(dev, RFPinsOutput, rw|oval|BB_HOST_BANG_CLK); udelay(2);
 389                 tmp = read_nic_word(dev, RFPinsInput);
 390
 391                 dataRead |= (tmp & BB_HOST_BANG_CLK ? mask : 0);
 392
 393                 write_nic_word(dev, RFPinsOutput, (rw|oval)); udelay(2);
 394
 395                 mask = (low2high) ? (mask<<1) : (mask>>1);
 396         }
 397
 398         write_nic_word(dev, RFPinsOutput, BB_HOST_BANG_EN|BB_HOST_BANG_RW|oval); udelay(2);
 399
 400         write_nic_word(dev, RFPinsEnable, oval2);
 401         write_nic_word(dev, RFPinsSelect, oval3); /* Set To SW Switch */
 402         write_nic_word(dev, RFPinsOutput, 0x3a0);
 403
 404         return dataRead;
 405 }
 406
 407 short rtl8225_is_V_z2(struct net_device *dev)
 408 {
 409         short vz2 = 1;
 410
 411         if (read_rtl8225(dev, 8) != 0x588)
 412                 vz2 = 0;
 413         else    /* reg 9 pg 1 = 24 */
 414                 if (read_rtl8225(dev, 9) != 0x700)
 415                         vz2 = 0;
 416
 417         /* sw back to pg 0 */
 418         write_rtl8225(dev, 0, 0xb7);
 419
 420         return vz2;
 421 }
 422
 423 void rtl8225z2_rf_close(struct net_device *dev)
 424 {
 425         RF_WriteReg(dev, 0x4, 0x1f);
 426
 427         force_pci_posting(dev);
 428         mdelay(1);
 429
 430         rtl8180_set_anaparam(dev, RTL8225z2_ANAPARAM_OFF);
 431         rtl8185_set_anaparam2(dev, RTL8225z2_ANAPARAM2_OFF);
 432 }
 433
 434 /*
 435  * Map dBm into Tx power index according to current HW model, for example,
 436  * RF and PA, and current wireless mode.
 437  */
 438 s8 DbmToTxPwrIdx(struct r8180_priv *priv, WIRELESS_MODE WirelessMode,
 439                  s32 PowerInDbm)
 440 {
 441         bool bUseDefault = true;
 442         s8 TxPwrIdx = 0;
 443
 444         /*
 445          * OFDM Power in dBm = Index * 0.5 + 0
 446          * CCK Power in dBm = Index * 0.25 + 13
 447          */
 448         if (priv->card_8185 >= VERSION_8187S_B) {
 449                 s32 tmp = 0;
 450
 451                 if (WirelessMode == WIRELESS_MODE_G) {
 452                         bUseDefault = false;
 453                         tmp = (2 * PowerInDbm);
 454
 455                         if (tmp < 0)
 456                                 TxPwrIdx = 0;
 457                         else if (tmp > 40) /* 40 means 20 dBm. */
 458                                 TxPwrIdx = 40;
 459                         else
 460                                 TxPwrIdx = (s8)tmp;
 461                 } else if (WirelessMode == WIRELESS_MODE_B) {
 462                         bUseDefault = false;
 463                         tmp = (4 * PowerInDbm) - 52;
 464
 465                         if(tmp < 0)
 466                                 TxPwrIdx = 0;
 467                         else if (tmp > 28) /* 28 means 20 dBm. */
 468                                 TxPwrIdx = 28;
 469                         else
 470                                 TxPwrIdx = (s8)tmp;
 471                 }
 472         }
 473
 474         /*
 475          * TRUE if we want to use a default implementation.
 476          * We shall set it to FALSE when we have exact translation formular
 477          * for target IC. 070622, by rcnjko.
 478          */
 479         if (bUseDefault) {
 480                 if (PowerInDbm < 0)
 481                         TxPwrIdx = 0;
 482                 else if (PowerInDbm > 35)
 483                         TxPwrIdx = 35;
 484                 else
 485                         TxPwrIdx = (u8)PowerInDbm;
 486         }
 487
 488         return TxPwrIdx;
 489 }
 490
 491 void rtl8225z2_SetTXPowerLevel(struct net_device *dev, short ch)
 492 {
 493         struct r8180_priv *priv = ieee80211_priv(dev);
 494         u8 max_cck_power_level;
 495         u8 max_ofdm_power_level;
 496         u8 min_ofdm_power_level;
 497         char cck_power_level = (char)(0xff & priv->chtxpwr[ch]);
 498         char ofdm_power_level = (char)(0xff & priv->chtxpwr_ofdm[ch]);
 499
 500         if (IS_DOT11D_ENABLE(priv->ieee80211) &&
 501             IS_DOT11D_STATE_DONE(priv->ieee80211)) {
 502                 u8 MaxTxPwrInDbm = DOT11D_GetMaxTxPwrInDbm(priv->ieee80211, ch);
 503                 u8 CckMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_B, MaxTxPwrInDbm);
 504                 u8 OfdmMaxPwrIdx = DbmToTxPwrIdx(priv, WIRELESS_MODE_G, MaxTxPwrInDbm);
 505
 506                 if (cck_power_level > CckMaxPwrIdx)
 507                         cck_power_level = CckMaxPwrIdx;
 508                 if (ofdm_power_level > OfdmMaxPwrIdx)
 509                         ofdm_power_level = OfdmMaxPwrIdx;
 510         }
 511
 512         max_cck_power_level = 15;
 513         max_ofdm_power_level = 25;
 514         min_ofdm_power_level = 10;
 515
 516         if (cck_power_level > 35)
 517                 cck_power_level = 35;
 518
 519         write_nic_byte(dev, CCK_TXAGC,
 520                        (ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)cck_power_level]));
 521         force_pci_posting(dev);
 522         mdelay(1);
 523
 524         if (ofdm_power_level > 35)
 525                 ofdm_power_level = 35;
 526
 527         if (priv->up == 0) {
 528                 write_phy_ofdm(dev, 2, 0x42);
 529                 write_phy_ofdm(dev, 5, 0x00);
 530                 write_phy_ofdm(dev, 6, 0x40);
 531                 write_phy_ofdm(dev, 7, 0x00);
 532                 write_phy_ofdm(dev, 8, 0x40);
 533         }
 534
 535         write_nic_byte(dev, OFDM_TXAGC,
 536                        ZEBRA2_CCK_OFDM_GAIN_SETTING[(u8)ofdm_power_level]);
 537
 538         if (ofdm_power_level <= 11) {
 539                 write_phy_ofdm(dev, 0x07, 0x5c);
 540                 write_phy_ofdm(dev, 0x09, 0x5c);
 541         }
 542
 543         if (ofdm_power_level <= 17) {
 544                 write_phy_ofdm(dev, 0x07, 0x54);
 545                 write_phy_ofdm(dev, 0x09, 0x54);
 546         } else {
 547                 write_phy_ofdm(dev, 0x07, 0x50);
 548                 write_phy_ofdm(dev, 0x09, 0x50);
 549         }
 550
 551         force_pci_posting(dev);
 552         mdelay(1);
 553 }
 554
 555 void rtl8225z2_rf_set_chan(struct net_device *dev, short ch)
 556 {
 557         rtl8225z2_SetTXPowerLevel(dev, ch);
 558
 559         RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 560
 561         if ((RF_ReadReg(dev, 0x7) & 0x0F80) != rtl8225_chan[ch])
 562                 RF_WriteReg(dev, 0x7, rtl8225_chan[ch]);
 563
 564         mdelay(1);
 565
 566         force_pci_posting(dev);
 567         mdelay(10);
 568 }
 569
 570 static void rtl8225_host_pci_init(struct net_device *dev)
 571 {
 572         write_nic_word(dev, RFPinsOutput, 0x480);
 573
 574         rtl8185_rf_pins_enable(dev);
 575
 576         write_nic_word(dev, RFPinsSelect, 0x88 | SW_CONTROL_GPIO);
 577
 578         write_nic_byte(dev, GP_ENABLE, 0);
 579
 580         force_pci_posting(dev);
 581         mdelay(200);
 582
 583         /* bit 6 is for RF on/off detection */
 584         write_nic_word(dev, GP_ENABLE, 0xff & (~(1 << 6)));
 585 }
 586
 587 static void rtl8225_rf_set_chan(struct net_device *dev, short ch)
 588 {
 589         struct r8180_priv *priv = ieee80211_priv(dev);
 590         short gset = (priv->ieee80211->state == IEEE80211_LINKED &&
 591                 ieee80211_is_54g(priv->ieee80211->current_network)) ||
 592                 priv->ieee80211->iw_mode == IW_MODE_MONITOR;
 593
 594         rtl8225_SetTXPowerLevel(dev, ch);
 595
 596         write_rtl8225(dev, 0x7, rtl8225_chan[ch]);
 597
 598         force_pci_posting(dev);
 599         mdelay(10);
 600
 601         if (gset) {
 602                 write_nic_byte(dev, SIFS, 0x22);
 603                 write_nic_byte(dev, DIFS, 0x14);
 604         } else {
 605                 write_nic_byte(dev, SIFS, 0x44);
 606                 write_nic_byte(dev, DIFS, 0x24);
 607         }
 608
 609         if (priv->ieee80211->state == IEEE80211_LINKED &&
 610             ieee80211_is_shortslot(priv->ieee80211->current_network))
 611                 write_nic_byte(dev, SLOT, 0x9);
 612         else
 613                 write_nic_byte(dev, SLOT, 0x14);
 614
 615         if (gset) {
 616                 write_nic_byte(dev, EIFS, 81);
 617                 write_nic_byte(dev, CW_VAL, 0x73);
 618         } else {
 619                 write_nic_byte(dev, EIFS, 81);
 620                 write_nic_byte(dev, CW_VAL, 0xa5);
 621         }
 622 }
 623
 624 void rtl8225z2_rf_init(struct net_device *dev)
 625 {
 626         struct r8180_priv *priv = ieee80211_priv(dev);
 627         int i;
 628         short channel = 1;
 629         u16     brsr;
 630         u32     data,addr;
 631
 632         priv->chan = channel;
 633
 634         if (priv->card_type != USB)
 635                 rtl8225_host_pci_init(dev);
 636
 637         write_nic_dword(dev, RF_TIMING, 0x000a8008);
 638
 639         brsr = read_nic_word(dev, BRSR);
 640
 641         write_nic_word(dev, BRSR, 0xffff);
 642
 643         write_nic_dword(dev, RF_PARA, 0x100044);
 644
 645         rtl8180_set_mode(dev, EPROM_CMD_CONFIG);
 646         write_nic_byte(dev, CONFIG3, 0x44);
 647         rtl8180_set_mode(dev, EPROM_CMD_NORMAL);
 648
 649         rtl8185_rf_pins_enable(dev);
 650
 651         write_rtl8225(dev, 0x0, 0x2bf); mdelay(1);
 652         write_rtl8225(dev, 0x1, 0xee0); mdelay(1);
 653         write_rtl8225(dev, 0x2, 0x44d); mdelay(1);
 654         write_rtl8225(dev, 0x3, 0x441); mdelay(1);
 655         write_rtl8225(dev, 0x4, 0x8c3); mdelay(1);
 656         write_rtl8225(dev, 0x5, 0xc72); mdelay(1);
 657         write_rtl8225(dev, 0x6, 0xe6);  mdelay(1);
 658         write_rtl8225(dev, 0x7, ((priv->card_type == USB)? 0x82a : rtl8225_chan[channel]));  mdelay(1);
 659         write_rtl8225(dev, 0x8, 0x3f);  mdelay(1);
 660         write_rtl8225(dev, 0x9, 0x335); mdelay(1);
 661         write_rtl8225(dev, 0xa, 0x9d4); mdelay(1);
 662         write_rtl8225(dev, 0xb, 0x7bb); mdelay(1);
 663         write_rtl8225(dev, 0xc, 0x850); mdelay(1);
 664         write_rtl8225(dev, 0xd, 0xcdf); mdelay(1);
 665         write_rtl8225(dev, 0xe, 0x2b);  mdelay(1);
 666         write_rtl8225(dev, 0xf, 0x114);
 667
 668         mdelay(100);
 669
 670         write_rtl8225(dev, 0x0, 0x1b7);
 671
 672         for (i = 0; i < 95; i++) {
 673                 write_rtl8225(dev, 0x1, (u8)(i + 1));
 674                 write_rtl8225(dev, 0x2, rtl8225z2_rxgain[i]);
 675         }
 676
 677         write_rtl8225(dev, 0x3, 0x80);
 678         write_rtl8225(dev, 0x5, 0x4);
 679
 680         write_rtl8225(dev, 0x0, 0xb7);
 681
 682         write_rtl8225(dev, 0x2, 0xc4d);
 683
 684         if (priv->card_type == USB) {
 685                 mdelay(200);
 686
 687                 write_rtl8225(dev, 0x2, 0x44d);
 688                 mdelay(100);
 689         }
 690
 691         /* FIXME!! rtl8187 we have to check if calibrarion
 692          * is successful and eventually cal. again (repeat
 693          * the two write on reg 2)
 694          */
 695         data = read_rtl8225(dev, 6);
 696         if (!(data & 0x00000080)) {
 697                 write_rtl8225(dev, 0x02, 0x0c4d);
 698                 force_pci_posting(dev); mdelay(200);
 699                 write_rtl8225(dev, 0x02, 0x044d);
 700                 force_pci_posting(dev); mdelay(100);
 701                 data = read_rtl8225(dev, 6);
 702                 if (!(data & 0x00000080))
 703                         DMESGW("RF Calibration Failed!!!!\n");
 704         }
 705
 706         mdelay(200);
 707
 708         write_rtl8225(dev, 0x0, 0x2bf);
 709
 710         if (priv->card_type != USB)
 711                 rtl8185_rf_pins_enable(dev);
 712
 713         for (i = 0; i < 128; i++) {
 714                 data = rtl8225_agc[i];
 715
 716                 addr = i + 0x80; /* enable writing AGC table */
 717                 write_phy_ofdm(dev, 0xb, data);
 718                 mdelay(1);
 719
 720                 write_phy_ofdm(dev, 0xa, addr);
 721                 mdelay(1);
 722         }
 723
 724         force_pci_posting(dev);
 725         mdelay(1);
 726
 727         write_phy_ofdm(dev, 0x00, 0x01); mdelay(1);
 728         write_phy_ofdm(dev, 0x01, 0x02); mdelay(1);
 729         write_phy_ofdm(dev, 0x02, ((priv->card_type == USB) ? 0x42 : 0x62)); mdelay(1);
 730         write_phy_ofdm(dev, 0x03, 0x00); mdelay(1);
 731         write_phy_ofdm(dev, 0x04, 0x00); mdelay(1);
 732         write_phy_ofdm(dev, 0x05, 0x00); mdelay(1);
 733         write_phy_ofdm(dev, 0x06, 0x40); mdelay(1);
 734         write_phy_ofdm(dev, 0x07, 0x00); mdelay(1);
 735         write_phy_ofdm(dev, 0x08, 0x40); mdelay(1);
 736         write_phy_ofdm(dev, 0x09, 0xfe); mdelay(1);
 737         write_phy_ofdm(dev, 0x0a, 0x08); mdelay(1);
 738         write_phy_ofdm(dev, 0x0b, 0x80); mdelay(1);
 739         write_phy_ofdm(dev, 0x0c, 0x01); mdelay(1);
 740         write_phy_ofdm(dev, 0x0d, 0x43);
 741         write_phy_ofdm(dev, 0x0e, 0xd3); mdelay(1);
 742         write_phy_ofdm(dev, 0x0f, 0x38); mdelay(1);
 743         write_phy_ofdm(dev, 0x10, 0x84); mdelay(1);
 744         write_phy_ofdm(dev, 0x11, 0x07); mdelay(1);
 745         write_phy_ofdm(dev, 0x12, 0x20); mdelay(1);
 746         write_phy_ofdm(dev, 0x13, 0x20); mdelay(1);
 747         write_phy_ofdm(dev, 0x14, 0x00); mdelay(1);
 748         write_phy_ofdm(dev, 0x15, 0x40); mdelay(1);
 749         write_phy_ofdm(dev, 0x16, 0x00); mdelay(1);
 750         write_phy_ofdm(dev, 0x17, 0x40); mdelay(1);
 751         write_phy_ofdm(dev, 0x18, 0xef); mdelay(1);
 752         write_phy_ofdm(dev, 0x19, 0x19); mdelay(1);
 753         write_phy_ofdm(dev, 0x1a, 0x20); mdelay(1);
 754         write_phy_ofdm(dev, 0x1b, 0x15); mdelay(1);
 755         write_phy_ofdm(dev, 0x1c, 0x04); mdelay(1);
 756         write_phy_ofdm(dev, 0x1d, 0xc5); mdelay(1);
 757         write_phy_ofdm(dev, 0x1e, 0x95); mdelay(1);
 758         write_phy_ofdm(dev, 0x1f, 0x75); mdelay(1);
 759         write_phy_ofdm(dev, 0x20, 0x1f); mdelay(1);
 760         write_phy_ofdm(dev, 0x21, 0x17); mdelay(1);
 761         write_phy_ofdm(dev, 0x22, 0x16); mdelay(1);
 762         write_phy_ofdm(dev, 0x23, 0x80); mdelay(1); /* FIXME maybe not needed */
 763         write_phy_ofdm(dev, 0x24, 0x46); mdelay(1);
 764         write_phy_ofdm(dev, 0x25, 0x00); mdelay(1);
 765         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);
 766         write_phy_ofdm(dev, 0x27, 0x88); mdelay(1);
 767
 768         rtl8225z2_set_gain(dev,4);
 769
 770         write_phy_cck(dev, 0x0, 0x98); mdelay(1);
 771         write_phy_cck(dev, 0x3, 0x20); mdelay(1);
 772         write_phy_cck(dev, 0x4, 0x7e); mdelay(1);
 773         write_phy_cck(dev, 0x5, 0x12); mdelay(1);
 774         write_phy_cck(dev, 0x6, 0xfc); mdelay(1);
 775         write_phy_cck(dev, 0x7, 0x78); mdelay(1);
 776         write_phy_cck(dev, 0x8, 0x2e); mdelay(1);
 777         write_phy_cck(dev, 0x10, ((priv->card_type == USB) ? 0x9b: 0x93)); mdelay(1);
 778         write_phy_cck(dev, 0x11, 0x88); mdelay(1);
 779         write_phy_cck(dev, 0x12, 0x47); mdelay(1);
 780         write_phy_cck(dev, 0x13, 0xd0);
 781         write_phy_cck(dev, 0x19, 0x00);
 782         write_phy_cck(dev, 0x1a, 0xa0);
 783         write_phy_cck(dev, 0x1b, 0x08);
 784         write_phy_cck(dev, 0x40, 0x86); /* CCK Carrier Sense Threshold */
 785         write_phy_cck(dev, 0x41, 0x8d); mdelay(1);
 786         write_phy_cck(dev, 0x42, 0x15); mdelay(1);
 787         write_phy_cck(dev, 0x43, 0x18); mdelay(1);
 788         write_phy_cck(dev, 0x44, 0x36); mdelay(1);
 789         write_phy_cck(dev, 0x45, 0x35); mdelay(1);
 790         write_phy_cck(dev, 0x46, 0x2e); mdelay(1);
 791         write_phy_cck(dev, 0x47, 0x25); mdelay(1);
 792         write_phy_cck(dev, 0x48, 0x1c); mdelay(1);
 793         write_phy_cck(dev, 0x49, 0x12); mdelay(1);
 794         write_phy_cck(dev, 0x4a, 0x09); mdelay(1);
 795         write_phy_cck(dev, 0x4b, 0x04); mdelay(1);
 796         write_phy_cck(dev, 0x4c, 0x05); mdelay(1);
 797
 798         write_nic_byte(dev, 0x5b, 0x0d); mdelay(1);
 799
 800         rtl8225z2_SetTXPowerLevel(dev, channel);
 801
 802         /* RX antenna default to A */
 803         write_phy_cck(dev, 0x11, 0x9b); mdelay(1);              /* B: 0xDB */
 804         write_phy_ofdm(dev, 0x26, 0x90); mdelay(1);             /* B: 0x10 */
 805
 806         rtl8185_tx_antenna(dev, 0x03);                          /* B: 0x00 */
 807
 808         /* switch to high-speed 3-wire
 809          * last digit. 2 for both cck and ofdm
 810          */
 811         if (priv->card_type == USB)
 812                 write_nic_dword(dev, 0x94, 0x3dc00002);
 813         else {
 814                 write_nic_dword(dev, 0x94, 0x15c00002);
 815                 rtl8185_rf_pins_enable(dev);
 816         }
 817
 818         rtl8225_rf_set_chan(dev, priv->chan);
 819 }
 820
 821 void rtl8225z2_rf_set_mode(struct net_device *dev)
 822 {
 823         struct r8180_priv *priv = ieee80211_priv(dev);
 824
 825         if (priv->ieee80211->mode == IEEE_A) {
 826                 write_rtl8225(dev, 0x5, 0x1865);
 827                 write_nic_dword(dev, RF_PARA, 0x10084);
 828                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 829                 write_phy_ofdm(dev, 0x0, 0x0);
 830                 write_phy_ofdm(dev, 0xa, 0x6);
 831                 write_phy_ofdm(dev, 0xb, 0x99);
 832                 write_phy_ofdm(dev, 0xf, 0x20);
 833                 write_phy_ofdm(dev, 0x11, 0x7);
 834
 835                 rtl8225z2_set_gain(dev,4);
 836
 837                 write_phy_ofdm(dev,0x15, 0x40);
 838                 write_phy_ofdm(dev,0x17, 0x40);
 839
 840                 write_nic_dword(dev, 0x94,0x10000000);
 841         } else {
 842                 write_rtl8225(dev, 0x5, 0x1864);
 843                 write_nic_dword(dev, RF_PARA, 0x10044);
 844                 write_nic_dword(dev, RF_TIMING, 0xa8008);
 845                 write_phy_ofdm(dev, 0x0, 0x1);
 846                 write_phy_ofdm(dev, 0xa, 0x6);
 847                 write_phy_ofdm(dev, 0xb, 0x99);
 848                 write_phy_ofdm(dev, 0xf, 0x20);
 849                 write_phy_ofdm(dev, 0x11, 0x7);
 850
 851                 rtl8225z2_set_gain(dev,4);
 852
 853                 write_phy_ofdm(dev,0x15, 0x40);
 854                 write_phy_ofdm(dev,0x17, 0x40);
 855
 856                 write_nic_dword(dev, 0x94,0x04000002);
 857         }
 858 }
 859
 860 #define MAX_DOZE_WAITING_TIMES_85B              20
 861 #define MAX_POLLING_24F_TIMES_87SE              10
 862 #define LPS_MAX_SLEEP_WAITING_TIMES_87SE        5
 863
 864 bool SetZebraRFPowerState8185(struct net_device *dev,
 865                               RT_RF_POWER_STATE eRFPowerState)
 866 {
 867         struct r8180_priv *priv = ieee80211_priv(dev);
 868         u8                      btCR9346, btConfig3;
 869         bool bActionAllowed = true, bTurnOffBB = true;
 870         u8                      u1bTmp;
 871         int                     i;
 872         bool            bResult = true;
 873         u8                      QueueID;
 874
 875         if (priv->SetRFPowerStateInProgress == true)
 876                 return false;
 877
 878         priv->SetRFPowerStateInProgress = true;
 879
 880         btCR9346 = read_nic_byte(dev, CR9346);
 881         write_nic_byte(dev, CR9346, (btCR9346 | 0xC0));
 882
 883         btConfig3 = read_nic_byte(dev, CONFIG3);
 884         write_nic_byte(dev, CONFIG3, (btConfig3 | CONFIG3_PARM_En));
 885
 886         switch (priv->rf_chip) {
 887         case RF_ZEBRA2:
 888                 switch (eRFPowerState) {
 889                 case eRfOn:
 890                         RF_WriteReg(dev,0x4,0x9FF);
 891
 892                         write_nic_dword(dev, ANAPARAM, ANAPARM_ON);
 893                         write_nic_dword(dev, ANAPARAM2, ANAPARM2_ON);
 894
 895                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
 896
 897                         /* turn on CCK and OFDM */
 898                         u1bTmp = read_nic_byte(dev, 0x24E);
 899                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 900                         break;
 901                 case eRfSleep:
 902                         break;
 903                 case eRfOff:
 904                         break;
 905                 default:
 906                         bResult = false;
 907                         break;
 908                 }
 909                 break;
 910         case RF_ZEBRA4:
 911                 switch (eRFPowerState) {
 912                 case eRfOn:
 913                         write_nic_word(dev, 0x37C, 0x00EC);
 914
 915                         /* turn on AFE */
 916                         write_nic_byte(dev, 0x54, 0x00);
 917                         write_nic_byte(dev, 0x62, 0x00);
 918
 919                         /* turn on RF */
 920                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 921                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 922
 923                         /* turn on RF again */
 924                         RF_WriteReg(dev, 0x0, 0x009f); udelay(500);
 925                         RF_WriteReg(dev, 0x4, 0x0972); udelay(500);
 926
 927                         /* turn on BB */
 928                         write_phy_ofdm(dev,0x10,0x40);
 929                         write_phy_ofdm(dev,0x12,0x40);
 930
 931                         /* Avoid power down at init time. */
 932                         write_nic_byte(dev, CONFIG4, priv->RFProgType);
 933
 934                         u1bTmp = read_nic_byte(dev, 0x24E);
 935                         write_nic_byte(dev, 0x24E, (u1bTmp & (~(BIT5 | BIT6))));
 936                         break;
 937                 case eRfSleep:
 938                         for (QueueID = 0, i = 0; QueueID < 6;) {
 939                                 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
 940                                         QueueID++;
 941                                         continue;
 942                                 } else {
 943                                         priv->TxPollingTimes ++;
 944                                         if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 945                                                 bActionAllowed = false;
 946                                                 break;
 947                                         } else
 948                                                 udelay(10);
 949                                 }
 950                         }
 951
 952                         if (bActionAllowed) {
 953                                 /* turn off BB RXIQ matrix to cut off rx signal */
 954                                 write_phy_ofdm(dev, 0x10, 0x00);
 955                                 write_phy_ofdm(dev, 0x12, 0x00);
 956
 957                                 /* turn off RF */
 958                                 RF_WriteReg(dev, 0x4, 0x0000);
 959                                 RF_WriteReg(dev, 0x0, 0x0000);
 960
 961                                 /* turn off AFE except PLL */
 962                                 write_nic_byte(dev, 0x62, 0xff);
 963                                 write_nic_byte(dev, 0x54, 0xec);
 964
 965                                 mdelay(1);
 966
 967                                 {
 968                                         int i = 0;
 969                                         while (true) {
 970                                                 u8 tmp24F = read_nic_byte(dev, 0x24f);
 971
 972                                                 if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
 973                                                         bTurnOffBB = true;
 974                                                         break;
 975                                                 } else {
 976                                                         udelay(10);
 977                                                         i++;
 978                                                         priv->TxPollingTimes++;
 979
 980                                                         if (priv->TxPollingTimes >= LPS_MAX_SLEEP_WAITING_TIMES_87SE) {
 981                                                                 bTurnOffBB = false;
 982                                                                 break;
 983                                                         } else
 984                                                                 udelay(10);
 985                                                 }
 986                                         }
 987                                 }
 988
 989                                 if (bTurnOffBB) {
 990                                         /* turn off BB */
 991                                         u1bTmp = read_nic_byte(dev, 0x24E);
 992                                         write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
 993
 994                                         /* turn off AFE PLL */
 995                                         write_nic_byte(dev, 0x54, 0xFC);
 996                                         write_nic_word(dev, 0x37C, 0x00FC);
 997                                 }
 998                         }
 999                         break;
1000                 case eRfOff:
1001                         for (QueueID = 0, i = 0; QueueID < 6;) {
1002                                 if (get_curr_tx_free_desc(dev, QueueID) == priv->txringcount) {
1003                                         QueueID++;
1004                                         continue;
1005                                 } else {
1006                                         udelay(10);
1007                                         i++;
1008                                 }
1009
1010                                 if (i >= MAX_DOZE_WAITING_TIMES_85B)
1011                                         break;
1012                         }
1013
1014                         /* turn off BB RXIQ matrix to cut off rx signal */
1015                         write_phy_ofdm(dev, 0x10, 0x00);
1016                         write_phy_ofdm(dev, 0x12, 0x00);
1017
1018                         /* turn off RF */
1019                         RF_WriteReg(dev, 0x4, 0x0000);
1020                         RF_WriteReg(dev, 0x0, 0x0000);
1021
1022                         /* turn off AFE except PLL */
1023                         write_nic_byte(dev, 0x62, 0xff);
1024                         write_nic_byte(dev, 0x54, 0xec);
1025
1026                         mdelay(1);
1027
1028                         {
1029                                 int i = 0;
1030
1031                                 while (true)
1032                                 {
1033                                         u8 tmp24F = read_nic_byte(dev, 0x24f);
1034
1035                                         if ((tmp24F == 0x01) || (tmp24F == 0x09)) {
1036                                                 bTurnOffBB = true;
1037                                                 break;
1038                                         } else {
1039                                                 bTurnOffBB = false;
1040                                                 udelay(10);
1041                                                 i++;
1042                                         }
1043
1044                                         if (i > MAX_POLLING_24F_TIMES_87SE)
1045                                                 break;
1046                                 }
1047                         }
1048
1049                         if (bTurnOffBB) {
1050                                 /* turn off BB */
1051                                 u1bTmp = read_nic_byte(dev, 0x24E);
1052                                 write_nic_byte(dev, 0x24E, (u1bTmp | BIT5 | BIT6));
1053
1054                                 /* turn off AFE PLL (80M) */
1055                                 write_nic_byte(dev, 0x54, 0xFC);
1056                                 write_nic_word(dev, 0x37C, 0x00FC);
1057                         }
1058                         break;
1059                 default:
1060                         bResult = false;
1061                         printk("SetZebraRFPowerState8185(): unknow state to set: 0x%X!!!\n", eRFPowerState);
1062                         break;
1063                 }
1064                 break;
1065         }
1066
1067         btConfig3 &= ~(CONFIG3_PARM_En);
1068         write_nic_byte(dev, CONFIG3, btConfig3);
1069
1070         btCR9346 &= ~(0xC0);
1071         write_nic_byte(dev, CR9346, btCR9346);
1072
1073         if (bResult && bActionAllowed)
1074                 priv->eRFPowerState = eRFPowerState;
1075
1076         priv->SetRFPowerStateInProgress = false;
1077
1078         return bResult && bActionAllowed;
1079 }
1080
1081 void rtl8225z4_rf_sleep(struct net_device *dev)
1082 {
1083         MgntActSet_RF_State(dev, eRfSleep, RF_CHANGE_BY_PS);
1084 }
1085
1086 void rtl8225z4_rf_wakeup(struct net_device *dev)
1087 {
1088         MgntActSet_RF_State(dev, eRfOn, RF_CHANGE_BY_PS);
1089 }