SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/net/wireless/iwlwifi/iwl-5000.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2009 Intel Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  * The full GNU General Public License is included in this distribution in the
  19  * file called LICENSE.
  20  *
  21  * Contact Information:
  22  * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
  23  *
  24  *****************************************************************************/
  25
  26 #include <linux/kernel.h>
  27 #include <linux/module.h>
  28 #include <linux/init.h>
  29 #include <linux/pci.h>
  30 #include <linux/dma-mapping.h>
  31 #include <linux/delay.h>
  32 #include <linux/sched.h>
  33 #include <linux/skbuff.h>
  34 #include <linux/netdevice.h>
  35 #include <linux/wireless.h>
  36 #include <net/mac80211.h>
  37 #include <linux/etherdevice.h>
  38 #include <asm/unaligned.h>
  39
  40 #include "iwl-eeprom.h"
  41 #include "iwl-dev.h"
  42 #include "iwl-core.h"
  43 #include "iwl-io.h"
  44 #include "iwl-sta.h"
  45 #include "iwl-helpers.h"
  46 #include "iwl-5000-hw.h"
  47 #include "iwl-6000-hw.h"
  48
  49 /* Highest firmware API version supported */
  50 #define IWL5000_UCODE_API_MAX 2
  51 #define IWL5150_UCODE_API_MAX 2
  52
  53 /* Lowest firmware API version supported */
  54 #define IWL5000_UCODE_API_MIN 1
  55 #define IWL5150_UCODE_API_MIN 1
  56
  57 #define IWL5000_FW_PRE "iwlwifi-5000-"
  58 #define _IWL5000_MODULE_FIRMWARE(api) IWL5000_FW_PRE #api ".ucode"
  59 #define IWL5000_MODULE_FIRMWARE(api) _IWL5000_MODULE_FIRMWARE(api)
  60
  61 #define IWL5150_FW_PRE "iwlwifi-5150-"
  62 #define _IWL5150_MODULE_FIRMWARE(api) IWL5150_FW_PRE #api ".ucode"
  63 #define IWL5150_MODULE_FIRMWARE(api) _IWL5150_MODULE_FIRMWARE(api)
  64
  65 static const u16 iwl5000_default_queue_to_tx_fifo[] = {
  66         IWL_TX_FIFO_AC3,
  67         IWL_TX_FIFO_AC2,
  68         IWL_TX_FIFO_AC1,
  69         IWL_TX_FIFO_AC0,
  70         IWL50_CMD_FIFO_NUM,
  71         IWL_TX_FIFO_HCCA_1,
  72         IWL_TX_FIFO_HCCA_2
  73 };
  74
  75 /* FIXME: same implementation as 4965 */
  76 static int iwl5000_apm_stop_master(struct iwl_priv *priv)
  77 {
  78         unsigned long flags;
  79
  80         spin_lock_irqsave(&priv->lock, flags);
  81
  82         /* set stop master bit */
  83         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER);
  84
  85         iwl_poll_direct_bit(priv, CSR_RESET,
  86                                   CSR_RESET_REG_FLAG_MASTER_DISABLED, 100);
  87
  88         spin_unlock_irqrestore(&priv->lock, flags);
  89         IWL_DEBUG_INFO(priv, "stop master\n");
  90
  91         return 0;
  92 }
  93
  94
  95 int iwl5000_apm_init(struct iwl_priv *priv)
  96 {
  97         int ret = 0;
  98
  99         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 100                     CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER);
 101
 102         /* disable L0s without affecting L1 :don't wait for ICH L0s bug W/A) */
 103         iwl_set_bit(priv, CSR_GIO_CHICKEN_BITS,
 104                     CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX);
 105
 106         /* Set FH wait threshold to maximum (HW error during stress W/A) */
 107         iwl_set_bit(priv, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL);
 108
 109         /* enable HAP INTA to move device L1a -> L0s */
 110         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 111                     CSR_HW_IF_CONFIG_REG_BIT_HAP_WAKE_L1A);
 112
 113         if (priv->cfg->need_pll_cfg)
 114                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 115
 116         /* set "initialization complete" bit to move adapter
 117          * D0U* --> D0A* state */
 118         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 119
 120         /* wait for clock stabilization */
 121         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 122                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 123         if (ret < 0) {
 124                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 125                 return ret;
 126         }
 127
 128         /* enable DMA */
 129         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 130
 131         udelay(20);
 132
 133         /* disable L1-Active */
 134         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 135                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 136
 137         return ret;
 138 }
 139
 140 /* FIXME: this is identical to 4965 */
 141 void iwl5000_apm_stop(struct iwl_priv *priv)
 142 {
 143         unsigned long flags;
 144
 145         iwl5000_apm_stop_master(priv);
 146
 147         spin_lock_irqsave(&priv->lock, flags);
 148
 149         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 150
 151         udelay(10);
 152
 153         /* clear "init complete"  move adapter D0A* --> D0U state */
 154         iwl_clear_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 155
 156         spin_unlock_irqrestore(&priv->lock, flags);
 157 }
 158
 159
 160 int iwl5000_apm_reset(struct iwl_priv *priv)
 161 {
 162         int ret = 0;
 163
 164         iwl5000_apm_stop_master(priv);
 165
 166         iwl_set_bit(priv, CSR_RESET, CSR_RESET_REG_FLAG_SW_RESET);
 167
 168         udelay(10);
 169
 170
 171         /* FIXME: put here L1A -L0S w/a */
 172
 173         if (priv->cfg->need_pll_cfg)
 174                 iwl_set_bit(priv, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL);
 175
 176         /* set "initialization complete" bit to move adapter
 177          * D0U* --> D0A* state */
 178         iwl_set_bit(priv, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE);
 179
 180         /* wait for clock stabilization */
 181         ret = iwl_poll_direct_bit(priv, CSR_GP_CNTRL,
 182                         CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY, 25000);
 183         if (ret < 0) {
 184                 IWL_DEBUG_INFO(priv, "Failed to init the card\n");
 185                 goto out;
 186         }
 187
 188         /* enable DMA */
 189         iwl_write_prph(priv, APMG_CLK_EN_REG, APMG_CLK_VAL_DMA_CLK_RQT);
 190
 191         udelay(20);
 192
 193         /* disable L1-Active */
 194         iwl_set_bits_prph(priv, APMG_PCIDEV_STT_REG,
 195                           APMG_PCIDEV_STT_VAL_L1_ACT_DIS);
 196 out:
 197
 198         return ret;
 199 }
 200
 201
 202 /* NIC configuration for 5000 series and up */
 203 void iwl5000_nic_config(struct iwl_priv *priv)
 204 {
 205         unsigned long flags;
 206         u16 radio_cfg;
 207         u16 lctl;
 208
 209         spin_lock_irqsave(&priv->lock, flags);
 210
 211         lctl = iwl_pcie_link_ctl(priv);
 212
 213         /* HW bug W/A */
 214         /* L1-ASPM is enabled by BIOS */
 215         if ((lctl & PCI_CFG_LINK_CTRL_VAL_L1_EN) == PCI_CFG_LINK_CTRL_VAL_L1_EN)
 216                 /* L1-APSM enabled: disable L0S  */
 217                 iwl_set_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 218         else
 219                 /* L1-ASPM disabled: enable L0S */
 220                 iwl_clear_bit(priv, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_ENABLED);
 221
 222         radio_cfg = iwl_eeprom_query16(priv, EEPROM_RADIO_CONFIG);
 223
 224         /* write radio config values to register */
 225         if (EEPROM_RF_CFG_TYPE_MSK(radio_cfg) < EEPROM_5000_RF_CFG_TYPE_MAX)
 226                 iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 227                             EEPROM_RF_CFG_TYPE_MSK(radio_cfg) |
 228                             EEPROM_RF_CFG_STEP_MSK(radio_cfg) |
 229                             EEPROM_RF_CFG_DASH_MSK(radio_cfg));
 230
 231         /* set CSR_HW_CONFIG_REG for uCode use */
 232         iwl_set_bit(priv, CSR_HW_IF_CONFIG_REG,
 233                     CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI |
 234                     CSR_HW_IF_CONFIG_REG_BIT_MAC_SI);
 235
 236         /* W/A : NIC is stuck in a reset state after Early PCIe power off
 237          * (PCIe power is lost before PERST# is asserted),
 238          * causing ME FW to lose ownership and not being able to obtain it back.
 239          */
 240         iwl_set_bits_mask_prph(priv, APMG_PS_CTRL_REG,
 241                                 APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS,
 242                                 ~APMG_PS_CTRL_EARLY_PWR_OFF_RESET_DIS);
 243
 244
 245         spin_unlock_irqrestore(&priv->lock, flags);
 246 }
 247
 248
 249 /*
 250  * EEPROM
 251  */
 252 static u32 eeprom_indirect_address(const struct iwl_priv *priv, u32 address)
 253 {
 254         u16 offset = 0;
 255
 256         if ((address & INDIRECT_ADDRESS) == 0)
 257                 return address;
 258
 259         switch (address & INDIRECT_TYPE_MSK) {
 260         case INDIRECT_HOST:
 261                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_HOST);
 262                 break;
 263         case INDIRECT_GENERAL:
 264                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_GENERAL);
 265                 break;
 266         case INDIRECT_REGULATORY:
 267                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_REGULATORY);
 268                 break;
 269         case INDIRECT_CALIBRATION:
 270                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_CALIBRATION);
 271                 break;
 272         case INDIRECT_PROCESS_ADJST:
 273                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_PROCESS_ADJST);
 274                 break;
 275         case INDIRECT_OTHERS:
 276                 offset = iwl_eeprom_query16(priv, EEPROM_5000_LINK_OTHERS);
 277                 break;
 278         default:
 279                 IWL_ERR(priv, "illegal indirect type: 0x%X\n",
 280                 address & INDIRECT_TYPE_MSK);
 281                 break;
 282         }
 283
 284         /* translate the offset from words to byte */
 285         return (address & ADDRESS_MSK) + (offset << 1);
 286 }
 287
 288 u16 iwl5000_eeprom_calib_version(struct iwl_priv *priv)
 289 {
 290         struct iwl_eeprom_calib_hdr {
 291                 u8 version;
 292                 u8 pa_type;
 293                 u16 voltage;
 294         } *hdr;
 295
 296         hdr = (struct iwl_eeprom_calib_hdr *)iwl_eeprom_query_addr(priv,
 297                                                         EEPROM_5000_CALIB_ALL);
 298         return hdr->version;
 299
 300 }
 301
 302 static void iwl5000_gain_computation(struct iwl_priv *priv,
 303                 u32 average_noise[NUM_RX_CHAINS],
 304                 u16 min_average_noise_antenna_i,
 305                 u32 min_average_noise)
 306 {
 307         int i;
 308         s32 delta_g;
 309         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 310
 311         /* Find Gain Code for the antennas B and C */
 312         for (i = 1; i < NUM_RX_CHAINS; i++) {
 313                 if ((data->disconn_array[i])) {
 314                         data->delta_gain_code[i] = 0;
 315                         continue;
 316                 }
 317                 delta_g = (1000 * ((s32)average_noise[0] -
 318                         (s32)average_noise[i])) / 1500;
 319                 /* bound gain by 2 bits value max, 3rd bit is sign */
 320                 data->delta_gain_code[i] =
 321                         min(abs(delta_g), CHAIN_NOISE_MAX_DELTA_GAIN_CODE);
 322
 323                 if (delta_g < 0)
 324                         /* set negative sign */
 325                         data->delta_gain_code[i] |= (1 << 2);
 326         }
 327
 328         IWL_DEBUG_CALIB(priv, "Delta gains: ANT_B = %d  ANT_C = %d\n",
 329                         data->delta_gain_code[1], data->delta_gain_code[2]);
 330
 331         if (!data->radio_write) {
 332                 struct iwl_calib_chain_noise_gain_cmd cmd;
 333
 334                 memset(&cmd, 0, sizeof(cmd));
 335
 336                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_GAIN_CMD;
 337                 cmd.hdr.first_group = 0;
 338                 cmd.hdr.groups_num = 1;
 339                 cmd.hdr.data_valid = 1;
 340                 cmd.delta_gain_1 = data->delta_gain_code[1];
 341                 cmd.delta_gain_2 = data->delta_gain_code[2];
 342                 iwl_send_cmd_pdu_async(priv, REPLY_PHY_CALIBRATION_CMD,
 343                         sizeof(cmd), &cmd, NULL);
 344
 345                 data->radio_write = 1;
 346                 data->state = IWL_CHAIN_NOISE_CALIBRATED;
 347         }
 348
 349         data->chain_noise_a = 0;
 350         data->chain_noise_b = 0;
 351         data->chain_noise_c = 0;
 352         data->chain_signal_a = 0;
 353         data->chain_signal_b = 0;
 354         data->chain_signal_c = 0;
 355         data->beacon_count = 0;
 356 }
 357
 358 static void iwl5000_chain_noise_reset(struct iwl_priv *priv)
 359 {
 360         struct iwl_chain_noise_data *data = &priv->chain_noise_data;
 361         int ret;
 362
 363         if ((data->state == IWL_CHAIN_NOISE_ALIVE) && iwl_is_associated(priv)) {
 364                 struct iwl_calib_chain_noise_reset_cmd cmd;
 365                 memset(&cmd, 0, sizeof(cmd));
 366
 367                 cmd.hdr.op_code = IWL_PHY_CALIBRATE_CHAIN_NOISE_RESET_CMD;
 368                 cmd.hdr.first_group = 0;
 369                 cmd.hdr.groups_num = 1;
 370                 cmd.hdr.data_valid = 1;
 371                 ret = iwl_send_cmd_pdu(priv, REPLY_PHY_CALIBRATION_CMD,
 372                                         sizeof(cmd), &cmd);
 373                 if (ret)
 374                         IWL_ERR(priv,
 375                                 "Could not send REPLY_PHY_CALIBRATION_CMD\n");
 376                 data->state = IWL_CHAIN_NOISE_ACCUMULATE;
 377                 IWL_DEBUG_CALIB(priv, "Run chain_noise_calibrate\n");
 378         }
 379 }
 380
 381 void iwl5000_rts_tx_cmd_flag(struct ieee80211_tx_info *info,
 382                         __le32 *tx_flags)
 383 {
 384         if ((info->control.rates[0].flags & IEEE80211_TX_RC_USE_RTS_CTS) ||
 385             (info->control.rates[0].flags & IEEE80211_TX_RC_USE_CTS_PROTECT))
 386                 *tx_flags |= TX_CMD_FLG_RTS_CTS_MSK;
 387         else
 388                 *tx_flags &= ~TX_CMD_FLG_RTS_CTS_MSK;
 389 }
 390
 391 static struct iwl_sensitivity_ranges iwl5000_sensitivity = {
 392         .min_nrg_cck = 95,
 393         .max_nrg_cck = 0, /* not used, set to 0 */
 394         .auto_corr_min_ofdm = 90,
 395         .auto_corr_min_ofdm_mrc = 170,
 396         .auto_corr_min_ofdm_x1 = 120,
 397         .auto_corr_min_ofdm_mrc_x1 = 240,
 398
 399         .auto_corr_max_ofdm = 120,
 400         .auto_corr_max_ofdm_mrc = 210,
 401         .auto_corr_max_ofdm_x1 = 155,
 402         .auto_corr_max_ofdm_mrc_x1 = 290,
 403
 404         .auto_corr_min_cck = 125,
 405         .auto_corr_max_cck = 200,
 406         .auto_corr_min_cck_mrc = 170,
 407         .auto_corr_max_cck_mrc = 400,
 408         .nrg_th_cck = 95,
 409         .nrg_th_ofdm = 95,
 410 };
 411
 412 static struct iwl_sensitivity_ranges iwl5150_sensitivity = {
 413         .min_nrg_cck = 95,
 414         .max_nrg_cck = 0, /* not used, set to 0 */
 415         .auto_corr_min_ofdm = 90,
 416         .auto_corr_min_ofdm_mrc = 170,
 417         .auto_corr_min_ofdm_x1 = 105,
 418         .auto_corr_min_ofdm_mrc_x1 = 220,
 419
 420         .auto_corr_max_ofdm = 120,
 421         .auto_corr_max_ofdm_mrc = 210,
 422         /* max = min for performance bug in 5150 DSP */
 423         .auto_corr_max_ofdm_x1 = 105,
 424         .auto_corr_max_ofdm_mrc_x1 = 220,
 425
 426         .auto_corr_min_cck = 125,
 427         .auto_corr_max_cck = 200,
 428         .auto_corr_min_cck_mrc = 170,
 429         .auto_corr_max_cck_mrc = 400,
 430         .nrg_th_cck = 95,
 431         .nrg_th_ofdm = 95,
 432 };
 433
 434 const u8 *iwl5000_eeprom_query_addr(const struct iwl_priv *priv,
 435                                            size_t offset)
 436 {
 437         u32 address = eeprom_indirect_address(priv, offset);
 438         BUG_ON(address >= priv->cfg->eeprom_size);
 439         return &priv->eeprom[address];
 440 }
 441
 442 static void iwl5150_set_ct_threshold(struct iwl_priv *priv)
 443 {
 444         const s32 volt2temp_coef = IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF;
 445         s32 threshold = (s32)CELSIUS_TO_KELVIN(CT_KILL_THRESHOLD_LEGACY) -
 446                         iwl_temp_calib_to_offset(priv);
 447
 448         priv->hw_params.ct_kill_threshold = threshold * volt2temp_coef;
 449 }
 450
 451 static void iwl5000_set_ct_threshold(struct iwl_priv *priv)
 452 {
 453         /* want Celsius */
 454         priv->hw_params.ct_kill_threshold = CT_KILL_THRESHOLD_LEGACY;
 455 }
 456
 457 /*
 458  *  Calibration
 459  */
 460 static int iwl5000_set_Xtal_calib(struct iwl_priv *priv)
 461 {
 462         struct iwl_calib_xtal_freq_cmd cmd;
 463         u16 *xtal_calib = (u16 *)iwl_eeprom_query_addr(priv, EEPROM_5000_XTAL);
 464
 465         cmd.hdr.op_code = IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD;
 466         cmd.hdr.first_group = 0;
 467         cmd.hdr.groups_num = 1;
 468         cmd.hdr.data_valid = 1;
 469         cmd.cap_pin1 = (u8)xtal_calib[0];
 470         cmd.cap_pin2 = (u8)xtal_calib[1];
 471         return iwl_calib_set(&priv->calib_results[IWL_CALIB_XTAL],
 472                              (u8 *)&cmd, sizeof(cmd));
 473 }
 474
 475 static int iwl5000_send_calib_cfg(struct iwl_priv *priv)
 476 {
 477         struct iwl_calib_cfg_cmd calib_cfg_cmd;
 478         struct iwl_host_cmd cmd = {
 479                 .id = CALIBRATION_CFG_CMD,
 480                 .len = sizeof(struct iwl_calib_cfg_cmd),
 481                 .data = &calib_cfg_cmd,
 482         };
 483
 484         memset(&calib_cfg_cmd, 0, sizeof(calib_cfg_cmd));
 485         calib_cfg_cmd.ucd_calib_cfg.once.is_enable = IWL_CALIB_INIT_CFG_ALL;
 486         calib_cfg_cmd.ucd_calib_cfg.once.start = IWL_CALIB_INIT_CFG_ALL;
 487         calib_cfg_cmd.ucd_calib_cfg.once.send_res = IWL_CALIB_INIT_CFG_ALL;
 488         calib_cfg_cmd.ucd_calib_cfg.flags = IWL_CALIB_INIT_CFG_ALL;
 489
 490         return iwl_send_cmd(priv, &cmd);
 491 }
 492
 493 static void iwl5000_rx_calib_result(struct iwl_priv *priv,
 494                              struct iwl_rx_mem_buffer *rxb)
 495 {
 496         struct iwl_rx_packet *pkt = (void *)rxb->skb->data;
 497         struct iwl_calib_hdr *hdr = (struct iwl_calib_hdr *)pkt->u.raw;
 498         int len = le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK;
 499         int index;
 500
 501         /* reduce the size of the length field itself */
 502         len -= 4;
 503
 504         /* Define the order in which the results will be sent to the runtime
 505          * uCode. iwl_send_calib_results sends them in a row according to their
 506          * index. We sort them here */
 507         switch (hdr->op_code) {
 508         case IWL_PHY_CALIBRATE_DC_CMD:
 509                 index = IWL_CALIB_DC;
 510                 break;
 511         case IWL_PHY_CALIBRATE_LO_CMD:
 512                 index = IWL_CALIB_LO;
 513                 break;
 514         case IWL_PHY_CALIBRATE_TX_IQ_CMD:
 515                 index = IWL_CALIB_TX_IQ;
 516                 break;
 517         case IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD:
 518                 index = IWL_CALIB_TX_IQ_PERD;
 519                 break;
 520         case IWL_PHY_CALIBRATE_BASE_BAND_CMD:
 521                 index = IWL_CALIB_BASE_BAND;
 522                 break;
 523         default:
 524                 IWL_ERR(priv, "Unknown calibration notification %d\n",
 525                           hdr->op_code);
 526                 return;
 527         }
 528         iwl_calib_set(&priv->calib_results[index], pkt->u.raw, len);
 529 }
 530
 531 static void iwl5000_rx_calib_complete(struct iwl_priv *priv,
 532                                struct iwl_rx_mem_buffer *rxb)
 533 {
 534         IWL_DEBUG_INFO(priv, "Init. calibration is completed, restarting fw.\n");
 535         queue_work(priv->workqueue, &priv->restart);
 536 }
 537
 538 /*
 539  * ucode
 540  */
 541 static int iwl5000_load_section(struct iwl_priv *priv,
 542                                 struct fw_desc *image,
 543                                 u32 dst_addr)
 544 {
 545         dma_addr_t phy_addr = image->p_addr;
 546         u32 byte_cnt = image->len;
 547
 548         iwl_write_direct32(priv,
 549                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 550                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE);
 551
 552         iwl_write_direct32(priv,
 553                 FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), dst_addr);
 554
 555         iwl_write_direct32(priv,
 556                 FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL),
 557                 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK);
 558
 559         iwl_write_direct32(priv,
 560                 FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL),
 561                 (iwl_get_dma_hi_addr(phy_addr)
 562                         << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt);
 563
 564         iwl_write_direct32(priv,
 565                 FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL),
 566                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM |
 567                 1 << FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX |
 568                 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID);
 569
 570         iwl_write_direct32(priv,
 571                 FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL),
 572                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE       |
 573                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE    |
 574                 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD);
 575
 576         return 0;
 577 }
 578
 579 static int iwl5000_load_given_ucode(struct iwl_priv *priv,
 580                 struct fw_desc *inst_image,
 581                 struct fw_desc *data_image)
 582 {
 583         int ret = 0;
 584
 585         ret = iwl5000_load_section(priv, inst_image,
 586                                    IWL50_RTC_INST_LOWER_BOUND);
 587         if (ret)
 588                 return ret;
 589
 590         IWL_DEBUG_INFO(priv, "INST uCode section being loaded...\n");
 591         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 592                                         priv->ucode_write_complete, 5 * HZ);
 593         if (ret == -ERESTARTSYS) {
 594                 IWL_ERR(priv, "Could not load the INST uCode section due "
 595                         "to interrupt\n");
 596                 return ret;
 597         }
 598         if (!ret) {
 599                 IWL_ERR(priv, "Could not load the INST uCode section\n");
 600                 return -ETIMEDOUT;
 601         }
 602
 603         priv->ucode_write_complete = 0;
 604
 605         ret = iwl5000_load_section(
 606                 priv, data_image, IWL50_RTC_DATA_LOWER_BOUND);
 607         if (ret)
 608                 return ret;
 609
 610         IWL_DEBUG_INFO(priv, "DATA uCode section being loaded...\n");
 611
 612         ret = wait_event_interruptible_timeout(priv->wait_command_queue,
 613                                 priv->ucode_write_complete, 5 * HZ);
 614         if (ret == -ERESTARTSYS) {
 615                 IWL_ERR(priv, "Could not load the INST uCode section due "
 616                         "to interrupt\n");
 617                 return ret;
 618         } else if (!ret) {
 619                 IWL_ERR(priv, "Could not load the DATA uCode section\n");
 620                 return -ETIMEDOUT;
 621         } else
 622                 ret = 0;
 623
 624         priv->ucode_write_complete = 0;
 625
 626         return ret;
 627 }
 628
 629 int iwl5000_load_ucode(struct iwl_priv *priv)
 630 {
 631         int ret = 0;
 632
 633         /* check whether init ucode should be loaded, or rather runtime ucode */
 634         if (priv->ucode_init.len && (priv->ucode_type == UCODE_NONE)) {
 635                 IWL_DEBUG_INFO(priv, "Init ucode found. Loading init ucode...\n");
 636                 ret = iwl5000_load_given_ucode(priv,
 637                         &priv->ucode_init, &priv->ucode_init_data);
 638                 if (!ret) {
 639                         IWL_DEBUG_INFO(priv, "Init ucode load complete.\n");
 640                         priv->ucode_type = UCODE_INIT;
 641                 }
 642         } else {
 643                 IWL_DEBUG_INFO(priv, "Init ucode not found, or already loaded. "
 644                         "Loading runtime ucode...\n");
 645                 ret = iwl5000_load_given_ucode(priv,
 646                         &priv->ucode_code, &priv->ucode_data);
 647                 if (!ret) {
 648                         IWL_DEBUG_INFO(priv, "Runtime ucode load complete.\n");
 649                         priv->ucode_type = UCODE_RT;
 650                 }
 651         }
 652
 653         return ret;
 654 }
 655
 656 void iwl5000_init_alive_start(struct iwl_priv *priv)
 657 {
 658         int ret = 0;
 659
 660         /* Check alive response for "valid" sign from uCode */
 661         if (priv->card_alive_init.is_valid != UCODE_VALID_OK) {
 662                 /* We had an error bringing up the hardware, so take it
 663                  * all the way back down so we can try again */
 664                 IWL_DEBUG_INFO(priv, "Initialize Alive failed.\n");
 665                 goto restart;
 666         }
 667
 668         /* initialize uCode was loaded... verify inst image.
 669          * This is a paranoid check, because we would not have gotten the
 670          * "initialize" alive if code weren't properly loaded.  */
 671         if (iwl_verify_ucode(priv)) {
 672                 /* Runtime instruction load was bad;
 673                  * take it all the way back down so we can try again */
 674                 IWL_DEBUG_INFO(priv, "Bad \"initialize\" uCode load.\n");
 675                 goto restart;
 676         }
 677
 678         iwl_clear_stations_table(priv);
 679         ret = priv->cfg->ops->lib->alive_notify(priv);
 680         if (ret) {
 681                 IWL_WARN(priv,
 682                         "Could not complete ALIVE transition: %d\n", ret);
 683                 goto restart;
 684         }
 685
 686         iwl5000_send_calib_cfg(priv);
 687         return;
 688
 689 restart:
 690         /* real restart (first load init_ucode) */
 691         queue_work(priv->workqueue, &priv->restart);
 692 }
 693
 694 static void iwl5000_set_wr_ptrs(struct iwl_priv *priv,
 695                                 int txq_id, u32 index)
 696 {
 697         iwl_write_direct32(priv, HBUS_TARG_WRPTR,
 698                         (index & 0xff) | (txq_id << 8));
 699         iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(txq_id), index);
 700 }
 701
 702 static void iwl5000_tx_queue_set_status(struct iwl_priv *priv,
 703                                         struct iwl_tx_queue *txq,
 704                                         int tx_fifo_id, int scd_retry)
 705 {
 706         int txq_id = txq->q.id;
 707         int active = test_bit(txq_id, &priv->txq_ctx_active_msk) ? 1 : 0;
 708
 709         iwl_write_prph(priv, IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 710                         (active << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE) |
 711                         (tx_fifo_id << IWL50_SCD_QUEUE_STTS_REG_POS_TXF) |
 712                         (1 << IWL50_SCD_QUEUE_STTS_REG_POS_WSL) |
 713                         IWL50_SCD_QUEUE_STTS_REG_MSK);
 714
 715         txq->sched_retry = scd_retry;
 716
 717         IWL_DEBUG_INFO(priv, "%s %s Queue %d on AC %d\n",
 718                        active ? "Activate" : "Deactivate",
 719                        scd_retry ? "BA" : "AC", txq_id, tx_fifo_id);
 720 }
 721
 722 static int iwl5000_send_wimax_coex(struct iwl_priv *priv)
 723 {
 724         struct iwl_wimax_coex_cmd coex_cmd;
 725
 726         memset(&coex_cmd, 0, sizeof(coex_cmd));
 727
 728         return iwl_send_cmd_pdu(priv, COEX_PRIORITY_TABLE_CMD,
 729                                 sizeof(coex_cmd), &coex_cmd);
 730 }
 731
 732 int iwl5000_alive_notify(struct iwl_priv *priv)
 733 {
 734         u32 a;
 735         unsigned long flags;
 736         int i, chan;
 737         u32 reg_val;
 738
 739         spin_lock_irqsave(&priv->lock, flags);
 740
 741         priv->scd_base_addr = iwl_read_prph(priv, IWL50_SCD_SRAM_BASE_ADDR);
 742         a = priv->scd_base_addr + IWL50_SCD_CONTEXT_DATA_OFFSET;
 743         for (; a < priv->scd_base_addr + IWL50_SCD_TX_STTS_BITMAP_OFFSET;
 744                 a += 4)
 745                 iwl_write_targ_mem(priv, a, 0);
 746         for (; a < priv->scd_base_addr + IWL50_SCD_TRANSLATE_TBL_OFFSET;
 747                 a += 4)
 748                 iwl_write_targ_mem(priv, a, 0);
 749         for (; a < sizeof(u16) * priv->hw_params.max_txq_num; a += 4)
 750                 iwl_write_targ_mem(priv, a, 0);
 751
 752         iwl_write_prph(priv, IWL50_SCD_DRAM_BASE_ADDR,
 753                        priv->scd_bc_tbls.dma >> 10);
 754
 755         /* Enable DMA channel */
 756         for (chan = 0; chan < FH50_TCSR_CHNL_NUM ; chan++)
 757                 iwl_write_direct32(priv, FH_TCSR_CHNL_TX_CONFIG_REG(chan),
 758                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE |
 759                                 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE);
 760
 761         /* Update FH chicken bits */
 762         reg_val = iwl_read_direct32(priv, FH_TX_CHICKEN_BITS_REG);
 763         iwl_write_direct32(priv, FH_TX_CHICKEN_BITS_REG,
 764                            reg_val | FH_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN);
 765
 766         iwl_write_prph(priv, IWL50_SCD_QUEUECHAIN_SEL,
 767                 IWL50_SCD_QUEUECHAIN_SEL_ALL(priv->hw_params.max_txq_num));
 768         iwl_write_prph(priv, IWL50_SCD_AGGR_SEL, 0);
 769
 770         /* initiate the queues */
 771         for (i = 0; i < priv->hw_params.max_txq_num; i++) {
 772                 iwl_write_prph(priv, IWL50_SCD_QUEUE_RDPTR(i), 0);
 773                 iwl_write_direct32(priv, HBUS_TARG_WRPTR, 0 | (i << 8));
 774                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 775                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i), 0);
 776                 iwl_write_targ_mem(priv, priv->scd_base_addr +
 777                                 IWL50_SCD_CONTEXT_QUEUE_OFFSET(i) +
 778                                 sizeof(u32),
 779                                 ((SCD_WIN_SIZE <<
 780                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
 781                                 IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
 782                                 ((SCD_FRAME_LIMIT <<
 783                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
 784                                 IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
 785         }
 786
 787         iwl_write_prph(priv, IWL50_SCD_INTERRUPT_MASK,
 788                         IWL_MASK(0, priv->hw_params.max_txq_num));
 789
 790         /* Activate all Tx DMA/FIFO channels */
 791         priv->cfg->ops->lib->txq_set_sched(priv, IWL_MASK(0, 7));
 792
 793         iwl5000_set_wr_ptrs(priv, IWL_CMD_QUEUE_NUM, 0);
 794
 795         /* map qos queues to fifos one-to-one */
 796         for (i = 0; i < ARRAY_SIZE(iwl5000_default_queue_to_tx_fifo); i++) {
 797                 int ac = iwl5000_default_queue_to_tx_fifo[i];
 798                 iwl_txq_ctx_activate(priv, i);
 799                 iwl5000_tx_queue_set_status(priv, &priv->txq[i], ac, 0);
 800         }
 801         /* TODO - need to initialize those FIFOs inside the loop above,
 802          * not only mark them as active */
 803         iwl_txq_ctx_activate(priv, 4);
 804         iwl_txq_ctx_activate(priv, 7);
 805         iwl_txq_ctx_activate(priv, 8);
 806         iwl_txq_ctx_activate(priv, 9);
 807
 808         spin_unlock_irqrestore(&priv->lock, flags);
 809
 810
 811         iwl5000_send_wimax_coex(priv);
 812
 813         iwl5000_set_Xtal_calib(priv);
 814         iwl_send_calib_results(priv);
 815
 816         return 0;
 817 }
 818
 819 int iwl5000_hw_set_hw_params(struct iwl_priv *priv)
 820 {
 821         if ((priv->cfg->mod_params->num_of_queues > IWL50_NUM_QUEUES) ||
 822             (priv->cfg->mod_params->num_of_queues < IWL_MIN_NUM_QUEUES)) {
 823                 IWL_ERR(priv,
 824                         "invalid queues_num, should be between %d and %d\n",
 825                         IWL_MIN_NUM_QUEUES, IWL50_NUM_QUEUES);
 826                 return -EINVAL;
 827         }
 828
 829         priv->hw_params.max_txq_num = priv->cfg->mod_params->num_of_queues;
 830         priv->hw_params.dma_chnl_num = FH50_TCSR_CHNL_NUM;
 831         priv->hw_params.scd_bc_tbls_size =
 832                         IWL50_NUM_QUEUES * sizeof(struct iwl5000_scd_bc_tbl);
 833         priv->hw_params.tfd_size = sizeof(struct iwl_tfd);
 834         priv->hw_params.max_stations = IWL5000_STATION_COUNT;
 835         priv->hw_params.bcast_sta_id = IWL5000_BROADCAST_ID;
 836
 837         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 838         case CSR_HW_REV_TYPE_6x00:
 839         case CSR_HW_REV_TYPE_6x50:
 840                 priv->hw_params.max_data_size = IWL60_RTC_DATA_SIZE;
 841                 priv->hw_params.max_inst_size = IWL60_RTC_INST_SIZE;
 842                 break;
 843         default:
 844                 priv->hw_params.max_data_size = IWL50_RTC_DATA_SIZE;
 845                 priv->hw_params.max_inst_size = IWL50_RTC_INST_SIZE;
 846         }
 847
 848         priv->hw_params.max_bsm_size = 0;
 849         priv->hw_params.ht40_channel =  BIT(IEEE80211_BAND_2GHZ) |
 850                                         BIT(IEEE80211_BAND_5GHZ);
 851         priv->hw_params.rx_wrt_ptr_reg = FH_RSCSR_CHNL0_WPTR;
 852
 853         priv->hw_params.tx_chains_num = num_of_ant(priv->cfg->valid_tx_ant);
 854         priv->hw_params.rx_chains_num = num_of_ant(priv->cfg->valid_rx_ant);
 855         priv->hw_params.valid_tx_ant = priv->cfg->valid_tx_ant;
 856         priv->hw_params.valid_rx_ant = priv->cfg->valid_rx_ant;
 857
 858         if (priv->cfg->ops->lib->temp_ops.set_ct_kill)
 859                 priv->cfg->ops->lib->temp_ops.set_ct_kill(priv);
 860
 861         /* Set initial sensitivity parameters */
 862         /* Set initial calibration set */
 863         switch (priv->hw_rev & CSR_HW_REV_TYPE_MSK) {
 864         case CSR_HW_REV_TYPE_5150:
 865                 priv->hw_params.sens = &iwl5150_sensitivity;
 866                 priv->hw_params.calib_init_cfg =
 867                         BIT(IWL_CALIB_DC)               |
 868                         BIT(IWL_CALIB_LO)               |
 869                         BIT(IWL_CALIB_TX_IQ)            |
 870                         BIT(IWL_CALIB_BASE_BAND);
 871
 872                 break;
 873         default:
 874                 priv->hw_params.sens = &iwl5000_sensitivity;
 875                 priv->hw_params.calib_init_cfg =
 876                         BIT(IWL_CALIB_XTAL)             |
 877                         BIT(IWL_CALIB_LO)               |
 878                         BIT(IWL_CALIB_TX_IQ)            |
 879                         BIT(IWL_CALIB_TX_IQ_PERD)       |
 880                         BIT(IWL_CALIB_BASE_BAND);
 881                 break;
 882         }
 883
 884         return 0;
 885 }
 886
 887 /**
 888  * iwl5000_txq_update_byte_cnt_tbl - Set up entry in Tx byte-count array
 889  */
 890 void iwl5000_txq_update_byte_cnt_tbl(struct iwl_priv *priv,
 891                                             struct iwl_tx_queue *txq,
 892                                             u16 byte_cnt)
 893 {
 894         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 895         int write_ptr = txq->q.write_ptr;
 896         int txq_id = txq->q.id;
 897         u8 sec_ctl = 0;
 898         u8 sta_id = 0;
 899         u16 len = byte_cnt + IWL_TX_CRC_SIZE + IWL_TX_DELIMITER_SIZE;
 900         __le16 bc_ent;
 901
 902         WARN_ON(len > 0xFFF || write_ptr >= TFD_QUEUE_SIZE_MAX);
 903
 904         if (txq_id != IWL_CMD_QUEUE_NUM) {
 905                 sta_id = txq->cmd[txq->q.write_ptr]->cmd.tx.sta_id;
 906                 sec_ctl = txq->cmd[txq->q.write_ptr]->cmd.tx.sec_ctl;
 907
 908                 switch (sec_ctl & TX_CMD_SEC_MSK) {
 909                 case TX_CMD_SEC_CCM:
 910                         len += CCMP_MIC_LEN;
 911                         break;
 912                 case TX_CMD_SEC_TKIP:
 913                         len += TKIP_ICV_LEN;
 914                         break;
 915                 case TX_CMD_SEC_WEP:
 916                         len += WEP_IV_LEN + WEP_ICV_LEN;
 917                         break;
 918                 }
 919         }
 920
 921         bc_ent = cpu_to_le16((len & 0xFFF) | (sta_id << 12));
 922
 923         scd_bc_tbl[txq_id].tfd_offset[write_ptr] = bc_ent;
 924
 925         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 926                 scd_bc_tbl[txq_id].
 927                         tfd_offset[TFD_QUEUE_SIZE_MAX + write_ptr] = bc_ent;
 928 }
 929
 930 void iwl5000_txq_inval_byte_cnt_tbl(struct iwl_priv *priv,
 931                                            struct iwl_tx_queue *txq)
 932 {
 933         struct iwl5000_scd_bc_tbl *scd_bc_tbl = priv->scd_bc_tbls.addr;
 934         int txq_id = txq->q.id;
 935         int read_ptr = txq->q.read_ptr;
 936         u8 sta_id = 0;
 937         __le16 bc_ent;
 938
 939         WARN_ON(read_ptr >= TFD_QUEUE_SIZE_MAX);
 940
 941         if (txq_id != IWL_CMD_QUEUE_NUM)
 942                 sta_id = txq->cmd[read_ptr]->cmd.tx.sta_id;
 943
 944         bc_ent =  cpu_to_le16(1 | (sta_id << 12));
 945         scd_bc_tbl[txq_id].tfd_offset[read_ptr] = bc_ent;
 946
 947         if (txq->q.write_ptr < TFD_QUEUE_SIZE_BC_DUP)
 948                 scd_bc_tbl[txq_id].
 949                         tfd_offset[TFD_QUEUE_SIZE_MAX + read_ptr] =  bc_ent;
 950 }
 951
 952 static int iwl5000_tx_queue_set_q2ratid(struct iwl_priv *priv, u16 ra_tid,
 953                                         u16 txq_id)
 954 {
 955         u32 tbl_dw_addr;
 956         u32 tbl_dw;
 957         u16 scd_q2ratid;
 958
 959         scd_q2ratid = ra_tid & IWL_SCD_QUEUE_RA_TID_MAP_RATID_MSK;
 960
 961         tbl_dw_addr = priv->scd_base_addr +
 962                         IWL50_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id);
 963
 964         tbl_dw = iwl_read_targ_mem(priv, tbl_dw_addr);
 965
 966         if (txq_id & 0x1)
 967                 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF);
 968         else
 969                 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000);
 970
 971         iwl_write_targ_mem(priv, tbl_dw_addr, tbl_dw);
 972
 973         return 0;
 974 }
 975 static void iwl5000_tx_queue_stop_scheduler(struct iwl_priv *priv, u16 txq_id)
 976 {
 977         /* Simply stop the queue, but don't change any configuration;
 978          * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */
 979         iwl_write_prph(priv,
 980                 IWL50_SCD_QUEUE_STATUS_BITS(txq_id),
 981                 (0 << IWL50_SCD_QUEUE_STTS_REG_POS_ACTIVE)|
 982                 (1 << IWL50_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN));
 983 }
 984
 985 int iwl5000_txq_agg_enable(struct iwl_priv *priv, int txq_id,
 986                                   int tx_fifo, int sta_id, int tid, u16 ssn_idx)
 987 {
 988         unsigned long flags;
 989         u16 ra_tid;
 990
 991         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
 992             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
 993                 IWL_WARN(priv,
 994                         "queue number out of range: %d, must be %d to %d\n",
 995                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
 996                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
 997                 return -EINVAL;
 998         }
 999
1000         ra_tid = BUILD_RAxTID(sta_id, tid);
1001
1002         /* Modify device's station table to Tx this TID */
1003         iwl_sta_tx_modify_enable_tid(priv, sta_id, tid);
1004
1005         spin_lock_irqsave(&priv->lock, flags);
1006
1007         /* Stop this Tx queue before configuring it */
1008         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1009
1010         /* Map receiver-address / traffic-ID to this queue */
1011         iwl5000_tx_queue_set_q2ratid(priv, ra_tid, txq_id);
1012
1013         /* Set this queue as a chain-building queue */
1014         iwl_set_bits_prph(priv, IWL50_SCD_QUEUECHAIN_SEL, (1<<txq_id));
1015
1016         /* enable aggregations for the queue */
1017         iwl_set_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1<<txq_id));
1018
1019         /* Place first TFD at index corresponding to start sequence number.
1020          * Assumes that ssn_idx is valid (!= 0xFFF) */
1021         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1022         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1023         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1024
1025         /* Set up Tx window size and frame limit for this queue */
1026         iwl_write_targ_mem(priv, priv->scd_base_addr +
1027                         IWL50_SCD_CONTEXT_QUEUE_OFFSET(txq_id) +
1028                         sizeof(u32),
1029                         ((SCD_WIN_SIZE <<
1030                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_POS) &
1031                         IWL50_SCD_QUEUE_CTX_REG2_WIN_SIZE_MSK) |
1032                         ((SCD_FRAME_LIMIT <<
1033                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) &
1034                         IWL50_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK));
1035
1036         iwl_set_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1037
1038         /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */
1039         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 1);
1040
1041         spin_unlock_irqrestore(&priv->lock, flags);
1042
1043         return 0;
1044 }
1045
1046 int iwl5000_txq_agg_disable(struct iwl_priv *priv, u16 txq_id,
1047                                    u16 ssn_idx, u8 tx_fifo)
1048 {
1049         if ((IWL50_FIRST_AMPDU_QUEUE > txq_id) ||
1050             (IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES <= txq_id)) {
1051                 IWL_ERR(priv,
1052                         "queue number out of range: %d, must be %d to %d\n",
1053                         txq_id, IWL50_FIRST_AMPDU_QUEUE,
1054                         IWL50_FIRST_AMPDU_QUEUE + IWL50_NUM_AMPDU_QUEUES - 1);
1055                 return -EINVAL;
1056         }
1057
1058         iwl5000_tx_queue_stop_scheduler(priv, txq_id);
1059
1060         iwl_clear_bits_prph(priv, IWL50_SCD_AGGR_SEL, (1 << txq_id));
1061
1062         priv->txq[txq_id].q.read_ptr = (ssn_idx & 0xff);
1063         priv->txq[txq_id].q.write_ptr = (ssn_idx & 0xff);
1064         /* supposes that ssn_idx is valid (!= 0xFFF) */
1065         iwl5000_set_wr_ptrs(priv, txq_id, ssn_idx);
1066
1067         iwl_clear_bits_prph(priv, IWL50_SCD_INTERRUPT_MASK, (1 << txq_id));
1068         iwl_txq_ctx_deactivate(priv, txq_id);
1069         iwl5000_tx_queue_set_status(priv, &priv->txq[txq_id], tx_fifo, 0);
1070
1071         return 0;
1072 }
1073
1074 u16 iwl5000_build_addsta_hcmd(const struct iwl_addsta_cmd *cmd, u8 *data)
1075 {
1076         u16 size = (u16)sizeof(struct iwl_addsta_cmd);
1077         struct iwl_addsta_cmd *addsta = (struct iwl_addsta_cmd *)data;
1078         memcpy(addsta, cmd, size);
1079         /* resrved in 5000 */
1080         addsta->rate_n_flags = cpu_to_le16(0);
1081         return size;
1082 }
1083
1084
1085 /*
1086  * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask
1087  * must be called under priv->lock and mac access
1088  */
1089 void iwl5000_txq_set_sched(struct iwl_priv *priv, u32 mask)
1090 {
1091         iwl_write_prph(priv, IWL50_SCD_TXFACT, mask);
1092 }
1093
1094
1095 static inline u32 iwl5000_get_scd_ssn(struct iwl5000_tx_resp *tx_resp)
1096 {
1097         return le32_to_cpup((__le32 *)&tx_resp->status +
1098                             tx_resp->frame_count) & MAX_SN;
1099 }
1100
1101 static int iwl5000_tx_status_reply_tx(struct iwl_priv *priv,
1102                                       struct iwl_ht_agg *agg,
1103                                       struct iwl5000_tx_resp *tx_resp,
1104                                       int txq_id, u16 start_idx)
1105 {
1106         u16 status;
1107         struct agg_tx_status *frame_status = &tx_resp->status;
1108         struct ieee80211_tx_info *info = NULL;
1109         struct ieee80211_hdr *hdr = NULL;
1110         u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags);
1111         int i, sh, idx;
1112         u16 seq;
1113
1114         if (agg->wait_for_ba)
1115                 IWL_DEBUG_TX_REPLY(priv, "got tx response w/o block-ack\n");
1116
1117         agg->frame_count = tx_resp->frame_count;
1118         agg->start_idx = start_idx;
1119         agg->rate_n_flags = rate_n_flags;
1120         agg->bitmap = 0;
1121
1122         /* # frames attempted by Tx command */
1123         if (agg->frame_count == 1) {
1124                 /* Only one frame was attempted; no block-ack will arrive */
1125                 status = le16_to_cpu(frame_status[0].status);
1126                 idx = start_idx;
1127
1128                 /* FIXME: code repetition */
1129                 IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, StartIdx=%d idx=%d\n",
1130                                    agg->frame_count, agg->start_idx, idx);
1131
1132                 info = IEEE80211_SKB_CB(priv->txq[txq_id].txb[idx].skb[0]);
1133                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1134                 info->flags &= ~IEEE80211_TX_CTL_AMPDU;
1135                 info->flags |= iwl_is_tx_success(status) ?
1136                                         IEEE80211_TX_STAT_ACK : 0;
1137                 iwl_hwrate_to_tx_control(priv, rate_n_flags, info);
1138
1139                 /* FIXME: code repetition end */
1140
1141                 IWL_DEBUG_TX_REPLY(priv, "1 Frame 0x%x failure :%d\n",
1142                                     status & 0xff, tx_resp->failure_frame);
1143                 IWL_DEBUG_TX_REPLY(priv, "Rate Info rate_n_flags=%x\n", rate_n_flags);
1144
1145                 agg->wait_for_ba = 0;
1146         } else {
1147                 /* Two or more frames were attempted; expect block-ack */
1148                 u64 bitmap = 0;
1149                 int start = agg->start_idx;
1150
1151                 /* Construct bit-map of pending frames within Tx window */
1152                 for (i = 0; i < agg->frame_count; i++) {
1153                         u16 sc;
1154                         status = le16_to_cpu(frame_status[i].status);
1155                         seq  = le16_to_cpu(frame_status[i].sequence);
1156                         idx = SEQ_TO_INDEX(seq);
1157                         txq_id = SEQ_TO_QUEUE(seq);
1158
1159                         if (status & (AGG_TX_STATE_FEW_BYTES_MSK |
1160                                       AGG_TX_STATE_ABORT_MSK))
1161                                 continue;
1162
1163                         IWL_DEBUG_TX_REPLY(priv, "FrameCnt = %d, txq_id=%d idx=%d\n",
1164                                            agg->frame_count, txq_id, idx);
1165
1166                         hdr = iwl_tx_queue_get_hdr(priv, txq_id, idx);
1167                         if (!hdr) {
1168                                 IWL_ERR(priv,
1169                                         "BUG_ON idx doesn't point to valid skb"
1170                                         " idx=%d, txq_id=%d\n", idx, txq_id);
1171                                 return -1;
1172                         }
1173
1174                         sc = le16_to_cpu(hdr->seq_ctrl);
1175                         if (idx != (SEQ_TO_SN(sc) & 0xff)) {
1176                                 IWL_ERR(priv,
1177                                         "BUG_ON idx doesn't match seq control"
1178                                         " idx=%d, seq_idx=%d, seq=%d\n",
1179                                           idx, SEQ_TO_SN(sc),
1180                                           hdr->seq_ctrl);
1181                                 return -1;
1182                         }
1183
1184                         IWL_DEBUG_TX_REPLY(priv, "AGG Frame i=%d idx %d seq=%d\n",
1185                                            i, idx, SEQ_TO_SN(sc));
1186
1187                         sh = idx - start;
1188                         if (sh > 64) {
1189                                 sh = (start - idx) + 0xff;
1190                                 bitmap = bitmap << sh;
1191                                 sh = 0;
1192                                 start = idx;
1193                         } else if (sh < -64)
1194                                 sh  = 0xff - (start - idx);
1195                         else if (sh < 0) {
1196                                 sh = start - idx;
1197                                 start = idx;
1198                                 bitmap = bitmap << sh;
1199                                 sh = 0;
1200                         }
1201                         bitmap |= 1ULL << sh;
1202                         IWL_DEBUG_TX_REPLY(priv, "start=%d bitmap=0x%llx\n",
1203                                            start, (unsigned long long)bitmap);
1204                 }
1205
1206                 agg->bitmap = bitmap;
1207                 agg->start_idx = start;
1208                 IWL_DEBUG_TX_REPLY(priv, "Frames %d start_idx=%d bitmap=0x%llx\n",
1209                                    agg->frame_count, agg->start_idx,
1210                                    (unsigned long long)agg->bitmap);
1211
1212                 if (bitmap)
1213                         agg->wait_for_ba = 1;
1214         }
1215         return 0;
1216 }
1217
1218 static void iwl5000_rx_reply_tx(struct iwl_priv *priv,
1219                                 struct iwl_rx_mem_buffer *rxb)
1220 {
1221         struct iwl_rx_packet *pkt = (struct iwl_rx_packet *)rxb->skb->data;
1222         u16 sequence = le16_to_cpu(pkt->hdr.sequence);
1223         int txq_id = SEQ_TO_QUEUE(sequence);
1224         int index = SEQ_TO_INDEX(sequence);
1225         struct iwl_tx_queue *txq = &priv->txq[txq_id];
1226         struct ieee80211_tx_info *info;
1227         struct iwl5000_tx_resp *tx_resp = (void *)&pkt->u.raw[0];
1228         u32  status = le16_to_cpu(tx_resp->status.status);
1229         int tid;
1230         int sta_id;
1231         int freed;
1232
1233         if ((index >= txq->q.n_bd) || (iwl_queue_used(&txq->q, index) == 0)) {
1234                 IWL_ERR(priv, "Read index for DMA queue txq_id (%d) index %d "
1235                           "is out of range [0-%d] %d %d\n", txq_id,
1236                           index, txq->q.n_bd, txq->q.write_ptr,
1237                           txq->q.read_ptr);
1238                 return;
1239         }
1240
1241         info = IEEE80211_SKB_CB(txq->txb[txq->q.read_ptr].skb[0]);
1242         memset(&info->status, 0, sizeof(info->status));
1243
1244         tid = (tx_resp->ra_tid & IWL50_TX_RES_TID_MSK) >> IWL50_TX_RES_TID_POS;
1245         sta_id = (tx_resp->ra_tid & IWL50_TX_RES_RA_MSK) >> IWL50_TX_RES_RA_POS;
1246
1247         if (txq->sched_retry) {
1248                 const u32 scd_ssn = iwl5000_get_scd_ssn(tx_resp);
1249                 struct iwl_ht_agg *agg = NULL;
1250
1251                 agg = &priv->stations[sta_id].tid[tid].agg;
1252
1253                 iwl5000_tx_status_reply_tx(priv, agg, tx_resp, txq_id, index);
1254
1255                 /* check if BAR is needed */
1256                 if ((tx_resp->frame_count == 1) && !iwl_is_tx_success(status))
1257                         info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK;
1258
1259                 if (txq->q.read_ptr != (scd_ssn & 0xff)) {
1260                         index = iwl_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd);
1261                         IWL_DEBUG_TX_REPLY(priv, "Retry scheduler reclaim "
1262                                         "scd_ssn=%d idx=%d txq=%d swq=%d\n",
1263                                         scd_ssn , index, txq_id, txq->swq_id);
1264
1265                         freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1266                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1267
1268                         if (priv->mac80211_registered &&
1269                             (iwl_queue_space(&txq->q) > txq->q.low_mark) &&
1270                             (agg->state != IWL_EMPTYING_HW_QUEUE_DELBA)) {
1271                                 if (agg->state == IWL_AGG_OFF)
1272                                         iwl_wake_queue(priv, txq_id);
1273                                 else
1274                                         iwl_wake_queue(priv, txq->swq_id);
1275                         }
1276                 }
1277         } else {
1278                 BUG_ON(txq_id != txq->swq_id);
1279
1280                 info->status.rates[0].count = tx_resp->failure_frame + 1;
1281                 info->flags |= iwl_is_tx_success(status) ?
1282                                         IEEE80211_TX_STAT_ACK : 0;
1283                 iwl_hwrate_to_tx_control(priv,
1284                                         le32_to_cpu(tx_resp->rate_n_flags),
1285                                         info);
1286
1287                 IWL_DEBUG_TX_REPLY(priv, "TXQ %d status %s (0x%08x) rate_n_flags "
1288                                    "0x%x retries %d\n",
1289                                    txq_id,
1290                                    iwl_get_tx_fail_reason(status), status,
1291                                    le32_to_cpu(tx_resp->rate_n_flags),
1292                                    tx_resp->failure_frame);
1293
1294                 freed = iwl_tx_queue_reclaim(priv, txq_id, index);
1295                 if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1296                         priv->stations[sta_id].tid[tid].tfds_in_queue -= freed;
1297
1298                 if (priv->mac80211_registered &&
1299                     (iwl_queue_space(&txq->q) > txq->q.low_mark))
1300                         iwl_wake_queue(priv, txq_id);
1301         }
1302
1303         if (ieee80211_is_data_qos(tx_resp->frame_ctrl))
1304                 iwl_txq_check_empty(priv, sta_id, tid, txq_id);
1305
1306         if (iwl_check_bits(status, TX_ABORT_REQUIRED_MSK))
1307                 IWL_ERR(priv, "TODO:  Implement Tx ABORT REQUIRED!!!\n");
1308 }
1309
1310 /* Currently 5000 is the superset of everything */
1311 u16 iwl5000_get_hcmd_size(u8 cmd_id, u16 len)
1312 {
1313         return len;
1314 }
1315
1316 void iwl5000_setup_deferred_work(struct iwl_priv *priv)
1317 {
1318         /* in 5000 the tx power calibration is done in uCode */
1319         priv->disable_tx_power_cal = 1;
1320 }
1321
1322 void iwl5000_rx_handler_setup(struct iwl_priv *priv)
1323 {
1324         /* init calibration handlers */
1325         priv->rx_handlers[CALIBRATION_RES_NOTIFICATION] =
1326                                         iwl5000_rx_calib_result;
1327         priv->rx_handlers[CALIBRATION_COMPLETE_NOTIFICATION] =
1328                                         iwl5000_rx_calib_complete;
1329         priv->rx_handlers[REPLY_TX] = iwl5000_rx_reply_tx;
1330 }
1331
1332
1333 int iwl5000_hw_valid_rtc_data_addr(u32 addr)
1334 {
1335         return (addr >= IWL50_RTC_DATA_LOWER_BOUND) &&
1336                 (addr < IWL50_RTC_DATA_UPPER_BOUND);
1337 }
1338
1339 static int iwl5000_send_rxon_assoc(struct iwl_priv *priv)
1340 {
1341         int ret = 0;
1342         struct iwl5000_rxon_assoc_cmd rxon_assoc;
1343         const struct iwl_rxon_cmd *rxon1 = &priv->staging_rxon;
1344         const struct iwl_rxon_cmd *rxon2 = &priv->active_rxon;
1345
1346         if ((rxon1->flags == rxon2->flags) &&
1347             (rxon1->filter_flags == rxon2->filter_flags) &&
1348             (rxon1->cck_basic_rates == rxon2->cck_basic_rates) &&
1349             (rxon1->ofdm_ht_single_stream_basic_rates ==
1350              rxon2->ofdm_ht_single_stream_basic_rates) &&
1351             (rxon1->ofdm_ht_dual_stream_basic_rates ==
1352              rxon2->ofdm_ht_dual_stream_basic_rates) &&
1353             (rxon1->ofdm_ht_triple_stream_basic_rates ==
1354              rxon2->ofdm_ht_triple_stream_basic_rates) &&
1355             (rxon1->acquisition_data == rxon2->acquisition_data) &&
1356             (rxon1->rx_chain == rxon2->rx_chain) &&
1357             (rxon1->ofdm_basic_rates == rxon2->ofdm_basic_rates)) {
1358                 IWL_DEBUG_INFO(priv, "Using current RXON_ASSOC.  Not resending.\n");
1359                 return 0;
1360         }
1361
1362         rxon_assoc.flags = priv->staging_rxon.flags;
1363         rxon_assoc.filter_flags = priv->staging_rxon.filter_flags;
1364         rxon_assoc.ofdm_basic_rates = priv->staging_rxon.ofdm_basic_rates;
1365         rxon_assoc.cck_basic_rates = priv->staging_rxon.cck_basic_rates;
1366         rxon_assoc.reserved1 = 0;
1367         rxon_assoc.reserved2 = 0;
1368         rxon_assoc.reserved3 = 0;
1369         rxon_assoc.ofdm_ht_single_stream_basic_rates =
1370             priv->staging_rxon.ofdm_ht_single_stream_basic_rates;
1371         rxon_assoc.ofdm_ht_dual_stream_basic_rates =
1372             priv->staging_rxon.ofdm_ht_dual_stream_basic_rates;
1373         rxon_assoc.rx_chain_select_flags = priv->staging_rxon.rx_chain;
1374         rxon_assoc.ofdm_ht_triple_stream_basic_rates =
1375                  priv->staging_rxon.ofdm_ht_triple_stream_basic_rates;
1376         rxon_assoc.acquisition_data = priv->staging_rxon.acquisition_data;
1377
1378         ret = iwl_send_cmd_pdu_async(priv, REPLY_RXON_ASSOC,
1379                                      sizeof(rxon_assoc), &rxon_assoc, NULL);
1380         if (ret)
1381                 return ret;
1382
1383         return ret;
1384 }
1385 int  iwl5000_send_tx_power(struct iwl_priv *priv)
1386 {
1387         struct iwl5000_tx_power_dbm_cmd tx_power_cmd;
1388         u8 tx_ant_cfg_cmd;
1389
1390         /* half dBm need to multiply */
1391         tx_power_cmd.global_lmt = (s8)(2 * priv->tx_power_user_lmt);
1392         tx_power_cmd.flags = IWL50_TX_POWER_NO_CLOSED;
1393         tx_power_cmd.srv_chan_lmt = IWL50_TX_POWER_AUTO;
1394
1395         if (IWL_UCODE_API(priv->ucode_ver) == 1)
1396                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD_V1;
1397         else
1398                 tx_ant_cfg_cmd = REPLY_TX_POWER_DBM_CMD;
1399
1400         return  iwl_send_cmd_pdu_async(priv, tx_ant_cfg_cmd,
1401                                        sizeof(tx_power_cmd), &tx_power_cmd,
1402                                        NULL);
1403 }
1404
1405 void iwl5000_temperature(struct iwl_priv *priv)
1406 {
1407         /* store temperature from statistics (in Celsius) */
1408         priv->temperature = le32_to_cpu(priv->statistics.general.temperature);
1409         iwl_tt_handler(priv);
1410 }
1411
1412 static void iwl5150_temperature(struct iwl_priv *priv)
1413 {
1414         u32 vt = 0;
1415         s32 offset =  iwl_temp_calib_to_offset(priv);
1416
1417         vt = le32_to_cpu(priv->statistics.general.temperature);
1418         vt = vt / IWL_5150_VOLTAGE_TO_TEMPERATURE_COEFF + offset;
1419         /* now vt hold the temperature in Kelvin */
1420         priv->temperature = KELVIN_TO_CELSIUS(vt);
1421         iwl_tt_handler(priv);
1422 }
1423
1424 /* Calc max signal level (dBm) among 3 possible receivers */
1425 int iwl5000_calc_rssi(struct iwl_priv *priv,
1426                              struct iwl_rx_phy_res *rx_resp)
1427 {
1428         /* data from PHY/DSP regarding signal strength, etc.,
1429          *   contents are always there, not configurable by host
1430          */
1431         struct iwl5000_non_cfg_phy *ncphy =
1432                 (struct iwl5000_non_cfg_phy *)rx_resp->non_cfg_phy_buf;
1433         u32 val, rssi_a, rssi_b, rssi_c, max_rssi;
1434         u8 agc;
1435
1436         val  = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_AGC_IDX]);
1437         agc = (val & IWL50_OFDM_AGC_MSK) >> IWL50_OFDM_AGC_BIT_POS;
1438
1439         /* Find max rssi among 3 possible receivers.
1440          * These values are measured by the digital signal processor (DSP).
1441          * They should stay fairly constant even as the signal strength varies,
1442          *   if the radio's automatic gain control (AGC) is working right.
1443          * AGC value (see below) will provide the "interesting" info.
1444          */
1445         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_AB_IDX]);
1446         rssi_a = (val & IWL50_OFDM_RSSI_A_MSK) >> IWL50_OFDM_RSSI_A_BIT_POS;
1447         rssi_b = (val & IWL50_OFDM_RSSI_B_MSK) >> IWL50_OFDM_RSSI_B_BIT_POS;
1448         val = le32_to_cpu(ncphy->non_cfg_phy[IWL50_RX_RES_RSSI_C_IDX]);
1449         rssi_c = (val & IWL50_OFDM_RSSI_C_MSK) >> IWL50_OFDM_RSSI_C_BIT_POS;
1450
1451         max_rssi = max_t(u32, rssi_a, rssi_b);
1452         max_rssi = max_t(u32, max_rssi, rssi_c);
1453
1454         IWL_DEBUG_STATS(priv, "Rssi In A %d B %d C %d Max %d AGC dB %d\n",
1455                 rssi_a, rssi_b, rssi_c, max_rssi, agc);
1456
1457         /* dBm = max_rssi dB - agc dB - constant.
1458          * Higher AGC (higher radio gain) means lower signal. */
1459         return max_rssi - agc - IWL49_RSSI_OFFSET;
1460 }
1461
1462 #define IWL5000_UCODE_GET(item)                                         \
1463 static u32 iwl5000_ucode_get_##item(const struct iwl_ucode_header *ucode,\
1464                                     u32 api_ver)                        \
1465 {                                                                       \
1466         if (api_ver <= 2)                                               \
1467                 return le32_to_cpu(ucode->u.v1.item);                   \
1468         return le32_to_cpu(ucode->u.v2.item);                           \
1469 }
1470
1471 static u32 iwl5000_ucode_get_header_size(u32 api_ver)
1472 {
1473         if (api_ver <= 2)
1474                 return UCODE_HEADER_SIZE(1);
1475         return UCODE_HEADER_SIZE(2);
1476 }
1477
1478 static u32 iwl5000_ucode_get_build(const struct iwl_ucode_header *ucode,
1479                                    u32 api_ver)
1480 {
1481         if (api_ver <= 2)
1482                 return 0;
1483         return le32_to_cpu(ucode->u.v2.build);
1484 }
1485
1486 static u8 *iwl5000_ucode_get_data(const struct iwl_ucode_header *ucode,
1487                                   u32 api_ver)
1488 {
1489         if (api_ver <= 2)
1490                 return (u8 *) ucode->u.v1.data;
1491         return (u8 *) ucode->u.v2.data;
1492 }
1493
1494 IWL5000_UCODE_GET(inst_size);
1495 IWL5000_UCODE_GET(data_size);
1496 IWL5000_UCODE_GET(init_size);
1497 IWL5000_UCODE_GET(init_data_size);
1498 IWL5000_UCODE_GET(boot_size);
1499
1500 struct iwl_hcmd_ops iwl5000_hcmd = {
1501         .rxon_assoc = iwl5000_send_rxon_assoc,
1502         .commit_rxon = iwl_commit_rxon,
1503         .set_rxon_chain = iwl_set_rxon_chain,
1504 };
1505
1506 struct iwl_hcmd_utils_ops iwl5000_hcmd_utils = {
1507         .get_hcmd_size = iwl5000_get_hcmd_size,
1508         .build_addsta_hcmd = iwl5000_build_addsta_hcmd,
1509         .gain_computation = iwl5000_gain_computation,
1510         .chain_noise_reset = iwl5000_chain_noise_reset,
1511         .rts_tx_cmd_flag = iwl5000_rts_tx_cmd_flag,
1512         .calc_rssi = iwl5000_calc_rssi,
1513 };
1514
1515 struct iwl_ucode_ops iwl5000_ucode = {
1516         .get_header_size = iwl5000_ucode_get_header_size,
1517         .get_build = iwl5000_ucode_get_build,
1518         .get_inst_size = iwl5000_ucode_get_inst_size,
1519         .get_data_size = iwl5000_ucode_get_data_size,
1520         .get_init_size = iwl5000_ucode_get_init_size,
1521         .get_init_data_size = iwl5000_ucode_get_init_data_size,
1522         .get_boot_size = iwl5000_ucode_get_boot_size,
1523         .get_data = iwl5000_ucode_get_data,
1524 };
1525
1526 struct iwl_lib_ops iwl5000_lib = {
1527         .set_hw_params = iwl5000_hw_set_hw_params,
1528         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1529         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1530         .txq_set_sched = iwl5000_txq_set_sched,
1531         .txq_agg_enable = iwl5000_txq_agg_enable,
1532         .txq_agg_disable = iwl5000_txq_agg_disable,
1533         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1534         .txq_free_tfd = iwl_hw_txq_free_tfd,
1535         .txq_init = iwl_hw_tx_queue_init,
1536         .rx_handler_setup = iwl5000_rx_handler_setup,
1537         .setup_deferred_work = iwl5000_setup_deferred_work,
1538         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1539         .dump_nic_event_log = iwl_dump_nic_event_log,
1540         .dump_nic_error_log = iwl_dump_nic_error_log,
1541         .load_ucode = iwl5000_load_ucode,
1542         .init_alive_start = iwl5000_init_alive_start,
1543         .alive_notify = iwl5000_alive_notify,
1544         .send_tx_power = iwl5000_send_tx_power,
1545         .update_chain_flags = iwl_update_chain_flags,
1546         .apm_ops = {
1547                 .init = iwl5000_apm_init,
1548                 .reset = iwl5000_apm_reset,
1549                 .stop = iwl5000_apm_stop,
1550                 .config = iwl5000_nic_config,
1551                 .set_pwr_src = iwl_set_pwr_src,
1552         },
1553         .eeprom_ops = {
1554                 .regulatory_bands = {
1555                         EEPROM_5000_REG_BAND_1_CHANNELS,
1556                         EEPROM_5000_REG_BAND_2_CHANNELS,
1557                         EEPROM_5000_REG_BAND_3_CHANNELS,
1558                         EEPROM_5000_REG_BAND_4_CHANNELS,
1559                         EEPROM_5000_REG_BAND_5_CHANNELS,
1560                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1561                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1562                 },
1563                 .verify_signature  = iwlcore_eeprom_verify_signature,
1564                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1565                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1566                 .calib_version  = iwl5000_eeprom_calib_version,
1567                 .query_addr = iwl5000_eeprom_query_addr,
1568         },
1569         .post_associate = iwl_post_associate,
1570         .isr = iwl_isr_ict,
1571         .config_ap = iwl_config_ap,
1572         .temp_ops = {
1573                 .temperature = iwl5000_temperature,
1574                 .set_ct_kill = iwl5000_set_ct_threshold,
1575          },
1576 };
1577
1578 static struct iwl_lib_ops iwl5150_lib = {
1579         .set_hw_params = iwl5000_hw_set_hw_params,
1580         .txq_update_byte_cnt_tbl = iwl5000_txq_update_byte_cnt_tbl,
1581         .txq_inval_byte_cnt_tbl = iwl5000_txq_inval_byte_cnt_tbl,
1582         .txq_set_sched = iwl5000_txq_set_sched,
1583         .txq_agg_enable = iwl5000_txq_agg_enable,
1584         .txq_agg_disable = iwl5000_txq_agg_disable,
1585         .txq_attach_buf_to_tfd = iwl_hw_txq_attach_buf_to_tfd,
1586         .txq_free_tfd = iwl_hw_txq_free_tfd,
1587         .txq_init = iwl_hw_tx_queue_init,
1588         .rx_handler_setup = iwl5000_rx_handler_setup,
1589         .setup_deferred_work = iwl5000_setup_deferred_work,
1590         .is_valid_rtc_data_addr = iwl5000_hw_valid_rtc_data_addr,
1591         .dump_nic_event_log = iwl_dump_nic_event_log,
1592         .dump_nic_error_log = iwl_dump_nic_error_log,
1593         .load_ucode = iwl5000_load_ucode,
1594         .init_alive_start = iwl5000_init_alive_start,
1595         .alive_notify = iwl5000_alive_notify,
1596         .send_tx_power = iwl5000_send_tx_power,
1597         .update_chain_flags = iwl_update_chain_flags,
1598         .apm_ops = {
1599                 .init = iwl5000_apm_init,
1600                 .reset = iwl5000_apm_reset,
1601                 .stop = iwl5000_apm_stop,
1602                 .config = iwl5000_nic_config,
1603                 .set_pwr_src = iwl_set_pwr_src,
1604         },
1605         .eeprom_ops = {
1606                 .regulatory_bands = {
1607                         EEPROM_5000_REG_BAND_1_CHANNELS,
1608                         EEPROM_5000_REG_BAND_2_CHANNELS,
1609                         EEPROM_5000_REG_BAND_3_CHANNELS,
1610                         EEPROM_5000_REG_BAND_4_CHANNELS,
1611                         EEPROM_5000_REG_BAND_5_CHANNELS,
1612                         EEPROM_5000_REG_BAND_24_HT40_CHANNELS,
1613                         EEPROM_5000_REG_BAND_52_HT40_CHANNELS
1614                 },
1615                 .verify_signature  = iwlcore_eeprom_verify_signature,
1616                 .acquire_semaphore = iwlcore_eeprom_acquire_semaphore,
1617                 .release_semaphore = iwlcore_eeprom_release_semaphore,
1618                 .calib_version  = iwl5000_eeprom_calib_version,
1619                 .query_addr = iwl5000_eeprom_query_addr,
1620         },
1621         .post_associate = iwl_post_associate,
1622         .isr = iwl_isr_ict,
1623         .config_ap = iwl_config_ap,
1624         .temp_ops = {
1625                 .temperature = iwl5150_temperature,
1626                 .set_ct_kill = iwl5150_set_ct_threshold,
1627          },
1628 };
1629
1630 struct iwl_ops iwl5000_ops = {
1631         .ucode = &iwl5000_ucode,
1632         .lib = &iwl5000_lib,
1633         .hcmd = &iwl5000_hcmd,
1634         .utils = &iwl5000_hcmd_utils,
1635 };
1636
1637 static struct iwl_ops iwl5150_ops = {
1638         .ucode = &iwl5000_ucode,
1639         .lib = &iwl5150_lib,
1640         .hcmd = &iwl5000_hcmd,
1641         .utils = &iwl5000_hcmd_utils,
1642 };
1643
1644 struct iwl_mod_params iwl50_mod_params = {
1645         .num_of_queues = IWL50_NUM_QUEUES,
1646         .num_of_ampdu_queues = IWL50_NUM_AMPDU_QUEUES,
1647         .amsdu_size_8K = 1,
1648         .restart_fw = 1,
1649         /* the rest are 0 by default */
1650 };
1651
1652
1653 struct iwl_cfg iwl5300_agn_cfg = {
1654         .name = "5300AGN",
1655         .fw_name_pre = IWL5000_FW_PRE,
1656         .ucode_api_max = IWL5000_UCODE_API_MAX,
1657         .ucode_api_min = IWL5000_UCODE_API_MIN,
1658         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1659         .ops = &iwl5000_ops,
1660         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1661         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1662         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1663         .mod_params = &iwl50_mod_params,
1664         .valid_tx_ant = ANT_ABC,
1665         .valid_rx_ant = ANT_ABC,
1666         .need_pll_cfg = true,
1667         .ht_greenfield_support = true,
1668 };
1669
1670 struct iwl_cfg iwl5100_bg_cfg = {
1671         .name = "5100BG",
1672         .fw_name_pre = IWL5000_FW_PRE,
1673         .ucode_api_max = IWL5000_UCODE_API_MAX,
1674         .ucode_api_min = IWL5000_UCODE_API_MIN,
1675         .sku = IWL_SKU_G,
1676         .ops = &iwl5000_ops,
1677         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1678         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1679         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1680         .mod_params = &iwl50_mod_params,
1681         .valid_tx_ant = ANT_B,
1682         .valid_rx_ant = ANT_AB,
1683         .need_pll_cfg = true,
1684         .ht_greenfield_support = true,
1685 };
1686
1687 struct iwl_cfg iwl5100_abg_cfg = {
1688         .name = "5100ABG",
1689         .fw_name_pre = IWL5000_FW_PRE,
1690         .ucode_api_max = IWL5000_UCODE_API_MAX,
1691         .ucode_api_min = IWL5000_UCODE_API_MIN,
1692         .sku = IWL_SKU_A|IWL_SKU_G,
1693         .ops = &iwl5000_ops,
1694         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1695         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1696         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1697         .mod_params = &iwl50_mod_params,
1698         .valid_tx_ant = ANT_B,
1699         .valid_rx_ant = ANT_AB,
1700         .need_pll_cfg = true,
1701         .ht_greenfield_support = true,
1702 };
1703
1704 struct iwl_cfg iwl5100_agn_cfg = {
1705         .name = "5100AGN",
1706         .fw_name_pre = IWL5000_FW_PRE,
1707         .ucode_api_max = IWL5000_UCODE_API_MAX,
1708         .ucode_api_min = IWL5000_UCODE_API_MIN,
1709         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1710         .ops = &iwl5000_ops,
1711         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1712         .eeprom_ver = EEPROM_5000_EEPROM_VERSION,
1713         .eeprom_calib_ver = EEPROM_5000_TX_POWER_VERSION,
1714         .mod_params = &iwl50_mod_params,
1715         .valid_tx_ant = ANT_B,
1716         .valid_rx_ant = ANT_AB,
1717         .need_pll_cfg = true,
1718         .ht_greenfield_support = true,
1719 };
1720
1721 struct iwl_cfg iwl5350_agn_cfg = {
1722         .name = "5350AGN",
1723         .fw_name_pre = IWL5000_FW_PRE,
1724         .ucode_api_max = IWL5000_UCODE_API_MAX,
1725         .ucode_api_min = IWL5000_UCODE_API_MIN,
1726         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1727         .ops = &iwl5000_ops,
1728         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1729         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1730         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1731         .mod_params = &iwl50_mod_params,
1732         .valid_tx_ant = ANT_ABC,
1733         .valid_rx_ant = ANT_ABC,
1734         .need_pll_cfg = true,
1735         .ht_greenfield_support = true,
1736 };
1737
1738 struct iwl_cfg iwl5150_agn_cfg = {
1739         .name = "5150AGN",
1740         .fw_name_pre = IWL5150_FW_PRE,
1741         .ucode_api_max = IWL5150_UCODE_API_MAX,
1742         .ucode_api_min = IWL5150_UCODE_API_MIN,
1743         .sku = IWL_SKU_A|IWL_SKU_G|IWL_SKU_N,
1744         .ops = &iwl5150_ops,
1745         .eeprom_size = IWL_5000_EEPROM_IMG_SIZE,
1746         .eeprom_ver = EEPROM_5050_EEPROM_VERSION,
1747         .eeprom_calib_ver = EEPROM_5050_TX_POWER_VERSION,
1748         .mod_params = &iwl50_mod_params,
1749         .valid_tx_ant = ANT_A,
1750         .valid_rx_ant = ANT_AB,
1751         .need_pll_cfg = true,
1752         .ht_greenfield_support = true,
1753 };
1754
1755 MODULE_FIRMWARE(IWL5000_MODULE_FIRMWARE(IWL5000_UCODE_API_MAX));
1756 MODULE_FIRMWARE(IWL5150_MODULE_FIRMWARE(IWL5150_UCODE_API_MAX));
1757
1758 module_param_named(swcrypto50, iwl50_mod_params.sw_crypto, bool, 0444);
1759 MODULE_PARM_DESC(swcrypto50,
1760                   "using software crypto engine (default 0 [hardware])\n");
1761 module_param_named(queues_num50, iwl50_mod_params.num_of_queues, int, 0444);
1762 MODULE_PARM_DESC(queues_num50, "number of hw queues in 50xx series");
1763 module_param_named(11n_disable50, iwl50_mod_params.disable_11n, int, 0444);
1764 MODULE_PARM_DESC(11n_disable50, "disable 50XX 11n functionality");
1765 module_param_named(amsdu_size_8K50, iwl50_mod_params.amsdu_size_8K, int, 0444);
1766 MODULE_PARM_DESC(amsdu_size_8K50, "enable 8K amsdu size in 50XX series");
1767 module_param_named(fw_restart50, iwl50_mod_params.restart_fw, int, 0444);
1768 MODULE_PARM_DESC(fw_restart50, "restart firmware in case of error");