SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/i2c/busses/i2c-mpc.c

   1 /*
   2  * (C) Copyright 2003-2004
   3  * Humboldt Solutions Ltd, adrian@humboldt.co.uk.
   4
   5  * This is a combined i2c adapter and algorithm driver for the
   6  * MPC107/Tsi107 PowerPC northbridge and processors that include
   7  * the same I2C unit (8240, 8245, 85xx).
   8  *
   9  * Release 0.8
  10  *
  11  * This file is licensed under the terms of the GNU General Public
  12  * License version 2. This program is licensed "as is" without any
  13  * warranty of any kind, whether express or implied.
  14  */
  15
  16 #include <linux/kernel.h>
  17 #include <linux/module.h>
  18 #include <linux/sched.h>
  19 #include <linux/init.h>
  20 #include <linux/of_platform.h>
  21 #include <linux/of_i2c.h>
  22 #include <linux/slab.h>
  23
  24 #include <linux/io.h>
  25 #include <linux/fsl_devices.h>
  26 #include <linux/i2c.h>
  27 #include <linux/interrupt.h>
  28 #include <linux/delay.h>
  29
  30 #include <asm/mpc52xx.h>
  31 #include <sysdev/fsl_soc.h>
  32
  33 #define DRV_NAME "mpc-i2c"
  34
  35 #define MPC_I2C_CLOCK_LEGACY   0
  36 #define MPC_I2C_CLOCK_PRESERVE (~0U)
  37
  38 #define MPC_I2C_FDR   0x04
  39 #define MPC_I2C_CR    0x08
  40 #define MPC_I2C_SR    0x0c
  41 #define MPC_I2C_DR    0x10
  42 #define MPC_I2C_DFSRR 0x14
  43
  44 #define CCR_MEN  0x80
  45 #define CCR_MIEN 0x40
  46 #define CCR_MSTA 0x20
  47 #define CCR_MTX  0x10
  48 #define CCR_TXAK 0x08
  49 #define CCR_RSTA 0x04
  50
  51 #define CSR_MCF  0x80
  52 #define CSR_MAAS 0x40
  53 #define CSR_MBB  0x20
  54 #define CSR_MAL  0x10
  55 #define CSR_SRW  0x04
  56 #define CSR_MIF  0x02
  57 #define CSR_RXAK 0x01
  58
  59 struct mpc_i2c {
  60         struct device *dev;
  61         void __iomem *base;
  62         u32 interrupt;
  63         wait_queue_head_t queue;
  64         struct i2c_adapter adap;
  65         int irq;
  66 };
  67
  68 struct mpc_i2c_divider {
  69         u16 divider;
  70         u16 fdr;        /* including dfsrr */
  71 };
  72
  73 struct mpc_i2c_data {
  74         void (*setup)(struct device_node *node, struct mpc_i2c *i2c,
  75                       u32 clock, u32 prescaler);
  76         u32 prescaler;
  77 };
  78
  79 static inline void writeccr(struct mpc_i2c *i2c, u32 x)
  80 {
  81         writeb(x, i2c->base + MPC_I2C_CR);
  82 }
  83
  84 static irqreturn_t mpc_i2c_isr(int irq, void *dev_id)
  85 {
  86         struct mpc_i2c *i2c = dev_id;
  87         if (readb(i2c->base + MPC_I2C_SR) & CSR_MIF) {
  88                 /* Read again to allow register to stabilise */
  89                 i2c->interrupt = readb(i2c->base + MPC_I2C_SR);
  90                 writeb(0, i2c->base + MPC_I2C_SR);
  91                 wake_up(&i2c->queue);
  92         }
  93         return IRQ_HANDLED;
  94 }
  95
  96 /* Sometimes 9th clock pulse isn't generated, and slave doesn't release
  97  * the bus, because it wants to send ACK.
  98  * Following sequence of enabling/disabling and sending start/stop generates
  99  * the pulse, so it's all OK.
 100  */
 101 static void mpc_i2c_fixup(struct mpc_i2c *i2c)
 102 {
 103         writeccr(i2c, 0);
 104         udelay(30);
 105         writeccr(i2c, CCR_MEN);
 106         udelay(30);
 107         writeccr(i2c, CCR_MSTA | CCR_MTX);
 108         udelay(30);
 109         writeccr(i2c, CCR_MSTA | CCR_MTX | CCR_MEN);
 110         udelay(30);
 111         writeccr(i2c, CCR_MEN);
 112         udelay(30);
 113 }
 114
 115 static int i2c_wait(struct mpc_i2c *i2c, unsigned timeout, int writing)
 116 {
 117         unsigned long orig_jiffies = jiffies;
 118         u32 x;
 119         int result = 0;
 120
 121         if (i2c->irq == NO_IRQ) {
 122                 while (!(readb(i2c->base + MPC_I2C_SR) & CSR_MIF)) {
 123                         schedule();
 124                         if (time_after(jiffies, orig_jiffies + timeout)) {
 125                                 dev_dbg(i2c->dev, "timeout\n");
 126                                 writeccr(i2c, 0);
 127                                 result = -EIO;
 128                                 break;
 129                         }
 130                 }
 131                 x = readb(i2c->base + MPC_I2C_SR);
 132                 writeb(0, i2c->base + MPC_I2C_SR);
 133         } else {
 134                 /* Interrupt mode */
 135                 result = wait_event_timeout(i2c->queue,
 136                         (i2c->interrupt & CSR_MIF), timeout);
 137
 138                 if (unlikely(!(i2c->interrupt & CSR_MIF))) {
 139                         dev_dbg(i2c->dev, "wait timeout\n");
 140                         writeccr(i2c, 0);
 141                         result = -ETIMEDOUT;
 142                 }
 143
 144                 x = i2c->interrupt;
 145                 i2c->interrupt = 0;
 146         }
 147
 148         if (result < 0)
 149                 return result;
 150
 151         if (!(x & CSR_MCF)) {
 152                 dev_dbg(i2c->dev, "unfinished\n");
 153                 return -EIO;
 154         }
 155
 156         if (x & CSR_MAL) {
 157                 dev_dbg(i2c->dev, "MAL\n");
 158                 return -EIO;
 159         }
 160
 161         if (writing && (x & CSR_RXAK)) {
 162                 dev_dbg(i2c->dev, "No RXAK\n");
 163                 /* generate stop */
 164                 writeccr(i2c, CCR_MEN);
 165                 return -EIO;
 166         }
 167         return 0;
 168 }
 169
 170 #if defined(CONFIG_PPC_MPC52xx) || defined(CONFIG_PPC_MPC512x)
 171 static const struct mpc_i2c_divider mpc_i2c_dividers_52xx[] __devinitconst = {
 172         {20, 0x20}, {22, 0x21}, {24, 0x22}, {26, 0x23},
 173         {28, 0x24}, {30, 0x01}, {32, 0x25}, {34, 0x02},
 174         {36, 0x26}, {40, 0x27}, {44, 0x04}, {48, 0x28},
 175         {52, 0x63}, {56, 0x29}, {60, 0x41}, {64, 0x2a},
 176         {68, 0x07}, {72, 0x2b}, {80, 0x2c}, {88, 0x09},
 177         {96, 0x2d}, {104, 0x0a}, {112, 0x2e}, {120, 0x81},
 178         {128, 0x2f}, {136, 0x47}, {144, 0x0c}, {160, 0x30},
 179         {176, 0x49}, {192, 0x31}, {208, 0x4a}, {224, 0x32},
 180         {240, 0x0f}, {256, 0x33}, {272, 0x87}, {288, 0x10},
 181         {320, 0x34}, {352, 0x89}, {384, 0x35}, {416, 0x8a},
 182         {448, 0x36}, {480, 0x13}, {512, 0x37}, {576, 0x14},
 183         {640, 0x38}, {768, 0x39}, {896, 0x3a}, {960, 0x17},
 184         {1024, 0x3b}, {1152, 0x18}, {1280, 0x3c}, {1536, 0x3d},
 185         {1792, 0x3e}, {1920, 0x1b}, {2048, 0x3f}, {2304, 0x1c},
 186         {2560, 0x1d}, {3072, 0x1e}, {3584, 0x7e}, {3840, 0x1f},
 187         {4096, 0x7f}, {4608, 0x5c}, {5120, 0x5d}, {6144, 0x5e},
 188         {7168, 0xbe}, {7680, 0x5f}, {8192, 0xbf}, {9216, 0x9c},
 189         {10240, 0x9d}, {12288, 0x9e}, {15360, 0x9f}
 190 };
 191
 192 static int __devinit mpc_i2c_get_fdr_52xx(struct device_node *node, u32 clock,
 193                                           int prescaler)
 194 {
 195         const struct mpc_i2c_divider *div = NULL;
 196         unsigned int pvr = mfspr(SPRN_PVR);
 197         u32 divider;
 198         int i;
 199
 200         if (clock == MPC_I2C_CLOCK_LEGACY)
 201                 return -EINVAL;
 202
 203         /* Determine divider value */
 204         divider = mpc5xxx_get_bus_frequency(node) / clock;
 205
 206         /*
 207          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 208          * is equal to or lower than the requested speed.
 209          */
 210         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_52xx); i++) {
 211                 div = &mpc_i2c_dividers_52xx[i];
 212                 /* Old MPC5200 rev A CPUs do not support the high bits */
 213                 if (div->fdr & 0xc0 && pvr == 0x80822011)
 214                         continue;
 215                 if (div->divider >= divider)
 216                         break;
 217         }
 218
 219         return div ? (int)div->fdr : -EINVAL;
 220 }
 221
 222 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
 223                                          struct mpc_i2c *i2c,
 224                                          u32 clock, u32 prescaler)
 225 {
 226         int ret, fdr;
 227
 228         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 229                 dev_dbg(i2c->dev, "using fdr %d\n",
 230                         readb(i2c->base + MPC_I2C_FDR));
 231                 return;
 232         }
 233
 234         ret = mpc_i2c_get_fdr_52xx(node, clock, prescaler);
 235         fdr = (ret >= 0) ? ret : 0x3f; /* backward compatibility */
 236
 237         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 238
 239         if (ret >= 0)
 240                 dev_info(i2c->dev, "clock %d Hz (fdr=%d)\n", clock, fdr);
 241 }
 242 #else /* !(CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x) */
 243 static void __devinit mpc_i2c_setup_52xx(struct device_node *node,
 244                                          struct mpc_i2c *i2c,
 245                                          u32 clock, u32 prescaler)
 246 {
 247 }
 248 #endif /* CONFIG_PPC_MPC52xx || CONFIG_PPC_MPC512x */
 249
 250 #ifdef CONFIG_PPC_MPC512x
 251 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
 252                                          struct mpc_i2c *i2c,
 253                                          u32 clock, u32 prescaler)
 254 {
 255         struct device_node *node_ctrl;
 256         void __iomem *ctrl;
 257         const u32 *pval;
 258         u32 idx;
 259
 260         /* Enable I2C interrupts for mpc5121 */
 261         node_ctrl = of_find_compatible_node(NULL, NULL,
 262                                             "fsl,mpc5121-i2c-ctrl");
 263         if (node_ctrl) {
 264                 ctrl = of_iomap(node_ctrl, 0);
 265                 if (ctrl) {
 266                         /* Interrupt enable bits for i2c-0/1/2: bit 24/26/28 */
 267                         pval = of_get_property(node, "reg", NULL);
 268                         idx = (*pval & 0xff) / 0x20;
 269                         setbits32(ctrl, 1 << (24 + idx * 2));
 270                         iounmap(ctrl);
 271                 }
 272                 of_node_put(node_ctrl);
 273         }
 274
 275         /* The clock setup for the 52xx works also fine for the 512x */
 276         mpc_i2c_setup_52xx(node, i2c, clock, prescaler);
 277 }
 278 #else /* CONFIG_PPC_MPC512x */
 279 static void __devinit mpc_i2c_setup_512x(struct device_node *node,
 280                                          struct mpc_i2c *i2c,
 281                                          u32 clock, u32 prescaler)
 282 {
 283 }
 284 #endif /* CONFIG_PPC_MPC512x */
 285
 286 #ifdef CONFIG_FSL_SOC
 287 static const struct mpc_i2c_divider mpc_i2c_dividers_8xxx[] __devinitconst = {
 288         {160, 0x0120}, {192, 0x0121}, {224, 0x0122}, {256, 0x0123},
 289         {288, 0x0100}, {320, 0x0101}, {352, 0x0601}, {384, 0x0102},
 290         {416, 0x0602}, {448, 0x0126}, {480, 0x0103}, {512, 0x0127},
 291         {544, 0x0b03}, {576, 0x0104}, {608, 0x1603}, {640, 0x0105},
 292         {672, 0x2003}, {704, 0x0b05}, {736, 0x2b03}, {768, 0x0106},
 293         {800, 0x3603}, {832, 0x0b06}, {896, 0x012a}, {960, 0x0107},
 294         {1024, 0x012b}, {1088, 0x1607}, {1152, 0x0108}, {1216, 0x2b07},
 295         {1280, 0x0109}, {1408, 0x1609}, {1536, 0x010a}, {1664, 0x160a},
 296         {1792, 0x012e}, {1920, 0x010b}, {2048, 0x012f}, {2176, 0x2b0b},
 297         {2304, 0x010c}, {2560, 0x010d}, {2816, 0x2b0d}, {3072, 0x010e},
 298         {3328, 0x2b0e}, {3584, 0x0132}, {3840, 0x010f}, {4096, 0x0133},
 299         {4608, 0x0110}, {5120, 0x0111}, {6144, 0x0112}, {7168, 0x0136},
 300         {7680, 0x0113}, {8192, 0x0137}, {9216, 0x0114}, {10240, 0x0115},
 301         {12288, 0x0116}, {14336, 0x013a}, {15360, 0x0117}, {16384, 0x013b},
 302         {18432, 0x0118}, {20480, 0x0119}, {24576, 0x011a}, {28672, 0x013e},
 303         {30720, 0x011b}, {32768, 0x013f}, {36864, 0x011c}, {40960, 0x011d},
 304         {49152, 0x011e}, {61440, 0x011f}
 305 };
 306
 307 static u32 __devinit mpc_i2c_get_sec_cfg_8xxx(void)
 308 {
 309         struct device_node *node = NULL;
 310         u32 __iomem *reg;
 311         u32 val = 0;
 312
 313         node = of_find_node_by_name(NULL, "global-utilities");
 314         if (node) {
 315                 const u32 *prop = of_get_property(node, "reg", NULL);
 316                 if (prop) {
 317                         /*
 318                          * Map and check POR Device Status Register 2
 319                          * (PORDEVSR2) at 0xE0014
 320                          */
 321                         reg = ioremap(get_immrbase() + *prop + 0x14, 0x4);
 322                         if (!reg)
 323                                 printk(KERN_ERR
 324                                        "Error: couldn't map PORDEVSR2\n");
 325                         else
 326                                 val = in_be32(reg) & 0x00000080; /* sec-cfg */
 327                         iounmap(reg);
 328                 }
 329         }
 330         if (node)
 331                 of_node_put(node);
 332
 333         return val;
 334 }
 335
 336 static int __devinit mpc_i2c_get_fdr_8xxx(struct device_node *node, u32 clock,
 337                                           u32 prescaler)
 338 {
 339         const struct mpc_i2c_divider *div = NULL;
 340         u32 divider;
 341         int i;
 342
 343         if (clock == MPC_I2C_CLOCK_LEGACY)
 344                 return -EINVAL;
 345
 346         /* Determine proper divider value */
 347         if (of_device_is_compatible(node, "fsl,mpc8544-i2c"))
 348                 prescaler = mpc_i2c_get_sec_cfg_8xxx() ? 3 : 2;
 349         if (!prescaler)
 350                 prescaler = 1;
 351
 352         divider = fsl_get_sys_freq() / clock / prescaler;
 353
 354         pr_debug("I2C: src_clock=%d clock=%d divider=%d\n",
 355                  fsl_get_sys_freq(), clock, divider);
 356
 357         /*
 358          * We want to choose an FDR/DFSR that generates an I2C bus speed that
 359          * is equal to or lower than the requested speed.
 360          */
 361         for (i = 0; i < ARRAY_SIZE(mpc_i2c_dividers_8xxx); i++) {
 362                 div = &mpc_i2c_dividers_8xxx[i];
 363                 if (div->divider >= divider)
 364                         break;
 365         }
 366
 367         return div ? (int)div->fdr : -EINVAL;
 368 }
 369
 370 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
 371                                          struct mpc_i2c *i2c,
 372                                          u32 clock, u32 prescaler)
 373 {
 374         int ret, fdr;
 375
 376         if (clock == MPC_I2C_CLOCK_PRESERVE) {
 377                 dev_dbg(i2c->dev, "using dfsrr %d, fdr %d\n",
 378                         readb(i2c->base + MPC_I2C_DFSRR),
 379                         readb(i2c->base + MPC_I2C_FDR));
 380                 return;
 381         }
 382
 383         ret = mpc_i2c_get_fdr_8xxx(node, clock, prescaler);
 384         fdr = (ret >= 0) ? ret : 0x1031; /* backward compatibility */
 385
 386         writeb(fdr & 0xff, i2c->base + MPC_I2C_FDR);
 387         writeb((fdr >> 8) & 0xff, i2c->base + MPC_I2C_DFSRR);
 388
 389         if (ret >= 0)
 390                 dev_info(i2c->dev, "clock %d Hz (dfsrr=%d fdr=%d)\n",
 391                          clock, fdr >> 8, fdr & 0xff);
 392 }
 393
 394 #else /* !CONFIG_FSL_SOC */
 395 static void __devinit mpc_i2c_setup_8xxx(struct device_node *node,
 396                                          struct mpc_i2c *i2c,
 397                                          u32 clock, u32 prescaler)
 398 {
 399 }
 400 #endif /* CONFIG_FSL_SOC */
 401
 402 static void mpc_i2c_start(struct mpc_i2c *i2c)
 403 {
 404         /* Clear arbitration */
 405         writeb(0, i2c->base + MPC_I2C_SR);
 406         /* Start with MEN */
 407         writeccr(i2c, CCR_MEN);
 408 }
 409
 410 static void mpc_i2c_stop(struct mpc_i2c *i2c)
 411 {
 412         writeccr(i2c, CCR_MEN);
 413 }
 414
 415 static int mpc_write(struct mpc_i2c *i2c, int target,
 416                      const u8 *data, int length, int restart)
 417 {
 418         int i, result;
 419         unsigned timeout = i2c->adap.timeout;
 420         u32 flags = restart ? CCR_RSTA : 0;
 421
 422         /* Start as master */
 423         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 424         /* Write target byte */
 425         writeb((target << 1), i2c->base + MPC_I2C_DR);
 426
 427         result = i2c_wait(i2c, timeout, 1);
 428         if (result < 0)
 429                 return result;
 430
 431         for (i = 0; i < length; i++) {
 432                 /* Write data byte */
 433                 writeb(data[i], i2c->base + MPC_I2C_DR);
 434
 435                 result = i2c_wait(i2c, timeout, 1);
 436                 if (result < 0)
 437                         return result;
 438         }
 439
 440         return 0;
 441 }
 442
 443 static int mpc_read(struct mpc_i2c *i2c, int target,
 444                     u8 *data, int length, int restart)
 445 {
 446         unsigned timeout = i2c->adap.timeout;
 447         int i, result;
 448         u32 flags = restart ? CCR_RSTA : 0;
 449
 450         /* Switch to read - restart */
 451         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX | flags);
 452         /* Write target address byte - this time with the read flag set */
 453         writeb((target << 1) | 1, i2c->base + MPC_I2C_DR);
 454
 455         result = i2c_wait(i2c, timeout, 1);
 456         if (result < 0)
 457                 return result;
 458
 459         if (length) {
 460                 if (length == 1)
 461                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 462                 else
 463                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA);
 464                 /* Dummy read */
 465                 readb(i2c->base + MPC_I2C_DR);
 466         }
 467
 468         for (i = 0; i < length; i++) {
 469                 result = i2c_wait(i2c, timeout, 0);
 470                 if (result < 0)
 471                         return result;
 472
 473                 /* Generate txack on next to last byte */
 474                 if (i == length - 2)
 475                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_TXAK);
 476                 /* Do not generate stop on last byte */
 477                 if (i == length - 1)
 478                         writeccr(i2c, CCR_MIEN | CCR_MEN | CCR_MSTA | CCR_MTX);
 479                 data[i] = readb(i2c->base + MPC_I2C_DR);
 480         }
 481
 482         return length;
 483 }
 484
 485 static int mpc_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 486 {
 487         struct i2c_msg *pmsg;
 488         int i;
 489         int ret = 0;
 490         unsigned long orig_jiffies = jiffies;
 491         struct mpc_i2c *i2c = i2c_get_adapdata(adap);
 492
 493         mpc_i2c_start(i2c);
 494
 495         /* Allow bus up to 1s to become not busy */
 496         while (readb(i2c->base + MPC_I2C_SR) & CSR_MBB) {
 497                 if (signal_pending(current)) {
 498                         dev_dbg(i2c->dev, "Interrupted\n");
 499                         writeccr(i2c, 0);
 500                         return -EINTR;
 501                 }
 502                 if (time_after(jiffies, orig_jiffies + HZ)) {
 503                         dev_dbg(i2c->dev, "timeout\n");
 504                         if (readb(i2c->base + MPC_I2C_SR) ==
 505                             (CSR_MCF | CSR_MBB | CSR_RXAK))
 506                                 mpc_i2c_fixup(i2c);
 507                         return -EIO;
 508                 }
 509                 schedule();
 510         }
 511
 512         for (i = 0; ret >= 0 && i < num; i++) {
 513                 pmsg = &msgs[i];
 514                 dev_dbg(i2c->dev,
 515                         "Doing %s %d bytes to 0x%02x - %d of %d messages\n",
 516                         pmsg->flags & I2C_M_RD ? "read" : "write",
 517                         pmsg->len, pmsg->addr, i + 1, num);
 518                 if (pmsg->flags & I2C_M_RD)
 519                         ret =
 520                             mpc_read(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 521                 else
 522                         ret =
 523                             mpc_write(i2c, pmsg->addr, pmsg->buf, pmsg->len, i);
 524         }
 525         mpc_i2c_stop(i2c);
 526         return (ret < 0) ? ret : num;
 527 }
 528
 529 static u32 mpc_functionality(struct i2c_adapter *adap)
 530 {
 531         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 532 }
 533
 534 static const struct i2c_algorithm mpc_algo = {
 535         .master_xfer = mpc_xfer,
 536         .functionality = mpc_functionality,
 537 };
 538
 539 static struct i2c_adapter mpc_ops = {
 540         .owner = THIS_MODULE,
 541         .name = "MPC adapter",
 542         .algo = &mpc_algo,
 543         .timeout = HZ,
 544 };
 545
 546 static int __devinit fsl_i2c_probe(struct of_device *op,
 547                                    const struct of_device_id *match)
 548 {
 549         struct mpc_i2c *i2c;
 550         const u32 *prop;
 551         u32 clock = MPC_I2C_CLOCK_LEGACY;
 552         int result = 0;
 553         int plen;
 554
 555         i2c = kzalloc(sizeof(*i2c), GFP_KERNEL);
 556         if (!i2c)
 557                 return -ENOMEM;
 558
 559         i2c->dev = &op->dev; /* for debug and error output */
 560
 561         init_waitqueue_head(&i2c->queue);
 562
 563         i2c->base = of_iomap(op->node, 0);
 564         if (!i2c->base) {
 565                 dev_err(i2c->dev, "failed to map controller\n");
 566                 result = -ENOMEM;
 567                 goto fail_map;
 568         }
 569
 570         i2c->irq = irq_of_parse_and_map(op->node, 0);
 571         if (i2c->irq != NO_IRQ) { /* i2c->irq = NO_IRQ implies polling */
 572                 result = request_irq(i2c->irq, mpc_i2c_isr,
 573                                      IRQF_SHARED, "i2c-mpc", i2c);
 574                 if (result < 0) {
 575                         dev_err(i2c->dev, "failed to attach interrupt\n");
 576                         goto fail_request;
 577                 }
 578         }
 579
 580         if (of_get_property(op->node, "fsl,preserve-clocking", NULL)) {
 581                 clock = MPC_I2C_CLOCK_PRESERVE;
 582         } else {
 583                 prop = of_get_property(op->node, "clock-frequency", &plen);
 584                 if (prop && plen == sizeof(u32))
 585                         clock = *prop;
 586         }
 587
 588         if (match->data) {
 589                 struct mpc_i2c_data *data = match->data;
 590                 data->setup(op->node, i2c, clock, data->prescaler);
 591         } else {
 592                 /* Backwards compatibility */
 593                 if (of_get_property(op->node, "dfsrr", NULL))
 594                         mpc_i2c_setup_8xxx(op->node, i2c, clock, 0);
 595         }
 596
 597         dev_set_drvdata(&op->dev, i2c);
 598
 599         i2c->adap = mpc_ops;
 600         i2c_set_adapdata(&i2c->adap, i2c);
 601         i2c->adap.dev.parent = &op->dev;
 602
 603         result = i2c_add_adapter(&i2c->adap);
 604         if (result < 0) {
 605                 dev_err(i2c->dev, "failed to add adapter\n");
 606                 goto fail_add;
 607         }
 608         of_register_i2c_devices(&i2c->adap, op->node);
 609
 610         return result;
 611
 612  fail_add:
 613         dev_set_drvdata(&op->dev, NULL);
 614         free_irq(i2c->irq, i2c);
 615  fail_request:
 616         irq_dispose_mapping(i2c->irq);
 617         iounmap(i2c->base);
 618  fail_map:
 619         kfree(i2c);
 620         return result;
 621 };
 622
 623 static int __devexit fsl_i2c_remove(struct of_device *op)
 624 {
 625         struct mpc_i2c *i2c = dev_get_drvdata(&op->dev);
 626
 627         i2c_del_adapter(&i2c->adap);
 628         dev_set_drvdata(&op->dev, NULL);
 629
 630         if (i2c->irq != NO_IRQ)
 631                 free_irq(i2c->irq, i2c);
 632
 633         irq_dispose_mapping(i2c->irq);
 634         iounmap(i2c->base);
 635         kfree(i2c);
 636         return 0;
 637 };
 638
 639 static struct mpc_i2c_data mpc_i2c_data_512x __devinitdata = {
 640         .setup = mpc_i2c_setup_512x,
 641 };
 642
 643 static struct mpc_i2c_data mpc_i2c_data_52xx __devinitdata = {
 644         .setup = mpc_i2c_setup_52xx,
 645 };
 646
 647 static struct mpc_i2c_data mpc_i2c_data_8313 __devinitdata = {
 648         .setup = mpc_i2c_setup_8xxx,
 649 };
 650
 651 static struct mpc_i2c_data mpc_i2c_data_8543 __devinitdata = {
 652         .setup = mpc_i2c_setup_8xxx,
 653         .prescaler = 2,
 654 };
 655
 656 static struct mpc_i2c_data mpc_i2c_data_8544 __devinitdata = {
 657         .setup = mpc_i2c_setup_8xxx,
 658         .prescaler = 3,
 659 };
 660
 661 static const struct of_device_id mpc_i2c_of_match[] = {
 662         {.compatible = "mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 663         {.compatible = "fsl,mpc5200b-i2c", .data = &mpc_i2c_data_52xx, },
 664         {.compatible = "fsl,mpc5200-i2c", .data = &mpc_i2c_data_52xx, },
 665         {.compatible = "fsl,mpc5121-i2c", .data = &mpc_i2c_data_512x, },
 666         {.compatible = "fsl,mpc8313-i2c", .data = &mpc_i2c_data_8313, },
 667         {.compatible = "fsl,mpc8543-i2c", .data = &mpc_i2c_data_8543, },
 668         {.compatible = "fsl,mpc8544-i2c", .data = &mpc_i2c_data_8544, },
 669         /* Backward compatibility */
 670         {.compatible = "fsl-i2c", },
 671         {},
 672 };
 673 MODULE_DEVICE_TABLE(of, mpc_i2c_of_match);
 674
 675 /* Structure for a device driver */
 676 static struct of_platform_driver mpc_i2c_driver = {
 677         .match_table    = mpc_i2c_of_match,
 678         .probe          = fsl_i2c_probe,
 679         .remove         = __devexit_p(fsl_i2c_remove),
 680         .driver         = {
 681                 .owner  = THIS_MODULE,
 682                 .name   = DRV_NAME,
 683         },
 684 };
 685
 686 static int __init fsl_i2c_init(void)
 687 {
 688         int rv;
 689
 690         rv = of_register_platform_driver(&mpc_i2c_driver);
 691         if (rv)
 692                 printk(KERN_ERR DRV_NAME
 693                        " of_register_platform_driver failed (%i)\n", rv);
 694         return rv;
 695 }
 696
 697 static void __exit fsl_i2c_exit(void)
 698 {
 699         of_unregister_platform_driver(&mpc_i2c_driver);
 700 }
 701
 702 module_init(fsl_i2c_init);
 703 module_exit(fsl_i2c_exit);
 704
 705 MODULE_AUTHOR("Adrian Cox <adrian@humboldt.co.uk>");
 706 MODULE_DESCRIPTION("I2C-Bus adapter for MPC107 bridge and "
 707                    "MPC824x/83xx/85xx/86xx/512x/52xx processors");
 708 MODULE_LICENSE("GPL");