SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/rv770.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/firmware.h>
  29 #include <linux/platform_device.h>
  30 #include "drmP.h"
  31 #include "radeon.h"
  32 #include "radeon_drm.h"
  33 #include "rv770d.h"
  34 #include "atom.h"
  35 #include "avivod.h"
  36
  37 #define R700_PFP_UCODE_SIZE 848
  38 #define R700_PM4_UCODE_SIZE 1360
  39
  40 static void rv770_gpu_init(struct radeon_device *rdev);
  41 void rv770_fini(struct radeon_device *rdev);
  42
  43
  44 /*
  45  * GART
  46  */
  47 int rv770_pcie_gart_enable(struct radeon_device *rdev)
  48 {
  49         u32 tmp;
  50         int r, i;
  51
  52         if (rdev->gart.table.vram.robj == NULL) {
  53                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
  54                 return -EINVAL;
  55         }
  56         r = radeon_gart_table_vram_pin(rdev);
  57         if (r)
  58                 return r;
  59         radeon_gart_restore(rdev);
  60         /* Setup L2 cache */
  61         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
  62                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
  63                                 EFFECTIVE_L2_QUEUE_SIZE(7));
  64         WREG32(VM_L2_CNTL2, 0);
  65         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
  66         /* Setup TLB control */
  67         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
  68                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
  69                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
  70                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
  71         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
  72         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
  73         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
  74         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
  75         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
  76         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
  77         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
  78         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
  79         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
  80         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
  81         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
  82                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
  83         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
  84                         (u32)(rdev->dummy_page.addr >> 12));
  85         for (i = 1; i < 7; i++)
  86                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
  87
  88         r600_pcie_gart_tlb_flush(rdev);
  89         rdev->gart.ready = true;
  90         return 0;
  91 }
  92
  93 void rv770_pcie_gart_disable(struct radeon_device *rdev)
  94 {
  95         u32 tmp;
  96         int i, r;
  97
  98         /* Disable all tables */
  99         for (i = 0; i < 7; i++)
 100                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 101
 102         /* Setup L2 cache */
 103         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 104                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 105         WREG32(VM_L2_CNTL2, 0);
 106         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 107         /* Setup TLB control */
 108         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 109         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 110         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 111         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 112         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 113         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 114         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 115         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 116         if (rdev->gart.table.vram.robj) {
 117                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 118                 if (likely(r == 0)) {
 119                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 120                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 121                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 122                 }
 123         }
 124 }
 125
 126 void rv770_pcie_gart_fini(struct radeon_device *rdev)
 127 {
 128         rv770_pcie_gart_disable(rdev);
 129         radeon_gart_table_vram_free(rdev);
 130         radeon_gart_fini(rdev);
 131 }
 132
 133
 134 void rv770_agp_enable(struct radeon_device *rdev)
 135 {
 136         u32 tmp;
 137         int i;
 138
 139         /* Setup L2 cache */
 140         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 141                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 142                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 143         WREG32(VM_L2_CNTL2, 0);
 144         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 145         /* Setup TLB control */
 146         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 147                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 148                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 149                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 150         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 151         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 152         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 153         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 154         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 155         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 156         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 157         for (i = 0; i < 7; i++)
 158                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 159 }
 160
 161 static void rv770_mc_program(struct radeon_device *rdev)
 162 {
 163         struct rv515_mc_save save;
 164         u32 tmp;
 165         int i, j;
 166
 167         /* Initialize HDP */
 168         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 169                 WREG32((0x2c14 + j), 0x00000000);
 170                 WREG32((0x2c18 + j), 0x00000000);
 171                 WREG32((0x2c1c + j), 0x00000000);
 172                 WREG32((0x2c20 + j), 0x00000000);
 173                 WREG32((0x2c24 + j), 0x00000000);
 174         }
 175         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 176
 177         rv515_mc_stop(rdev, &save);
 178         if (r600_mc_wait_for_idle(rdev)) {
 179                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 180         }
 181         /* Lockout access through VGA aperture*/
 182         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 183         /* Update configuration */
 184         if (rdev->flags & RADEON_IS_AGP) {
 185                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 186                         /* VRAM before AGP */
 187                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 188                                 rdev->mc.vram_start >> 12);
 189                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 190                                 rdev->mc.gtt_end >> 12);
 191                 } else {
 192                         /* VRAM after AGP */
 193                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 194                                 rdev->mc.gtt_start >> 12);
 195                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 196                                 rdev->mc.vram_end >> 12);
 197                 }
 198         } else {
 199                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 200                         rdev->mc.vram_start >> 12);
 201                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 202                         rdev->mc.vram_end >> 12);
 203         }
 204         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 205         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 206         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 207         WREG32(MC_VM_FB_LOCATION, tmp);
 208         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 209         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 210         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 211         if (rdev->flags & RADEON_IS_AGP) {
 212                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 213                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 214                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 215         } else {
 216                 WREG32(MC_VM_AGP_BASE, 0);
 217                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 218                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 219         }
 220         if (r600_mc_wait_for_idle(rdev)) {
 221                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 222         }
 223         rv515_mc_resume(rdev, &save);
 224         /* we need to own VRAM, so turn off the VGA renderer here
 225          * to stop it overwriting our objects */
 226         rv515_vga_render_disable(rdev);
 227 }
 228
 229
 230 /*
 231  * CP.
 232  */
 233 void r700_cp_stop(struct radeon_device *rdev)
 234 {
 235         WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT));
 236 }
 237
 238
 239 static int rv770_cp_load_microcode(struct radeon_device *rdev)
 240 {
 241         const __be32 *fw_data;
 242         int i;
 243
 244         if (!rdev->me_fw || !rdev->pfp_fw)
 245                 return -EINVAL;
 246
 247         r700_cp_stop(rdev);
 248         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 249
 250         /* Reset cp */
 251         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
 252         RREG32(GRBM_SOFT_RESET);
 253         mdelay(15);
 254         WREG32(GRBM_SOFT_RESET, 0);
 255
 256         fw_data = (const __be32 *)rdev->pfp_fw->data;
 257         WREG32(CP_PFP_UCODE_ADDR, 0);
 258         for (i = 0; i < R700_PFP_UCODE_SIZE; i++)
 259                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 260         WREG32(CP_PFP_UCODE_ADDR, 0);
 261
 262         fw_data = (const __be32 *)rdev->me_fw->data;
 263         WREG32(CP_ME_RAM_WADDR, 0);
 264         for (i = 0; i < R700_PM4_UCODE_SIZE; i++)
 265                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 266
 267         WREG32(CP_PFP_UCODE_ADDR, 0);
 268         WREG32(CP_ME_RAM_WADDR, 0);
 269         WREG32(CP_ME_RAM_RADDR, 0);
 270         return 0;
 271 }
 272
 273
 274 /*
 275  * Core functions
 276  */
 277 static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 278                                                 u32 num_backends,
 279                                                 u32 backend_disable_mask)
 280 {
 281         u32 backend_map = 0;
 282         u32 enabled_backends_mask;
 283         u32 enabled_backends_count;
 284         u32 cur_pipe;
 285         u32 swizzle_pipe[R7XX_MAX_PIPES];
 286         u32 cur_backend;
 287         u32 i;
 288
 289         if (num_tile_pipes > R7XX_MAX_PIPES)
 290                 num_tile_pipes = R7XX_MAX_PIPES;
 291         if (num_tile_pipes < 1)
 292                 num_tile_pipes = 1;
 293         if (num_backends > R7XX_MAX_BACKENDS)
 294                 num_backends = R7XX_MAX_BACKENDS;
 295         if (num_backends < 1)
 296                 num_backends = 1;
 297
 298         enabled_backends_mask = 0;
 299         enabled_backends_count = 0;
 300         for (i = 0; i < R7XX_MAX_BACKENDS; ++i) {
 301                 if (((backend_disable_mask >> i) & 1) == 0) {
 302                         enabled_backends_mask |= (1 << i);
 303                         ++enabled_backends_count;
 304                 }
 305                 if (enabled_backends_count == num_backends)
 306                         break;
 307         }
 308
 309         if (enabled_backends_count == 0) {
 310                 enabled_backends_mask = 1;
 311                 enabled_backends_count = 1;
 312         }
 313
 314         if (enabled_backends_count != num_backends)
 315                 num_backends = enabled_backends_count;
 316
 317         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES);
 318         switch (num_tile_pipes) {
 319         case 1:
 320                 swizzle_pipe[0] = 0;
 321                 break;
 322         case 2:
 323                 swizzle_pipe[0] = 0;
 324                 swizzle_pipe[1] = 1;
 325                 break;
 326         case 3:
 327                 swizzle_pipe[0] = 0;
 328                 swizzle_pipe[1] = 2;
 329                 swizzle_pipe[2] = 1;
 330                 break;
 331         case 4:
 332                 swizzle_pipe[0] = 0;
 333                 swizzle_pipe[1] = 2;
 334                 swizzle_pipe[2] = 3;
 335                 swizzle_pipe[3] = 1;
 336                 break;
 337         case 5:
 338                 swizzle_pipe[0] = 0;
 339                 swizzle_pipe[1] = 2;
 340                 swizzle_pipe[2] = 4;
 341                 swizzle_pipe[3] = 1;
 342                 swizzle_pipe[4] = 3;
 343                 break;
 344         case 6:
 345                 swizzle_pipe[0] = 0;
 346                 swizzle_pipe[1] = 2;
 347                 swizzle_pipe[2] = 4;
 348                 swizzle_pipe[3] = 5;
 349                 swizzle_pipe[4] = 3;
 350                 swizzle_pipe[5] = 1;
 351                 break;
 352         case 7:
 353                 swizzle_pipe[0] = 0;
 354                 swizzle_pipe[1] = 2;
 355                 swizzle_pipe[2] = 4;
 356                 swizzle_pipe[3] = 6;
 357                 swizzle_pipe[4] = 3;
 358                 swizzle_pipe[5] = 1;
 359                 swizzle_pipe[6] = 5;
 360                 break;
 361         case 8:
 362                 swizzle_pipe[0] = 0;
 363                 swizzle_pipe[1] = 2;
 364                 swizzle_pipe[2] = 4;
 365                 swizzle_pipe[3] = 6;
 366                 swizzle_pipe[4] = 3;
 367                 swizzle_pipe[5] = 1;
 368                 swizzle_pipe[6] = 7;
 369                 swizzle_pipe[7] = 5;
 370                 break;
 371         }
 372
 373         cur_backend = 0;
 374         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 375                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 376                         cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 377
 378                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 379
 380                 cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS;
 381         }
 382
 383         return backend_map;
 384 }
 385
 386 static void rv770_gpu_init(struct radeon_device *rdev)
 387 {
 388         int i, j, num_qd_pipes;
 389         u32 sx_debug_1;
 390         u32 smx_dc_ctl0;
 391         u32 num_gs_verts_per_thread;
 392         u32 vgt_gs_per_es;
 393         u32 gs_prim_buffer_depth = 0;
 394         u32 sq_ms_fifo_sizes;
 395         u32 sq_config;
 396         u32 sq_thread_resource_mgmt;
 397         u32 hdp_host_path_cntl;
 398         u32 sq_dyn_gpr_size_simd_ab_0;
 399         u32 backend_map;
 400         u32 gb_tiling_config = 0;
 401         u32 cc_rb_backend_disable = 0;
 402         u32 cc_gc_shader_pipe_config = 0;
 403         u32 mc_arb_ramcfg;
 404         u32 db_debug4;
 405
 406         /* setup chip specs */
 407         switch (rdev->family) {
 408         case CHIP_RV770:
 409                 rdev->config.rv770.max_pipes = 4;
 410                 rdev->config.rv770.max_tile_pipes = 8;
 411                 rdev->config.rv770.max_simds = 10;
 412                 rdev->config.rv770.max_backends = 4;
 413                 rdev->config.rv770.max_gprs = 256;
 414                 rdev->config.rv770.max_threads = 248;
 415                 rdev->config.rv770.max_stack_entries = 512;
 416                 rdev->config.rv770.max_hw_contexts = 8;
 417                 rdev->config.rv770.max_gs_threads = 16 * 2;
 418                 rdev->config.rv770.sx_max_export_size = 128;
 419                 rdev->config.rv770.sx_max_export_pos_size = 16;
 420                 rdev->config.rv770.sx_max_export_smx_size = 112;
 421                 rdev->config.rv770.sq_num_cf_insts = 2;
 422
 423                 rdev->config.rv770.sx_num_of_sets = 7;
 424                 rdev->config.rv770.sc_prim_fifo_size = 0xF9;
 425                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 426                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 427                 break;
 428         case CHIP_RV730:
 429                 rdev->config.rv770.max_pipes = 2;
 430                 rdev->config.rv770.max_tile_pipes = 4;
 431                 rdev->config.rv770.max_simds = 8;
 432                 rdev->config.rv770.max_backends = 2;
 433                 rdev->config.rv770.max_gprs = 128;
 434                 rdev->config.rv770.max_threads = 248;
 435                 rdev->config.rv770.max_stack_entries = 256;
 436                 rdev->config.rv770.max_hw_contexts = 8;
 437                 rdev->config.rv770.max_gs_threads = 16 * 2;
 438                 rdev->config.rv770.sx_max_export_size = 256;
 439                 rdev->config.rv770.sx_max_export_pos_size = 32;
 440                 rdev->config.rv770.sx_max_export_smx_size = 224;
 441                 rdev->config.rv770.sq_num_cf_insts = 2;
 442
 443                 rdev->config.rv770.sx_num_of_sets = 7;
 444                 rdev->config.rv770.sc_prim_fifo_size = 0xf9;
 445                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 446                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 447                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 448                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 449                         rdev->config.rv770.sx_max_export_smx_size += 16;
 450                 }
 451                 break;
 452         case CHIP_RV710:
 453                 rdev->config.rv770.max_pipes = 2;
 454                 rdev->config.rv770.max_tile_pipes = 2;
 455                 rdev->config.rv770.max_simds = 2;
 456                 rdev->config.rv770.max_backends = 1;
 457                 rdev->config.rv770.max_gprs = 256;
 458                 rdev->config.rv770.max_threads = 192;
 459                 rdev->config.rv770.max_stack_entries = 256;
 460                 rdev->config.rv770.max_hw_contexts = 4;
 461                 rdev->config.rv770.max_gs_threads = 8 * 2;
 462                 rdev->config.rv770.sx_max_export_size = 128;
 463                 rdev->config.rv770.sx_max_export_pos_size = 16;
 464                 rdev->config.rv770.sx_max_export_smx_size = 112;
 465                 rdev->config.rv770.sq_num_cf_insts = 1;
 466
 467                 rdev->config.rv770.sx_num_of_sets = 7;
 468                 rdev->config.rv770.sc_prim_fifo_size = 0x40;
 469                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 470                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 471                 break;
 472         case CHIP_RV740:
 473                 rdev->config.rv770.max_pipes = 4;
 474                 rdev->config.rv770.max_tile_pipes = 4;
 475                 rdev->config.rv770.max_simds = 8;
 476                 rdev->config.rv770.max_backends = 4;
 477                 rdev->config.rv770.max_gprs = 256;
 478                 rdev->config.rv770.max_threads = 248;
 479                 rdev->config.rv770.max_stack_entries = 512;
 480                 rdev->config.rv770.max_hw_contexts = 8;
 481                 rdev->config.rv770.max_gs_threads = 16 * 2;
 482                 rdev->config.rv770.sx_max_export_size = 256;
 483                 rdev->config.rv770.sx_max_export_pos_size = 32;
 484                 rdev->config.rv770.sx_max_export_smx_size = 224;
 485                 rdev->config.rv770.sq_num_cf_insts = 2;
 486
 487                 rdev->config.rv770.sx_num_of_sets = 7;
 488                 rdev->config.rv770.sc_prim_fifo_size = 0x100;
 489                 rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30;
 490                 rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130;
 491
 492                 if (rdev->config.rv770.sx_max_export_pos_size > 16) {
 493                         rdev->config.rv770.sx_max_export_pos_size -= 16;
 494                         rdev->config.rv770.sx_max_export_smx_size += 16;
 495                 }
 496                 break;
 497         default:
 498                 break;
 499         }
 500
 501         /* Initialize HDP */
 502         j = 0;
 503         for (i = 0; i < 32; i++) {
 504                 WREG32((0x2c14 + j), 0x00000000);
 505                 WREG32((0x2c18 + j), 0x00000000);
 506                 WREG32((0x2c1c + j), 0x00000000);
 507                 WREG32((0x2c20 + j), 0x00000000);
 508                 WREG32((0x2c24 + j), 0x00000000);
 509                 j += 0x18;
 510         }
 511
 512         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 513
 514         /* setup tiling, simd, pipe config */
 515         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
 516
 517         switch (rdev->config.rv770.max_tile_pipes) {
 518         case 1:
 519                 gb_tiling_config |= PIPE_TILING(0);
 520                 rdev->config.rv770.tiling_npipes = 1;
 521                 break;
 522         case 2:
 523                 gb_tiling_config |= PIPE_TILING(1);
 524                 rdev->config.rv770.tiling_npipes = 2;
 525                 break;
 526         case 4:
 527                 gb_tiling_config |= PIPE_TILING(2);
 528                 rdev->config.rv770.tiling_npipes = 4;
 529                 break;
 530         case 8:
 531                 gb_tiling_config |= PIPE_TILING(3);
 532                 rdev->config.rv770.tiling_npipes = 8;
 533                 break;
 534         default:
 535                 break;
 536         }
 537
 538         if (rdev->family == CHIP_RV770)
 539                 gb_tiling_config |= BANK_TILING(1);
 540         else
 541                 gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
 542         rdev->config.rv770.tiling_nbanks = 4 << ((gb_tiling_config >> 4) & 0x3);
 543
 544         gb_tiling_config |= GROUP_SIZE(0);
 545         rdev->config.rv770.tiling_group_size = 256;
 546
 547         if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) {
 548                 gb_tiling_config |= ROW_TILING(3);
 549                 gb_tiling_config |= SAMPLE_SPLIT(3);
 550         } else {
 551                 gb_tiling_config |=
 552                         ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 553                 gb_tiling_config |=
 554                         SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT));
 555         }
 556
 557         gb_tiling_config |= BANK_SWAPS(1);
 558
 559         backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes,
 560                                                         rdev->config.rv770.max_backends,
 561                                                         (0xff << rdev->config.rv770.max_backends) & 0xff);
 562         gb_tiling_config |= BACKEND_MAP(backend_map);
 563
 564         cc_gc_shader_pipe_config =
 565                 INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK);
 566         cc_gc_shader_pipe_config |=
 567                 INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK);
 568
 569         cc_rb_backend_disable =
 570                 BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK);
 571
 572         WREG32(GB_TILING_CONFIG, gb_tiling_config);
 573         WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 574         WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff));
 575
 576         WREG32(CC_RB_BACKEND_DISABLE,      cc_rb_backend_disable);
 577         WREG32(CC_GC_SHADER_PIPE_CONFIG,   cc_gc_shader_pipe_config);
 578         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
 579
 580         WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable);
 581         WREG32(CGTS_SYS_TCC_DISABLE, 0);
 582         WREG32(CGTS_TCC_DISABLE, 0);
 583         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
 584         WREG32(CGTS_USER_TCC_DISABLE, 0);
 585
 586         num_qd_pipes =
 587                 R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK);
 588         WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK);
 589         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK);
 590
 591         /* set HW defaults for 3D engine */
 592         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
 593                                      ROQ_IB2_START(0x2b)));
 594
 595         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
 596
 597         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
 598                              SYNC_GRADIENT |
 599                              SYNC_WALKER |
 600                              SYNC_ALIGNER));
 601
 602         sx_debug_1 = RREG32(SX_DEBUG_1);
 603         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
 604         WREG32(SX_DEBUG_1, sx_debug_1);
 605
 606         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
 607         smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff);
 608         smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1);
 609         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
 610
 611         WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) |
 612                                GS_FLUSH_CTL(4) |
 613                                ACK_FLUSH_CTL(3) |
 614                                SYNC_FLUSH_CTL));
 615
 616         if (rdev->family == CHIP_RV770)
 617                 WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f));
 618         else {
 619                 db_debug4 = RREG32(DB_DEBUG4);
 620                 db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER;
 621                 WREG32(DB_DEBUG4, db_debug4);
 622         }
 623
 624         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) |
 625                                         POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) |
 626                                         SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1)));
 627
 628         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) |
 629                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) |
 630                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize)));
 631
 632         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 633
 634         WREG32(VGT_NUM_INSTANCES, 1);
 635
 636         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
 637
 638         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
 639
 640         WREG32(CP_PERFMON_CNTL, 0);
 641
 642         sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) |
 643                             DONE_FIFO_HIWATER(0xe0) |
 644                             ALU_UPDATE_FIFO_HIWATER(0x8));
 645         switch (rdev->family) {
 646         case CHIP_RV770:
 647                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1);
 648                 break;
 649         case CHIP_RV730:
 650         case CHIP_RV710:
 651         case CHIP_RV740:
 652         default:
 653                 sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4);
 654                 break;
 655         }
 656         WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes);
 657
 658         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
 659          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
 660          */
 661         sq_config = RREG32(SQ_CONFIG);
 662         sq_config &= ~(PS_PRIO(3) |
 663                        VS_PRIO(3) |
 664                        GS_PRIO(3) |
 665                        ES_PRIO(3));
 666         sq_config |= (DX9_CONSTS |
 667                       VC_ENABLE |
 668                       EXPORT_SRC_C |
 669                       PS_PRIO(0) |
 670                       VS_PRIO(1) |
 671                       GS_PRIO(2) |
 672                       ES_PRIO(3));
 673         if (rdev->family == CHIP_RV710)
 674                 /* no vertex cache */
 675                 sq_config &= ~VC_ENABLE;
 676
 677         WREG32(SQ_CONFIG, sq_config);
 678
 679         WREG32(SQ_GPR_RESOURCE_MGMT_1,  (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 680                                          NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) |
 681                                          NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2)));
 682
 683         WREG32(SQ_GPR_RESOURCE_MGMT_2,  (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) |
 684                                          NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64)));
 685
 686         sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) |
 687                                    NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) |
 688                                    NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8));
 689         if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads)
 690                 sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads);
 691         else
 692                 sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8);
 693         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
 694
 695         WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 696                                                      NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 697
 698         WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) |
 699                                                      NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4)));
 700
 701         sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 702                                      SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) |
 703                                      SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) |
 704                                      SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64));
 705
 706         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0);
 707         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0);
 708         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0);
 709         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0);
 710         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0);
 711         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0);
 712         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0);
 713         WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0);
 714
 715         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
 716                                           FORCE_EOV_MAX_REZ_CNT(255)));
 717
 718         if (rdev->family == CHIP_RV710)
 719                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) |
 720                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 721         else
 722                 WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) |
 723                                                 AUTO_INVLD_EN(ES_AND_GS_AUTO)));
 724
 725         switch (rdev->family) {
 726         case CHIP_RV770:
 727         case CHIP_RV730:
 728         case CHIP_RV740:
 729                 gs_prim_buffer_depth = 384;
 730                 break;
 731         case CHIP_RV710:
 732                 gs_prim_buffer_depth = 128;
 733                 break;
 734         default:
 735                 break;
 736         }
 737
 738         num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16;
 739         vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread;
 740         /* Max value for this is 256 */
 741         if (vgt_gs_per_es > 256)
 742                 vgt_gs_per_es = 256;
 743
 744         WREG32(VGT_ES_PER_GS, 128);
 745         WREG32(VGT_GS_PER_ES, vgt_gs_per_es);
 746         WREG32(VGT_GS_PER_VS, 2);
 747
 748         /* more default values. 2D/3D driver should adjust as needed */
 749         WREG32(VGT_GS_VERTEX_REUSE, 16);
 750         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
 751         WREG32(VGT_STRMOUT_EN, 0);
 752         WREG32(SX_MISC, 0);
 753         WREG32(PA_SC_MODE_CNTL, 0);
 754         WREG32(PA_SC_EDGERULE, 0xaaaaaaaa);
 755         WREG32(PA_SC_AA_CONFIG, 0);
 756         WREG32(PA_SC_CLIPRECT_RULE, 0xffff);
 757         WREG32(PA_SC_LINE_STIPPLE, 0);
 758         WREG32(SPI_INPUT_Z, 0);
 759         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
 760         WREG32(CB_COLOR7_FRAG, 0);
 761
 762         /* clear render buffer base addresses */
 763         WREG32(CB_COLOR0_BASE, 0);
 764         WREG32(CB_COLOR1_BASE, 0);
 765         WREG32(CB_COLOR2_BASE, 0);
 766         WREG32(CB_COLOR3_BASE, 0);
 767         WREG32(CB_COLOR4_BASE, 0);
 768         WREG32(CB_COLOR5_BASE, 0);
 769         WREG32(CB_COLOR6_BASE, 0);
 770         WREG32(CB_COLOR7_BASE, 0);
 771
 772         WREG32(TCP_CNTL, 0);
 773
 774         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
 775         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
 776
 777         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
 778
 779         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
 780                                           NUM_CLIP_SEQ(3)));
 781
 782 }
 783
 784 int rv770_mc_init(struct radeon_device *rdev)
 785 {
 786         fixed20_12 a;
 787         u32 tmp;
 788         int chansize, numchan;
 789
 790         /* Get VRAM informations */
 791         rdev->mc.vram_is_ddr = true;
 792         tmp = RREG32(MC_ARB_RAMCFG);
 793         if (tmp & CHANSIZE_OVERRIDE) {
 794                 chansize = 16;
 795         } else if (tmp & CHANSIZE_MASK) {
 796                 chansize = 64;
 797         } else {
 798                 chansize = 32;
 799         }
 800         tmp = RREG32(MC_SHARED_CHMAP);
 801         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 802         case 0:
 803         default:
 804                 numchan = 1;
 805                 break;
 806         case 1:
 807                 numchan = 2;
 808                 break;
 809         case 2:
 810                 numchan = 4;
 811                 break;
 812         case 3:
 813                 numchan = 8;
 814                 break;
 815         }
 816         rdev->mc.vram_width = numchan * chansize;
 817         /* Could aper size report 0 ? */
 818         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 819         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 820         /* Setup GPU memory space */
 821         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 822         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 823         /* FIXME remove this once we support unmappable VRAM */
 824         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 825                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 826                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 827         }
 828         r600_vram_gtt_location(rdev, &rdev->mc);
 829         /* FIXME: we should enforce default clock in case GPU is not in
 830          * default setup
 831          */
 832         a.full = rfixed_const(100);
 833         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 834         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 835         return 0;
 836 }
 837
 838 int rv770_gpu_reset(struct radeon_device *rdev)
 839 {
 840         /* FIXME: implement any rv770 specific bits */
 841         return r600_gpu_reset(rdev);
 842 }
 843
 844 static int rv770_startup(struct radeon_device *rdev)
 845 {
 846         int r;
 847
 848         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
 849                 r = r600_init_microcode(rdev);
 850                 if (r) {
 851                         DRM_ERROR("Failed to load firmware!\n");
 852                         return r;
 853                 }
 854         }
 855
 856         rv770_mc_program(rdev);
 857         if (rdev->flags & RADEON_IS_AGP) {
 858                 rv770_agp_enable(rdev);
 859         } else {
 860                 r = rv770_pcie_gart_enable(rdev);
 861                 if (r)
 862                         return r;
 863         }
 864         rv770_gpu_init(rdev);
 865         r = r600_blit_init(rdev);
 866         if (r) {
 867                 r600_blit_fini(rdev);
 868                 rdev->asic->copy = NULL;
 869                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
 870         }
 871         /* pin copy shader into vram */
 872         if (rdev->r600_blit.shader_obj) {
 873                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 874                 if (unlikely(r != 0))
 875                         return r;
 876                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
 877                                 &rdev->r600_blit.shader_gpu_addr);
 878                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 879                 if (r) {
 880                         DRM_ERROR("failed to pin blit object %d\n", r);
 881                         return r;
 882                 }
 883         }
 884         /* Enable IRQ */
 885         r = r600_irq_init(rdev);
 886         if (r) {
 887                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
 888                 radeon_irq_kms_fini(rdev);
 889                 return r;
 890         }
 891         r600_irq_set(rdev);
 892
 893         r = radeon_ring_init(rdev, rdev->cp.ring_size);
 894         if (r)
 895                 return r;
 896         r = rv770_cp_load_microcode(rdev);
 897         if (r)
 898                 return r;
 899         r = r600_cp_resume(rdev);
 900         if (r)
 901                 return r;
 902         /* write back buffer are not vital so don't worry about failure */
 903         r600_wb_enable(rdev);
 904         return 0;
 905 }
 906
 907 int rv770_resume(struct radeon_device *rdev)
 908 {
 909         int r;
 910
 911         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
 912          * posting will perform necessary task to bring back GPU into good
 913          * shape.
 914          */
 915         /* post card */
 916         atom_asic_init(rdev->mode_info.atom_context);
 917         /* Initialize clocks */
 918         r = radeon_clocks_init(rdev);
 919         if (r) {
 920                 return r;
 921         }
 922
 923         r = rv770_startup(rdev);
 924         if (r) {
 925                 DRM_ERROR("r600 startup failed on resume\n");
 926                 return r;
 927         }
 928
 929         r = r600_ib_test(rdev);
 930         if (r) {
 931                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
 932                 return r;
 933         }
 934         return r;
 935
 936 }
 937
 938 int rv770_suspend(struct radeon_device *rdev)
 939 {
 940         int r;
 941
 942         /* FIXME: we should wait for ring to be empty */
 943         r700_cp_stop(rdev);
 944         rdev->cp.ready = false;
 945         r600_irq_suspend(rdev);
 946         r600_wb_disable(rdev);
 947         rv770_pcie_gart_disable(rdev);
 948         /* unpin shaders bo */
 949         if (rdev->r600_blit.shader_obj) {
 950                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
 951                 if (likely(r == 0)) {
 952                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
 953                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
 954                 }
 955         }
 956         return 0;
 957 }
 958
 959 /* Plan is to move initialization in that function and use
 960  * helper function so that radeon_device_init pretty much
 961  * do nothing more than calling asic specific function. This
 962  * should also allow to remove a bunch of callback function
 963  * like vram_info.
 964  */
 965 int rv770_init(struct radeon_device *rdev)
 966 {
 967         int r;
 968
 969         r = radeon_dummy_page_init(rdev);
 970         if (r)
 971                 return r;
 972         /* This don't do much */
 973         r = radeon_gem_init(rdev);
 974         if (r)
 975                 return r;
 976         /* Read BIOS */
 977         if (!radeon_get_bios(rdev)) {
 978                 if (ASIC_IS_AVIVO(rdev))
 979                         return -EINVAL;
 980         }
 981         /* Must be an ATOMBIOS */
 982         if (!rdev->is_atom_bios) {
 983                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
 984                 return -EINVAL;
 985         }
 986         r = radeon_atombios_init(rdev);
 987         if (r)
 988                 return r;
 989         /* Post card if necessary */
 990         if (!r600_card_posted(rdev)) {
 991                 if (!rdev->bios) {
 992                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
 993                         return -EINVAL;
 994                 }
 995                 DRM_INFO("GPU not posted. posting now...\n");
 996                 atom_asic_init(rdev->mode_info.atom_context);
 997         }
 998         /* Initialize scratch registers */
 999         r600_scratch_init(rdev);
1000         /* Initialize surface registers */
1001         radeon_surface_init(rdev);
1002         /* Initialize clocks */
1003         radeon_get_clock_info(rdev->ddev);
1004         r = radeon_clocks_init(rdev);
1005         if (r)
1006                 return r;
1007         /* Initialize power management */
1008         radeon_pm_init(rdev);
1009         /* Fence driver */
1010         r = radeon_fence_driver_init(rdev);
1011         if (r)
1012                 return r;
1013         /* initialize AGP */
1014         if (rdev->flags & RADEON_IS_AGP) {
1015                 r = radeon_agp_init(rdev);
1016                 if (r)
1017                         radeon_agp_disable(rdev);
1018         }
1019         r = rv770_mc_init(rdev);
1020         if (r)
1021                 return r;
1022         /* Memory manager */
1023         r = radeon_bo_init(rdev);
1024         if (r)
1025                 return r;
1026
1027         r = radeon_irq_kms_init(rdev);
1028         if (r)
1029                 return r;
1030
1031         rdev->cp.ring_obj = NULL;
1032         r600_ring_init(rdev, 1024 * 1024);
1033
1034         rdev->ih.ring_obj = NULL;
1035         r600_ih_ring_init(rdev, 64 * 1024);
1036
1037         r = r600_pcie_gart_init(rdev);
1038         if (r)
1039                 return r;
1040
1041         rdev->accel_working = true;
1042         r = rv770_startup(rdev);
1043         if (r) {
1044                 dev_err(rdev->dev, "disabling GPU acceleration\n");
1045                 r600_cp_fini(rdev);
1046                 r600_wb_fini(rdev);
1047                 r600_irq_fini(rdev);
1048                 radeon_irq_kms_fini(rdev);
1049                 rv770_pcie_gart_fini(rdev);
1050                 rdev->accel_working = false;
1051         }
1052         if (rdev->accel_working) {
1053                 r = radeon_ib_pool_init(rdev);
1054                 if (r) {
1055                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
1056                         rdev->accel_working = false;
1057                 } else {
1058                         r = r600_ib_test(rdev);
1059                         if (r) {
1060                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
1061                                 rdev->accel_working = false;
1062                         }
1063                 }
1064         }
1065         return 0;
1066 }
1067
1068 void rv770_fini(struct radeon_device *rdev)
1069 {
1070         r600_blit_fini(rdev);
1071         r600_cp_fini(rdev);
1072         r600_wb_fini(rdev);
1073         r600_irq_fini(rdev);
1074         radeon_irq_kms_fini(rdev);
1075         rv770_pcie_gart_fini(rdev);
1076         radeon_gem_fini(rdev);
1077         radeon_fence_driver_fini(rdev);
1078         radeon_clocks_fini(rdev);
1079         radeon_agp_fini(rdev);
1080         radeon_bo_fini(rdev);
1081         radeon_atombios_fini(rdev);
1082         kfree(rdev->bios);
1083         rdev->bios = NULL;
1084         radeon_dummy_page_fini(rdev);
1085 }