SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include "drmP.h"
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #ifdef CONFIG_ACPI
  27 #include <linux/acpi.h>
  28 #endif
  29 #include <linux/power_supply.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34 #define RADEON_WAIT_IDLE_TIMEOUT 200
  35
  36 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  37 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  38 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  39 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  40 static void radeon_pm_update_profile(struct radeon_device *rdev);
  41 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  42
  43 #define ACPI_AC_CLASS           "ac_adapter"
  44
  45 #ifdef CONFIG_ACPI
  46 static int radeon_acpi_event(struct notifier_block *nb,
  47                              unsigned long val,
  48                              void *data)
  49 {
  50         struct radeon_device *rdev = container_of(nb, struct radeon_device, acpi_nb);
  51         struct acpi_bus_event *entry = (struct acpi_bus_event *)data;
  52
  53         if (strcmp(entry->device_class, ACPI_AC_CLASS) == 0) {
  54                 if (power_supply_is_system_supplied() > 0)
  55                         DRM_DEBUG("pm: AC\n");
  56                 else
  57                         DRM_DEBUG("pm: DC\n");
  58
  59                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  60                         if (rdev->pm.profile == PM_PROFILE_AUTO) {
  61                                 mutex_lock(&rdev->pm.mutex);
  62                                 radeon_pm_update_profile(rdev);
  63                                 radeon_pm_set_clocks(rdev);
  64                                 mutex_unlock(&rdev->pm.mutex);
  65                         }
  66                 }
  67         }
  68
  69         return NOTIFY_OK;
  70 }
  71 #endif
  72
  73 static void radeon_pm_update_profile(struct radeon_device *rdev)
  74 {
  75         switch (rdev->pm.profile) {
  76         case PM_PROFILE_DEFAULT:
  77                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  78                 break;
  79         case PM_PROFILE_AUTO:
  80                 if (power_supply_is_system_supplied() > 0) {
  81                         if (rdev->pm.active_crtc_count > 1)
  82                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  83                         else
  84                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  85                 } else {
  86                         if (rdev->pm.active_crtc_count > 1)
  87                                 rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  88                         else
  89                                 rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  90                 }
  91                 break;
  92         case PM_PROFILE_LOW:
  93                 if (rdev->pm.active_crtc_count > 1)
  94                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
  95                 else
  96                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
  97                 break;
  98         case PM_PROFILE_HIGH:
  99                 if (rdev->pm.active_crtc_count > 1)
 100                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 101                 else
 102                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 103                 break;
 104         }
 105
 106         if (rdev->pm.active_crtc_count == 0) {
 107                 rdev->pm.requested_power_state_index =
 108                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 109                 rdev->pm.requested_clock_mode_index =
 110                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 111         } else {
 112                 rdev->pm.requested_power_state_index =
 113                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 114                 rdev->pm.requested_clock_mode_index =
 115                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 116         }
 117 }
 118
 119 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 120 {
 121         struct radeon_bo *bo, *n;
 122
 123         if (list_empty(&rdev->gem.objects))
 124                 return;
 125
 126         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 127                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 128                         ttm_bo_unmap_virtual(&bo->tbo);
 129         }
 130 }
 131
 132 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 133 {
 134         if (rdev->pm.active_crtcs) {
 135                 rdev->pm.vblank_sync = false;
 136                 wait_event_timeout(
 137                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 138                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 139         }
 140 }
 141
 142 static void radeon_set_power_state(struct radeon_device *rdev)
 143 {
 144         u32 sclk, mclk;
 145         bool misc_after = false;
 146
 147         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 148             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 149                 return;
 150
 151         if (radeon_gui_idle(rdev)) {
 152                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 153                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 154                 if (sclk > rdev->clock.default_sclk)
 155                         sclk = rdev->clock.default_sclk;
 156
 157                 mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 158                         clock_info[rdev->pm.requested_clock_mode_index].mclk;
 159                 if (mclk > rdev->clock.default_mclk)
 160                         mclk = rdev->clock.default_mclk;
 161
 162                 /* upvolt before raising clocks, downvolt after lowering clocks */
 163                 if (sclk < rdev->pm.current_sclk)
 164                         misc_after = true;
 165
 166                 radeon_sync_with_vblank(rdev);
 167
 168                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 169                         if (!radeon_pm_in_vbl(rdev))
 170                                 return;
 171                 }
 172
 173                 radeon_pm_prepare(rdev);
 174
 175                 if (!misc_after)
 176                         /* voltage, pcie lanes, etc.*/
 177                         radeon_pm_misc(rdev);
 178
 179                 /* set engine clock */
 180                 if (sclk != rdev->pm.current_sclk) {
 181                         radeon_pm_debug_check_in_vbl(rdev, false);
 182                         radeon_set_engine_clock(rdev, sclk);
 183                         radeon_pm_debug_check_in_vbl(rdev, true);
 184                         rdev->pm.current_sclk = sclk;
 185                         DRM_DEBUG("Setting: e: %d\n", sclk);
 186                 }
 187
 188                 /* set memory clock */
 189                 if (rdev->asic->set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 190                         radeon_pm_debug_check_in_vbl(rdev, false);
 191                         radeon_set_memory_clock(rdev, mclk);
 192                         radeon_pm_debug_check_in_vbl(rdev, true);
 193                         rdev->pm.current_mclk = mclk;
 194                         DRM_DEBUG("Setting: m: %d\n", mclk);
 195                 }
 196
 197                 if (misc_after)
 198                         /* voltage, pcie lanes, etc.*/
 199                         radeon_pm_misc(rdev);
 200
 201                 radeon_pm_finish(rdev);
 202
 203                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 204                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 205         } else
 206                 DRM_DEBUG("pm: GUI not idle!!!\n");
 207 }
 208
 209 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 210 {
 211         int i;
 212
 213         mutex_lock(&rdev->ddev->struct_mutex);
 214         mutex_lock(&rdev->vram_mutex);
 215         mutex_lock(&rdev->cp.mutex);
 216
 217         /* gui idle int has issues on older chips it seems */
 218         if (rdev->family >= CHIP_R600) {
 219                 if (rdev->irq.installed) {
 220                         /* wait for GPU idle */
 221                         rdev->pm.gui_idle = false;
 222                         rdev->irq.gui_idle = true;
 223                         radeon_irq_set(rdev);
 224                         wait_event_interruptible_timeout(
 225                                 rdev->irq.idle_queue, rdev->pm.gui_idle,
 226                                 msecs_to_jiffies(RADEON_WAIT_IDLE_TIMEOUT));
 227                         rdev->irq.gui_idle = false;
 228                         radeon_irq_set(rdev);
 229                 }
 230         } else {
 231                 if (rdev->cp.ready) {
 232                         struct radeon_fence *fence;
 233                         radeon_ring_alloc(rdev, 64);
 234                         radeon_fence_create(rdev, &fence);
 235                         radeon_fence_emit(rdev, fence);
 236                         radeon_ring_commit(rdev);
 237                         radeon_fence_wait(fence, false);
 238                         radeon_fence_unref(&fence);
 239                 }
 240         }
 241         radeon_unmap_vram_bos(rdev);
 242
 243         if (rdev->irq.installed) {
 244                 for (i = 0; i < rdev->num_crtc; i++) {
 245                         if (rdev->pm.active_crtcs & (1 << i)) {
 246                                 rdev->pm.req_vblank |= (1 << i);
 247                                 drm_vblank_get(rdev->ddev, i);
 248                         }
 249                 }
 250         }
 251
 252         radeon_set_power_state(rdev);
 253
 254         if (rdev->irq.installed) {
 255                 for (i = 0; i < rdev->num_crtc; i++) {
 256                         if (rdev->pm.req_vblank & (1 << i)) {
 257                                 rdev->pm.req_vblank &= ~(1 << i);
 258                                 drm_vblank_put(rdev->ddev, i);
 259                         }
 260                 }
 261         }
 262
 263         /* update display watermarks based on new power state */
 264         radeon_update_bandwidth_info(rdev);
 265         if (rdev->pm.active_crtc_count)
 266                 radeon_bandwidth_update(rdev);
 267
 268         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 269
 270         mutex_unlock(&rdev->cp.mutex);
 271         mutex_unlock(&rdev->vram_mutex);
 272         mutex_unlock(&rdev->ddev->struct_mutex);
 273 }
 274
 275 static ssize_t radeon_get_pm_profile(struct device *dev,
 276                                      struct device_attribute *attr,
 277                                      char *buf)
 278 {
 279         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 280         struct radeon_device *rdev = ddev->dev_private;
 281         int cp = rdev->pm.profile;
 282
 283         return snprintf(buf, PAGE_SIZE, "%s\n",
 284                         (cp == PM_PROFILE_AUTO) ? "auto" :
 285                         (cp == PM_PROFILE_LOW) ? "low" :
 286                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 287 }
 288
 289 static ssize_t radeon_set_pm_profile(struct device *dev,
 290                                      struct device_attribute *attr,
 291                                      const char *buf,
 292                                      size_t count)
 293 {
 294         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 295         struct radeon_device *rdev = ddev->dev_private;
 296
 297         mutex_lock(&rdev->pm.mutex);
 298         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 299                 if (strncmp("default", buf, strlen("default")) == 0)
 300                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 301                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 302                         rdev->pm.profile = PM_PROFILE_AUTO;
 303                 else if (strncmp("low", buf, strlen("low")) == 0)
 304                         rdev->pm.profile = PM_PROFILE_LOW;
 305                 else if (strncmp("high", buf, strlen("high")) == 0)
 306                         rdev->pm.profile = PM_PROFILE_HIGH;
 307                 else {
 308                         DRM_ERROR("invalid power profile!\n");
 309                         goto fail;
 310                 }
 311                 radeon_pm_update_profile(rdev);
 312                 radeon_pm_set_clocks(rdev);
 313         }
 314 fail:
 315         mutex_unlock(&rdev->pm.mutex);
 316
 317         return count;
 318 }
 319
 320 static ssize_t radeon_get_pm_method(struct device *dev,
 321                                     struct device_attribute *attr,
 322                                     char *buf)
 323 {
 324         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 325         struct radeon_device *rdev = ddev->dev_private;
 326         int pm = rdev->pm.pm_method;
 327
 328         return snprintf(buf, PAGE_SIZE, "%s\n",
 329                         (pm == PM_METHOD_DYNPM) ? "dynpm" : "profile");
 330 }
 331
 332 static ssize_t radeon_set_pm_method(struct device *dev,
 333                                     struct device_attribute *attr,
 334                                     const char *buf,
 335                                     size_t count)
 336 {
 337         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 338         struct radeon_device *rdev = ddev->dev_private;
 339
 340
 341         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 342                 mutex_lock(&rdev->pm.mutex);
 343                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 344                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 345                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 346                 mutex_unlock(&rdev->pm.mutex);
 347         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 348                 mutex_lock(&rdev->pm.mutex);
 349                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 350                 /* disable dynpm */
 351                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 352                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 353                 cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 354                 mutex_unlock(&rdev->pm.mutex);
 355         } else {
 356                 DRM_ERROR("invalid power method!\n");
 357                 goto fail;
 358         }
 359         radeon_pm_compute_clocks(rdev);
 360 fail:
 361         return count;
 362 }
 363
 364 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 365 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 366
 367 void radeon_pm_suspend(struct radeon_device *rdev)
 368 {
 369         mutex_lock(&rdev->pm.mutex);
 370         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 371         mutex_unlock(&rdev->pm.mutex);
 372 }
 373
 374 void radeon_pm_resume(struct radeon_device *rdev)
 375 {
 376         /* asic init will reset the default power state */
 377         mutex_lock(&rdev->pm.mutex);
 378         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 379         rdev->pm.current_clock_mode_index = 0;
 380         rdev->pm.current_sclk = rdev->clock.default_sclk;
 381         rdev->pm.current_mclk = rdev->clock.default_mclk;
 382         mutex_unlock(&rdev->pm.mutex);
 383         radeon_pm_compute_clocks(rdev);
 384 }
 385
 386 int radeon_pm_init(struct radeon_device *rdev)
 387 {
 388         int ret;
 389         /* default to profile method */
 390         rdev->pm.pm_method = PM_METHOD_PROFILE;
 391         rdev->pm.profile = PM_PROFILE_DEFAULT;
 392         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 393         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 394         rdev->pm.dynpm_can_upclock = true;
 395         rdev->pm.dynpm_can_downclock = true;
 396         rdev->pm.current_sclk = rdev->clock.default_sclk;
 397         rdev->pm.current_mclk = rdev->clock.default_mclk;
 398
 399         if (rdev->bios) {
 400                 if (rdev->is_atom_bios)
 401                         radeon_atombios_get_power_modes(rdev);
 402                 else
 403                         radeon_combios_get_power_modes(rdev);
 404                 radeon_pm_init_profile(rdev);
 405         }
 406
 407         if (rdev->pm.num_power_states > 1) {
 408                 /* where's the best place to put these? */
 409                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 410                 if (ret)
 411                         DRM_ERROR("failed to create device file for power profile\n");
 412                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 413                 if (ret)
 414                         DRM_ERROR("failed to create device file for power method\n");
 415
 416 #ifdef CONFIG_ACPI
 417                 rdev->acpi_nb.notifier_call = radeon_acpi_event;
 418                 register_acpi_notifier(&rdev->acpi_nb);
 419 #endif
 420                 INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 421
 422                 if (radeon_debugfs_pm_init(rdev)) {
 423                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 424                 }
 425
 426                 DRM_INFO("radeon: power management initialized\n");
 427         }
 428
 429         return 0;
 430 }
 431
 432 void radeon_pm_fini(struct radeon_device *rdev)
 433 {
 434         if (rdev->pm.num_power_states > 1) {
 435                 mutex_lock(&rdev->pm.mutex);
 436                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 437                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 438                         radeon_pm_update_profile(rdev);
 439                         radeon_pm_set_clocks(rdev);
 440                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 441                         /* cancel work */
 442                         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 443                         /* reset default clocks */
 444                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 445                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 446                         radeon_pm_set_clocks(rdev);
 447                 }
 448                 mutex_unlock(&rdev->pm.mutex);
 449
 450                 device_remove_file(rdev->dev, &dev_attr_power_profile);
 451                 device_remove_file(rdev->dev, &dev_attr_power_method);
 452 #ifdef CONFIG_ACPI
 453                 unregister_acpi_notifier(&rdev->acpi_nb);
 454 #endif
 455         }
 456
 457         if (rdev->pm.i2c_bus)
 458                 radeon_i2c_destroy(rdev->pm.i2c_bus);
 459 }
 460
 461 void radeon_pm_compute_clocks(struct radeon_device *rdev)
 462 {
 463         struct drm_device *ddev = rdev->ddev;
 464         struct drm_crtc *crtc;
 465         struct radeon_crtc *radeon_crtc;
 466
 467         if (rdev->pm.num_power_states < 2)
 468                 return;
 469
 470         mutex_lock(&rdev->pm.mutex);
 471
 472         rdev->pm.active_crtcs = 0;
 473         rdev->pm.active_crtc_count = 0;
 474         list_for_each_entry(crtc,
 475                 &ddev->mode_config.crtc_list, head) {
 476                 radeon_crtc = to_radeon_crtc(crtc);
 477                 if (radeon_crtc->enabled) {
 478                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
 479                         rdev->pm.active_crtc_count++;
 480                 }
 481         }
 482
 483         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 484                 radeon_pm_update_profile(rdev);
 485                 radeon_pm_set_clocks(rdev);
 486         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 487                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
 488                         if (rdev->pm.active_crtc_count > 1) {
 489                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 490                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 491
 492                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 493                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 494                                         radeon_pm_get_dynpm_state(rdev);
 495                                         radeon_pm_set_clocks(rdev);
 496
 497                                         DRM_DEBUG("radeon: dynamic power management deactivated\n");
 498                                 }
 499                         } else if (rdev->pm.active_crtc_count == 1) {
 500                                 /* TODO: Increase clocks if needed for current mode */
 501
 502                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
 503                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 504                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
 505                                         radeon_pm_get_dynpm_state(rdev);
 506                                         radeon_pm_set_clocks(rdev);
 507
 508                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 509                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 510                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
 511                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 512                                         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 513                                                            msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 514                                         DRM_DEBUG("radeon: dynamic power management activated\n");
 515                                 }
 516                         } else { /* count == 0 */
 517                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
 518                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
 519
 520                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
 521                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
 522                                         radeon_pm_get_dynpm_state(rdev);
 523                                         radeon_pm_set_clocks(rdev);
 524                                 }
 525                         }
 526                 }
 527         }
 528
 529         mutex_unlock(&rdev->pm.mutex);
 530 }
 531
 532 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
 533 {
 534         u32 stat_crtc = 0, vbl = 0, position = 0;
 535         bool in_vbl = true;
 536
 537         if (ASIC_IS_DCE4(rdev)) {
 538                 if (rdev->pm.active_crtcs & (1 << 0)) {
 539                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 540                                      EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 541                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 542                                           EVERGREEN_CRTC0_REGISTER_OFFSET) & 0xfff;
 543                 }
 544                 if (rdev->pm.active_crtcs & (1 << 1)) {
 545                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 546                                      EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 547                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 548                                           EVERGREEN_CRTC1_REGISTER_OFFSET) & 0xfff;
 549                 }
 550                 if (rdev->pm.active_crtcs & (1 << 2)) {
 551                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 552                                      EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 553                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 554                                           EVERGREEN_CRTC2_REGISTER_OFFSET) & 0xfff;
 555                 }
 556                 if (rdev->pm.active_crtcs & (1 << 3)) {
 557                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 558                                      EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 559                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 560                                           EVERGREEN_CRTC3_REGISTER_OFFSET) & 0xfff;
 561                 }
 562                 if (rdev->pm.active_crtcs & (1 << 4)) {
 563                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 564                                      EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 565                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 566                                           EVERGREEN_CRTC4_REGISTER_OFFSET) & 0xfff;
 567                 }
 568                 if (rdev->pm.active_crtcs & (1 << 5)) {
 569                         vbl = RREG32(EVERGREEN_CRTC_V_BLANK_START_END +
 570                                      EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 571                         position = RREG32(EVERGREEN_CRTC_STATUS_POSITION +
 572                                           EVERGREEN_CRTC5_REGISTER_OFFSET) & 0xfff;
 573                 }
 574         } else if (ASIC_IS_AVIVO(rdev)) {
 575                 if (rdev->pm.active_crtcs & (1 << 0)) {
 576                         vbl = RREG32(AVIVO_D1CRTC_V_BLANK_START_END) & 0xfff;
 577                         position = RREG32(AVIVO_D1CRTC_STATUS_POSITION) & 0xfff;
 578                 }
 579                 if (rdev->pm.active_crtcs & (1 << 1)) {
 580                         vbl = RREG32(AVIVO_D2CRTC_V_BLANK_START_END) & 0xfff;
 581                         position = RREG32(AVIVO_D2CRTC_STATUS_POSITION) & 0xfff;
 582                 }
 583                 if (position < vbl && position > 1)
 584                         in_vbl = false;
 585         } else {
 586                 if (rdev->pm.active_crtcs & (1 << 0)) {
 587                         stat_crtc = RREG32(RADEON_CRTC_STATUS);
 588                         if (!(stat_crtc & 1))
 589                                 in_vbl = false;
 590                 }
 591                 if (rdev->pm.active_crtcs & (1 << 1)) {
 592                         stat_crtc = RREG32(RADEON_CRTC2_STATUS);
 593                         if (!(stat_crtc & 1))
 594                                 in_vbl = false;
 595                 }
 596         }
 597
 598         if (position < vbl && position > 1)
 599                 in_vbl = false;
 600
 601         return in_vbl;
 602 }
 603
 604 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
 605 {
 606         u32 stat_crtc = 0;
 607         bool in_vbl = radeon_pm_in_vbl(rdev);
 608
 609         if (in_vbl == false)
 610                 DRM_DEBUG("not in vbl for pm change %08x at %s\n", stat_crtc,
 611                          finish ? "exit" : "entry");
 612         return in_vbl;
 613 }
 614
 615 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
 616 {
 617         struct radeon_device *rdev;
 618         int resched;
 619         rdev = container_of(work, struct radeon_device,
 620                                 pm.dynpm_idle_work.work);
 621
 622         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
 623         mutex_lock(&rdev->pm.mutex);
 624         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
 625                 unsigned long irq_flags;
 626                 int not_processed = 0;
 627
 628                 read_lock_irqsave(&rdev->fence_drv.lock, irq_flags);
 629                 if (!list_empty(&rdev->fence_drv.emited)) {
 630                         struct list_head *ptr;
 631                         list_for_each(ptr, &rdev->fence_drv.emited) {
 632                                 /* count up to 3, that's enought info */
 633                                 if (++not_processed >= 3)
 634                                         break;
 635                         }
 636                 }
 637                 read_unlock_irqrestore(&rdev->fence_drv.lock, irq_flags);
 638
 639                 if (not_processed >= 3) { /* should upclock */
 640                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
 641                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 642                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 643                                    rdev->pm.dynpm_can_upclock) {
 644                                 rdev->pm.dynpm_planned_action =
 645                                         DYNPM_ACTION_UPCLOCK;
 646                                 rdev->pm.dynpm_action_timeout = jiffies +
 647                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 648                         }
 649                 } else if (not_processed == 0) { /* should downclock */
 650                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
 651                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 652                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
 653                                    rdev->pm.dynpm_can_downclock) {
 654                                 rdev->pm.dynpm_planned_action =
 655                                         DYNPM_ACTION_DOWNCLOCK;
 656                                 rdev->pm.dynpm_action_timeout = jiffies +
 657                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
 658                         }
 659                 }
 660
 661                 /* Note, radeon_pm_set_clocks is called with static_switch set
 662                  * to false since we want to wait for vbl to avoid flicker.
 663                  */
 664                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
 665                     jiffies > rdev->pm.dynpm_action_timeout) {
 666                         radeon_pm_get_dynpm_state(rdev);
 667                         radeon_pm_set_clocks(rdev);
 668                 }
 669         }
 670         mutex_unlock(&rdev->pm.mutex);
 671         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
 672
 673         queue_delayed_work(rdev->wq, &rdev->pm.dynpm_idle_work,
 674                                         msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 675 }
 676
 677 /*
 678  * Debugfs info
 679  */
 680 #if defined(CONFIG_DEBUG_FS)
 681
 682 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
 683 {
 684         struct drm_info_node *node = (struct drm_info_node *) m->private;
 685         struct drm_device *dev = node->minor->dev;
 686         struct radeon_device *rdev = dev->dev_private;
 687
 688         seq_printf(m, "default engine clock: %u0 kHz\n", rdev->clock.default_sclk);
 689         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
 690         seq_printf(m, "default memory clock: %u0 kHz\n", rdev->clock.default_mclk);
 691         if (rdev->asic->get_memory_clock)
 692                 seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
 693         if (rdev->asic->get_pcie_lanes)
 694                 seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
 695
 696         return 0;
 697 }
 698
 699 static struct drm_info_list radeon_pm_info_list[] = {
 700         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
 701 };
 702 #endif
 703
 704 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
 705 {
 706 #if defined(CONFIG_DEBUG_FS)
 707         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
 708 #else
 709         return 0;
 710 #endif
 711 }