SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include "drmP.h"
  29 #include "drm_sarea.h"
  30 #include "radeon.h"
  31 #include "radeon_drm.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34
  35 int radeon_driver_unload_kms(struct drm_device *dev)
  36 {
  37         struct radeon_device *rdev = dev->dev_private;
  38
  39         if (rdev == NULL)
  40                 return 0;
  41         radeon_modeset_fini(rdev);
  42         radeon_device_fini(rdev);
  43         kfree(rdev);
  44         dev->dev_private = NULL;
  45         return 0;
  46 }
  47
  48 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  49 {
  50         struct radeon_device *rdev;
  51         int r;
  52
  53         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  54         if (rdev == NULL) {
  55                 return -ENOMEM;
  56         }
  57         dev->dev_private = (void *)rdev;
  58
  59         /* update BUS flag */
  60         if (drm_device_is_agp(dev)) {
  61                 flags |= RADEON_IS_AGP;
  62         } else if (drm_device_is_pcie(dev)) {
  63                 flags |= RADEON_IS_PCIE;
  64         } else {
  65                 flags |= RADEON_IS_PCI;
  66         }
  67
  68         /* radeon_device_init should report only fatal error
  69          * like memory allocation failure or iomapping failure,
  70          * or memory manager initialization failure, it must
  71          * properly initialize the GPU MC controller and permit
  72          * VRAM allocation
  73          */
  74         r = radeon_device_init(rdev, dev, dev->pdev, flags);
  75         if (r) {
  76                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
  77                 goto out;
  78         }
  79         /* Again modeset_init should fail only on fatal error
  80          * otherwise it should provide enough functionalities
  81          * for shadowfb to run
  82          */
  83         r = radeon_modeset_init(rdev);
  84         if (r)
  85                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
  86 out:
  87         if (r)
  88                 radeon_driver_unload_kms(dev);
  89         return r;
  90 }
  91
  92
  93 /*
  94  * Userspace get informations ioctl
  95  */
  96 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
  97 {
  98         struct radeon_device *rdev = dev->dev_private;
  99         struct drm_radeon_info *info;
 100         uint32_t *value_ptr;
 101         uint32_t value;
 102
 103         info = data;
 104         value_ptr = (uint32_t *)((unsigned long)info->value);
 105         switch (info->request) {
 106         case RADEON_INFO_DEVICE_ID:
 107                 value = dev->pci_device;
 108                 break;
 109         case RADEON_INFO_NUM_GB_PIPES:
 110                 value = rdev->num_gb_pipes;
 111                 break;
 112         case RADEON_INFO_NUM_Z_PIPES:
 113                 value = rdev->num_z_pipes;
 114                 break;
 115         case RADEON_INFO_ACCEL_WORKING:
 116                 value = rdev->accel_working;
 117                 break;
 118         default:
 119                 DRM_DEBUG("Invalid request %d\n", info->request);
 120                 return -EINVAL;
 121         }
 122         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 123                 DRM_ERROR("copy_to_user\n");
 124                 return -EFAULT;
 125         }
 126         return 0;
 127 }
 128
 129
 130 /*
 131  * Outdated mess for old drm with Xorg being in charge (void function now).
 132  */
 133 int radeon_driver_firstopen_kms(struct drm_device *dev)
 134 {
 135         return 0;
 136 }
 137
 138
 139 void radeon_driver_lastclose_kms(struct drm_device *dev)
 140 {
 141         vga_switcheroo_process_delayed_switch();
 142 }
 143
 144 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 145 {
 146         return 0;
 147 }
 148
 149 void radeon_driver_postclose_kms(struct drm_device *dev,
 150                                  struct drm_file *file_priv)
 151 {
 152 }
 153
 154 void radeon_driver_preclose_kms(struct drm_device *dev,
 155                                 struct drm_file *file_priv)
 156 {
 157 }
 158
 159
 160 /*
 161  * VBlank related functions.
 162  */
 163 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 164 {
 165         struct radeon_device *rdev = dev->dev_private;
 166
 167         if (crtc < 0 || crtc > 1) {
 168                 DRM_ERROR("Invalid crtc %d\n", crtc);
 169                 return -EINVAL;
 170         }
 171
 172         return radeon_get_vblank_counter(rdev, crtc);
 173 }
 174
 175 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 176 {
 177         struct radeon_device *rdev = dev->dev_private;
 178
 179         if (crtc < 0 || crtc > 1) {
 180                 DRM_ERROR("Invalid crtc %d\n", crtc);
 181                 return -EINVAL;
 182         }
 183
 184         rdev->irq.crtc_vblank_int[crtc] = true;
 185
 186         return radeon_irq_set(rdev);
 187 }
 188
 189 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 190 {
 191         struct radeon_device *rdev = dev->dev_private;
 192
 193         if (crtc < 0 || crtc > 1) {
 194                 DRM_ERROR("Invalid crtc %d\n", crtc);
 195                 return;
 196         }
 197
 198         rdev->irq.crtc_vblank_int[crtc] = false;
 199
 200         radeon_irq_set(rdev);
 201 }
 202
 203
 204 /*
 205  * IOCTL.
 206  */
 207 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 208                          struct drm_file *file_priv)
 209 {
 210         /* Not valid in KMS. */
 211         return -EINVAL;
 212 }
 213
 214 #define KMS_INVALID_IOCTL(name)                                         \
 215 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 216 {                                                                       \
 217         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 218         return -EINVAL;                                                 \
 219 }
 220
 221 /*
 222  * All these ioctls are invalid in kms world.
 223  */
 224 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 225 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 226 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 227 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 228 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 229 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 230 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 231 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 232 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 233 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 234 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 235 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 236 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 237 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 238 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 239 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 240 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 241 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 242 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 243 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 244 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 245 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 246 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 247 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 248 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 249 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 250 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 251
 252
 253 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 254         DRM_IOCTL_DEF(DRM_RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 255         DRM_IOCTL_DEF(DRM_RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 256         DRM_IOCTL_DEF(DRM_RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 257         DRM_IOCTL_DEF(DRM_RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 258         DRM_IOCTL_DEF(DRM_RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 259         DRM_IOCTL_DEF(DRM_RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 260         DRM_IOCTL_DEF(DRM_RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 261         DRM_IOCTL_DEF(DRM_RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 262         DRM_IOCTL_DEF(DRM_RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 263         DRM_IOCTL_DEF(DRM_RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 264         DRM_IOCTL_DEF(DRM_RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 265         DRM_IOCTL_DEF(DRM_RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 266         DRM_IOCTL_DEF(DRM_RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 267         DRM_IOCTL_DEF(DRM_RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 268         DRM_IOCTL_DEF(DRM_RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 269         DRM_IOCTL_DEF(DRM_RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 270         DRM_IOCTL_DEF(DRM_RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 271         DRM_IOCTL_DEF(DRM_RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 272         DRM_IOCTL_DEF(DRM_RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 273         DRM_IOCTL_DEF(DRM_RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 274         DRM_IOCTL_DEF(DRM_RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 275         DRM_IOCTL_DEF(DRM_RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 276         DRM_IOCTL_DEF(DRM_RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 277         DRM_IOCTL_DEF(DRM_RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 278         DRM_IOCTL_DEF(DRM_RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 279         DRM_IOCTL_DEF(DRM_RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 280         DRM_IOCTL_DEF(DRM_RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 281         /* KMS */
 282         DRM_IOCTL_DEF(DRM_RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 283         DRM_IOCTL_DEF(DRM_RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 284         DRM_IOCTL_DEF(DRM_RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 285         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 286         DRM_IOCTL_DEF(DRM_RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 287         DRM_IOCTL_DEF(DRM_RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 288         DRM_IOCTL_DEF(DRM_RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 289         DRM_IOCTL_DEF(DRM_RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 290         DRM_IOCTL_DEF(DRM_RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 291         DRM_IOCTL_DEF(DRM_RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 292         DRM_IOCTL_DEF(DRM_RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 293         DRM_IOCTL_DEF(DRM_RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 294 };
 295 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);