2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
31 /* TODO: Here are things that needs to be done :
32 * - surface allocator & initializer : (bit like scratch reg) should
33 * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings
35 * - WB : write back stuff (do it bit like scratch reg things)
36 * - Vblank : look at Jesse's rework and what we should do
37 * - r600/r700: gart & cp
38 * - cs : clean cs ioctl use bitmap & things like that.
39 * - power management stuff
40 * - Barrier in gart code
41 * - Unmappabled vram ?
42 * - TESTING, TESTING, TESTING
45 /* Initialization path:
46 * We expect that acceleration initialization might fail for various
47 * reasons even thought we work hard to make it works on most
48 * configurations. In order to still have a working userspace in such
49 * situation the init path must succeed up to the memory controller
50 * initialization point. Failure before this point are considered as
51 * fatal error. Here is the init callchain :
52 * radeon_device_init perform common structure, mutex initialization
53 * asic_init setup the GPU memory layout and perform all
54 * one time initialization (failure in this
55 * function are considered fatal)
56 * asic_startup setup the GPU acceleration, in order to
57 * follow guideline the first thing this
58 * function should do is setting the GPU
59 * memory controller (only MC setup failure
60 * are considered as fatal)
63 #include <asm/atomic.h>
64 #include <linux/wait.h>
65 #include <linux/list.h>
66 #include <linux/kref.h>
68 #include <ttm/ttm_bo_api.h>
69 #include <ttm/ttm_bo_driver.h>
70 #include <ttm/ttm_placement.h>
71 #include <ttm/ttm_module.h>
73 #include "radeon_family.h"
74 #include "radeon_mode.h"
75 #include "radeon_reg.h"
80 extern int radeon_no_wb;
81 extern int radeon_modeset;
82 extern int radeon_dynclks;
83 extern int radeon_r4xx_atom;
84 extern int radeon_agpmode;
85 extern int radeon_vram_limit;
86 extern int radeon_gart_size;
87 extern int radeon_benchmarking;
88 extern int radeon_testing;
89 extern int radeon_connector_table;
91 extern int radeon_new_pll;
92 extern int radeon_audio;
93 extern int radeon_disp_priority;
94 extern int radeon_hw_i2c;
97 * Copy from radeon_drv.h so we don't have to include both and have conflicting
100 #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
101 #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
102 /* RADEON_IB_POOL_SIZE must be a power of 2 */
103 #define RADEON_IB_POOL_SIZE 16
104 #define RADEON_DEBUGFS_MAX_NUM_FILES 32
105 #define RADEONFB_CONN_LIMIT 4
106 #define RADEON_BIOS_NUM_SCRATCH 8
109 * Errata workarounds.
111 enum radeon_pll_errata {
112 CHIP_ERRATA_R300_CG = 0x00000001,
113 CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002,
114 CHIP_ERRATA_PLL_DELAY = 0x00000004
118 struct radeon_device;
124 #define ATRM_BIOS_PAGE 4096
126 #if defined(CONFIG_VGA_SWITCHEROO)
127 bool radeon_atrm_supported(struct pci_dev *pdev);
128 int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len);
130 static inline bool radeon_atrm_supported(struct pci_dev *pdev)
135 static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){
139 bool radeon_get_bios(struct radeon_device *rdev);
145 struct radeon_dummy_page {
149 int radeon_dummy_page_init(struct radeon_device *rdev);
150 void radeon_dummy_page_fini(struct radeon_device *rdev);
156 struct radeon_clock {
157 struct radeon_pll p1pll;
158 struct radeon_pll p2pll;
159 struct radeon_pll dcpll;
160 struct radeon_pll spll;
161 struct radeon_pll mpll;
163 uint32_t default_mclk;
164 uint32_t default_sclk;
165 uint32_t default_dispclk;
172 int radeon_pm_init(struct radeon_device *rdev);
173 void radeon_pm_fini(struct radeon_device *rdev);
174 void radeon_pm_compute_clocks(struct radeon_device *rdev);
175 void radeon_pm_suspend(struct radeon_device *rdev);
176 void radeon_pm_resume(struct radeon_device *rdev);
177 void radeon_combios_get_power_modes(struct radeon_device *rdev);
178 void radeon_atombios_get_power_modes(struct radeon_device *rdev);
179 void radeon_atom_set_voltage(struct radeon_device *rdev, u16 level);
184 struct radeon_fence_driver {
185 uint32_t scratch_reg;
188 unsigned long last_jiffies;
189 unsigned long last_timeout;
190 wait_queue_head_t queue;
192 struct list_head created;
193 struct list_head emited;
194 struct list_head signaled;
198 struct radeon_fence {
199 struct radeon_device *rdev;
201 struct list_head list;
202 /* protected by radeon_fence.lock */
208 int radeon_fence_driver_init(struct radeon_device *rdev);
209 void radeon_fence_driver_fini(struct radeon_device *rdev);
210 int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence);
211 int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence);
212 void radeon_fence_process(struct radeon_device *rdev);
213 bool radeon_fence_signaled(struct radeon_fence *fence);
214 int radeon_fence_wait(struct radeon_fence *fence, bool interruptible);
215 int radeon_fence_wait_next(struct radeon_device *rdev);
216 int radeon_fence_wait_last(struct radeon_device *rdev);
217 struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence);
218 void radeon_fence_unref(struct radeon_fence **fence);
223 struct radeon_surface_reg {
224 struct radeon_bo *bo;
227 #define RADEON_GEM_MAX_SURFACES 8
233 struct ttm_bo_global_ref bo_global_ref;
234 struct ttm_global_reference mem_global_ref;
235 struct ttm_bo_device bdev;
236 bool mem_global_referenced;
241 /* Protected by gem.mutex */
242 struct list_head list;
243 /* Protected by tbo.reserved */
245 struct ttm_placement placement;
246 struct ttm_buffer_object tbo;
247 struct ttm_bo_kmap_obj kmap;
253 /* Constant after initialization */
254 struct radeon_device *rdev;
255 struct drm_gem_object *gobj;
258 struct radeon_bo_list {
259 struct list_head list;
260 struct radeon_bo *bo;
273 struct list_head objects;
276 int radeon_gem_init(struct radeon_device *rdev);
277 void radeon_gem_fini(struct radeon_device *rdev);
278 int radeon_gem_object_create(struct radeon_device *rdev, int size,
279 int alignment, int initial_domain,
280 bool discardable, bool kernel,
281 struct drm_gem_object **obj);
282 int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain,
284 void radeon_gem_object_unpin(struct drm_gem_object *obj);
288 * GART structures, functions & helpers
292 struct radeon_gart_table_ram {
293 volatile uint32_t *ptr;
296 struct radeon_gart_table_vram {
297 struct radeon_bo *robj;
298 volatile uint32_t *ptr;
301 union radeon_gart_table {
302 struct radeon_gart_table_ram ram;
303 struct radeon_gart_table_vram vram;
306 #define RADEON_GPU_PAGE_SIZE 4096
307 #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1)
310 dma_addr_t table_addr;
311 unsigned num_gpu_pages;
312 unsigned num_cpu_pages;
314 union radeon_gart_table table;
316 dma_addr_t *pages_addr;
320 int radeon_gart_table_ram_alloc(struct radeon_device *rdev);
321 void radeon_gart_table_ram_free(struct radeon_device *rdev);
322 int radeon_gart_table_vram_alloc(struct radeon_device *rdev);
323 void radeon_gart_table_vram_free(struct radeon_device *rdev);
324 int radeon_gart_init(struct radeon_device *rdev);
325 void radeon_gart_fini(struct radeon_device *rdev);
326 void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset,
328 int radeon_gart_bind(struct radeon_device *rdev, unsigned offset,
329 int pages, struct page **pagelist);
333 * GPU MC structures, functions & helpers
336 resource_size_t aper_size;
337 resource_size_t aper_base;
338 resource_size_t agp_base;
339 /* for some chips with <= 32MB we need to lie
340 * about vram size near mc fb location */
342 u64 visible_vram_size;
352 bool igp_sideport_enabled;
355 bool radeon_combios_sideport_present(struct radeon_device *rdev);
356 bool radeon_atombios_sideport_present(struct radeon_device *rdev);
359 * GPU scratch registers structures, functions & helpers
361 struct radeon_scratch {
367 int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg);
368 void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg);
377 /* FIXME: use a define max crtc rather than hardcode it */
378 bool crtc_vblank_int[6];
379 wait_queue_head_t vblank_queue;
380 /* FIXME: use defines for max hpd/dacs */
384 wait_queue_head_t idle_queue;
385 /* FIXME: use defines for max HDMI blocks */
391 int radeon_irq_kms_init(struct radeon_device *rdev);
392 void radeon_irq_kms_fini(struct radeon_device *rdev);
393 void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev);
394 void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev);
400 struct list_head list;
403 struct radeon_fence *fence;
411 * mutex protects scheduled_ibs, ready, alloc_bm
413 struct radeon_ib_pool {
415 struct radeon_bo *robj;
416 struct list_head bogus_ib;
417 struct radeon_ib ibs[RADEON_IB_POOL_SIZE];
423 struct radeon_bo *ring_obj;
424 volatile uint32_t *ring;
429 unsigned ring_free_dw;
442 struct radeon_bo *ring_obj;
443 volatile uint32_t *ring;
456 struct radeon_bo *shader_obj;
458 u32 vs_offset, ps_offset;
461 u32 vb_used, vb_total;
462 struct radeon_ib *vb_ib;
465 int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib);
466 void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib);
467 int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib);
468 int radeon_ib_pool_init(struct radeon_device *rdev);
469 void radeon_ib_pool_fini(struct radeon_device *rdev);
470 int radeon_ib_test(struct radeon_device *rdev);
471 extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib);
472 /* Ring access between begin & end cannot sleep */
473 void radeon_ring_free_size(struct radeon_device *rdev);
474 int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw);
475 int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw);
476 void radeon_ring_commit(struct radeon_device *rdev);
477 void radeon_ring_unlock_commit(struct radeon_device *rdev);
478 void radeon_ring_unlock_undo(struct radeon_device *rdev);
479 int radeon_ring_test(struct radeon_device *rdev);
480 int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size);
481 void radeon_ring_fini(struct radeon_device *rdev);
487 struct radeon_cs_reloc {
488 struct drm_gem_object *gobj;
489 struct radeon_bo *robj;
490 struct radeon_bo_list lobj;
495 struct radeon_cs_chunk {
501 void __user *user_ptr;
502 int last_copied_page;
506 struct radeon_cs_parser {
508 struct radeon_device *rdev;
509 struct drm_file *filp;
512 struct radeon_cs_chunk *chunks;
513 uint64_t *chunks_array;
518 struct radeon_cs_reloc *relocs;
519 struct radeon_cs_reloc **relocs_ptr;
520 struct list_head validated;
521 /* indices of various chunks */
523 int chunk_relocs_idx;
524 struct radeon_ib *ib;
530 extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx);
531 extern int radeon_cs_finish_pages(struct radeon_cs_parser *p);
534 static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx)
536 struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx];
537 u32 pg_idx, pg_offset;
541 pg_idx = (idx * 4) / PAGE_SIZE;
542 pg_offset = (idx * 4) % PAGE_SIZE;
544 if (ibc->kpage_idx[0] == pg_idx)
545 return ibc->kpage[0][pg_offset/4];
546 if (ibc->kpage_idx[1] == pg_idx)
547 return ibc->kpage[1][pg_offset/4];
549 new_page = radeon_cs_update_pages(p, pg_idx);
551 p->parser_error = new_page;
555 idx_value = ibc->kpage[new_page][pg_offset/4];
559 struct radeon_cs_packet {
568 typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p,
569 struct radeon_cs_packet *pkt,
570 unsigned idx, unsigned reg);
571 typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p,
572 struct radeon_cs_packet *pkt);
578 int radeon_agp_init(struct radeon_device *rdev);
579 void radeon_agp_resume(struct radeon_device *rdev);
580 void radeon_agp_suspend(struct radeon_device *rdev);
581 void radeon_agp_fini(struct radeon_device *rdev);
588 struct radeon_bo *wb_obj;
589 volatile uint32_t *wb;
594 * struct radeon_pm - power management datas
595 * @max_bandwidth: maximum bandwidth the gpu has (MByte/s)
596 * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880)
597 * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880)
598 * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880)
599 * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880)
600 * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP)
601 * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP)
602 * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP)
603 * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP)
604 * @sclk: GPU clock Mhz (core bandwith depends of this clock)
605 * @needed_bandwidth: current bandwidth needs
607 * It keeps track of various data needed to take powermanagement decision.
608 * Bandwith need is used to determine minimun clock of the GPU and memory.
609 * Equation between gpu/memory clock and available bandwidth is hw dependent
610 * (type of memory, bus size, efficiency, ...)
613 enum radeon_pm_method {
618 enum radeon_dynpm_state {
619 DYNPM_STATE_DISABLED,
624 enum radeon_dynpm_action {
626 DYNPM_ACTION_MINIMUM,
627 DYNPM_ACTION_DOWNCLOCK,
628 DYNPM_ACTION_UPCLOCK,
632 enum radeon_voltage_type {
639 enum radeon_pm_state_type {
640 POWER_STATE_TYPE_DEFAULT,
641 POWER_STATE_TYPE_POWERSAVE,
642 POWER_STATE_TYPE_BATTERY,
643 POWER_STATE_TYPE_BALANCED,
644 POWER_STATE_TYPE_PERFORMANCE,
647 enum radeon_pm_profile_type {
655 #define PM_PROFILE_DEFAULT_IDX 0
656 #define PM_PROFILE_LOW_SH_IDX 1
657 #define PM_PROFILE_MID_SH_IDX 2
658 #define PM_PROFILE_HIGH_SH_IDX 3
659 #define PM_PROFILE_LOW_MH_IDX 4
660 #define PM_PROFILE_MID_MH_IDX 5
661 #define PM_PROFILE_HIGH_MH_IDX 6
662 #define PM_PROFILE_MAX 7
664 struct radeon_pm_profile {
671 struct radeon_voltage {
672 enum radeon_voltage_type type;
674 struct radeon_gpio_rec gpio;
675 u32 delay; /* delay in usec from voltage drop to sclk change */
676 bool active_high; /* voltage drop is active when bit is high */
678 u8 vddc_id; /* index into vddc voltage table */
679 u8 vddci_id; /* index into vddci voltage table */
685 /* clock mode flags */
686 #define RADEON_PM_MODE_NO_DISPLAY (1 << 0)
688 struct radeon_pm_clock_info {
694 struct radeon_voltage voltage;
695 /* standardized clock flags */
700 #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0)
702 struct radeon_power_state {
703 enum radeon_pm_state_type type;
704 /* XXX: use a define for num clock modes */
705 struct radeon_pm_clock_info clock_info[8];
706 /* number of valid clock modes in this power state */
708 struct radeon_pm_clock_info *default_clock_mode;
709 /* standardized state flags */
711 u32 misc; /* vbios specific flags */
712 u32 misc2; /* vbios specific flags */
713 int pcie_lanes; /* pcie lanes */
717 * Some modes are overclocked by very low value, accept them
719 #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */
724 int active_crtc_count;
728 fixed20_12 max_bandwidth;
729 fixed20_12 igp_sideport_mclk;
730 fixed20_12 igp_system_mclk;
731 fixed20_12 igp_ht_link_clk;
732 fixed20_12 igp_ht_link_width;
733 fixed20_12 k8_bandwidth;
734 fixed20_12 sideport_bandwidth;
735 fixed20_12 ht_bandwidth;
736 fixed20_12 core_bandwidth;
739 fixed20_12 needed_bandwidth;
740 /* XXX: use a define for num power modes */
741 struct radeon_power_state power_state[8];
742 /* number of valid power states */
743 int num_power_states;
744 int current_power_state_index;
745 int current_clock_mode_index;
746 int requested_power_state_index;
747 int requested_clock_mode_index;
748 int default_power_state_index;
751 struct radeon_i2c_chan *i2c_bus;
752 /* selected pm method */
753 enum radeon_pm_method pm_method;
754 /* dynpm power management */
755 struct delayed_work dynpm_idle_work;
756 enum radeon_dynpm_state dynpm_state;
757 enum radeon_dynpm_action dynpm_planned_action;
758 unsigned long dynpm_action_timeout;
759 bool dynpm_can_upclock;
760 bool dynpm_can_downclock;
761 /* profile-based power management */
762 enum radeon_pm_profile_type profile;
764 struct radeon_pm_profile profiles[PM_PROFILE_MAX];
771 void radeon_benchmark(struct radeon_device *rdev);
777 void radeon_test_moves(struct radeon_device *rdev);
783 int radeon_debugfs_add_files(struct radeon_device *rdev,
784 struct drm_info_list *files,
786 int radeon_debugfs_fence_init(struct radeon_device *rdev);
790 * ASIC specific functions.
793 int (*init)(struct radeon_device *rdev);
794 void (*fini)(struct radeon_device *rdev);
795 int (*resume)(struct radeon_device *rdev);
796 int (*suspend)(struct radeon_device *rdev);
797 void (*vga_set_state)(struct radeon_device *rdev, bool state);
798 bool (*gpu_is_lockup)(struct radeon_device *rdev);
799 int (*asic_reset)(struct radeon_device *rdev);
800 void (*gart_tlb_flush)(struct radeon_device *rdev);
801 int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr);
802 int (*cp_init)(struct radeon_device *rdev, unsigned ring_size);
803 void (*cp_fini)(struct radeon_device *rdev);
804 void (*cp_disable)(struct radeon_device *rdev);
805 void (*cp_commit)(struct radeon_device *rdev);
806 void (*ring_start)(struct radeon_device *rdev);
807 int (*ring_test)(struct radeon_device *rdev);
808 void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib);
809 int (*irq_set)(struct radeon_device *rdev);
810 int (*irq_process)(struct radeon_device *rdev);
811 u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc);
812 void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence);
813 int (*cs_parse)(struct radeon_cs_parser *p);
814 int (*copy_blit)(struct radeon_device *rdev,
818 struct radeon_fence *fence);
819 int (*copy_dma)(struct radeon_device *rdev,
823 struct radeon_fence *fence);
824 int (*copy)(struct radeon_device *rdev,
828 struct radeon_fence *fence);
829 uint32_t (*get_engine_clock)(struct radeon_device *rdev);
830 void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock);
831 uint32_t (*get_memory_clock)(struct radeon_device *rdev);
832 void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock);
833 int (*get_pcie_lanes)(struct radeon_device *rdev);
834 void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes);
835 void (*set_clock_gating)(struct radeon_device *rdev, int enable);
836 int (*set_surface_reg)(struct radeon_device *rdev, int reg,
837 uint32_t tiling_flags, uint32_t pitch,
838 uint32_t offset, uint32_t obj_size);
839 void (*clear_surface_reg)(struct radeon_device *rdev, int reg);
840 void (*bandwidth_update)(struct radeon_device *rdev);
841 void (*hpd_init)(struct radeon_device *rdev);
842 void (*hpd_fini)(struct radeon_device *rdev);
843 bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
844 void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd);
845 /* ioctl hw specific callback. Some hw might want to perform special
846 * operation on specific ioctl. For instance on wait idle some hw
847 * might want to perform and HDP flush through MMIO as it seems that
848 * some R6XX/R7XX hw doesn't take HDP flush into account if programmed
851 void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo);
852 bool (*gui_idle)(struct radeon_device *rdev);
853 /* power management */
854 void (*pm_misc)(struct radeon_device *rdev);
855 void (*pm_prepare)(struct radeon_device *rdev);
856 void (*pm_finish)(struct radeon_device *rdev);
857 void (*pm_init_profile)(struct radeon_device *rdev);
858 void (*pm_get_dynpm_state)(struct radeon_device *rdev);
864 struct r100_gpu_lockup {
865 unsigned long last_jiffies;
870 const unsigned *reg_safe_bm;
871 unsigned reg_safe_bm_size;
873 struct r100_gpu_lockup lockup;
877 const unsigned *reg_safe_bm;
878 unsigned reg_safe_bm_size;
881 struct r100_gpu_lockup lockup;
886 unsigned max_tile_pipes;
888 unsigned max_backends;
890 unsigned max_threads;
891 unsigned max_stack_entries;
892 unsigned max_hw_contexts;
893 unsigned max_gs_threads;
894 unsigned sx_max_export_size;
895 unsigned sx_max_export_pos_size;
896 unsigned sx_max_export_smx_size;
897 unsigned sq_num_cf_insts;
898 unsigned tiling_nbanks;
899 unsigned tiling_npipes;
900 unsigned tiling_group_size;
901 struct r100_gpu_lockup lockup;
906 unsigned max_tile_pipes;
908 unsigned max_backends;
910 unsigned max_threads;
911 unsigned max_stack_entries;
912 unsigned max_hw_contexts;
913 unsigned max_gs_threads;
914 unsigned sx_max_export_size;
915 unsigned sx_max_export_pos_size;
916 unsigned sx_max_export_smx_size;
917 unsigned sq_num_cf_insts;
918 unsigned sx_num_of_sets;
919 unsigned sc_prim_fifo_size;
920 unsigned sc_hiz_tile_fifo_size;
921 unsigned sc_earlyz_tile_fifo_fize;
922 unsigned tiling_nbanks;
923 unsigned tiling_npipes;
924 unsigned tiling_group_size;
925 struct r100_gpu_lockup lockup;
928 struct evergreen_asic {
931 unsigned max_tile_pipes;
933 unsigned max_backends;
935 unsigned max_threads;
936 unsigned max_stack_entries;
937 unsigned max_hw_contexts;
938 unsigned max_gs_threads;
939 unsigned sx_max_export_size;
940 unsigned sx_max_export_pos_size;
941 unsigned sx_max_export_smx_size;
942 unsigned sq_num_cf_insts;
943 unsigned sx_num_of_sets;
944 unsigned sc_prim_fifo_size;
945 unsigned sc_hiz_tile_fifo_size;
946 unsigned sc_earlyz_tile_fifo_size;
947 unsigned tiling_nbanks;
948 unsigned tiling_npipes;
949 unsigned tiling_group_size;
952 union radeon_asic_config {
953 struct r300_asic r300;
954 struct r100_asic r100;
955 struct r600_asic r600;
956 struct rv770_asic rv770;
957 struct evergreen_asic evergreen;
961 * asic initizalization from radeon_asic.c
963 void radeon_agp_disable(struct radeon_device *rdev);
964 int radeon_asic_init(struct radeon_device *rdev);
970 int radeon_gem_info_ioctl(struct drm_device *dev, void *data,
971 struct drm_file *filp);
972 int radeon_gem_create_ioctl(struct drm_device *dev, void *data,
973 struct drm_file *filp);
974 int radeon_gem_pin_ioctl(struct drm_device *dev, void *data,
975 struct drm_file *file_priv);
976 int radeon_gem_unpin_ioctl(struct drm_device *dev, void *data,
977 struct drm_file *file_priv);
978 int radeon_gem_pwrite_ioctl(struct drm_device *dev, void *data,
979 struct drm_file *file_priv);
980 int radeon_gem_pread_ioctl(struct drm_device *dev, void *data,
981 struct drm_file *file_priv);
982 int radeon_gem_set_domain_ioctl(struct drm_device *dev, void *data,
983 struct drm_file *filp);
984 int radeon_gem_mmap_ioctl(struct drm_device *dev, void *data,
985 struct drm_file *filp);
986 int radeon_gem_busy_ioctl(struct drm_device *dev, void *data,
987 struct drm_file *filp);
988 int radeon_gem_wait_idle_ioctl(struct drm_device *dev, void *data,
989 struct drm_file *filp);
990 int radeon_cs_ioctl(struct drm_device *dev, void *data, struct drm_file *filp);
991 int radeon_gem_set_tiling_ioctl(struct drm_device *dev, void *data,
992 struct drm_file *filp);
993 int radeon_gem_get_tiling_ioctl(struct drm_device *dev, void *data,
994 struct drm_file *filp);
998 * Core structure, functions and helpers.
1000 typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t);
1001 typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t);
1003 struct radeon_device {
1005 struct drm_device *ddev;
1006 struct pci_dev *pdev;
1008 union radeon_asic_config config;
1009 enum radeon_family family;
1010 unsigned long flags;
1012 enum radeon_pll_errata pll_errata;
1019 uint16_t bios_header_start;
1020 struct radeon_bo *stollen_vga_memory;
1022 resource_size_t rmmio_base;
1023 resource_size_t rmmio_size;
1025 radeon_rreg_t mc_rreg;
1026 radeon_wreg_t mc_wreg;
1027 radeon_rreg_t pll_rreg;
1028 radeon_wreg_t pll_wreg;
1029 uint32_t pcie_reg_mask;
1030 radeon_rreg_t pciep_rreg;
1031 radeon_wreg_t pciep_wreg;
1032 struct radeon_clock clock;
1033 struct radeon_mc mc;
1034 struct radeon_gart gart;
1035 struct radeon_mode_info mode_info;
1036 struct radeon_scratch scratch;
1037 struct radeon_mman mman;
1038 struct radeon_fence_driver fence_drv;
1039 struct radeon_cp cp;
1040 struct radeon_ib_pool ib_pool;
1041 struct radeon_irq irq;
1042 struct radeon_asic *asic;
1043 struct radeon_gem gem;
1044 struct radeon_pm pm;
1045 uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH];
1046 struct mutex cs_mutex;
1047 struct radeon_wb wb;
1048 struct radeon_dummy_page dummy_page;
1054 struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES];
1055 const struct firmware *me_fw; /* all family ME firmware */
1056 const struct firmware *pfp_fw; /* r6/700 PFP firmware */
1057 const struct firmware *rlc_fw; /* r6/700 RLC firmware */
1058 struct r600_blit r600_blit;
1059 int msi_enabled; /* msi enabled */
1060 struct r600_ih ih; /* r6/700 interrupt ring */
1061 struct workqueue_struct *wq;
1062 struct work_struct hotplug_work;
1063 int num_crtc; /* number of crtcs */
1064 struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */
1065 struct mutex vram_mutex;
1068 struct timer_list audio_timer;
1071 int audio_bits_per_sample;
1072 uint8_t audio_status_bits;
1073 uint8_t audio_category_code;
1076 struct notifier_block acpi_nb;
1079 int radeon_device_init(struct radeon_device *rdev,
1080 struct drm_device *ddev,
1081 struct pci_dev *pdev,
1083 void radeon_device_fini(struct radeon_device *rdev);
1084 int radeon_gpu_wait_for_idle(struct radeon_device *rdev);
1087 int r600_blit_prepare_copy(struct radeon_device *rdev, int size_bytes);
1088 void r600_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence);
1089 void r600_kms_blit_copy(struct radeon_device *rdev,
1090 u64 src_gpu_addr, u64 dst_gpu_addr,
1093 static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg)
1095 if (reg < rdev->rmmio_size)
1096 return readl(((void __iomem *)rdev->rmmio) + reg);
1098 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1099 return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1103 static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1105 if (reg < rdev->rmmio_size)
1106 writel(v, ((void __iomem *)rdev->rmmio) + reg);
1108 writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX);
1109 writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA);
1116 #define to_radeon_fence(p) ((struct radeon_fence *)(p))
1119 * Registers read & write functions.
1121 #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg))
1122 #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg))
1123 #define RREG32(reg) r100_mm_rreg(rdev, (reg))
1124 #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg)))
1125 #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v))
1126 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1127 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK)
1128 #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg))
1129 #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v))
1130 #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg))
1131 #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v))
1132 #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg))
1133 #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v))
1134 #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg))
1135 #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v))
1136 #define WREG32_P(reg, val, mask) \
1138 uint32_t tmp_ = RREG32(reg); \
1140 tmp_ |= ((val) & ~(mask)); \
1141 WREG32(reg, tmp_); \
1143 #define WREG32_PLL_P(reg, val, mask) \
1145 uint32_t tmp_ = RREG32_PLL(reg); \
1147 tmp_ |= ((val) & ~(mask)); \
1148 WREG32_PLL(reg, tmp_); \
1150 #define DREG32_SYS(sqf, rdev, reg) seq_printf((sqf), #reg " : 0x%08X\n", r100_mm_rreg((rdev), (reg)))
1153 * Indirect registers accessor
1155 static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg)
1159 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1160 r = RREG32(RADEON_PCIE_DATA);
1164 static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
1166 WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask));
1167 WREG32(RADEON_PCIE_DATA, (v));
1170 void r100_pll_errata_after_index(struct radeon_device *rdev);
1176 #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \
1177 (rdev->pdev->device == 0x5969))
1178 #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \
1179 (rdev->family == CHIP_RV200) || \
1180 (rdev->family == CHIP_RS100) || \
1181 (rdev->family == CHIP_RS200) || \
1182 (rdev->family == CHIP_RV250) || \
1183 (rdev->family == CHIP_RV280) || \
1184 (rdev->family == CHIP_RS300))
1185 #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \
1186 (rdev->family == CHIP_RV350) || \
1187 (rdev->family == CHIP_R350) || \
1188 (rdev->family == CHIP_RV380) || \
1189 (rdev->family == CHIP_R420) || \
1190 (rdev->family == CHIP_R423) || \
1191 (rdev->family == CHIP_RV410) || \
1192 (rdev->family == CHIP_RS400) || \
1193 (rdev->family == CHIP_RS480))
1194 #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600))
1195 #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620))
1196 #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730))
1197 #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR))
1202 #define RBIOS8(i) (rdev->bios[i])
1203 #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8))
1204 #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16))
1206 int radeon_combios_init(struct radeon_device *rdev);
1207 void radeon_combios_fini(struct radeon_device *rdev);
1208 int radeon_atombios_init(struct radeon_device *rdev);
1209 void radeon_atombios_fini(struct radeon_device *rdev);
1215 static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v)
1218 if (rdev->cp.count_dw <= 0) {
1219 DRM_ERROR("radeon: writting more dword to ring than expected !\n");
1222 rdev->cp.ring[rdev->cp.wptr++] = v;
1223 rdev->cp.wptr &= rdev->cp.ptr_mask;
1224 rdev->cp.count_dw--;
1225 rdev->cp.ring_free_dw--;
1232 #define radeon_init(rdev) (rdev)->asic->init((rdev))
1233 #define radeon_fini(rdev) (rdev)->asic->fini((rdev))
1234 #define radeon_resume(rdev) (rdev)->asic->resume((rdev))
1235 #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev))
1236 #define radeon_cs_parse(p) rdev->asic->cs_parse((p))
1237 #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state))
1238 #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev))
1239 #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev))
1240 #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev))
1241 #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p))
1242 #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev))
1243 #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev))
1244 #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev))
1245 #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib))
1246 #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev))
1247 #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev))
1248 #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc))
1249 #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence))
1250 #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f))
1251 #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f))
1252 #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f))
1253 #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev))
1254 #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e))
1255 #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev))
1256 #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e))
1257 #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev))
1258 #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l))
1259 #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e))
1260 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s)))
1261 #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r)))
1262 #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev))
1263 #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev))
1264 #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev))
1265 #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd))
1266 #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd))
1267 #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev))
1268 #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev))
1269 #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev))
1270 #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev))
1271 #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev))
1272 #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev))
1274 /* Common functions */
1276 extern int radeon_gpu_reset(struct radeon_device *rdev);
1277 extern void radeon_agp_disable(struct radeon_device *rdev);
1278 extern int radeon_gart_table_vram_pin(struct radeon_device *rdev);
1279 extern void radeon_gart_restore(struct radeon_device *rdev);
1280 extern int radeon_modeset_init(struct radeon_device *rdev);
1281 extern void radeon_modeset_fini(struct radeon_device *rdev);
1282 extern bool radeon_card_posted(struct radeon_device *rdev);
1283 extern void radeon_update_bandwidth_info(struct radeon_device *rdev);
1284 extern void radeon_update_display_priority(struct radeon_device *rdev);
1285 extern bool radeon_boot_test_post_card(struct radeon_device *rdev);
1286 extern int radeon_clocks_init(struct radeon_device *rdev);
1287 extern void radeon_clocks_fini(struct radeon_device *rdev);
1288 extern void radeon_scratch_init(struct radeon_device *rdev);
1289 extern void radeon_surface_init(struct radeon_device *rdev);
1290 extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data);
1291 extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable);
1292 extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable);
1293 extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain);
1294 extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo);
1295 extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base);
1296 extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1297 extern int radeon_resume_kms(struct drm_device *dev);
1298 extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state);
1300 /* r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280 */
1301 extern void r100_gpu_lockup_update(struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1302 extern bool r100_gpu_cp_is_lockup(struct radeon_device *rdev, struct r100_gpu_lockup *lockup, struct radeon_cp *cp);
1304 /* rv200,rv250,rv280 */
1305 extern void r200_set_safe_registers(struct radeon_device *rdev);
1307 /* r300,r350,rv350,rv370,rv380 */
1308 extern void r300_set_reg_safe(struct radeon_device *rdev);
1309 extern void r300_mc_program(struct radeon_device *rdev);
1310 extern void r300_mc_init(struct radeon_device *rdev);
1311 extern void r300_clock_startup(struct radeon_device *rdev);
1312 extern int r300_mc_wait_for_idle(struct radeon_device *rdev);
1313 extern int rv370_pcie_gart_init(struct radeon_device *rdev);
1314 extern void rv370_pcie_gart_fini(struct radeon_device *rdev);
1315 extern int rv370_pcie_gart_enable(struct radeon_device *rdev);
1316 extern void rv370_pcie_gart_disable(struct radeon_device *rdev);
1318 /* r420,r423,rv410 */
1319 extern u32 r420_mc_rreg(struct radeon_device *rdev, u32 reg);
1320 extern void r420_mc_wreg(struct radeon_device *rdev, u32 reg, u32 v);
1321 extern int r420_debugfs_pipes_info_init(struct radeon_device *rdev);
1322 extern void r420_pipes_init(struct radeon_device *rdev);
1325 struct rv515_mc_save {
1328 u32 vga_render_control;
1329 u32 vga_hdp_control;
1333 extern void rv515_bandwidth_avivo_update(struct radeon_device *rdev);
1334 extern void rv515_vga_render_disable(struct radeon_device *rdev);
1335 extern void rv515_set_safe_registers(struct radeon_device *rdev);
1336 extern void rv515_mc_stop(struct radeon_device *rdev, struct rv515_mc_save *save);
1337 extern void rv515_mc_resume(struct radeon_device *rdev, struct rv515_mc_save *save);
1338 extern void rv515_clock_startup(struct radeon_device *rdev);
1339 extern void rv515_debugfs(struct radeon_device *rdev);
1340 extern int rv515_suspend(struct radeon_device *rdev);
1343 extern int rs400_gart_init(struct radeon_device *rdev);
1344 extern int rs400_gart_enable(struct radeon_device *rdev);
1345 extern void rs400_gart_adjust_size(struct radeon_device *rdev);
1346 extern void rs400_gart_disable(struct radeon_device *rdev);
1347 extern void rs400_gart_fini(struct radeon_device *rdev);
1350 extern void rs600_set_safe_registers(struct radeon_device *rdev);
1351 extern int rs600_irq_set(struct radeon_device *rdev);
1352 extern void rs600_irq_disable(struct radeon_device *rdev);
1355 extern void rs690_line_buffer_adjust(struct radeon_device *rdev,
1356 struct drm_display_mode *mode1,
1357 struct drm_display_mode *mode2);
1359 /* r600, rv610, rv630, rv620, rv635, rv670, rs780, rs880 */
1360 extern void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc);
1361 extern bool r600_card_posted(struct radeon_device *rdev);
1362 extern void r600_cp_stop(struct radeon_device *rdev);
1363 extern int r600_cp_start(struct radeon_device *rdev);
1364 extern void r600_ring_init(struct radeon_device *rdev, unsigned ring_size);
1365 extern int r600_cp_resume(struct radeon_device *rdev);
1366 extern void r600_cp_fini(struct radeon_device *rdev);
1367 extern int r600_count_pipe_bits(uint32_t val);
1368 extern int r600_mc_wait_for_idle(struct radeon_device *rdev);
1369 extern int r600_pcie_gart_init(struct radeon_device *rdev);
1370 extern void r600_pcie_gart_tlb_flush(struct radeon_device *rdev);
1371 extern int r600_ib_test(struct radeon_device *rdev);
1372 extern int r600_ring_test(struct radeon_device *rdev);
1373 extern void r600_wb_fini(struct radeon_device *rdev);
1374 extern int r600_wb_enable(struct radeon_device *rdev);
1375 extern void r600_wb_disable(struct radeon_device *rdev);
1376 extern void r600_scratch_init(struct radeon_device *rdev);
1377 extern int r600_blit_init(struct radeon_device *rdev);
1378 extern void r600_blit_fini(struct radeon_device *rdev);
1379 extern int r600_init_microcode(struct radeon_device *rdev);
1380 extern int r600_asic_reset(struct radeon_device *rdev);
1382 extern int r600_irq_init(struct radeon_device *rdev);
1383 extern void r600_irq_fini(struct radeon_device *rdev);
1384 extern void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size);
1385 extern int r600_irq_set(struct radeon_device *rdev);
1386 extern void r600_irq_suspend(struct radeon_device *rdev);
1387 extern void r600_disable_interrupts(struct radeon_device *rdev);
1388 extern void r600_rlc_stop(struct radeon_device *rdev);
1390 extern int r600_audio_init(struct radeon_device *rdev);
1391 extern int r600_audio_tmds_index(struct drm_encoder *encoder);
1392 extern void r600_audio_set_clock(struct drm_encoder *encoder, int clock);
1393 extern int r600_audio_channels(struct radeon_device *rdev);
1394 extern int r600_audio_bits_per_sample(struct radeon_device *rdev);
1395 extern int r600_audio_rate(struct radeon_device *rdev);
1396 extern uint8_t r600_audio_status_bits(struct radeon_device *rdev);
1397 extern uint8_t r600_audio_category_code(struct radeon_device *rdev);
1398 extern void r600_audio_schedule_polling(struct radeon_device *rdev);
1399 extern void r600_audio_enable_polling(struct drm_encoder *encoder);
1400 extern void r600_audio_disable_polling(struct drm_encoder *encoder);
1401 extern void r600_audio_fini(struct radeon_device *rdev);
1402 extern void r600_hdmi_init(struct drm_encoder *encoder);
1403 extern void r600_hdmi_enable(struct drm_encoder *encoder);
1404 extern void r600_hdmi_disable(struct drm_encoder *encoder);
1405 extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode);
1406 extern int r600_hdmi_buffer_status_changed(struct drm_encoder *encoder);
1407 extern void r600_hdmi_update_audio_settings(struct drm_encoder *encoder);
1409 extern void r700_cp_stop(struct radeon_device *rdev);
1410 extern void r700_cp_fini(struct radeon_device *rdev);
1411 extern void evergreen_disable_interrupt_state(struct radeon_device *rdev);
1412 extern int evergreen_irq_set(struct radeon_device *rdev);
1415 struct evergreen_mc_save {
1417 u32 vga_render_control;
1418 u32 vga_hdp_control;
1419 u32 crtc_control[6];
1422 #include "radeon_object.h"