2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/slab.h>
29 #include <linux/seq_file.h>
30 #include <linux/firmware.h>
31 #include <linux/platform_device.h>
33 #include "radeon_drm.h"
35 #include "radeon_asic.h"
36 #include "radeon_mode.h"
41 #define PFP_UCODE_SIZE 576
42 #define PM4_UCODE_SIZE 1792
43 #define RLC_UCODE_SIZE 768
44 #define R700_PFP_UCODE_SIZE 848
45 #define R700_PM4_UCODE_SIZE 1360
46 #define R700_RLC_UCODE_SIZE 1024
47 #define EVERGREEN_PFP_UCODE_SIZE 1120
48 #define EVERGREEN_PM4_UCODE_SIZE 1376
49 #define EVERGREEN_RLC_UCODE_SIZE 768
52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
53 MODULE_FIRMWARE("radeon/R600_me.bin");
54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
55 MODULE_FIRMWARE("radeon/RV610_me.bin");
56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
57 MODULE_FIRMWARE("radeon/RV630_me.bin");
58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
59 MODULE_FIRMWARE("radeon/RV620_me.bin");
60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
61 MODULE_FIRMWARE("radeon/RV635_me.bin");
62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
63 MODULE_FIRMWARE("radeon/RV670_me.bin");
64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
65 MODULE_FIRMWARE("radeon/RS780_me.bin");
66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
67 MODULE_FIRMWARE("radeon/RV770_me.bin");
68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
69 MODULE_FIRMWARE("radeon/RV730_me.bin");
70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
71 MODULE_FIRMWARE("radeon/RV710_me.bin");
72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
89 /* r600,rv610,rv630,rv620,rv635,rv670 */
90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
91 void r600_gpu_init(struct radeon_device *rdev);
92 void r600_fini(struct radeon_device *rdev);
93 void r600_irq_disable(struct radeon_device *rdev);
95 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
99 rdev->pm.dynpm_can_upclock = true;
100 rdev->pm.dynpm_can_downclock = true;
102 /* power state array is low to high, default is first */
103 if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
104 int min_power_state_index = 0;
106 if (rdev->pm.num_power_states > 2)
107 min_power_state_index = 1;
109 switch (rdev->pm.dynpm_planned_action) {
110 case DYNPM_ACTION_MINIMUM:
111 rdev->pm.requested_power_state_index = min_power_state_index;
112 rdev->pm.requested_clock_mode_index = 0;
113 rdev->pm.dynpm_can_downclock = false;
115 case DYNPM_ACTION_DOWNCLOCK:
116 if (rdev->pm.current_power_state_index == min_power_state_index) {
117 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
118 rdev->pm.dynpm_can_downclock = false;
120 if (rdev->pm.active_crtc_count > 1) {
121 for (i = 0; i < rdev->pm.num_power_states; i++) {
122 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
124 else if (i >= rdev->pm.current_power_state_index) {
125 rdev->pm.requested_power_state_index =
126 rdev->pm.current_power_state_index;
129 rdev->pm.requested_power_state_index = i;
134 rdev->pm.requested_power_state_index =
135 rdev->pm.current_power_state_index - 1;
137 rdev->pm.requested_clock_mode_index = 0;
138 /* don't use the power state if crtcs are active and no display flag is set */
139 if ((rdev->pm.active_crtc_count > 0) &&
140 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
141 clock_info[rdev->pm.requested_clock_mode_index].flags &
142 RADEON_PM_MODE_NO_DISPLAY)) {
143 rdev->pm.requested_power_state_index++;
146 case DYNPM_ACTION_UPCLOCK:
147 if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
148 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
149 rdev->pm.dynpm_can_upclock = false;
151 if (rdev->pm.active_crtc_count > 1) {
152 for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
153 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
155 else if (i <= rdev->pm.current_power_state_index) {
156 rdev->pm.requested_power_state_index =
157 rdev->pm.current_power_state_index;
160 rdev->pm.requested_power_state_index = i;
165 rdev->pm.requested_power_state_index =
166 rdev->pm.current_power_state_index + 1;
168 rdev->pm.requested_clock_mode_index = 0;
170 case DYNPM_ACTION_DEFAULT:
171 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
172 rdev->pm.requested_clock_mode_index = 0;
173 rdev->pm.dynpm_can_upclock = false;
175 case DYNPM_ACTION_NONE:
177 DRM_ERROR("Requested mode for not defined action\n");
181 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
182 /* for now just select the first power state and switch between clock modes */
183 /* power state array is low to high, default is first (0) */
184 if (rdev->pm.active_crtc_count > 1) {
185 rdev->pm.requested_power_state_index = -1;
186 /* start at 1 as we don't want the default mode */
187 for (i = 1; i < rdev->pm.num_power_states; i++) {
188 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
190 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
191 (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
192 rdev->pm.requested_power_state_index = i;
196 /* if nothing selected, grab the default state. */
197 if (rdev->pm.requested_power_state_index == -1)
198 rdev->pm.requested_power_state_index = 0;
200 rdev->pm.requested_power_state_index = 1;
202 switch (rdev->pm.dynpm_planned_action) {
203 case DYNPM_ACTION_MINIMUM:
204 rdev->pm.requested_clock_mode_index = 0;
205 rdev->pm.dynpm_can_downclock = false;
207 case DYNPM_ACTION_DOWNCLOCK:
208 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
209 if (rdev->pm.current_clock_mode_index == 0) {
210 rdev->pm.requested_clock_mode_index = 0;
211 rdev->pm.dynpm_can_downclock = false;
213 rdev->pm.requested_clock_mode_index =
214 rdev->pm.current_clock_mode_index - 1;
216 rdev->pm.requested_clock_mode_index = 0;
217 rdev->pm.dynpm_can_downclock = false;
219 /* don't use the power state if crtcs are active and no display flag is set */
220 if ((rdev->pm.active_crtc_count > 0) &&
221 (rdev->pm.power_state[rdev->pm.requested_power_state_index].
222 clock_info[rdev->pm.requested_clock_mode_index].flags &
223 RADEON_PM_MODE_NO_DISPLAY)) {
224 rdev->pm.requested_clock_mode_index++;
227 case DYNPM_ACTION_UPCLOCK:
228 if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
229 if (rdev->pm.current_clock_mode_index ==
230 (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
231 rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
232 rdev->pm.dynpm_can_upclock = false;
234 rdev->pm.requested_clock_mode_index =
235 rdev->pm.current_clock_mode_index + 1;
237 rdev->pm.requested_clock_mode_index =
238 rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
239 rdev->pm.dynpm_can_upclock = false;
242 case DYNPM_ACTION_DEFAULT:
243 rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
244 rdev->pm.requested_clock_mode_index = 0;
245 rdev->pm.dynpm_can_upclock = false;
247 case DYNPM_ACTION_NONE:
249 DRM_ERROR("Requested mode for not defined action\n");
254 DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
255 rdev->pm.power_state[rdev->pm.requested_power_state_index].
256 clock_info[rdev->pm.requested_clock_mode_index].sclk,
257 rdev->pm.power_state[rdev->pm.requested_power_state_index].
258 clock_info[rdev->pm.requested_clock_mode_index].mclk,
259 rdev->pm.power_state[rdev->pm.requested_power_state_index].
263 static int r600_pm_get_type_index(struct radeon_device *rdev,
264 enum radeon_pm_state_type ps_type,
268 int found_instance = -1;
270 for (i = 0; i < rdev->pm.num_power_states; i++) {
271 if (rdev->pm.power_state[i].type == ps_type) {
273 if (found_instance == instance)
277 /* return default if no match */
278 return rdev->pm.default_power_state_index;
281 void rs780_pm_init_profile(struct radeon_device *rdev)
283 if (rdev->pm.num_power_states == 2) {
285 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
286 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
287 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
288 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
290 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
291 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
292 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
293 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
295 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
296 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
297 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
298 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
300 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
301 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
302 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
303 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
305 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
306 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
307 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
308 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
310 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
311 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
312 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
313 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
315 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
316 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
317 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
318 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
319 } else if (rdev->pm.num_power_states == 3) {
321 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
322 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
323 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
324 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
326 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
327 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
328 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
329 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
331 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
332 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
333 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
334 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
336 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
337 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
338 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
339 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
341 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
342 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
343 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
344 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
346 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
347 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
348 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
349 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
351 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
352 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
353 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
354 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
357 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
358 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
359 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
360 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
362 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
363 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
364 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
365 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
367 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
368 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
369 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
370 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
372 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
373 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
374 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
375 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
377 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
378 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
379 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
380 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
382 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
383 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
384 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
385 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
387 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
388 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
389 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
390 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
394 void r600_pm_init_profile(struct radeon_device *rdev)
396 if (rdev->family == CHIP_R600) {
399 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
400 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
401 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
402 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
404 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
405 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
406 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
407 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
409 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
410 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
411 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
412 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
414 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
415 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
416 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
417 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
419 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
420 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
421 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
422 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
424 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
425 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
426 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
427 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
429 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
430 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
431 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
432 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
434 if (rdev->pm.num_power_states < 4) {
436 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
437 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
438 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
439 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
441 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
442 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
443 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
444 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
446 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
447 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
448 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
449 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
451 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
452 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
453 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
454 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
456 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
457 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
458 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
459 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
461 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
462 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
463 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
464 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
466 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
467 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
468 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
469 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
472 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
473 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
474 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
475 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
477 if (rdev->flags & RADEON_IS_MOBILITY) {
478 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
479 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
480 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
481 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
482 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
483 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
485 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
486 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
487 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
488 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
489 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
490 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
493 if (rdev->flags & RADEON_IS_MOBILITY) {
494 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
495 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
496 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
497 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
498 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
499 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
501 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
502 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
503 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
504 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
505 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
506 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
509 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
510 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
511 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
512 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
513 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
514 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
516 if (rdev->flags & RADEON_IS_MOBILITY) {
517 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
518 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
519 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
520 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
521 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
522 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
524 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
525 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
526 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
527 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
528 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
529 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
532 if (rdev->flags & RADEON_IS_MOBILITY) {
533 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
534 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
535 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
536 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
537 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
538 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
540 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
541 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
542 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
543 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
544 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
545 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
548 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
549 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
550 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
551 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
552 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
553 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
558 void r600_pm_misc(struct radeon_device *rdev)
560 int requested_index = rdev->pm.requested_power_state_index;
561 struct radeon_power_state *ps = &rdev->pm.power_state[requested_index];
562 struct radeon_voltage *voltage = &ps->clock_info[0].voltage;
564 if ((voltage->type == VOLTAGE_SW) && voltage->voltage)
565 radeon_atom_set_voltage(rdev, voltage->voltage);
569 bool r600_gui_idle(struct radeon_device *rdev)
571 if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
577 /* hpd for digital panel detect/disconnect */
578 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
580 bool connected = false;
582 if (ASIC_IS_DCE3(rdev)) {
585 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
589 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
593 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
597 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
602 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
606 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
615 if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
619 if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
623 if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
633 void r600_hpd_set_polarity(struct radeon_device *rdev,
634 enum radeon_hpd_id hpd)
637 bool connected = r600_hpd_sense(rdev, hpd);
639 if (ASIC_IS_DCE3(rdev)) {
642 tmp = RREG32(DC_HPD1_INT_CONTROL);
644 tmp &= ~DC_HPDx_INT_POLARITY;
646 tmp |= DC_HPDx_INT_POLARITY;
647 WREG32(DC_HPD1_INT_CONTROL, tmp);
650 tmp = RREG32(DC_HPD2_INT_CONTROL);
652 tmp &= ~DC_HPDx_INT_POLARITY;
654 tmp |= DC_HPDx_INT_POLARITY;
655 WREG32(DC_HPD2_INT_CONTROL, tmp);
658 tmp = RREG32(DC_HPD3_INT_CONTROL);
660 tmp &= ~DC_HPDx_INT_POLARITY;
662 tmp |= DC_HPDx_INT_POLARITY;
663 WREG32(DC_HPD3_INT_CONTROL, tmp);
666 tmp = RREG32(DC_HPD4_INT_CONTROL);
668 tmp &= ~DC_HPDx_INT_POLARITY;
670 tmp |= DC_HPDx_INT_POLARITY;
671 WREG32(DC_HPD4_INT_CONTROL, tmp);
674 tmp = RREG32(DC_HPD5_INT_CONTROL);
676 tmp &= ~DC_HPDx_INT_POLARITY;
678 tmp |= DC_HPDx_INT_POLARITY;
679 WREG32(DC_HPD5_INT_CONTROL, tmp);
683 tmp = RREG32(DC_HPD6_INT_CONTROL);
685 tmp &= ~DC_HPDx_INT_POLARITY;
687 tmp |= DC_HPDx_INT_POLARITY;
688 WREG32(DC_HPD6_INT_CONTROL, tmp);
696 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
698 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
700 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
701 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
704 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
706 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
708 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
709 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
712 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
714 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
716 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
717 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
725 void r600_hpd_init(struct radeon_device *rdev)
727 struct drm_device *dev = rdev->ddev;
728 struct drm_connector *connector;
730 if (ASIC_IS_DCE3(rdev)) {
731 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
732 if (ASIC_IS_DCE32(rdev))
735 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
736 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
737 switch (radeon_connector->hpd.hpd) {
739 WREG32(DC_HPD1_CONTROL, tmp);
740 rdev->irq.hpd[0] = true;
743 WREG32(DC_HPD2_CONTROL, tmp);
744 rdev->irq.hpd[1] = true;
747 WREG32(DC_HPD3_CONTROL, tmp);
748 rdev->irq.hpd[2] = true;
751 WREG32(DC_HPD4_CONTROL, tmp);
752 rdev->irq.hpd[3] = true;
756 WREG32(DC_HPD5_CONTROL, tmp);
757 rdev->irq.hpd[4] = true;
760 WREG32(DC_HPD6_CONTROL, tmp);
761 rdev->irq.hpd[5] = true;
768 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
769 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
770 switch (radeon_connector->hpd.hpd) {
772 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
773 rdev->irq.hpd[0] = true;
776 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
777 rdev->irq.hpd[1] = true;
780 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
781 rdev->irq.hpd[2] = true;
788 if (rdev->irq.installed)
792 void r600_hpd_fini(struct radeon_device *rdev)
794 struct drm_device *dev = rdev->ddev;
795 struct drm_connector *connector;
797 if (ASIC_IS_DCE3(rdev)) {
798 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
799 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
800 switch (radeon_connector->hpd.hpd) {
802 WREG32(DC_HPD1_CONTROL, 0);
803 rdev->irq.hpd[0] = false;
806 WREG32(DC_HPD2_CONTROL, 0);
807 rdev->irq.hpd[1] = false;
810 WREG32(DC_HPD3_CONTROL, 0);
811 rdev->irq.hpd[2] = false;
814 WREG32(DC_HPD4_CONTROL, 0);
815 rdev->irq.hpd[3] = false;
819 WREG32(DC_HPD5_CONTROL, 0);
820 rdev->irq.hpd[4] = false;
823 WREG32(DC_HPD6_CONTROL, 0);
824 rdev->irq.hpd[5] = false;
831 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
832 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
833 switch (radeon_connector->hpd.hpd) {
835 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
836 rdev->irq.hpd[0] = false;
839 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
840 rdev->irq.hpd[1] = false;
843 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
844 rdev->irq.hpd[2] = false;
856 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
861 /* flush hdp cache so updates hit vram */
862 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
864 WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
865 WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
866 WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
867 for (i = 0; i < rdev->usec_timeout; i++) {
869 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
870 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
872 printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
882 int r600_pcie_gart_init(struct radeon_device *rdev)
886 if (rdev->gart.table.vram.robj) {
887 WARN(1, "R600 PCIE GART already initialized.\n");
890 /* Initialize common gart structure */
891 r = radeon_gart_init(rdev);
894 rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
895 return radeon_gart_table_vram_alloc(rdev);
898 int r600_pcie_gart_enable(struct radeon_device *rdev)
903 if (rdev->gart.table.vram.robj == NULL) {
904 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
907 r = radeon_gart_table_vram_pin(rdev);
910 radeon_gart_restore(rdev);
913 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
914 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
915 EFFECTIVE_L2_QUEUE_SIZE(7));
916 WREG32(VM_L2_CNTL2, 0);
917 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
918 /* Setup TLB control */
919 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
920 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
921 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
922 ENABLE_WAIT_L2_QUERY;
923 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
924 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
925 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
926 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
927 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
928 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
929 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
930 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
931 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
932 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
933 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
934 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
935 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
936 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
937 WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
938 WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
939 WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
940 WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
941 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
942 WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
943 (u32)(rdev->dummy_page.addr >> 12));
944 for (i = 1; i < 7; i++)
945 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
947 r600_pcie_gart_tlb_flush(rdev);
948 rdev->gart.ready = true;
952 void r600_pcie_gart_disable(struct radeon_device *rdev)
957 /* Disable all tables */
958 for (i = 0; i < 7; i++)
959 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
961 /* Disable L2 cache */
962 WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
963 EFFECTIVE_L2_QUEUE_SIZE(7));
964 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
965 /* Setup L1 TLB control */
966 tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
967 ENABLE_WAIT_L2_QUERY;
968 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
969 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
970 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
971 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
972 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
973 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
974 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
975 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
976 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
977 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
978 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
979 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
980 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
981 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
982 if (rdev->gart.table.vram.robj) {
983 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
984 if (likely(r == 0)) {
985 radeon_bo_kunmap(rdev->gart.table.vram.robj);
986 radeon_bo_unpin(rdev->gart.table.vram.robj);
987 radeon_bo_unreserve(rdev->gart.table.vram.robj);
992 void r600_pcie_gart_fini(struct radeon_device *rdev)
994 radeon_gart_fini(rdev);
995 r600_pcie_gart_disable(rdev);
996 radeon_gart_table_vram_free(rdev);
999 void r600_agp_enable(struct radeon_device *rdev)
1004 /* Setup L2 cache */
1005 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1006 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1007 EFFECTIVE_L2_QUEUE_SIZE(7));
1008 WREG32(VM_L2_CNTL2, 0);
1009 WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1010 /* Setup TLB control */
1011 tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1012 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1013 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1014 ENABLE_WAIT_L2_QUERY;
1015 WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1016 WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1017 WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1018 WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1019 WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1020 WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1021 WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1022 WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1023 WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1024 WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1025 WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1026 WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1027 WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1028 WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1029 for (i = 0; i < 7; i++)
1030 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1033 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1038 for (i = 0; i < rdev->usec_timeout; i++) {
1039 /* read MC_STATUS */
1040 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1048 static void r600_mc_program(struct radeon_device *rdev)
1050 struct rv515_mc_save save;
1054 /* Initialize HDP */
1055 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1056 WREG32((0x2c14 + j), 0x00000000);
1057 WREG32((0x2c18 + j), 0x00000000);
1058 WREG32((0x2c1c + j), 0x00000000);
1059 WREG32((0x2c20 + j), 0x00000000);
1060 WREG32((0x2c24 + j), 0x00000000);
1062 WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1064 rv515_mc_stop(rdev, &save);
1065 if (r600_mc_wait_for_idle(rdev)) {
1066 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1068 /* Lockout access through VGA aperture (doesn't exist before R600) */
1069 WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1070 /* Update configuration */
1071 if (rdev->flags & RADEON_IS_AGP) {
1072 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1073 /* VRAM before AGP */
1074 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1075 rdev->mc.vram_start >> 12);
1076 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1077 rdev->mc.gtt_end >> 12);
1079 /* VRAM after AGP */
1080 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1081 rdev->mc.gtt_start >> 12);
1082 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1083 rdev->mc.vram_end >> 12);
1086 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1087 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1089 WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1090 tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1091 tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1092 WREG32(MC_VM_FB_LOCATION, tmp);
1093 WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1094 WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1095 WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
1096 if (rdev->flags & RADEON_IS_AGP) {
1097 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1098 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1099 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1101 WREG32(MC_VM_AGP_BASE, 0);
1102 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1103 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1105 if (r600_mc_wait_for_idle(rdev)) {
1106 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1108 rv515_mc_resume(rdev, &save);
1109 /* we need to own VRAM, so turn off the VGA renderer here
1110 * to stop it overwriting our objects */
1111 rv515_vga_render_disable(rdev);
1115 * r600_vram_gtt_location - try to find VRAM & GTT location
1116 * @rdev: radeon device structure holding all necessary informations
1117 * @mc: memory controller structure holding memory informations
1119 * Function will place try to place VRAM at same place as in CPU (PCI)
1120 * address space as some GPU seems to have issue when we reprogram at
1121 * different address space.
1123 * If there is not enough space to fit the unvisible VRAM after the
1124 * aperture then we limit the VRAM size to the aperture.
1126 * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1127 * them to be in one from GPU point of view so that we can program GPU to
1128 * catch access outside them (weird GPU policy see ??).
1130 * This function will never fails, worst case are limiting VRAM or GTT.
1132 * Note: GTT start, end, size should be initialized before calling this
1133 * function on AGP platform.
1135 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1137 u64 size_bf, size_af;
1139 if (mc->mc_vram_size > 0xE0000000) {
1140 /* leave room for at least 512M GTT */
1141 dev_warn(rdev->dev, "limiting VRAM\n");
1142 mc->real_vram_size = 0xE0000000;
1143 mc->mc_vram_size = 0xE0000000;
1145 if (rdev->flags & RADEON_IS_AGP) {
1146 size_bf = mc->gtt_start;
1147 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1148 if (size_bf > size_af) {
1149 if (mc->mc_vram_size > size_bf) {
1150 dev_warn(rdev->dev, "limiting VRAM\n");
1151 mc->real_vram_size = size_bf;
1152 mc->mc_vram_size = size_bf;
1154 mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1156 if (mc->mc_vram_size > size_af) {
1157 dev_warn(rdev->dev, "limiting VRAM\n");
1158 mc->real_vram_size = size_af;
1159 mc->mc_vram_size = size_af;
1161 mc->vram_start = mc->gtt_end;
1163 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1164 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1165 mc->mc_vram_size >> 20, mc->vram_start,
1166 mc->vram_end, mc->real_vram_size >> 20);
1169 if (rdev->flags & RADEON_IS_IGP)
1170 base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1171 radeon_vram_location(rdev, &rdev->mc, base);
1172 radeon_gtt_location(rdev, mc);
1176 int r600_mc_init(struct radeon_device *rdev)
1179 int chansize, numchan;
1181 /* Get VRAM informations */
1182 rdev->mc.vram_is_ddr = true;
1183 tmp = RREG32(RAMCFG);
1184 if (tmp & CHANSIZE_OVERRIDE) {
1186 } else if (tmp & CHANSIZE_MASK) {
1191 tmp = RREG32(CHMAP);
1192 switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1207 rdev->mc.vram_width = numchan * chansize;
1208 /* Could aper size report 0 ? */
1209 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1210 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1211 /* Setup GPU memory space */
1212 rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1213 rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1214 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1215 r600_vram_gtt_location(rdev, &rdev->mc);
1217 if (rdev->flags & RADEON_IS_IGP)
1218 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1219 radeon_update_bandwidth_info(rdev);
1223 /* We doesn't check that the GPU really needs a reset we simply do the
1224 * reset, it's up to the caller to determine if the GPU needs one. We
1225 * might add an helper function to check that.
1227 int r600_gpu_soft_reset(struct radeon_device *rdev)
1229 struct rv515_mc_save save;
1230 u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1231 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1232 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1233 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1234 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1235 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1236 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1237 S_008010_GUI_ACTIVE(1);
1238 u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1239 S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1240 S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1241 S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1242 S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1243 S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1244 S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1245 S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1248 dev_info(rdev->dev, "GPU softreset \n");
1249 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1250 RREG32(R_008010_GRBM_STATUS));
1251 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1252 RREG32(R_008014_GRBM_STATUS2));
1253 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1254 RREG32(R_000E50_SRBM_STATUS));
1255 rv515_mc_stop(rdev, &save);
1256 if (r600_mc_wait_for_idle(rdev)) {
1257 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1259 /* Disable CP parsing/prefetching */
1260 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1261 /* Check if any of the rendering block is busy and reset it */
1262 if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1263 (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1264 tmp = S_008020_SOFT_RESET_CR(1) |
1265 S_008020_SOFT_RESET_DB(1) |
1266 S_008020_SOFT_RESET_CB(1) |
1267 S_008020_SOFT_RESET_PA(1) |
1268 S_008020_SOFT_RESET_SC(1) |
1269 S_008020_SOFT_RESET_SMX(1) |
1270 S_008020_SOFT_RESET_SPI(1) |
1271 S_008020_SOFT_RESET_SX(1) |
1272 S_008020_SOFT_RESET_SH(1) |
1273 S_008020_SOFT_RESET_TC(1) |
1274 S_008020_SOFT_RESET_TA(1) |
1275 S_008020_SOFT_RESET_VC(1) |
1276 S_008020_SOFT_RESET_VGT(1);
1277 dev_info(rdev->dev, " R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1278 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1279 RREG32(R_008020_GRBM_SOFT_RESET);
1281 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1283 /* Reset CP (we always reset CP) */
1284 tmp = S_008020_SOFT_RESET_CP(1);
1285 dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1286 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1287 RREG32(R_008020_GRBM_SOFT_RESET);
1289 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1290 /* Wait a little for things to settle down */
1292 dev_info(rdev->dev, " R_008010_GRBM_STATUS=0x%08X\n",
1293 RREG32(R_008010_GRBM_STATUS));
1294 dev_info(rdev->dev, " R_008014_GRBM_STATUS2=0x%08X\n",
1295 RREG32(R_008014_GRBM_STATUS2));
1296 dev_info(rdev->dev, " R_000E50_SRBM_STATUS=0x%08X\n",
1297 RREG32(R_000E50_SRBM_STATUS));
1298 rv515_mc_resume(rdev, &save);
1302 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1309 srbm_status = RREG32(R_000E50_SRBM_STATUS);
1310 grbm_status = RREG32(R_008010_GRBM_STATUS);
1311 grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1312 if (!G_008010_GUI_ACTIVE(grbm_status)) {
1313 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1316 /* force CP activities */
1317 r = radeon_ring_lock(rdev, 2);
1320 radeon_ring_write(rdev, 0x80000000);
1321 radeon_ring_write(rdev, 0x80000000);
1322 radeon_ring_unlock_commit(rdev);
1324 rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1325 return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1328 int r600_asic_reset(struct radeon_device *rdev)
1330 return r600_gpu_soft_reset(rdev);
1333 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1335 u32 backend_disable_mask)
1337 u32 backend_map = 0;
1338 u32 enabled_backends_mask;
1339 u32 enabled_backends_count;
1341 u32 swizzle_pipe[R6XX_MAX_PIPES];
1345 if (num_tile_pipes > R6XX_MAX_PIPES)
1346 num_tile_pipes = R6XX_MAX_PIPES;
1347 if (num_tile_pipes < 1)
1349 if (num_backends > R6XX_MAX_BACKENDS)
1350 num_backends = R6XX_MAX_BACKENDS;
1351 if (num_backends < 1)
1354 enabled_backends_mask = 0;
1355 enabled_backends_count = 0;
1356 for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1357 if (((backend_disable_mask >> i) & 1) == 0) {
1358 enabled_backends_mask |= (1 << i);
1359 ++enabled_backends_count;
1361 if (enabled_backends_count == num_backends)
1365 if (enabled_backends_count == 0) {
1366 enabled_backends_mask = 1;
1367 enabled_backends_count = 1;
1370 if (enabled_backends_count != num_backends)
1371 num_backends = enabled_backends_count;
1373 memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1374 switch (num_tile_pipes) {
1376 swizzle_pipe[0] = 0;
1379 swizzle_pipe[0] = 0;
1380 swizzle_pipe[1] = 1;
1383 swizzle_pipe[0] = 0;
1384 swizzle_pipe[1] = 1;
1385 swizzle_pipe[2] = 2;
1388 swizzle_pipe[0] = 0;
1389 swizzle_pipe[1] = 1;
1390 swizzle_pipe[2] = 2;
1391 swizzle_pipe[3] = 3;
1394 swizzle_pipe[0] = 0;
1395 swizzle_pipe[1] = 1;
1396 swizzle_pipe[2] = 2;
1397 swizzle_pipe[3] = 3;
1398 swizzle_pipe[4] = 4;
1401 swizzle_pipe[0] = 0;
1402 swizzle_pipe[1] = 2;
1403 swizzle_pipe[2] = 4;
1404 swizzle_pipe[3] = 5;
1405 swizzle_pipe[4] = 1;
1406 swizzle_pipe[5] = 3;
1409 swizzle_pipe[0] = 0;
1410 swizzle_pipe[1] = 2;
1411 swizzle_pipe[2] = 4;
1412 swizzle_pipe[3] = 6;
1413 swizzle_pipe[4] = 1;
1414 swizzle_pipe[5] = 3;
1415 swizzle_pipe[6] = 5;
1418 swizzle_pipe[0] = 0;
1419 swizzle_pipe[1] = 2;
1420 swizzle_pipe[2] = 4;
1421 swizzle_pipe[3] = 6;
1422 swizzle_pipe[4] = 1;
1423 swizzle_pipe[5] = 3;
1424 swizzle_pipe[6] = 5;
1425 swizzle_pipe[7] = 7;
1430 for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1431 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1432 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1434 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1436 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1442 int r600_count_pipe_bits(uint32_t val)
1446 for (i = 0; i < 32; i++) {
1453 void r600_gpu_init(struct radeon_device *rdev)
1458 u32 cc_rb_backend_disable;
1459 u32 cc_gc_shader_pipe_config;
1463 u32 sq_gpr_resource_mgmt_1 = 0;
1464 u32 sq_gpr_resource_mgmt_2 = 0;
1465 u32 sq_thread_resource_mgmt = 0;
1466 u32 sq_stack_resource_mgmt_1 = 0;
1467 u32 sq_stack_resource_mgmt_2 = 0;
1469 /* FIXME: implement */
1470 switch (rdev->family) {
1472 rdev->config.r600.max_pipes = 4;
1473 rdev->config.r600.max_tile_pipes = 8;
1474 rdev->config.r600.max_simds = 4;
1475 rdev->config.r600.max_backends = 4;
1476 rdev->config.r600.max_gprs = 256;
1477 rdev->config.r600.max_threads = 192;
1478 rdev->config.r600.max_stack_entries = 256;
1479 rdev->config.r600.max_hw_contexts = 8;
1480 rdev->config.r600.max_gs_threads = 16;
1481 rdev->config.r600.sx_max_export_size = 128;
1482 rdev->config.r600.sx_max_export_pos_size = 16;
1483 rdev->config.r600.sx_max_export_smx_size = 128;
1484 rdev->config.r600.sq_num_cf_insts = 2;
1488 rdev->config.r600.max_pipes = 2;
1489 rdev->config.r600.max_tile_pipes = 2;
1490 rdev->config.r600.max_simds = 3;
1491 rdev->config.r600.max_backends = 1;
1492 rdev->config.r600.max_gprs = 128;
1493 rdev->config.r600.max_threads = 192;
1494 rdev->config.r600.max_stack_entries = 128;
1495 rdev->config.r600.max_hw_contexts = 8;
1496 rdev->config.r600.max_gs_threads = 4;
1497 rdev->config.r600.sx_max_export_size = 128;
1498 rdev->config.r600.sx_max_export_pos_size = 16;
1499 rdev->config.r600.sx_max_export_smx_size = 128;
1500 rdev->config.r600.sq_num_cf_insts = 2;
1506 rdev->config.r600.max_pipes = 1;
1507 rdev->config.r600.max_tile_pipes = 1;
1508 rdev->config.r600.max_simds = 2;
1509 rdev->config.r600.max_backends = 1;
1510 rdev->config.r600.max_gprs = 128;
1511 rdev->config.r600.max_threads = 192;
1512 rdev->config.r600.max_stack_entries = 128;
1513 rdev->config.r600.max_hw_contexts = 4;
1514 rdev->config.r600.max_gs_threads = 4;
1515 rdev->config.r600.sx_max_export_size = 128;
1516 rdev->config.r600.sx_max_export_pos_size = 16;
1517 rdev->config.r600.sx_max_export_smx_size = 128;
1518 rdev->config.r600.sq_num_cf_insts = 1;
1521 rdev->config.r600.max_pipes = 4;
1522 rdev->config.r600.max_tile_pipes = 4;
1523 rdev->config.r600.max_simds = 4;
1524 rdev->config.r600.max_backends = 4;
1525 rdev->config.r600.max_gprs = 192;
1526 rdev->config.r600.max_threads = 192;
1527 rdev->config.r600.max_stack_entries = 256;
1528 rdev->config.r600.max_hw_contexts = 8;
1529 rdev->config.r600.max_gs_threads = 16;
1530 rdev->config.r600.sx_max_export_size = 128;
1531 rdev->config.r600.sx_max_export_pos_size = 16;
1532 rdev->config.r600.sx_max_export_smx_size = 128;
1533 rdev->config.r600.sq_num_cf_insts = 2;
1539 /* Initialize HDP */
1540 for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1541 WREG32((0x2c14 + j), 0x00000000);
1542 WREG32((0x2c18 + j), 0x00000000);
1543 WREG32((0x2c1c + j), 0x00000000);
1544 WREG32((0x2c20 + j), 0x00000000);
1545 WREG32((0x2c24 + j), 0x00000000);
1548 WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1552 ramcfg = RREG32(RAMCFG);
1553 switch (rdev->config.r600.max_tile_pipes) {
1555 tiling_config |= PIPE_TILING(0);
1558 tiling_config |= PIPE_TILING(1);
1561 tiling_config |= PIPE_TILING(2);
1564 tiling_config |= PIPE_TILING(3);
1569 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1570 rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1571 tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1572 tiling_config |= GROUP_SIZE(0);
1573 rdev->config.r600.tiling_group_size = 256;
1574 tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1576 tiling_config |= ROW_TILING(3);
1577 tiling_config |= SAMPLE_SPLIT(3);
1579 tiling_config |= ROW_TILING(tmp);
1580 tiling_config |= SAMPLE_SPLIT(tmp);
1582 tiling_config |= BANK_SWAPS(1);
1584 cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1585 cc_rb_backend_disable |=
1586 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1588 cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1589 cc_gc_shader_pipe_config |=
1590 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1591 cc_gc_shader_pipe_config |=
1592 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1594 backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1595 (R6XX_MAX_BACKENDS -
1596 r600_count_pipe_bits((cc_rb_backend_disable &
1597 R6XX_MAX_BACKENDS_MASK) >> 16)),
1598 (cc_rb_backend_disable >> 16));
1600 tiling_config |= BACKEND_MAP(backend_map);
1601 WREG32(GB_TILING_CONFIG, tiling_config);
1602 WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1603 WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1606 WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1607 WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1608 WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1610 tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1611 WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1612 WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1614 /* Setup some CP states */
1615 WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1616 WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1618 WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1619 SYNC_WALKER | SYNC_ALIGNER));
1620 /* Setup various GPU states */
1621 if (rdev->family == CHIP_RV670)
1622 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1624 tmp = RREG32(SX_DEBUG_1);
1625 tmp |= SMX_EVENT_RELEASE;
1626 if ((rdev->family > CHIP_R600))
1627 tmp |= ENABLE_NEW_SMX_ADDRESS;
1628 WREG32(SX_DEBUG_1, tmp);
1630 if (((rdev->family) == CHIP_R600) ||
1631 ((rdev->family) == CHIP_RV630) ||
1632 ((rdev->family) == CHIP_RV610) ||
1633 ((rdev->family) == CHIP_RV620) ||
1634 ((rdev->family) == CHIP_RS780) ||
1635 ((rdev->family) == CHIP_RS880)) {
1636 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1638 WREG32(DB_DEBUG, 0);
1640 WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1641 DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1643 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1644 WREG32(VGT_NUM_INSTANCES, 0);
1646 WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1647 WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1649 tmp = RREG32(SQ_MS_FIFO_SIZES);
1650 if (((rdev->family) == CHIP_RV610) ||
1651 ((rdev->family) == CHIP_RV620) ||
1652 ((rdev->family) == CHIP_RS780) ||
1653 ((rdev->family) == CHIP_RS880)) {
1654 tmp = (CACHE_FIFO_SIZE(0xa) |
1655 FETCH_FIFO_HIWATER(0xa) |
1656 DONE_FIFO_HIWATER(0xe0) |
1657 ALU_UPDATE_FIFO_HIWATER(0x8));
1658 } else if (((rdev->family) == CHIP_R600) ||
1659 ((rdev->family) == CHIP_RV630)) {
1660 tmp &= ~DONE_FIFO_HIWATER(0xff);
1661 tmp |= DONE_FIFO_HIWATER(0x4);
1663 WREG32(SQ_MS_FIFO_SIZES, tmp);
1665 /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1666 * should be adjusted as needed by the 2D/3D drivers. This just sets default values
1668 sq_config = RREG32(SQ_CONFIG);
1669 sq_config &= ~(PS_PRIO(3) |
1673 sq_config |= (DX9_CONSTS |
1680 if ((rdev->family) == CHIP_R600) {
1681 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1683 NUM_CLAUSE_TEMP_GPRS(4));
1684 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1686 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1687 NUM_VS_THREADS(48) |
1690 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1691 NUM_VS_STACK_ENTRIES(128));
1692 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1693 NUM_ES_STACK_ENTRIES(0));
1694 } else if (((rdev->family) == CHIP_RV610) ||
1695 ((rdev->family) == CHIP_RV620) ||
1696 ((rdev->family) == CHIP_RS780) ||
1697 ((rdev->family) == CHIP_RS880)) {
1698 /* no vertex cache */
1699 sq_config &= ~VC_ENABLE;
1701 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1703 NUM_CLAUSE_TEMP_GPRS(2));
1704 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1706 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1707 NUM_VS_THREADS(78) |
1709 NUM_ES_THREADS(31));
1710 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1711 NUM_VS_STACK_ENTRIES(40));
1712 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1713 NUM_ES_STACK_ENTRIES(16));
1714 } else if (((rdev->family) == CHIP_RV630) ||
1715 ((rdev->family) == CHIP_RV635)) {
1716 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1718 NUM_CLAUSE_TEMP_GPRS(2));
1719 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1721 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1722 NUM_VS_THREADS(78) |
1724 NUM_ES_THREADS(31));
1725 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1726 NUM_VS_STACK_ENTRIES(40));
1727 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1728 NUM_ES_STACK_ENTRIES(16));
1729 } else if ((rdev->family) == CHIP_RV670) {
1730 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1732 NUM_CLAUSE_TEMP_GPRS(2));
1733 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1735 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1736 NUM_VS_THREADS(78) |
1738 NUM_ES_THREADS(31));
1739 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1740 NUM_VS_STACK_ENTRIES(64));
1741 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1742 NUM_ES_STACK_ENTRIES(64));
1745 WREG32(SQ_CONFIG, sq_config);
1746 WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1747 WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1748 WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1749 WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1750 WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1752 if (((rdev->family) == CHIP_RV610) ||
1753 ((rdev->family) == CHIP_RV620) ||
1754 ((rdev->family) == CHIP_RS780) ||
1755 ((rdev->family) == CHIP_RS880)) {
1756 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1758 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1761 /* More default values. 2D/3D driver should adjust as needed */
1762 WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1763 S1_X(0x4) | S1_Y(0xc)));
1764 WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1765 S1_X(0x2) | S1_Y(0x2) |
1766 S2_X(0xa) | S2_Y(0x6) |
1767 S3_X(0x6) | S3_Y(0xa)));
1768 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1769 S1_X(0x4) | S1_Y(0xc) |
1770 S2_X(0x1) | S2_Y(0x6) |
1771 S3_X(0xa) | S3_Y(0xe)));
1772 WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1773 S5_X(0x0) | S5_Y(0x0) |
1774 S6_X(0xb) | S6_Y(0x4) |
1775 S7_X(0x7) | S7_Y(0x8)));
1777 WREG32(VGT_STRMOUT_EN, 0);
1778 tmp = rdev->config.r600.max_pipes * 16;
1779 switch (rdev->family) {
1795 WREG32(VGT_ES_PER_GS, 128);
1796 WREG32(VGT_GS_PER_ES, tmp);
1797 WREG32(VGT_GS_PER_VS, 2);
1798 WREG32(VGT_GS_VERTEX_REUSE, 16);
1800 /* more default values. 2D/3D driver should adjust as needed */
1801 WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1802 WREG32(VGT_STRMOUT_EN, 0);
1804 WREG32(PA_SC_MODE_CNTL, 0);
1805 WREG32(PA_SC_AA_CONFIG, 0);
1806 WREG32(PA_SC_LINE_STIPPLE, 0);
1807 WREG32(SPI_INPUT_Z, 0);
1808 WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1809 WREG32(CB_COLOR7_FRAG, 0);
1811 /* Clear render buffer base addresses */
1812 WREG32(CB_COLOR0_BASE, 0);
1813 WREG32(CB_COLOR1_BASE, 0);
1814 WREG32(CB_COLOR2_BASE, 0);
1815 WREG32(CB_COLOR3_BASE, 0);
1816 WREG32(CB_COLOR4_BASE, 0);
1817 WREG32(CB_COLOR5_BASE, 0);
1818 WREG32(CB_COLOR6_BASE, 0);
1819 WREG32(CB_COLOR7_BASE, 0);
1820 WREG32(CB_COLOR7_FRAG, 0);
1822 switch (rdev->family) {
1827 tmp = TC_L2_SIZE(8);
1831 tmp = TC_L2_SIZE(4);
1834 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1837 tmp = TC_L2_SIZE(0);
1840 WREG32(TC_CNTL, tmp);
1842 tmp = RREG32(HDP_HOST_PATH_CNTL);
1843 WREG32(HDP_HOST_PATH_CNTL, tmp);
1845 tmp = RREG32(ARB_POP);
1846 tmp |= ENABLE_TC128;
1847 WREG32(ARB_POP, tmp);
1849 WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1850 WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1852 WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1857 * Indirect registers accessor
1859 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1863 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1864 (void)RREG32(PCIE_PORT_INDEX);
1865 r = RREG32(PCIE_PORT_DATA);
1869 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1871 WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1872 (void)RREG32(PCIE_PORT_INDEX);
1873 WREG32(PCIE_PORT_DATA, (v));
1874 (void)RREG32(PCIE_PORT_DATA);
1880 void r600_cp_stop(struct radeon_device *rdev)
1882 WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1885 int r600_init_microcode(struct radeon_device *rdev)
1887 struct platform_device *pdev;
1888 const char *chip_name;
1889 const char *rlc_chip_name;
1890 size_t pfp_req_size, me_req_size, rlc_req_size;
1896 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1899 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1903 switch (rdev->family) {
1906 rlc_chip_name = "R600";
1909 chip_name = "RV610";
1910 rlc_chip_name = "R600";
1913 chip_name = "RV630";
1914 rlc_chip_name = "R600";
1917 chip_name = "RV620";
1918 rlc_chip_name = "R600";
1921 chip_name = "RV635";
1922 rlc_chip_name = "R600";
1925 chip_name = "RV670";
1926 rlc_chip_name = "R600";
1930 chip_name = "RS780";
1931 rlc_chip_name = "R600";
1934 chip_name = "RV770";
1935 rlc_chip_name = "R700";
1939 chip_name = "RV730";
1940 rlc_chip_name = "R700";
1943 chip_name = "RV710";
1944 rlc_chip_name = "R700";
1947 chip_name = "CEDAR";
1948 rlc_chip_name = "CEDAR";
1951 chip_name = "REDWOOD";
1952 rlc_chip_name = "REDWOOD";
1955 chip_name = "JUNIPER";
1956 rlc_chip_name = "JUNIPER";
1960 chip_name = "CYPRESS";
1961 rlc_chip_name = "CYPRESS";
1966 if (rdev->family >= CHIP_CEDAR) {
1967 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1968 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1969 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1970 } else if (rdev->family >= CHIP_RV770) {
1971 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1972 me_req_size = R700_PM4_UCODE_SIZE * 4;
1973 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1975 pfp_req_size = PFP_UCODE_SIZE * 4;
1976 me_req_size = PM4_UCODE_SIZE * 12;
1977 rlc_req_size = RLC_UCODE_SIZE * 4;
1980 DRM_INFO("Loading %s Microcode\n", chip_name);
1982 snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1983 err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1986 if (rdev->pfp_fw->size != pfp_req_size) {
1988 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1989 rdev->pfp_fw->size, fw_name);
1994 snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1995 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1998 if (rdev->me_fw->size != me_req_size) {
2000 "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2001 rdev->me_fw->size, fw_name);
2005 snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2006 err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2009 if (rdev->rlc_fw->size != rlc_req_size) {
2011 "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2012 rdev->rlc_fw->size, fw_name);
2017 platform_device_unregister(pdev);
2022 "r600_cp: Failed to load firmware \"%s\"\n",
2024 release_firmware(rdev->pfp_fw);
2025 rdev->pfp_fw = NULL;
2026 release_firmware(rdev->me_fw);
2028 release_firmware(rdev->rlc_fw);
2029 rdev->rlc_fw = NULL;
2034 static int r600_cp_load_microcode(struct radeon_device *rdev)
2036 const __be32 *fw_data;
2039 if (!rdev->me_fw || !rdev->pfp_fw)
2044 WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2047 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2048 RREG32(GRBM_SOFT_RESET);
2050 WREG32(GRBM_SOFT_RESET, 0);
2052 WREG32(CP_ME_RAM_WADDR, 0);
2054 fw_data = (const __be32 *)rdev->me_fw->data;
2055 WREG32(CP_ME_RAM_WADDR, 0);
2056 for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2057 WREG32(CP_ME_RAM_DATA,
2058 be32_to_cpup(fw_data++));
2060 fw_data = (const __be32 *)rdev->pfp_fw->data;
2061 WREG32(CP_PFP_UCODE_ADDR, 0);
2062 for (i = 0; i < PFP_UCODE_SIZE; i++)
2063 WREG32(CP_PFP_UCODE_DATA,
2064 be32_to_cpup(fw_data++));
2066 WREG32(CP_PFP_UCODE_ADDR, 0);
2067 WREG32(CP_ME_RAM_WADDR, 0);
2068 WREG32(CP_ME_RAM_RADDR, 0);
2072 int r600_cp_start(struct radeon_device *rdev)
2077 r = radeon_ring_lock(rdev, 7);
2079 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2082 radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2083 radeon_ring_write(rdev, 0x1);
2084 if (rdev->family >= CHIP_CEDAR) {
2085 radeon_ring_write(rdev, 0x0);
2086 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2087 } else if (rdev->family >= CHIP_RV770) {
2088 radeon_ring_write(rdev, 0x0);
2089 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2091 radeon_ring_write(rdev, 0x3);
2092 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2094 radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2095 radeon_ring_write(rdev, 0);
2096 radeon_ring_write(rdev, 0);
2097 radeon_ring_unlock_commit(rdev);
2100 WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2104 int r600_cp_resume(struct radeon_device *rdev)
2111 WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2112 RREG32(GRBM_SOFT_RESET);
2114 WREG32(GRBM_SOFT_RESET, 0);
2116 /* Set ring buffer size */
2117 rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2118 tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2120 tmp |= BUF_SWAP_32BIT;
2122 WREG32(CP_RB_CNTL, tmp);
2123 WREG32(CP_SEM_WAIT_TIMER, 0x4);
2125 /* Set the write pointer delay */
2126 WREG32(CP_RB_WPTR_DELAY, 0);
2128 /* Initialize the ring buffer's read and write pointers */
2129 WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2130 WREG32(CP_RB_RPTR_WR, 0);
2131 WREG32(CP_RB_WPTR, 0);
2132 WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2133 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2135 WREG32(CP_RB_CNTL, tmp);
2137 WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2138 WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2140 rdev->cp.rptr = RREG32(CP_RB_RPTR);
2141 rdev->cp.wptr = RREG32(CP_RB_WPTR);
2143 r600_cp_start(rdev);
2144 rdev->cp.ready = true;
2145 r = radeon_ring_test(rdev);
2147 rdev->cp.ready = false;
2153 void r600_cp_commit(struct radeon_device *rdev)
2155 WREG32(CP_RB_WPTR, rdev->cp.wptr);
2156 (void)RREG32(CP_RB_WPTR);
2159 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2163 /* Align ring size */
2164 rb_bufsz = drm_order(ring_size / 8);
2165 ring_size = (1 << (rb_bufsz + 1)) * 4;
2166 rdev->cp.ring_size = ring_size;
2167 rdev->cp.align_mask = 16 - 1;
2170 void r600_cp_fini(struct radeon_device *rdev)
2173 radeon_ring_fini(rdev);
2178 * GPU scratch registers helpers function.
2180 void r600_scratch_init(struct radeon_device *rdev)
2184 rdev->scratch.num_reg = 7;
2185 for (i = 0; i < rdev->scratch.num_reg; i++) {
2186 rdev->scratch.free[i] = true;
2187 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2191 int r600_ring_test(struct radeon_device *rdev)
2198 r = radeon_scratch_get(rdev, &scratch);
2200 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2203 WREG32(scratch, 0xCAFEDEAD);
2204 r = radeon_ring_lock(rdev, 3);
2206 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2207 radeon_scratch_free(rdev, scratch);
2210 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2211 radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2212 radeon_ring_write(rdev, 0xDEADBEEF);
2213 radeon_ring_unlock_commit(rdev);
2214 for (i = 0; i < rdev->usec_timeout; i++) {
2215 tmp = RREG32(scratch);
2216 if (tmp == 0xDEADBEEF)
2220 if (i < rdev->usec_timeout) {
2221 DRM_INFO("ring test succeeded in %d usecs\n", i);
2223 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2227 radeon_scratch_free(rdev, scratch);
2231 void r600_wb_disable(struct radeon_device *rdev)
2235 WREG32(SCRATCH_UMSK, 0);
2236 if (rdev->wb.wb_obj) {
2237 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2238 if (unlikely(r != 0))
2240 radeon_bo_kunmap(rdev->wb.wb_obj);
2241 radeon_bo_unpin(rdev->wb.wb_obj);
2242 radeon_bo_unreserve(rdev->wb.wb_obj);
2246 void r600_wb_fini(struct radeon_device *rdev)
2248 r600_wb_disable(rdev);
2249 if (rdev->wb.wb_obj) {
2250 radeon_bo_unref(&rdev->wb.wb_obj);
2252 rdev->wb.wb_obj = NULL;
2256 int r600_wb_enable(struct radeon_device *rdev)
2260 if (rdev->wb.wb_obj == NULL) {
2261 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2262 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2264 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2267 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2268 if (unlikely(r != 0)) {
2272 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2273 &rdev->wb.gpu_addr);
2275 radeon_bo_unreserve(rdev->wb.wb_obj);
2276 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2280 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2281 radeon_bo_unreserve(rdev->wb.wb_obj);
2283 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2288 WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2289 WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2290 WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2291 WREG32(SCRATCH_UMSK, 0xff);
2295 void r600_fence_ring_emit(struct radeon_device *rdev,
2296 struct radeon_fence *fence)
2298 /* Also consider EVENT_WRITE_EOP. it handles the interrupts + timestamps + events */
2300 radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2301 radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2302 /* wait for 3D idle clean */
2303 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2304 radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2305 radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2306 /* Emit fence sequence & fire IRQ */
2307 radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2308 radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2309 radeon_ring_write(rdev, fence->seq);
2310 /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2311 radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2312 radeon_ring_write(rdev, RB_INT_STAT);
2315 int r600_copy_blit(struct radeon_device *rdev,
2316 uint64_t src_offset, uint64_t dst_offset,
2317 unsigned num_pages, struct radeon_fence *fence)
2321 mutex_lock(&rdev->r600_blit.mutex);
2322 rdev->r600_blit.vb_ib = NULL;
2323 r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2325 if (rdev->r600_blit.vb_ib)
2326 radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2327 mutex_unlock(&rdev->r600_blit.mutex);
2330 r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2331 r600_blit_done_copy(rdev, fence);
2332 mutex_unlock(&rdev->r600_blit.mutex);
2336 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2337 uint32_t tiling_flags, uint32_t pitch,
2338 uint32_t offset, uint32_t obj_size)
2340 /* FIXME: implement */
2344 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2346 /* FIXME: implement */
2350 bool r600_card_posted(struct radeon_device *rdev)
2354 /* first check CRTCs */
2355 reg = RREG32(D1CRTC_CONTROL) |
2356 RREG32(D2CRTC_CONTROL);
2360 /* then check MEM_SIZE, in case the crtcs are off */
2361 if (RREG32(CONFIG_MEMSIZE))
2367 int r600_startup(struct radeon_device *rdev)
2371 if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2372 r = r600_init_microcode(rdev);
2374 DRM_ERROR("Failed to load firmware!\n");
2379 r600_mc_program(rdev);
2380 if (rdev->flags & RADEON_IS_AGP) {
2381 r600_agp_enable(rdev);
2383 r = r600_pcie_gart_enable(rdev);
2387 r600_gpu_init(rdev);
2388 r = r600_blit_init(rdev);
2390 r600_blit_fini(rdev);
2391 rdev->asic->copy = NULL;
2392 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2394 /* pin copy shader into vram */
2395 if (rdev->r600_blit.shader_obj) {
2396 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2397 if (unlikely(r != 0))
2399 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2400 &rdev->r600_blit.shader_gpu_addr);
2401 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2403 dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2408 r = r600_irq_init(rdev);
2410 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2411 radeon_irq_kms_fini(rdev);
2416 r = radeon_ring_init(rdev, rdev->cp.ring_size);
2419 r = r600_cp_load_microcode(rdev);
2422 r = r600_cp_resume(rdev);
2425 /* write back buffer are not vital so don't worry about failure */
2426 r600_wb_enable(rdev);
2430 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2434 temp = RREG32(CONFIG_CNTL);
2435 if (state == false) {
2441 WREG32(CONFIG_CNTL, temp);
2444 int r600_resume(struct radeon_device *rdev)
2448 /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2449 * posting will perform necessary task to bring back GPU into good
2453 atom_asic_init(rdev->mode_info.atom_context);
2454 /* Initialize clocks */
2455 r = radeon_clocks_init(rdev);
2460 r = r600_startup(rdev);
2462 DRM_ERROR("r600 startup failed on resume\n");
2466 r = r600_ib_test(rdev);
2468 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2472 r = r600_audio_init(rdev);
2474 DRM_ERROR("radeon: audio resume failed\n");
2481 int r600_suspend(struct radeon_device *rdev)
2485 r600_audio_fini(rdev);
2486 /* FIXME: we should wait for ring to be empty */
2488 rdev->cp.ready = false;
2489 r600_irq_suspend(rdev);
2490 r600_wb_disable(rdev);
2491 r600_pcie_gart_disable(rdev);
2492 /* unpin shaders bo */
2493 if (rdev->r600_blit.shader_obj) {
2494 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2496 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2497 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2503 /* Plan is to move initialization in that function and use
2504 * helper function so that radeon_device_init pretty much
2505 * do nothing more than calling asic specific function. This
2506 * should also allow to remove a bunch of callback function
2509 int r600_init(struct radeon_device *rdev)
2513 r = radeon_dummy_page_init(rdev);
2516 if (r600_debugfs_mc_info_init(rdev)) {
2517 DRM_ERROR("Failed to register debugfs file for mc !\n");
2519 /* This don't do much */
2520 r = radeon_gem_init(rdev);
2524 if (!radeon_get_bios(rdev)) {
2525 if (ASIC_IS_AVIVO(rdev))
2528 /* Must be an ATOMBIOS */
2529 if (!rdev->is_atom_bios) {
2530 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2533 r = radeon_atombios_init(rdev);
2536 /* Post card if necessary */
2537 if (!r600_card_posted(rdev)) {
2539 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2542 DRM_INFO("GPU not posted. posting now...\n");
2543 atom_asic_init(rdev->mode_info.atom_context);
2545 /* Initialize scratch registers */
2546 r600_scratch_init(rdev);
2547 /* Initialize surface registers */
2548 radeon_surface_init(rdev);
2549 /* Initialize clocks */
2550 radeon_get_clock_info(rdev->ddev);
2551 r = radeon_clocks_init(rdev);
2555 r = radeon_fence_driver_init(rdev);
2558 if (rdev->flags & RADEON_IS_AGP) {
2559 r = radeon_agp_init(rdev);
2561 radeon_agp_disable(rdev);
2563 r = r600_mc_init(rdev);
2566 /* Memory manager */
2567 r = radeon_bo_init(rdev);
2571 r = radeon_irq_kms_init(rdev);
2575 rdev->cp.ring_obj = NULL;
2576 r600_ring_init(rdev, 1024 * 1024);
2578 rdev->ih.ring_obj = NULL;
2579 r600_ih_ring_init(rdev, 64 * 1024);
2581 r = r600_pcie_gart_init(rdev);
2585 rdev->accel_working = true;
2586 r = r600_startup(rdev);
2588 dev_err(rdev->dev, "disabling GPU acceleration\n");
2591 r600_irq_fini(rdev);
2592 radeon_irq_kms_fini(rdev);
2593 r600_pcie_gart_fini(rdev);
2594 rdev->accel_working = false;
2596 if (rdev->accel_working) {
2597 r = radeon_ib_pool_init(rdev);
2599 dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2600 rdev->accel_working = false;
2602 r = r600_ib_test(rdev);
2604 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2605 rdev->accel_working = false;
2610 r = r600_audio_init(rdev);
2612 return r; /* TODO error handling */
2616 void r600_fini(struct radeon_device *rdev)
2618 r600_audio_fini(rdev);
2619 r600_blit_fini(rdev);
2622 r600_irq_fini(rdev);
2623 radeon_irq_kms_fini(rdev);
2624 r600_pcie_gart_fini(rdev);
2625 radeon_agp_fini(rdev);
2626 radeon_gem_fini(rdev);
2627 radeon_fence_driver_fini(rdev);
2628 radeon_clocks_fini(rdev);
2629 radeon_bo_fini(rdev);
2630 radeon_atombios_fini(rdev);
2633 radeon_dummy_page_fini(rdev);
2640 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2642 /* FIXME: implement */
2643 radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2644 radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2645 radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2646 radeon_ring_write(rdev, ib->length_dw);
2649 int r600_ib_test(struct radeon_device *rdev)
2651 struct radeon_ib *ib;
2657 r = radeon_scratch_get(rdev, &scratch);
2659 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2662 WREG32(scratch, 0xCAFEDEAD);
2663 r = radeon_ib_get(rdev, &ib);
2665 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2668 ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2669 ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2670 ib->ptr[2] = 0xDEADBEEF;
2671 ib->ptr[3] = PACKET2(0);
2672 ib->ptr[4] = PACKET2(0);
2673 ib->ptr[5] = PACKET2(0);
2674 ib->ptr[6] = PACKET2(0);
2675 ib->ptr[7] = PACKET2(0);
2676 ib->ptr[8] = PACKET2(0);
2677 ib->ptr[9] = PACKET2(0);
2678 ib->ptr[10] = PACKET2(0);
2679 ib->ptr[11] = PACKET2(0);
2680 ib->ptr[12] = PACKET2(0);
2681 ib->ptr[13] = PACKET2(0);
2682 ib->ptr[14] = PACKET2(0);
2683 ib->ptr[15] = PACKET2(0);
2685 r = radeon_ib_schedule(rdev, ib);
2687 radeon_scratch_free(rdev, scratch);
2688 radeon_ib_free(rdev, &ib);
2689 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2692 r = radeon_fence_wait(ib->fence, false);
2694 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2697 for (i = 0; i < rdev->usec_timeout; i++) {
2698 tmp = RREG32(scratch);
2699 if (tmp == 0xDEADBEEF)
2703 if (i < rdev->usec_timeout) {
2704 DRM_INFO("ib test succeeded in %u usecs\n", i);
2706 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2710 radeon_scratch_free(rdev, scratch);
2711 radeon_ib_free(rdev, &ib);
2718 * Interrupts use a ring buffer on r6xx/r7xx hardware. It works pretty
2719 * the same as the CP ring buffer, but in reverse. Rather than the CPU
2720 * writing to the ring and the GPU consuming, the GPU writes to the ring
2721 * and host consumes. As the host irq handler processes interrupts, it
2722 * increments the rptr. When the rptr catches up with the wptr, all the
2723 * current interrupts have been processed.
2726 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2730 /* Align ring size */
2731 rb_bufsz = drm_order(ring_size / 4);
2732 ring_size = (1 << rb_bufsz) * 4;
2733 rdev->ih.ring_size = ring_size;
2734 rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2738 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2742 /* Allocate ring buffer */
2743 if (rdev->ih.ring_obj == NULL) {
2744 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2746 RADEON_GEM_DOMAIN_GTT,
2747 &rdev->ih.ring_obj);
2749 DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2752 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2753 if (unlikely(r != 0))
2755 r = radeon_bo_pin(rdev->ih.ring_obj,
2756 RADEON_GEM_DOMAIN_GTT,
2757 &rdev->ih.gpu_addr);
2759 radeon_bo_unreserve(rdev->ih.ring_obj);
2760 DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2763 r = radeon_bo_kmap(rdev->ih.ring_obj,
2764 (void **)&rdev->ih.ring);
2765 radeon_bo_unreserve(rdev->ih.ring_obj);
2767 DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2774 static void r600_ih_ring_fini(struct radeon_device *rdev)
2777 if (rdev->ih.ring_obj) {
2778 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2779 if (likely(r == 0)) {
2780 radeon_bo_kunmap(rdev->ih.ring_obj);
2781 radeon_bo_unpin(rdev->ih.ring_obj);
2782 radeon_bo_unreserve(rdev->ih.ring_obj);
2784 radeon_bo_unref(&rdev->ih.ring_obj);
2785 rdev->ih.ring = NULL;
2786 rdev->ih.ring_obj = NULL;
2790 void r600_rlc_stop(struct radeon_device *rdev)
2793 if ((rdev->family >= CHIP_RV770) &&
2794 (rdev->family <= CHIP_RV740)) {
2795 /* r7xx asics need to soft reset RLC before halting */
2796 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2797 RREG32(SRBM_SOFT_RESET);
2799 WREG32(SRBM_SOFT_RESET, 0);
2800 RREG32(SRBM_SOFT_RESET);
2803 WREG32(RLC_CNTL, 0);
2806 static void r600_rlc_start(struct radeon_device *rdev)
2808 WREG32(RLC_CNTL, RLC_ENABLE);
2811 static int r600_rlc_init(struct radeon_device *rdev)
2814 const __be32 *fw_data;
2819 r600_rlc_stop(rdev);
2821 WREG32(RLC_HB_BASE, 0);
2822 WREG32(RLC_HB_CNTL, 0);
2823 WREG32(RLC_HB_RPTR, 0);
2824 WREG32(RLC_HB_WPTR, 0);
2825 WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2826 WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2827 WREG32(RLC_MC_CNTL, 0);
2828 WREG32(RLC_UCODE_CNTL, 0);
2830 fw_data = (const __be32 *)rdev->rlc_fw->data;
2831 if (rdev->family >= CHIP_CEDAR) {
2832 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2833 WREG32(RLC_UCODE_ADDR, i);
2834 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2836 } else if (rdev->family >= CHIP_RV770) {
2837 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2838 WREG32(RLC_UCODE_ADDR, i);
2839 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2842 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2843 WREG32(RLC_UCODE_ADDR, i);
2844 WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2847 WREG32(RLC_UCODE_ADDR, 0);
2849 r600_rlc_start(rdev);
2854 static void r600_enable_interrupts(struct radeon_device *rdev)
2856 u32 ih_cntl = RREG32(IH_CNTL);
2857 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2859 ih_cntl |= ENABLE_INTR;
2860 ih_rb_cntl |= IH_RB_ENABLE;
2861 WREG32(IH_CNTL, ih_cntl);
2862 WREG32(IH_RB_CNTL, ih_rb_cntl);
2863 rdev->ih.enabled = true;
2866 void r600_disable_interrupts(struct radeon_device *rdev)
2868 u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2869 u32 ih_cntl = RREG32(IH_CNTL);
2871 ih_rb_cntl &= ~IH_RB_ENABLE;
2872 ih_cntl &= ~ENABLE_INTR;
2873 WREG32(IH_RB_CNTL, ih_rb_cntl);
2874 WREG32(IH_CNTL, ih_cntl);
2875 /* set rptr, wptr to 0 */
2876 WREG32(IH_RB_RPTR, 0);
2877 WREG32(IH_RB_WPTR, 0);
2878 rdev->ih.enabled = false;
2883 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2887 WREG32(CP_INT_CNTL, 0);
2888 WREG32(GRBM_INT_CNTL, 0);
2889 WREG32(DxMODE_INT_MASK, 0);
2890 if (ASIC_IS_DCE3(rdev)) {
2891 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2892 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2893 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2894 WREG32(DC_HPD1_INT_CONTROL, tmp);
2895 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2896 WREG32(DC_HPD2_INT_CONTROL, tmp);
2897 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2898 WREG32(DC_HPD3_INT_CONTROL, tmp);
2899 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2900 WREG32(DC_HPD4_INT_CONTROL, tmp);
2901 if (ASIC_IS_DCE32(rdev)) {
2902 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2903 WREG32(DC_HPD5_INT_CONTROL, tmp);
2904 tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2905 WREG32(DC_HPD6_INT_CONTROL, tmp);
2908 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2909 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2910 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2911 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2912 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2913 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2914 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2915 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2919 int r600_irq_init(struct radeon_device *rdev)
2923 u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2926 ret = r600_ih_ring_alloc(rdev);
2931 r600_disable_interrupts(rdev);
2934 ret = r600_rlc_init(rdev);
2936 r600_ih_ring_fini(rdev);
2940 /* setup interrupt control */
2941 /* set dummy read address to ring address */
2942 WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2943 interrupt_cntl = RREG32(INTERRUPT_CNTL);
2944 /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2945 * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2947 interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2948 /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2949 interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2950 WREG32(INTERRUPT_CNTL, interrupt_cntl);
2952 WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2953 rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2955 ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2956 IH_WPTR_OVERFLOW_CLEAR |
2958 /* WPTR writeback, not yet */
2959 /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2960 WREG32(IH_RB_WPTR_ADDR_LO, 0);
2961 WREG32(IH_RB_WPTR_ADDR_HI, 0);
2963 WREG32(IH_RB_CNTL, ih_rb_cntl);
2965 /* set rptr, wptr to 0 */
2966 WREG32(IH_RB_RPTR, 0);
2967 WREG32(IH_RB_WPTR, 0);
2969 /* Default settings for IH_CNTL (disabled at first) */
2970 ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2971 /* RPTR_REARM only works if msi's are enabled */
2972 if (rdev->msi_enabled)
2973 ih_cntl |= RPTR_REARM;
2976 ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2978 WREG32(IH_CNTL, ih_cntl);
2980 /* force the active interrupt state to all disabled */
2981 if (rdev->family >= CHIP_CEDAR)
2982 evergreen_disable_interrupt_state(rdev);
2984 r600_disable_interrupt_state(rdev);
2987 r600_enable_interrupts(rdev);
2992 void r600_irq_suspend(struct radeon_device *rdev)
2994 r600_irq_disable(rdev);
2995 r600_rlc_stop(rdev);
2998 void r600_irq_fini(struct radeon_device *rdev)
3000 r600_irq_suspend(rdev);
3001 r600_ih_ring_fini(rdev);
3004 int r600_irq_set(struct radeon_device *rdev)
3006 u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3008 u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3009 u32 grbm_int_cntl = 0;
3012 if (!rdev->irq.installed) {
3013 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3016 /* don't enable anything if the ih is disabled */
3017 if (!rdev->ih.enabled) {
3018 r600_disable_interrupts(rdev);
3019 /* force the active interrupt state to all disabled */
3020 r600_disable_interrupt_state(rdev);
3024 hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3025 if (ASIC_IS_DCE3(rdev)) {
3026 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3027 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3028 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3029 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3030 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3031 if (ASIC_IS_DCE32(rdev)) {
3032 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3033 hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3036 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3037 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3039 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042 if (rdev->irq.sw_int) {
3043 DRM_DEBUG("r600_irq_set: sw int\n");
3044 cp_int_cntl |= RB_INT_ENABLE;
3046 if (rdev->irq.crtc_vblank_int[0]) {
3047 DRM_DEBUG("r600_irq_set: vblank 0\n");
3048 mode_int |= D1MODE_VBLANK_INT_MASK;
3050 if (rdev->irq.crtc_vblank_int[1]) {
3051 DRM_DEBUG("r600_irq_set: vblank 1\n");
3052 mode_int |= D2MODE_VBLANK_INT_MASK;
3054 if (rdev->irq.hpd[0]) {
3055 DRM_DEBUG("r600_irq_set: hpd 1\n");
3056 hpd1 |= DC_HPDx_INT_EN;
3058 if (rdev->irq.hpd[1]) {
3059 DRM_DEBUG("r600_irq_set: hpd 2\n");
3060 hpd2 |= DC_HPDx_INT_EN;
3062 if (rdev->irq.hpd[2]) {
3063 DRM_DEBUG("r600_irq_set: hpd 3\n");
3064 hpd3 |= DC_HPDx_INT_EN;
3066 if (rdev->irq.hpd[3]) {
3067 DRM_DEBUG("r600_irq_set: hpd 4\n");
3068 hpd4 |= DC_HPDx_INT_EN;
3070 if (rdev->irq.hpd[4]) {
3071 DRM_DEBUG("r600_irq_set: hpd 5\n");
3072 hpd5 |= DC_HPDx_INT_EN;
3074 if (rdev->irq.hpd[5]) {
3075 DRM_DEBUG("r600_irq_set: hpd 6\n");
3076 hpd6 |= DC_HPDx_INT_EN;
3078 if (rdev->irq.hdmi[0]) {
3079 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3080 hdmi1 |= R600_HDMI_INT_EN;
3082 if (rdev->irq.hdmi[1]) {
3083 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3084 hdmi2 |= R600_HDMI_INT_EN;
3086 if (rdev->irq.gui_idle) {
3087 DRM_DEBUG("gui idle\n");
3088 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3091 WREG32(CP_INT_CNTL, cp_int_cntl);
3092 WREG32(DxMODE_INT_MASK, mode_int);
3093 WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3094 WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3095 if (ASIC_IS_DCE3(rdev)) {
3096 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3097 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3098 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3099 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3100 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3101 if (ASIC_IS_DCE32(rdev)) {
3102 WREG32(DC_HPD5_INT_CONTROL, hpd5);
3103 WREG32(DC_HPD6_INT_CONTROL, hpd6);
3106 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3107 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3108 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3109 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3115 static inline void r600_irq_ack(struct radeon_device *rdev,
3118 u32 *disp_int_cont2)
3122 if (ASIC_IS_DCE3(rdev)) {
3123 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3124 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3125 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3127 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3128 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3129 *disp_int_cont2 = 0;
3132 if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3133 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3134 if (*disp_int & LB_D1_VLINE_INTERRUPT)
3135 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3136 if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3137 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3138 if (*disp_int & LB_D2_VLINE_INTERRUPT)
3139 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3140 if (*disp_int & DC_HPD1_INTERRUPT) {
3141 if (ASIC_IS_DCE3(rdev)) {
3142 tmp = RREG32(DC_HPD1_INT_CONTROL);
3143 tmp |= DC_HPDx_INT_ACK;
3144 WREG32(DC_HPD1_INT_CONTROL, tmp);
3146 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3147 tmp |= DC_HPDx_INT_ACK;
3148 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3151 if (*disp_int & DC_HPD2_INTERRUPT) {
3152 if (ASIC_IS_DCE3(rdev)) {
3153 tmp = RREG32(DC_HPD2_INT_CONTROL);
3154 tmp |= DC_HPDx_INT_ACK;
3155 WREG32(DC_HPD2_INT_CONTROL, tmp);
3157 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3158 tmp |= DC_HPDx_INT_ACK;
3159 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3162 if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3163 if (ASIC_IS_DCE3(rdev)) {
3164 tmp = RREG32(DC_HPD3_INT_CONTROL);
3165 tmp |= DC_HPDx_INT_ACK;
3166 WREG32(DC_HPD3_INT_CONTROL, tmp);
3168 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3169 tmp |= DC_HPDx_INT_ACK;
3170 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3173 if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3174 tmp = RREG32(DC_HPD4_INT_CONTROL);
3175 tmp |= DC_HPDx_INT_ACK;
3176 WREG32(DC_HPD4_INT_CONTROL, tmp);
3178 if (ASIC_IS_DCE32(rdev)) {
3179 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3180 tmp = RREG32(DC_HPD5_INT_CONTROL);
3181 tmp |= DC_HPDx_INT_ACK;
3182 WREG32(DC_HPD5_INT_CONTROL, tmp);
3184 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3185 tmp = RREG32(DC_HPD5_INT_CONTROL);
3186 tmp |= DC_HPDx_INT_ACK;
3187 WREG32(DC_HPD6_INT_CONTROL, tmp);
3190 if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3191 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3193 if (ASIC_IS_DCE3(rdev)) {
3194 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3195 WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3198 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3199 WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3204 void r600_irq_disable(struct radeon_device *rdev)
3206 u32 disp_int, disp_int_cont, disp_int_cont2;
3208 r600_disable_interrupts(rdev);
3209 /* Wait and acknowledge irq */
3211 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3212 r600_disable_interrupt_state(rdev);
3215 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3219 /* XXX use writeback */
3220 wptr = RREG32(IH_RB_WPTR);
3222 if (wptr & RB_OVERFLOW) {
3223 /* When a ring buffer overflow happen start parsing interrupt
3224 * from the last not overwritten vector (wptr + 16). Hopefully
3225 * this should allow us to catchup.
3227 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3228 wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3229 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3230 tmp = RREG32(IH_RB_CNTL);
3231 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3232 WREG32(IH_RB_CNTL, tmp);
3234 return (wptr & rdev->ih.ptr_mask);
3238 * Each IV ring entry is 128 bits:
3239 * [7:0] - interrupt source id
3241 * [59:32] - interrupt source data
3242 * [127:60] - reserved
3244 * The basic interrupt vector entries
3245 * are decoded as follows:
3246 * src_id src_data description
3251 * 19 0 FP Hot plug detection A
3252 * 19 1 FP Hot plug detection B
3253 * 19 2 DAC A auto-detection
3254 * 19 3 DAC B auto-detection
3260 * 181 - EOP Interrupt
3263 * Note, these are based on r600 and may need to be
3264 * adjusted or added to on newer asics
3267 int r600_irq_process(struct radeon_device *rdev)
3269 u32 wptr = r600_get_ih_wptr(rdev);
3270 u32 rptr = rdev->ih.rptr;
3271 u32 src_id, src_data;
3272 u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3273 unsigned long flags;
3274 bool queue_hotplug = false;
3276 DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3277 if (!rdev->ih.enabled)
3280 spin_lock_irqsave(&rdev->ih.lock, flags);
3283 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3286 if (rdev->shutdown) {
3287 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3292 /* display interrupts */
3293 r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3295 rdev->ih.wptr = wptr;
3296 while (rptr != wptr) {
3297 /* wptr/rptr are in bytes! */
3298 ring_index = rptr / 4;
3299 src_id = rdev->ih.ring[ring_index] & 0xff;
3300 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3303 case 1: /* D1 vblank/vline */
3305 case 0: /* D1 vblank */
3306 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3307 drm_handle_vblank(rdev->ddev, 0);
3308 rdev->pm.vblank_sync = true;
3309 wake_up(&rdev->irq.vblank_queue);
3310 disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3311 DRM_DEBUG("IH: D1 vblank\n");
3314 case 1: /* D1 vline */
3315 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3316 disp_int &= ~LB_D1_VLINE_INTERRUPT;
3317 DRM_DEBUG("IH: D1 vline\n");
3321 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3325 case 5: /* D2 vblank/vline */
3327 case 0: /* D2 vblank */
3328 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3329 drm_handle_vblank(rdev->ddev, 1);
3330 rdev->pm.vblank_sync = true;
3331 wake_up(&rdev->irq.vblank_queue);
3332 disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3333 DRM_DEBUG("IH: D2 vblank\n");
3336 case 1: /* D1 vline */
3337 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3338 disp_int &= ~LB_D2_VLINE_INTERRUPT;
3339 DRM_DEBUG("IH: D2 vline\n");
3343 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3347 case 19: /* HPD/DAC hotplug */
3350 if (disp_int & DC_HPD1_INTERRUPT) {
3351 disp_int &= ~DC_HPD1_INTERRUPT;
3352 queue_hotplug = true;
3353 DRM_DEBUG("IH: HPD1\n");
3357 if (disp_int & DC_HPD2_INTERRUPT) {
3358 disp_int &= ~DC_HPD2_INTERRUPT;
3359 queue_hotplug = true;
3360 DRM_DEBUG("IH: HPD2\n");
3364 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3365 disp_int_cont &= ~DC_HPD3_INTERRUPT;
3366 queue_hotplug = true;
3367 DRM_DEBUG("IH: HPD3\n");
3371 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3372 disp_int_cont &= ~DC_HPD4_INTERRUPT;
3373 queue_hotplug = true;
3374 DRM_DEBUG("IH: HPD4\n");
3378 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3379 disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3380 queue_hotplug = true;
3381 DRM_DEBUG("IH: HPD5\n");
3385 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3386 disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3387 queue_hotplug = true;
3388 DRM_DEBUG("IH: HPD6\n");
3392 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3397 DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3398 r600_audio_schedule_polling(rdev);
3400 case 176: /* CP_INT in ring buffer */
3401 case 177: /* CP_INT in IB1 */
3402 case 178: /* CP_INT in IB2 */
3403 DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3404 radeon_fence_process(rdev);
3406 case 181: /* CP EOP event */
3407 DRM_DEBUG("IH: CP EOP\n");
3409 case 233: /* GUI IDLE */
3410 DRM_DEBUG("IH: CP EOP\n");
3411 rdev->pm.gui_idle = true;
3412 wake_up(&rdev->irq.idle_queue);
3415 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3419 /* wptr/rptr are in bytes! */
3421 rptr &= rdev->ih.ptr_mask;
3423 /* make sure wptr hasn't changed while processing */
3424 wptr = r600_get_ih_wptr(rdev);
3425 if (wptr != rdev->ih.wptr)
3428 queue_work(rdev->wq, &rdev->hotplug_work);
3429 rdev->ih.rptr = rptr;
3430 WREG32(IH_RB_RPTR, rdev->ih.rptr);
3431 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3438 #if defined(CONFIG_DEBUG_FS)
3440 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3442 struct drm_info_node *node = (struct drm_info_node *) m->private;
3443 struct drm_device *dev = node->minor->dev;
3444 struct radeon_device *rdev = dev->dev_private;
3445 unsigned count, i, j;
3447 radeon_ring_free_size(rdev);
3448 count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3449 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3450 seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3451 seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3452 seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3453 seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3454 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3455 seq_printf(m, "%u dwords in ring\n", count);
3457 for (j = 0; j <= count; j++) {
3458 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3459 i = (i + 1) & rdev->cp.ptr_mask;
3464 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3466 struct drm_info_node *node = (struct drm_info_node *) m->private;
3467 struct drm_device *dev = node->minor->dev;
3468 struct radeon_device *rdev = dev->dev_private;
3470 DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3471 DREG32_SYS(m, rdev, VM_L2_STATUS);
3475 static struct drm_info_list r600_mc_info_list[] = {
3476 {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3477 {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3481 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3483 #if defined(CONFIG_DEBUG_FS)
3484 return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3491 * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3492 * rdev: radeon device structure
3493 * bo: buffer object struct which userspace is waiting for idle
3495 * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3496 * through ring buffer, this leads to corruption in rendering, see
3497 * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3498 * directly perform HDP flush by writing register through MMIO.
3500 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3502 WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
git://ftp.safe.ca / safe / jmp / linux-2.6 / blob