SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_mode.h"
  36 #include "r600d.h"
  37 #include "atom.h"
  38 #include "avivod.h"
  39
  40 #define PFP_UCODE_SIZE 576
  41 #define PM4_UCODE_SIZE 1792
  42 #define RLC_UCODE_SIZE 768
  43 #define R700_PFP_UCODE_SIZE 848
  44 #define R700_PM4_UCODE_SIZE 1360
  45 #define R700_RLC_UCODE_SIZE 1024
  46
  47 /* Firmware Names */
  48 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  49 MODULE_FIRMWARE("radeon/R600_me.bin");
  50 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  51 MODULE_FIRMWARE("radeon/RV610_me.bin");
  52 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  53 MODULE_FIRMWARE("radeon/RV630_me.bin");
  54 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV620_me.bin");
  56 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV635_me.bin");
  58 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV670_me.bin");
  60 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RS780_me.bin");
  62 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV770_me.bin");
  64 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RV730_me.bin");
  66 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV710_me.bin");
  68 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  69 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  70
  71 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  72
  73 /* r600,rv610,rv630,rv620,rv635,rv670 */
  74 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  75 void r600_gpu_init(struct radeon_device *rdev);
  76 void r600_fini(struct radeon_device *rdev);
  77
  78 /* hpd for digital panel detect/disconnect */
  79 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  80 {
  81         bool connected = false;
  82
  83         if (ASIC_IS_DCE3(rdev)) {
  84                 switch (hpd) {
  85                 case RADEON_HPD_1:
  86                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
  87                                 connected = true;
  88                         break;
  89                 case RADEON_HPD_2:
  90                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
  91                                 connected = true;
  92                         break;
  93                 case RADEON_HPD_3:
  94                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
  95                                 connected = true;
  96                         break;
  97                 case RADEON_HPD_4:
  98                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
  99                                 connected = true;
 100                         break;
 101                         /* DCE 3.2 */
 102                 case RADEON_HPD_5:
 103                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 104                                 connected = true;
 105                         break;
 106                 case RADEON_HPD_6:
 107                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 108                                 connected = true;
 109                         break;
 110                 default:
 111                         break;
 112                 }
 113         } else {
 114                 switch (hpd) {
 115                 case RADEON_HPD_1:
 116                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 117                                 connected = true;
 118                         break;
 119                 case RADEON_HPD_2:
 120                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 121                                 connected = true;
 122                         break;
 123                 case RADEON_HPD_3:
 124                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 125                                 connected = true;
 126                         break;
 127                 default:
 128                         break;
 129                 }
 130         }
 131         return connected;
 132 }
 133
 134 void r600_hpd_set_polarity(struct radeon_device *rdev,
 135                            enum radeon_hpd_id hpd)
 136 {
 137         u32 tmp;
 138         bool connected = r600_hpd_sense(rdev, hpd);
 139
 140         if (ASIC_IS_DCE3(rdev)) {
 141                 switch (hpd) {
 142                 case RADEON_HPD_1:
 143                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 144                         if (connected)
 145                                 tmp &= ~DC_HPDx_INT_POLARITY;
 146                         else
 147                                 tmp |= DC_HPDx_INT_POLARITY;
 148                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 149                         break;
 150                 case RADEON_HPD_2:
 151                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 152                         if (connected)
 153                                 tmp &= ~DC_HPDx_INT_POLARITY;
 154                         else
 155                                 tmp |= DC_HPDx_INT_POLARITY;
 156                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 157                         break;
 158                 case RADEON_HPD_3:
 159                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 160                         if (connected)
 161                                 tmp &= ~DC_HPDx_INT_POLARITY;
 162                         else
 163                                 tmp |= DC_HPDx_INT_POLARITY;
 164                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 165                         break;
 166                 case RADEON_HPD_4:
 167                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 168                         if (connected)
 169                                 tmp &= ~DC_HPDx_INT_POLARITY;
 170                         else
 171                                 tmp |= DC_HPDx_INT_POLARITY;
 172                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 173                         break;
 174                 case RADEON_HPD_5:
 175                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 176                         if (connected)
 177                                 tmp &= ~DC_HPDx_INT_POLARITY;
 178                         else
 179                                 tmp |= DC_HPDx_INT_POLARITY;
 180                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 181                         break;
 182                         /* DCE 3.2 */
 183                 case RADEON_HPD_6:
 184                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 185                         if (connected)
 186                                 tmp &= ~DC_HPDx_INT_POLARITY;
 187                         else
 188                                 tmp |= DC_HPDx_INT_POLARITY;
 189                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 190                         break;
 191                 default:
 192                         break;
 193                 }
 194         } else {
 195                 switch (hpd) {
 196                 case RADEON_HPD_1:
 197                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 198                         if (connected)
 199                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 200                         else
 201                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 202                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 203                         break;
 204                 case RADEON_HPD_2:
 205                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 206                         if (connected)
 207                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 208                         else
 209                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 210                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 211                         break;
 212                 case RADEON_HPD_3:
 213                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 214                         if (connected)
 215                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 216                         else
 217                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 218                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 219                         break;
 220                 default:
 221                         break;
 222                 }
 223         }
 224 }
 225
 226 void r600_hpd_init(struct radeon_device *rdev)
 227 {
 228         struct drm_device *dev = rdev->ddev;
 229         struct drm_connector *connector;
 230
 231         if (ASIC_IS_DCE3(rdev)) {
 232                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 233                 if (ASIC_IS_DCE32(rdev))
 234                         tmp |= DC_HPDx_EN;
 235
 236                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 237                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 238                         switch (radeon_connector->hpd.hpd) {
 239                         case RADEON_HPD_1:
 240                                 WREG32(DC_HPD1_CONTROL, tmp);
 241                                 rdev->irq.hpd[0] = true;
 242                                 break;
 243                         case RADEON_HPD_2:
 244                                 WREG32(DC_HPD2_CONTROL, tmp);
 245                                 rdev->irq.hpd[1] = true;
 246                                 break;
 247                         case RADEON_HPD_3:
 248                                 WREG32(DC_HPD3_CONTROL, tmp);
 249                                 rdev->irq.hpd[2] = true;
 250                                 break;
 251                         case RADEON_HPD_4:
 252                                 WREG32(DC_HPD4_CONTROL, tmp);
 253                                 rdev->irq.hpd[3] = true;
 254                                 break;
 255                                 /* DCE 3.2 */
 256                         case RADEON_HPD_5:
 257                                 WREG32(DC_HPD5_CONTROL, tmp);
 258                                 rdev->irq.hpd[4] = true;
 259                                 break;
 260                         case RADEON_HPD_6:
 261                                 WREG32(DC_HPD6_CONTROL, tmp);
 262                                 rdev->irq.hpd[5] = true;
 263                                 break;
 264                         default:
 265                                 break;
 266                         }
 267                 }
 268         } else {
 269                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 270                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 271                         switch (radeon_connector->hpd.hpd) {
 272                         case RADEON_HPD_1:
 273                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 274                                 rdev->irq.hpd[0] = true;
 275                                 break;
 276                         case RADEON_HPD_2:
 277                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 278                                 rdev->irq.hpd[1] = true;
 279                                 break;
 280                         case RADEON_HPD_3:
 281                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 282                                 rdev->irq.hpd[2] = true;
 283                                 break;
 284                         default:
 285                                 break;
 286                         }
 287                 }
 288         }
 289         if (rdev->irq.installed)
 290                 r600_irq_set(rdev);
 291 }
 292
 293 void r600_hpd_fini(struct radeon_device *rdev)
 294 {
 295         struct drm_device *dev = rdev->ddev;
 296         struct drm_connector *connector;
 297
 298         if (ASIC_IS_DCE3(rdev)) {
 299                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 300                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 301                         switch (radeon_connector->hpd.hpd) {
 302                         case RADEON_HPD_1:
 303                                 WREG32(DC_HPD1_CONTROL, 0);
 304                                 rdev->irq.hpd[0] = false;
 305                                 break;
 306                         case RADEON_HPD_2:
 307                                 WREG32(DC_HPD2_CONTROL, 0);
 308                                 rdev->irq.hpd[1] = false;
 309                                 break;
 310                         case RADEON_HPD_3:
 311                                 WREG32(DC_HPD3_CONTROL, 0);
 312                                 rdev->irq.hpd[2] = false;
 313                                 break;
 314                         case RADEON_HPD_4:
 315                                 WREG32(DC_HPD4_CONTROL, 0);
 316                                 rdev->irq.hpd[3] = false;
 317                                 break;
 318                                 /* DCE 3.2 */
 319                         case RADEON_HPD_5:
 320                                 WREG32(DC_HPD5_CONTROL, 0);
 321                                 rdev->irq.hpd[4] = false;
 322                                 break;
 323                         case RADEON_HPD_6:
 324                                 WREG32(DC_HPD6_CONTROL, 0);
 325                                 rdev->irq.hpd[5] = false;
 326                                 break;
 327                         default:
 328                                 break;
 329                         }
 330                 }
 331         } else {
 332                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 333                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 334                         switch (radeon_connector->hpd.hpd) {
 335                         case RADEON_HPD_1:
 336                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 337                                 rdev->irq.hpd[0] = false;
 338                                 break;
 339                         case RADEON_HPD_2:
 340                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 341                                 rdev->irq.hpd[1] = false;
 342                                 break;
 343                         case RADEON_HPD_3:
 344                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 345                                 rdev->irq.hpd[2] = false;
 346                                 break;
 347                         default:
 348                                 break;
 349                         }
 350                 }
 351         }
 352 }
 353
 354 /*
 355  * R600 PCIE GART
 356  */
 357 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 358 {
 359         unsigned i;
 360         u32 tmp;
 361
 362         /* flush hdp cache so updates hit vram */
 363         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 364
 365         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 366         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 367         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 368         for (i = 0; i < rdev->usec_timeout; i++) {
 369                 /* read MC_STATUS */
 370                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 371                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 372                 if (tmp == 2) {
 373                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 374                         return;
 375                 }
 376                 if (tmp) {
 377                         return;
 378                 }
 379                 udelay(1);
 380         }
 381 }
 382
 383 int r600_pcie_gart_init(struct radeon_device *rdev)
 384 {
 385         int r;
 386
 387         if (rdev->gart.table.vram.robj) {
 388                 WARN(1, "R600 PCIE GART already initialized.\n");
 389                 return 0;
 390         }
 391         /* Initialize common gart structure */
 392         r = radeon_gart_init(rdev);
 393         if (r)
 394                 return r;
 395         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 396         return radeon_gart_table_vram_alloc(rdev);
 397 }
 398
 399 int r600_pcie_gart_enable(struct radeon_device *rdev)
 400 {
 401         u32 tmp;
 402         int r, i;
 403
 404         if (rdev->gart.table.vram.robj == NULL) {
 405                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 406                 return -EINVAL;
 407         }
 408         r = radeon_gart_table_vram_pin(rdev);
 409         if (r)
 410                 return r;
 411         radeon_gart_restore(rdev);
 412
 413         /* Setup L2 cache */
 414         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 415                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 416                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 417         WREG32(VM_L2_CNTL2, 0);
 418         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 419         /* Setup TLB control */
 420         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 421                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 422                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 423                 ENABLE_WAIT_L2_QUERY;
 424         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 425         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 426         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 427         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 428         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 429         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 430         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 431         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 432         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 433         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 434         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 435         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 436         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 437         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 438         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 439         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 440         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 441         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 442                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 443         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 444                         (u32)(rdev->dummy_page.addr >> 12));
 445         for (i = 1; i < 7; i++)
 446                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 447
 448         r600_pcie_gart_tlb_flush(rdev);
 449         rdev->gart.ready = true;
 450         return 0;
 451 }
 452
 453 void r600_pcie_gart_disable(struct radeon_device *rdev)
 454 {
 455         u32 tmp;
 456         int i, r;
 457
 458         /* Disable all tables */
 459         for (i = 0; i < 7; i++)
 460                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 461
 462         /* Disable L2 cache */
 463         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 464                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 465         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 466         /* Setup L1 TLB control */
 467         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 468                 ENABLE_WAIT_L2_QUERY;
 469         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 470         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 471         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 472         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 473         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 474         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 475         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 476         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 477         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 478         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 479         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 480         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 481         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 482         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 483         if (rdev->gart.table.vram.robj) {
 484                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 485                 if (likely(r == 0)) {
 486                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 487                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 488                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 489                 }
 490         }
 491 }
 492
 493 void r600_pcie_gart_fini(struct radeon_device *rdev)
 494 {
 495         r600_pcie_gart_disable(rdev);
 496         radeon_gart_table_vram_free(rdev);
 497         radeon_gart_fini(rdev);
 498 }
 499
 500 void r600_agp_enable(struct radeon_device *rdev)
 501 {
 502         u32 tmp;
 503         int i;
 504
 505         /* Setup L2 cache */
 506         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 507                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 508                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 509         WREG32(VM_L2_CNTL2, 0);
 510         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 511         /* Setup TLB control */
 512         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 513                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 514                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 515                 ENABLE_WAIT_L2_QUERY;
 516         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 517         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 518         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 519         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 520         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 521         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 522         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 523         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 524         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 525         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 526         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 527         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 528         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 529         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 530         for (i = 0; i < 7; i++)
 531                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 532 }
 533
 534 int r600_mc_wait_for_idle(struct radeon_device *rdev)
 535 {
 536         unsigned i;
 537         u32 tmp;
 538
 539         for (i = 0; i < rdev->usec_timeout; i++) {
 540                 /* read MC_STATUS */
 541                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
 542                 if (!tmp)
 543                         return 0;
 544                 udelay(1);
 545         }
 546         return -1;
 547 }
 548
 549 static void r600_mc_program(struct radeon_device *rdev)
 550 {
 551         struct rv515_mc_save save;
 552         u32 tmp;
 553         int i, j;
 554
 555         /* Initialize HDP */
 556         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 557                 WREG32((0x2c14 + j), 0x00000000);
 558                 WREG32((0x2c18 + j), 0x00000000);
 559                 WREG32((0x2c1c + j), 0x00000000);
 560                 WREG32((0x2c20 + j), 0x00000000);
 561                 WREG32((0x2c24 + j), 0x00000000);
 562         }
 563         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 564
 565         rv515_mc_stop(rdev, &save);
 566         if (r600_mc_wait_for_idle(rdev)) {
 567                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 568         }
 569         /* Lockout access through VGA aperture (doesn't exist before R600) */
 570         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 571         /* Update configuration */
 572         if (rdev->flags & RADEON_IS_AGP) {
 573                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 574                         /* VRAM before AGP */
 575                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 576                                 rdev->mc.vram_start >> 12);
 577                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 578                                 rdev->mc.gtt_end >> 12);
 579                 } else {
 580                         /* VRAM after AGP */
 581                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 582                                 rdev->mc.gtt_start >> 12);
 583                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 584                                 rdev->mc.vram_end >> 12);
 585                 }
 586         } else {
 587                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
 588                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
 589         }
 590         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 591         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 592         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 593         WREG32(MC_VM_FB_LOCATION, tmp);
 594         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 595         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 596         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
 597         if (rdev->flags & RADEON_IS_AGP) {
 598                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
 599                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
 600                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 601         } else {
 602                 WREG32(MC_VM_AGP_BASE, 0);
 603                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 604                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 605         }
 606         if (r600_mc_wait_for_idle(rdev)) {
 607                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 608         }
 609         rv515_mc_resume(rdev, &save);
 610         /* we need to own VRAM, so turn off the VGA renderer here
 611          * to stop it overwriting our objects */
 612         rv515_vga_render_disable(rdev);
 613 }
 614
 615 /**
 616  * r600_vram_gtt_location - try to find VRAM & GTT location
 617  * @rdev: radeon device structure holding all necessary informations
 618  * @mc: memory controller structure holding memory informations
 619  *
 620  * Function will place try to place VRAM at same place as in CPU (PCI)
 621  * address space as some GPU seems to have issue when we reprogram at
 622  * different address space.
 623  *
 624  * If there is not enough space to fit the unvisible VRAM after the
 625  * aperture then we limit the VRAM size to the aperture.
 626  *
 627  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
 628  * them to be in one from GPU point of view so that we can program GPU to
 629  * catch access outside them (weird GPU policy see ??).
 630  *
 631  * This function will never fails, worst case are limiting VRAM or GTT.
 632  *
 633  * Note: GTT start, end, size should be initialized before calling this
 634  * function on AGP platform.
 635  */
 636 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
 637 {
 638         u64 size_bf, size_af;
 639
 640         if (mc->mc_vram_size > 0xE0000000) {
 641                 /* leave room for at least 512M GTT */
 642                 dev_warn(rdev->dev, "limiting VRAM\n");
 643                 mc->real_vram_size = 0xE0000000;
 644                 mc->mc_vram_size = 0xE0000000;
 645         }
 646         if (rdev->flags & RADEON_IS_AGP) {
 647                 size_bf = mc->gtt_start;
 648                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
 649                 if (size_bf > size_af) {
 650                         if (mc->mc_vram_size > size_bf) {
 651                                 dev_warn(rdev->dev, "limiting VRAM\n");
 652                                 mc->real_vram_size = size_bf;
 653                                 mc->mc_vram_size = size_bf;
 654                         }
 655                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
 656                 } else {
 657                         if (mc->mc_vram_size > size_af) {
 658                                 dev_warn(rdev->dev, "limiting VRAM\n");
 659                                 mc->real_vram_size = size_af;
 660                                 mc->mc_vram_size = size_af;
 661                         }
 662                         mc->vram_start = mc->gtt_end;
 663                 }
 664                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
 665                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
 666                                 mc->mc_vram_size >> 20, mc->vram_start,
 667                                 mc->vram_end, mc->real_vram_size >> 20);
 668         } else {
 669                 u64 base = 0;
 670                 if (rdev->flags & RADEON_IS_IGP)
 671                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
 672                 radeon_vram_location(rdev, &rdev->mc, base);
 673                 radeon_gtt_location(rdev, mc);
 674         }
 675 }
 676
 677 int r600_mc_init(struct radeon_device *rdev)
 678 {
 679         fixed20_12 a;
 680         u32 tmp;
 681         int chansize, numchan;
 682
 683         /* Get VRAM informations */
 684         rdev->mc.vram_is_ddr = true;
 685         tmp = RREG32(RAMCFG);
 686         if (tmp & CHANSIZE_OVERRIDE) {
 687                 chansize = 16;
 688         } else if (tmp & CHANSIZE_MASK) {
 689                 chansize = 64;
 690         } else {
 691                 chansize = 32;
 692         }
 693         tmp = RREG32(CHMAP);
 694         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
 695         case 0:
 696         default:
 697                 numchan = 1;
 698                 break;
 699         case 1:
 700                 numchan = 2;
 701                 break;
 702         case 2:
 703                 numchan = 4;
 704                 break;
 705         case 3:
 706                 numchan = 8;
 707                 break;
 708         }
 709         rdev->mc.vram_width = numchan * chansize;
 710         /* Could aper size report 0 ? */
 711         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
 712         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
 713         /* Setup GPU memory space */
 714         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
 715         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
 716         rdev->mc.visible_vram_size = rdev->mc.aper_size;
 717         /* FIXME remove this once we support unmappable VRAM */
 718         if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
 719                 rdev->mc.mc_vram_size = rdev->mc.aper_size;
 720                 rdev->mc.real_vram_size = rdev->mc.aper_size;
 721         }
 722         r600_vram_gtt_location(rdev, &rdev->mc);
 723         /* FIXME: we should enforce default clock in case GPU is not in
 724          * default setup
 725          */
 726         a.full = rfixed_const(100);
 727         rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk);
 728         rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a);
 729         if (rdev->flags & RADEON_IS_IGP)
 730                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
 731         return 0;
 732 }
 733
 734 /* We doesn't check that the GPU really needs a reset we simply do the
 735  * reset, it's up to the caller to determine if the GPU needs one. We
 736  * might add an helper function to check that.
 737  */
 738 int r600_gpu_soft_reset(struct radeon_device *rdev)
 739 {
 740         struct rv515_mc_save save;
 741         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
 742                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
 743                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
 744                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
 745                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
 746                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
 747                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
 748                                 S_008010_GUI_ACTIVE(1);
 749         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
 750                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
 751                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
 752                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
 753                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
 754                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
 755                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
 756                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
 757         u32 srbm_reset = 0;
 758         u32 tmp;
 759
 760         dev_info(rdev->dev, "GPU softreset \n");
 761         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 762                 RREG32(R_008010_GRBM_STATUS));
 763         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 764                 RREG32(R_008014_GRBM_STATUS2));
 765         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 766                 RREG32(R_000E50_SRBM_STATUS));
 767         rv515_mc_stop(rdev, &save);
 768         if (r600_mc_wait_for_idle(rdev)) {
 769                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 770         }
 771         /* Disable CP parsing/prefetching */
 772         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(0xff));
 773         /* Check if any of the rendering block is busy and reset it */
 774         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
 775             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
 776                 tmp = S_008020_SOFT_RESET_CR(1) |
 777                         S_008020_SOFT_RESET_DB(1) |
 778                         S_008020_SOFT_RESET_CB(1) |
 779                         S_008020_SOFT_RESET_PA(1) |
 780                         S_008020_SOFT_RESET_SC(1) |
 781                         S_008020_SOFT_RESET_SMX(1) |
 782                         S_008020_SOFT_RESET_SPI(1) |
 783                         S_008020_SOFT_RESET_SX(1) |
 784                         S_008020_SOFT_RESET_SH(1) |
 785                         S_008020_SOFT_RESET_TC(1) |
 786                         S_008020_SOFT_RESET_TA(1) |
 787                         S_008020_SOFT_RESET_VC(1) |
 788                         S_008020_SOFT_RESET_VGT(1);
 789                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 790                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 791                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 792                 udelay(50);
 793                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
 794                 (void)RREG32(R_008020_GRBM_SOFT_RESET);
 795         }
 796         /* Reset CP (we always reset CP) */
 797         tmp = S_008020_SOFT_RESET_CP(1);
 798         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
 799         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
 800         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 801         udelay(50);
 802         WREG32(R_008020_GRBM_SOFT_RESET, 0);
 803         (void)RREG32(R_008020_GRBM_SOFT_RESET);
 804         /* Reset others GPU block if necessary */
 805         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 806                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 807         if (G_000E50_GRBM_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 808                 srbm_reset |= S_000E60_SOFT_RESET_GRBM(1);
 809         if (G_000E50_HI_RQ_PENDING(RREG32(R_000E50_SRBM_STATUS)))
 810                 srbm_reset |= S_000E60_SOFT_RESET_IH(1);
 811         if (G_000E50_VMC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 812                 srbm_reset |= S_000E60_SOFT_RESET_VMC(1);
 813         if (G_000E50_MCB_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 814                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 815         if (G_000E50_MCDZ_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 816                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 817         if (G_000E50_MCDY_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 818                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 819         if (G_000E50_MCDX_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 820                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 821         if (G_000E50_MCDW_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 822                 srbm_reset |= S_000E60_SOFT_RESET_MC(1);
 823         if (G_000E50_RLC_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 824                 srbm_reset |= S_000E60_SOFT_RESET_RLC(1);
 825         if (G_000E50_SEM_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 826                 srbm_reset |= S_000E60_SOFT_RESET_SEM(1);
 827         if (G_000E50_BIF_BUSY(RREG32(R_000E50_SRBM_STATUS)))
 828                 srbm_reset |= S_000E60_SOFT_RESET_BIF(1);
 829         dev_info(rdev->dev, "  R_000E60_SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
 830         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 831         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 832         udelay(50);
 833         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 834         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 835         WREG32(R_000E60_SRBM_SOFT_RESET, srbm_reset);
 836         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 837         udelay(50);
 838         WREG32(R_000E60_SRBM_SOFT_RESET, 0);
 839         (void)RREG32(R_000E60_SRBM_SOFT_RESET);
 840         /* Wait a little for things to settle down */
 841         udelay(50);
 842         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
 843                 RREG32(R_008010_GRBM_STATUS));
 844         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
 845                 RREG32(R_008014_GRBM_STATUS2));
 846         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
 847                 RREG32(R_000E50_SRBM_STATUS));
 848         /* After reset we need to reinit the asic as GPU often endup in an
 849          * incoherent state.
 850          */
 851         atom_asic_init(rdev->mode_info.atom_context);
 852         rv515_mc_resume(rdev, &save);
 853         return 0;
 854 }
 855
 856 int r600_gpu_reset(struct radeon_device *rdev)
 857 {
 858         return r600_gpu_soft_reset(rdev);
 859 }
 860
 861 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
 862                                              u32 num_backends,
 863                                              u32 backend_disable_mask)
 864 {
 865         u32 backend_map = 0;
 866         u32 enabled_backends_mask;
 867         u32 enabled_backends_count;
 868         u32 cur_pipe;
 869         u32 swizzle_pipe[R6XX_MAX_PIPES];
 870         u32 cur_backend;
 871         u32 i;
 872
 873         if (num_tile_pipes > R6XX_MAX_PIPES)
 874                 num_tile_pipes = R6XX_MAX_PIPES;
 875         if (num_tile_pipes < 1)
 876                 num_tile_pipes = 1;
 877         if (num_backends > R6XX_MAX_BACKENDS)
 878                 num_backends = R6XX_MAX_BACKENDS;
 879         if (num_backends < 1)
 880                 num_backends = 1;
 881
 882         enabled_backends_mask = 0;
 883         enabled_backends_count = 0;
 884         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
 885                 if (((backend_disable_mask >> i) & 1) == 0) {
 886                         enabled_backends_mask |= (1 << i);
 887                         ++enabled_backends_count;
 888                 }
 889                 if (enabled_backends_count == num_backends)
 890                         break;
 891         }
 892
 893         if (enabled_backends_count == 0) {
 894                 enabled_backends_mask = 1;
 895                 enabled_backends_count = 1;
 896         }
 897
 898         if (enabled_backends_count != num_backends)
 899                 num_backends = enabled_backends_count;
 900
 901         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
 902         switch (num_tile_pipes) {
 903         case 1:
 904                 swizzle_pipe[0] = 0;
 905                 break;
 906         case 2:
 907                 swizzle_pipe[0] = 0;
 908                 swizzle_pipe[1] = 1;
 909                 break;
 910         case 3:
 911                 swizzle_pipe[0] = 0;
 912                 swizzle_pipe[1] = 1;
 913                 swizzle_pipe[2] = 2;
 914                 break;
 915         case 4:
 916                 swizzle_pipe[0] = 0;
 917                 swizzle_pipe[1] = 1;
 918                 swizzle_pipe[2] = 2;
 919                 swizzle_pipe[3] = 3;
 920                 break;
 921         case 5:
 922                 swizzle_pipe[0] = 0;
 923                 swizzle_pipe[1] = 1;
 924                 swizzle_pipe[2] = 2;
 925                 swizzle_pipe[3] = 3;
 926                 swizzle_pipe[4] = 4;
 927                 break;
 928         case 6:
 929                 swizzle_pipe[0] = 0;
 930                 swizzle_pipe[1] = 2;
 931                 swizzle_pipe[2] = 4;
 932                 swizzle_pipe[3] = 5;
 933                 swizzle_pipe[4] = 1;
 934                 swizzle_pipe[5] = 3;
 935                 break;
 936         case 7:
 937                 swizzle_pipe[0] = 0;
 938                 swizzle_pipe[1] = 2;
 939                 swizzle_pipe[2] = 4;
 940                 swizzle_pipe[3] = 6;
 941                 swizzle_pipe[4] = 1;
 942                 swizzle_pipe[5] = 3;
 943                 swizzle_pipe[6] = 5;
 944                 break;
 945         case 8:
 946                 swizzle_pipe[0] = 0;
 947                 swizzle_pipe[1] = 2;
 948                 swizzle_pipe[2] = 4;
 949                 swizzle_pipe[3] = 6;
 950                 swizzle_pipe[4] = 1;
 951                 swizzle_pipe[5] = 3;
 952                 swizzle_pipe[6] = 5;
 953                 swizzle_pipe[7] = 7;
 954                 break;
 955         }
 956
 957         cur_backend = 0;
 958         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 959                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 960                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 961
 962                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
 963
 964                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
 965         }
 966
 967         return backend_map;
 968 }
 969
 970 int r600_count_pipe_bits(uint32_t val)
 971 {
 972         int i, ret = 0;
 973
 974         for (i = 0; i < 32; i++) {
 975                 ret += val & 1;
 976                 val >>= 1;
 977         }
 978         return ret;
 979 }
 980
 981 void r600_gpu_init(struct radeon_device *rdev)
 982 {
 983         u32 tiling_config;
 984         u32 ramcfg;
 985         u32 backend_map;
 986         u32 cc_rb_backend_disable;
 987         u32 cc_gc_shader_pipe_config;
 988         u32 tmp;
 989         int i, j;
 990         u32 sq_config;
 991         u32 sq_gpr_resource_mgmt_1 = 0;
 992         u32 sq_gpr_resource_mgmt_2 = 0;
 993         u32 sq_thread_resource_mgmt = 0;
 994         u32 sq_stack_resource_mgmt_1 = 0;
 995         u32 sq_stack_resource_mgmt_2 = 0;
 996
 997         /* FIXME: implement */
 998         switch (rdev->family) {
 999         case CHIP_R600:
1000                 rdev->config.r600.max_pipes = 4;
1001                 rdev->config.r600.max_tile_pipes = 8;
1002                 rdev->config.r600.max_simds = 4;
1003                 rdev->config.r600.max_backends = 4;
1004                 rdev->config.r600.max_gprs = 256;
1005                 rdev->config.r600.max_threads = 192;
1006                 rdev->config.r600.max_stack_entries = 256;
1007                 rdev->config.r600.max_hw_contexts = 8;
1008                 rdev->config.r600.max_gs_threads = 16;
1009                 rdev->config.r600.sx_max_export_size = 128;
1010                 rdev->config.r600.sx_max_export_pos_size = 16;
1011                 rdev->config.r600.sx_max_export_smx_size = 128;
1012                 rdev->config.r600.sq_num_cf_insts = 2;
1013                 break;
1014         case CHIP_RV630:
1015         case CHIP_RV635:
1016                 rdev->config.r600.max_pipes = 2;
1017                 rdev->config.r600.max_tile_pipes = 2;
1018                 rdev->config.r600.max_simds = 3;
1019                 rdev->config.r600.max_backends = 1;
1020                 rdev->config.r600.max_gprs = 128;
1021                 rdev->config.r600.max_threads = 192;
1022                 rdev->config.r600.max_stack_entries = 128;
1023                 rdev->config.r600.max_hw_contexts = 8;
1024                 rdev->config.r600.max_gs_threads = 4;
1025                 rdev->config.r600.sx_max_export_size = 128;
1026                 rdev->config.r600.sx_max_export_pos_size = 16;
1027                 rdev->config.r600.sx_max_export_smx_size = 128;
1028                 rdev->config.r600.sq_num_cf_insts = 2;
1029                 break;
1030         case CHIP_RV610:
1031         case CHIP_RV620:
1032         case CHIP_RS780:
1033         case CHIP_RS880:
1034                 rdev->config.r600.max_pipes = 1;
1035                 rdev->config.r600.max_tile_pipes = 1;
1036                 rdev->config.r600.max_simds = 2;
1037                 rdev->config.r600.max_backends = 1;
1038                 rdev->config.r600.max_gprs = 128;
1039                 rdev->config.r600.max_threads = 192;
1040                 rdev->config.r600.max_stack_entries = 128;
1041                 rdev->config.r600.max_hw_contexts = 4;
1042                 rdev->config.r600.max_gs_threads = 4;
1043                 rdev->config.r600.sx_max_export_size = 128;
1044                 rdev->config.r600.sx_max_export_pos_size = 16;
1045                 rdev->config.r600.sx_max_export_smx_size = 128;
1046                 rdev->config.r600.sq_num_cf_insts = 1;
1047                 break;
1048         case CHIP_RV670:
1049                 rdev->config.r600.max_pipes = 4;
1050                 rdev->config.r600.max_tile_pipes = 4;
1051                 rdev->config.r600.max_simds = 4;
1052                 rdev->config.r600.max_backends = 4;
1053                 rdev->config.r600.max_gprs = 192;
1054                 rdev->config.r600.max_threads = 192;
1055                 rdev->config.r600.max_stack_entries = 256;
1056                 rdev->config.r600.max_hw_contexts = 8;
1057                 rdev->config.r600.max_gs_threads = 16;
1058                 rdev->config.r600.sx_max_export_size = 128;
1059                 rdev->config.r600.sx_max_export_pos_size = 16;
1060                 rdev->config.r600.sx_max_export_smx_size = 128;
1061                 rdev->config.r600.sq_num_cf_insts = 2;
1062                 break;
1063         default:
1064                 break;
1065         }
1066
1067         /* Initialize HDP */
1068         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1069                 WREG32((0x2c14 + j), 0x00000000);
1070                 WREG32((0x2c18 + j), 0x00000000);
1071                 WREG32((0x2c1c + j), 0x00000000);
1072                 WREG32((0x2c20 + j), 0x00000000);
1073                 WREG32((0x2c24 + j), 0x00000000);
1074         }
1075
1076         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1077
1078         /* Setup tiling */
1079         tiling_config = 0;
1080         ramcfg = RREG32(RAMCFG);
1081         switch (rdev->config.r600.max_tile_pipes) {
1082         case 1:
1083                 tiling_config |= PIPE_TILING(0);
1084                 break;
1085         case 2:
1086                 tiling_config |= PIPE_TILING(1);
1087                 break;
1088         case 4:
1089                 tiling_config |= PIPE_TILING(2);
1090                 break;
1091         case 8:
1092                 tiling_config |= PIPE_TILING(3);
1093                 break;
1094         default:
1095                 break;
1096         }
1097         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1098         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1099         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1100         tiling_config |= GROUP_SIZE(0);
1101         rdev->config.r600.tiling_group_size = 256;
1102         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1103         if (tmp > 3) {
1104                 tiling_config |= ROW_TILING(3);
1105                 tiling_config |= SAMPLE_SPLIT(3);
1106         } else {
1107                 tiling_config |= ROW_TILING(tmp);
1108                 tiling_config |= SAMPLE_SPLIT(tmp);
1109         }
1110         tiling_config |= BANK_SWAPS(1);
1111
1112         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1113         cc_rb_backend_disable |=
1114                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1115
1116         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1117         cc_gc_shader_pipe_config |=
1118                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1119         cc_gc_shader_pipe_config |=
1120                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1121
1122         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1123                                                         (R6XX_MAX_BACKENDS -
1124                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1125                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1126                                                         (cc_rb_backend_disable >> 16));
1127
1128         tiling_config |= BACKEND_MAP(backend_map);
1129         WREG32(GB_TILING_CONFIG, tiling_config);
1130         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1131         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1132
1133         /* Setup pipes */
1134         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1135         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1136
1137         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1138         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1139         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1140
1141         /* Setup some CP states */
1142         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1143         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1144
1145         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1146                              SYNC_WALKER | SYNC_ALIGNER));
1147         /* Setup various GPU states */
1148         if (rdev->family == CHIP_RV670)
1149                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1150
1151         tmp = RREG32(SX_DEBUG_1);
1152         tmp |= SMX_EVENT_RELEASE;
1153         if ((rdev->family > CHIP_R600))
1154                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1155         WREG32(SX_DEBUG_1, tmp);
1156
1157         if (((rdev->family) == CHIP_R600) ||
1158             ((rdev->family) == CHIP_RV630) ||
1159             ((rdev->family) == CHIP_RV610) ||
1160             ((rdev->family) == CHIP_RV620) ||
1161             ((rdev->family) == CHIP_RS780) ||
1162             ((rdev->family) == CHIP_RS880)) {
1163                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1164         } else {
1165                 WREG32(DB_DEBUG, 0);
1166         }
1167         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1168                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1169
1170         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1171         WREG32(VGT_NUM_INSTANCES, 0);
1172
1173         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1174         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1175
1176         tmp = RREG32(SQ_MS_FIFO_SIZES);
1177         if (((rdev->family) == CHIP_RV610) ||
1178             ((rdev->family) == CHIP_RV620) ||
1179             ((rdev->family) == CHIP_RS780) ||
1180             ((rdev->family) == CHIP_RS880)) {
1181                 tmp = (CACHE_FIFO_SIZE(0xa) |
1182                        FETCH_FIFO_HIWATER(0xa) |
1183                        DONE_FIFO_HIWATER(0xe0) |
1184                        ALU_UPDATE_FIFO_HIWATER(0x8));
1185         } else if (((rdev->family) == CHIP_R600) ||
1186                    ((rdev->family) == CHIP_RV630)) {
1187                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1188                 tmp |= DONE_FIFO_HIWATER(0x4);
1189         }
1190         WREG32(SQ_MS_FIFO_SIZES, tmp);
1191
1192         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1193          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1194          */
1195         sq_config = RREG32(SQ_CONFIG);
1196         sq_config &= ~(PS_PRIO(3) |
1197                        VS_PRIO(3) |
1198                        GS_PRIO(3) |
1199                        ES_PRIO(3));
1200         sq_config |= (DX9_CONSTS |
1201                       VC_ENABLE |
1202                       PS_PRIO(0) |
1203                       VS_PRIO(1) |
1204                       GS_PRIO(2) |
1205                       ES_PRIO(3));
1206
1207         if ((rdev->family) == CHIP_R600) {
1208                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1209                                           NUM_VS_GPRS(124) |
1210                                           NUM_CLAUSE_TEMP_GPRS(4));
1211                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1212                                           NUM_ES_GPRS(0));
1213                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1214                                            NUM_VS_THREADS(48) |
1215                                            NUM_GS_THREADS(4) |
1216                                            NUM_ES_THREADS(4));
1217                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1218                                             NUM_VS_STACK_ENTRIES(128));
1219                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1220                                             NUM_ES_STACK_ENTRIES(0));
1221         } else if (((rdev->family) == CHIP_RV610) ||
1222                    ((rdev->family) == CHIP_RV620) ||
1223                    ((rdev->family) == CHIP_RS780) ||
1224                    ((rdev->family) == CHIP_RS880)) {
1225                 /* no vertex cache */
1226                 sq_config &= ~VC_ENABLE;
1227
1228                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1229                                           NUM_VS_GPRS(44) |
1230                                           NUM_CLAUSE_TEMP_GPRS(2));
1231                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1232                                           NUM_ES_GPRS(17));
1233                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1234                                            NUM_VS_THREADS(78) |
1235                                            NUM_GS_THREADS(4) |
1236                                            NUM_ES_THREADS(31));
1237                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1238                                             NUM_VS_STACK_ENTRIES(40));
1239                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1240                                             NUM_ES_STACK_ENTRIES(16));
1241         } else if (((rdev->family) == CHIP_RV630) ||
1242                    ((rdev->family) == CHIP_RV635)) {
1243                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1244                                           NUM_VS_GPRS(44) |
1245                                           NUM_CLAUSE_TEMP_GPRS(2));
1246                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1247                                           NUM_ES_GPRS(18));
1248                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1249                                            NUM_VS_THREADS(78) |
1250                                            NUM_GS_THREADS(4) |
1251                                            NUM_ES_THREADS(31));
1252                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1253                                             NUM_VS_STACK_ENTRIES(40));
1254                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1255                                             NUM_ES_STACK_ENTRIES(16));
1256         } else if ((rdev->family) == CHIP_RV670) {
1257                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1258                                           NUM_VS_GPRS(44) |
1259                                           NUM_CLAUSE_TEMP_GPRS(2));
1260                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1261                                           NUM_ES_GPRS(17));
1262                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1263                                            NUM_VS_THREADS(78) |
1264                                            NUM_GS_THREADS(4) |
1265                                            NUM_ES_THREADS(31));
1266                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1267                                             NUM_VS_STACK_ENTRIES(64));
1268                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1269                                             NUM_ES_STACK_ENTRIES(64));
1270         }
1271
1272         WREG32(SQ_CONFIG, sq_config);
1273         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1274         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1275         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1276         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1277         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1278
1279         if (((rdev->family) == CHIP_RV610) ||
1280             ((rdev->family) == CHIP_RV620) ||
1281             ((rdev->family) == CHIP_RS780) ||
1282             ((rdev->family) == CHIP_RS880)) {
1283                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1284         } else {
1285                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1286         }
1287
1288         /* More default values. 2D/3D driver should adjust as needed */
1289         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1290                                          S1_X(0x4) | S1_Y(0xc)));
1291         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1292                                          S1_X(0x2) | S1_Y(0x2) |
1293                                          S2_X(0xa) | S2_Y(0x6) |
1294                                          S3_X(0x6) | S3_Y(0xa)));
1295         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1296                                              S1_X(0x4) | S1_Y(0xc) |
1297                                              S2_X(0x1) | S2_Y(0x6) |
1298                                              S3_X(0xa) | S3_Y(0xe)));
1299         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1300                                              S5_X(0x0) | S5_Y(0x0) |
1301                                              S6_X(0xb) | S6_Y(0x4) |
1302                                              S7_X(0x7) | S7_Y(0x8)));
1303
1304         WREG32(VGT_STRMOUT_EN, 0);
1305         tmp = rdev->config.r600.max_pipes * 16;
1306         switch (rdev->family) {
1307         case CHIP_RV610:
1308         case CHIP_RV620:
1309         case CHIP_RS780:
1310         case CHIP_RS880:
1311                 tmp += 32;
1312                 break;
1313         case CHIP_RV670:
1314                 tmp += 128;
1315                 break;
1316         default:
1317                 break;
1318         }
1319         if (tmp > 256) {
1320                 tmp = 256;
1321         }
1322         WREG32(VGT_ES_PER_GS, 128);
1323         WREG32(VGT_GS_PER_ES, tmp);
1324         WREG32(VGT_GS_PER_VS, 2);
1325         WREG32(VGT_GS_VERTEX_REUSE, 16);
1326
1327         /* more default values. 2D/3D driver should adjust as needed */
1328         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1329         WREG32(VGT_STRMOUT_EN, 0);
1330         WREG32(SX_MISC, 0);
1331         WREG32(PA_SC_MODE_CNTL, 0);
1332         WREG32(PA_SC_AA_CONFIG, 0);
1333         WREG32(PA_SC_LINE_STIPPLE, 0);
1334         WREG32(SPI_INPUT_Z, 0);
1335         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1336         WREG32(CB_COLOR7_FRAG, 0);
1337
1338         /* Clear render buffer base addresses */
1339         WREG32(CB_COLOR0_BASE, 0);
1340         WREG32(CB_COLOR1_BASE, 0);
1341         WREG32(CB_COLOR2_BASE, 0);
1342         WREG32(CB_COLOR3_BASE, 0);
1343         WREG32(CB_COLOR4_BASE, 0);
1344         WREG32(CB_COLOR5_BASE, 0);
1345         WREG32(CB_COLOR6_BASE, 0);
1346         WREG32(CB_COLOR7_BASE, 0);
1347         WREG32(CB_COLOR7_FRAG, 0);
1348
1349         switch (rdev->family) {
1350         case CHIP_RV610:
1351         case CHIP_RV620:
1352         case CHIP_RS780:
1353         case CHIP_RS880:
1354                 tmp = TC_L2_SIZE(8);
1355                 break;
1356         case CHIP_RV630:
1357         case CHIP_RV635:
1358                 tmp = TC_L2_SIZE(4);
1359                 break;
1360         case CHIP_R600:
1361                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1362                 break;
1363         default:
1364                 tmp = TC_L2_SIZE(0);
1365                 break;
1366         }
1367         WREG32(TC_CNTL, tmp);
1368
1369         tmp = RREG32(HDP_HOST_PATH_CNTL);
1370         WREG32(HDP_HOST_PATH_CNTL, tmp);
1371
1372         tmp = RREG32(ARB_POP);
1373         tmp |= ENABLE_TC128;
1374         WREG32(ARB_POP, tmp);
1375
1376         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1377         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1378                                NUM_CLIP_SEQ(3)));
1379         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1380 }
1381
1382
1383 /*
1384  * Indirect registers accessor
1385  */
1386 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1387 {
1388         u32 r;
1389
1390         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1391         (void)RREG32(PCIE_PORT_INDEX);
1392         r = RREG32(PCIE_PORT_DATA);
1393         return r;
1394 }
1395
1396 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1397 {
1398         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1399         (void)RREG32(PCIE_PORT_INDEX);
1400         WREG32(PCIE_PORT_DATA, (v));
1401         (void)RREG32(PCIE_PORT_DATA);
1402 }
1403
1404 /*
1405  * CP & Ring
1406  */
1407 void r600_cp_stop(struct radeon_device *rdev)
1408 {
1409         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1410 }
1411
1412 int r600_init_microcode(struct radeon_device *rdev)
1413 {
1414         struct platform_device *pdev;
1415         const char *chip_name;
1416         const char *rlc_chip_name;
1417         size_t pfp_req_size, me_req_size, rlc_req_size;
1418         char fw_name[30];
1419         int err;
1420
1421         DRM_DEBUG("\n");
1422
1423         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1424         err = IS_ERR(pdev);
1425         if (err) {
1426                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1427                 return -EINVAL;
1428         }
1429
1430         switch (rdev->family) {
1431         case CHIP_R600:
1432                 chip_name = "R600";
1433                 rlc_chip_name = "R600";
1434                 break;
1435         case CHIP_RV610:
1436                 chip_name = "RV610";
1437                 rlc_chip_name = "R600";
1438                 break;
1439         case CHIP_RV630:
1440                 chip_name = "RV630";
1441                 rlc_chip_name = "R600";
1442                 break;
1443         case CHIP_RV620:
1444                 chip_name = "RV620";
1445                 rlc_chip_name = "R600";
1446                 break;
1447         case CHIP_RV635:
1448                 chip_name = "RV635";
1449                 rlc_chip_name = "R600";
1450                 break;
1451         case CHIP_RV670:
1452                 chip_name = "RV670";
1453                 rlc_chip_name = "R600";
1454                 break;
1455         case CHIP_RS780:
1456         case CHIP_RS880:
1457                 chip_name = "RS780";
1458                 rlc_chip_name = "R600";
1459                 break;
1460         case CHIP_RV770:
1461                 chip_name = "RV770";
1462                 rlc_chip_name = "R700";
1463                 break;
1464         case CHIP_RV730:
1465         case CHIP_RV740:
1466                 chip_name = "RV730";
1467                 rlc_chip_name = "R700";
1468                 break;
1469         case CHIP_RV710:
1470                 chip_name = "RV710";
1471                 rlc_chip_name = "R700";
1472                 break;
1473         default: BUG();
1474         }
1475
1476         if (rdev->family >= CHIP_RV770) {
1477                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1478                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1479                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1480         } else {
1481                 pfp_req_size = PFP_UCODE_SIZE * 4;
1482                 me_req_size = PM4_UCODE_SIZE * 12;
1483                 rlc_req_size = RLC_UCODE_SIZE * 4;
1484         }
1485
1486         DRM_INFO("Loading %s Microcode\n", chip_name);
1487
1488         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1489         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1490         if (err)
1491                 goto out;
1492         if (rdev->pfp_fw->size != pfp_req_size) {
1493                 printk(KERN_ERR
1494                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1495                        rdev->pfp_fw->size, fw_name);
1496                 err = -EINVAL;
1497                 goto out;
1498         }
1499
1500         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1501         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
1502         if (err)
1503                 goto out;
1504         if (rdev->me_fw->size != me_req_size) {
1505                 printk(KERN_ERR
1506                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1507                        rdev->me_fw->size, fw_name);
1508                 err = -EINVAL;
1509         }
1510
1511         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
1512         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
1513         if (err)
1514                 goto out;
1515         if (rdev->rlc_fw->size != rlc_req_size) {
1516                 printk(KERN_ERR
1517                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
1518                        rdev->rlc_fw->size, fw_name);
1519                 err = -EINVAL;
1520         }
1521
1522 out:
1523         platform_device_unregister(pdev);
1524
1525         if (err) {
1526                 if (err != -EINVAL)
1527                         printk(KERN_ERR
1528                                "r600_cp: Failed to load firmware \"%s\"\n",
1529                                fw_name);
1530                 release_firmware(rdev->pfp_fw);
1531                 rdev->pfp_fw = NULL;
1532                 release_firmware(rdev->me_fw);
1533                 rdev->me_fw = NULL;
1534                 release_firmware(rdev->rlc_fw);
1535                 rdev->rlc_fw = NULL;
1536         }
1537         return err;
1538 }
1539
1540 static int r600_cp_load_microcode(struct radeon_device *rdev)
1541 {
1542         const __be32 *fw_data;
1543         int i;
1544
1545         if (!rdev->me_fw || !rdev->pfp_fw)
1546                 return -EINVAL;
1547
1548         r600_cp_stop(rdev);
1549
1550         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
1551
1552         /* Reset cp */
1553         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1554         RREG32(GRBM_SOFT_RESET);
1555         mdelay(15);
1556         WREG32(GRBM_SOFT_RESET, 0);
1557
1558         WREG32(CP_ME_RAM_WADDR, 0);
1559
1560         fw_data = (const __be32 *)rdev->me_fw->data;
1561         WREG32(CP_ME_RAM_WADDR, 0);
1562         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
1563                 WREG32(CP_ME_RAM_DATA,
1564                        be32_to_cpup(fw_data++));
1565
1566         fw_data = (const __be32 *)rdev->pfp_fw->data;
1567         WREG32(CP_PFP_UCODE_ADDR, 0);
1568         for (i = 0; i < PFP_UCODE_SIZE; i++)
1569                 WREG32(CP_PFP_UCODE_DATA,
1570                        be32_to_cpup(fw_data++));
1571
1572         WREG32(CP_PFP_UCODE_ADDR, 0);
1573         WREG32(CP_ME_RAM_WADDR, 0);
1574         WREG32(CP_ME_RAM_RADDR, 0);
1575         return 0;
1576 }
1577
1578 int r600_cp_start(struct radeon_device *rdev)
1579 {
1580         int r;
1581         uint32_t cp_me;
1582
1583         r = radeon_ring_lock(rdev, 7);
1584         if (r) {
1585                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1586                 return r;
1587         }
1588         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
1589         radeon_ring_write(rdev, 0x1);
1590         if (rdev->family < CHIP_RV770) {
1591                 radeon_ring_write(rdev, 0x3);
1592                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
1593         } else {
1594                 radeon_ring_write(rdev, 0x0);
1595                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
1596         }
1597         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
1598         radeon_ring_write(rdev, 0);
1599         radeon_ring_write(rdev, 0);
1600         radeon_ring_unlock_commit(rdev);
1601
1602         cp_me = 0xff;
1603         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
1604         return 0;
1605 }
1606
1607 int r600_cp_resume(struct radeon_device *rdev)
1608 {
1609         u32 tmp;
1610         u32 rb_bufsz;
1611         int r;
1612
1613         /* Reset cp */
1614         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
1615         RREG32(GRBM_SOFT_RESET);
1616         mdelay(15);
1617         WREG32(GRBM_SOFT_RESET, 0);
1618
1619         /* Set ring buffer size */
1620         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
1621         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
1622 #ifdef __BIG_ENDIAN
1623         tmp |= BUF_SWAP_32BIT;
1624 #endif
1625         WREG32(CP_RB_CNTL, tmp);
1626         WREG32(CP_SEM_WAIT_TIMER, 0x4);
1627
1628         /* Set the write pointer delay */
1629         WREG32(CP_RB_WPTR_DELAY, 0);
1630
1631         /* Initialize the ring buffer's read and write pointers */
1632         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
1633         WREG32(CP_RB_RPTR_WR, 0);
1634         WREG32(CP_RB_WPTR, 0);
1635         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
1636         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
1637         mdelay(1);
1638         WREG32(CP_RB_CNTL, tmp);
1639
1640         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
1641         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
1642
1643         rdev->cp.rptr = RREG32(CP_RB_RPTR);
1644         rdev->cp.wptr = RREG32(CP_RB_WPTR);
1645
1646         r600_cp_start(rdev);
1647         rdev->cp.ready = true;
1648         r = radeon_ring_test(rdev);
1649         if (r) {
1650                 rdev->cp.ready = false;
1651                 return r;
1652         }
1653         return 0;
1654 }
1655
1656 void r600_cp_commit(struct radeon_device *rdev)
1657 {
1658         WREG32(CP_RB_WPTR, rdev->cp.wptr);
1659         (void)RREG32(CP_RB_WPTR);
1660 }
1661
1662 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
1663 {
1664         u32 rb_bufsz;
1665
1666         /* Align ring size */
1667         rb_bufsz = drm_order(ring_size / 8);
1668         ring_size = (1 << (rb_bufsz + 1)) * 4;
1669         rdev->cp.ring_size = ring_size;
1670         rdev->cp.align_mask = 16 - 1;
1671 }
1672
1673 void r600_cp_fini(struct radeon_device *rdev)
1674 {
1675         r600_cp_stop(rdev);
1676         radeon_ring_fini(rdev);
1677 }
1678
1679
1680 /*
1681  * GPU scratch registers helpers function.
1682  */
1683 void r600_scratch_init(struct radeon_device *rdev)
1684 {
1685         int i;
1686
1687         rdev->scratch.num_reg = 7;
1688         for (i = 0; i < rdev->scratch.num_reg; i++) {
1689                 rdev->scratch.free[i] = true;
1690                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
1691         }
1692 }
1693
1694 int r600_ring_test(struct radeon_device *rdev)
1695 {
1696         uint32_t scratch;
1697         uint32_t tmp = 0;
1698         unsigned i;
1699         int r;
1700
1701         r = radeon_scratch_get(rdev, &scratch);
1702         if (r) {
1703                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
1704                 return r;
1705         }
1706         WREG32(scratch, 0xCAFEDEAD);
1707         r = radeon_ring_lock(rdev, 3);
1708         if (r) {
1709                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
1710                 radeon_scratch_free(rdev, scratch);
1711                 return r;
1712         }
1713         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1714         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1715         radeon_ring_write(rdev, 0xDEADBEEF);
1716         radeon_ring_unlock_commit(rdev);
1717         for (i = 0; i < rdev->usec_timeout; i++) {
1718                 tmp = RREG32(scratch);
1719                 if (tmp == 0xDEADBEEF)
1720                         break;
1721                 DRM_UDELAY(1);
1722         }
1723         if (i < rdev->usec_timeout) {
1724                 DRM_INFO("ring test succeeded in %d usecs\n", i);
1725         } else {
1726                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
1727                           scratch, tmp);
1728                 r = -EINVAL;
1729         }
1730         radeon_scratch_free(rdev, scratch);
1731         return r;
1732 }
1733
1734 void r600_wb_disable(struct radeon_device *rdev)
1735 {
1736         int r;
1737
1738         WREG32(SCRATCH_UMSK, 0);
1739         if (rdev->wb.wb_obj) {
1740                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1741                 if (unlikely(r != 0))
1742                         return;
1743                 radeon_bo_kunmap(rdev->wb.wb_obj);
1744                 radeon_bo_unpin(rdev->wb.wb_obj);
1745                 radeon_bo_unreserve(rdev->wb.wb_obj);
1746         }
1747 }
1748
1749 void r600_wb_fini(struct radeon_device *rdev)
1750 {
1751         r600_wb_disable(rdev);
1752         if (rdev->wb.wb_obj) {
1753                 radeon_bo_unref(&rdev->wb.wb_obj);
1754                 rdev->wb.wb = NULL;
1755                 rdev->wb.wb_obj = NULL;
1756         }
1757 }
1758
1759 int r600_wb_enable(struct radeon_device *rdev)
1760 {
1761         int r;
1762
1763         if (rdev->wb.wb_obj == NULL) {
1764                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
1765                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
1766                 if (r) {
1767                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
1768                         return r;
1769                 }
1770                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
1771                 if (unlikely(r != 0)) {
1772                         r600_wb_fini(rdev);
1773                         return r;
1774                 }
1775                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
1776                                 &rdev->wb.gpu_addr);
1777                 if (r) {
1778                         radeon_bo_unreserve(rdev->wb.wb_obj);
1779                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
1780                         r600_wb_fini(rdev);
1781                         return r;
1782                 }
1783                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
1784                 radeon_bo_unreserve(rdev->wb.wb_obj);
1785                 if (r) {
1786                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
1787                         r600_wb_fini(rdev);
1788                         return r;
1789                 }
1790         }
1791         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
1792         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
1793         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
1794         WREG32(SCRATCH_UMSK, 0xff);
1795         return 0;
1796 }
1797
1798 void r600_fence_ring_emit(struct radeon_device *rdev,
1799                           struct radeon_fence *fence)
1800 {
1801         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
1802
1803         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
1804         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
1805         /* wait for 3D idle clean */
1806         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1807         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
1808         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
1809         /* Emit fence sequence & fire IRQ */
1810         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
1811         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
1812         radeon_ring_write(rdev, fence->seq);
1813         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
1814         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
1815         radeon_ring_write(rdev, RB_INT_STAT);
1816 }
1817
1818 int r600_copy_blit(struct radeon_device *rdev,
1819                    uint64_t src_offset, uint64_t dst_offset,
1820                    unsigned num_pages, struct radeon_fence *fence)
1821 {
1822         int r;
1823
1824         mutex_lock(&rdev->r600_blit.mutex);
1825         rdev->r600_blit.vb_ib = NULL;
1826         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
1827         if (r) {
1828                 if (rdev->r600_blit.vb_ib)
1829                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
1830                 mutex_unlock(&rdev->r600_blit.mutex);
1831                 return r;
1832         }
1833         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
1834         r600_blit_done_copy(rdev, fence);
1835         mutex_unlock(&rdev->r600_blit.mutex);
1836         return 0;
1837 }
1838
1839 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
1840                          uint32_t tiling_flags, uint32_t pitch,
1841                          uint32_t offset, uint32_t obj_size)
1842 {
1843         /* FIXME: implement */
1844         return 0;
1845 }
1846
1847 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
1848 {
1849         /* FIXME: implement */
1850 }
1851
1852
1853 bool r600_card_posted(struct radeon_device *rdev)
1854 {
1855         uint32_t reg;
1856
1857         /* first check CRTCs */
1858         reg = RREG32(D1CRTC_CONTROL) |
1859                 RREG32(D2CRTC_CONTROL);
1860         if (reg & CRTC_EN)
1861                 return true;
1862
1863         /* then check MEM_SIZE, in case the crtcs are off */
1864         if (RREG32(CONFIG_MEMSIZE))
1865                 return true;
1866
1867         return false;
1868 }
1869
1870 int r600_startup(struct radeon_device *rdev)
1871 {
1872         int r;
1873
1874         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1875                 r = r600_init_microcode(rdev);
1876                 if (r) {
1877                         DRM_ERROR("Failed to load firmware!\n");
1878                         return r;
1879                 }
1880         }
1881
1882         r600_mc_program(rdev);
1883         if (rdev->flags & RADEON_IS_AGP) {
1884                 r600_agp_enable(rdev);
1885         } else {
1886                 r = r600_pcie_gart_enable(rdev);
1887                 if (r)
1888                         return r;
1889         }
1890         r600_gpu_init(rdev);
1891         r = r600_blit_init(rdev);
1892         if (r) {
1893                 r600_blit_fini(rdev);
1894                 rdev->asic->copy = NULL;
1895                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
1896         }
1897         /* pin copy shader into vram */
1898         if (rdev->r600_blit.shader_obj) {
1899                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1900                 if (unlikely(r != 0))
1901                         return r;
1902                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1903                                 &rdev->r600_blit.shader_gpu_addr);
1904                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1905                 if (r) {
1906                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
1907                         return r;
1908                 }
1909         }
1910         /* Enable IRQ */
1911         r = r600_irq_init(rdev);
1912         if (r) {
1913                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1914                 radeon_irq_kms_fini(rdev);
1915                 return r;
1916         }
1917         r600_irq_set(rdev);
1918
1919         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1920         if (r)
1921                 return r;
1922         r = r600_cp_load_microcode(rdev);
1923         if (r)
1924                 return r;
1925         r = r600_cp_resume(rdev);
1926         if (r)
1927                 return r;
1928         /* write back buffer are not vital so don't worry about failure */
1929         r600_wb_enable(rdev);
1930         return 0;
1931 }
1932
1933 void r600_vga_set_state(struct radeon_device *rdev, bool state)
1934 {
1935         uint32_t temp;
1936
1937         temp = RREG32(CONFIG_CNTL);
1938         if (state == false) {
1939                 temp &= ~(1<<0);
1940                 temp |= (1<<1);
1941         } else {
1942                 temp &= ~(1<<1);
1943         }
1944         WREG32(CONFIG_CNTL, temp);
1945 }
1946
1947 int r600_resume(struct radeon_device *rdev)
1948 {
1949         int r;
1950
1951         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
1952          * posting will perform necessary task to bring back GPU into good
1953          * shape.
1954          */
1955         /* post card */
1956         atom_asic_init(rdev->mode_info.atom_context);
1957         /* Initialize clocks */
1958         r = radeon_clocks_init(rdev);
1959         if (r) {
1960                 return r;
1961         }
1962
1963         r = r600_startup(rdev);
1964         if (r) {
1965                 DRM_ERROR("r600 startup failed on resume\n");
1966                 return r;
1967         }
1968
1969         r = r600_ib_test(rdev);
1970         if (r) {
1971                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
1972                 return r;
1973         }
1974
1975         r = r600_audio_init(rdev);
1976         if (r) {
1977                 DRM_ERROR("radeon: audio resume failed\n");
1978                 return r;
1979         }
1980
1981         return r;
1982 }
1983
1984 int r600_suspend(struct radeon_device *rdev)
1985 {
1986         int r;
1987
1988         r600_audio_fini(rdev);
1989         /* FIXME: we should wait for ring to be empty */
1990         r600_cp_stop(rdev);
1991         rdev->cp.ready = false;
1992         r600_irq_suspend(rdev);
1993         r600_wb_disable(rdev);
1994         r600_pcie_gart_disable(rdev);
1995         /* unpin shaders bo */
1996         if (rdev->r600_blit.shader_obj) {
1997                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1998                 if (!r) {
1999                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2000                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2001                 }
2002         }
2003         return 0;
2004 }
2005
2006 /* Plan is to move initialization in that function and use
2007  * helper function so that radeon_device_init pretty much
2008  * do nothing more than calling asic specific function. This
2009  * should also allow to remove a bunch of callback function
2010  * like vram_info.
2011  */
2012 int r600_init(struct radeon_device *rdev)
2013 {
2014         int r;
2015
2016         r = radeon_dummy_page_init(rdev);
2017         if (r)
2018                 return r;
2019         if (r600_debugfs_mc_info_init(rdev)) {
2020                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2021         }
2022         /* This don't do much */
2023         r = radeon_gem_init(rdev);
2024         if (r)
2025                 return r;
2026         /* Read BIOS */
2027         if (!radeon_get_bios(rdev)) {
2028                 if (ASIC_IS_AVIVO(rdev))
2029                         return -EINVAL;
2030         }
2031         /* Must be an ATOMBIOS */
2032         if (!rdev->is_atom_bios) {
2033                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2034                 return -EINVAL;
2035         }
2036         r = radeon_atombios_init(rdev);
2037         if (r)
2038                 return r;
2039         /* Post card if necessary */
2040         if (!r600_card_posted(rdev)) {
2041                 if (!rdev->bios) {
2042                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2043                         return -EINVAL;
2044                 }
2045                 DRM_INFO("GPU not posted. posting now...\n");
2046                 atom_asic_init(rdev->mode_info.atom_context);
2047         }
2048         /* Initialize scratch registers */
2049         r600_scratch_init(rdev);
2050         /* Initialize surface registers */
2051         radeon_surface_init(rdev);
2052         /* Initialize clocks */
2053         radeon_get_clock_info(rdev->ddev);
2054         r = radeon_clocks_init(rdev);
2055         if (r)
2056                 return r;
2057         /* Initialize power management */
2058         radeon_pm_init(rdev);
2059         /* Fence driver */
2060         r = radeon_fence_driver_init(rdev);
2061         if (r)
2062                 return r;
2063         if (rdev->flags & RADEON_IS_AGP) {
2064                 r = radeon_agp_init(rdev);
2065                 if (r)
2066                         radeon_agp_disable(rdev);
2067         }
2068         r = r600_mc_init(rdev);
2069         if (r)
2070                 return r;
2071         /* Memory manager */
2072         r = radeon_bo_init(rdev);
2073         if (r)
2074                 return r;
2075
2076         r = radeon_irq_kms_init(rdev);
2077         if (r)
2078                 return r;
2079
2080         rdev->cp.ring_obj = NULL;
2081         r600_ring_init(rdev, 1024 * 1024);
2082
2083         rdev->ih.ring_obj = NULL;
2084         r600_ih_ring_init(rdev, 64 * 1024);
2085
2086         r = r600_pcie_gart_init(rdev);
2087         if (r)
2088                 return r;
2089
2090         rdev->accel_working = true;
2091         r = r600_startup(rdev);
2092         if (r) {
2093                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2094                 r600_cp_fini(rdev);
2095                 r600_wb_fini(rdev);
2096                 r600_irq_fini(rdev);
2097                 radeon_irq_kms_fini(rdev);
2098                 r600_pcie_gart_fini(rdev);
2099                 rdev->accel_working = false;
2100         }
2101         if (rdev->accel_working) {
2102                 r = radeon_ib_pool_init(rdev);
2103                 if (r) {
2104                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2105                         rdev->accel_working = false;
2106                 } else {
2107                         r = r600_ib_test(rdev);
2108                         if (r) {
2109                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2110                                 rdev->accel_working = false;
2111                         }
2112                 }
2113         }
2114
2115         r = r600_audio_init(rdev);
2116         if (r)
2117                 return r; /* TODO error handling */
2118         return 0;
2119 }
2120
2121 void r600_fini(struct radeon_device *rdev)
2122 {
2123         r600_audio_fini(rdev);
2124         r600_blit_fini(rdev);
2125         r600_cp_fini(rdev);
2126         r600_wb_fini(rdev);
2127         r600_irq_fini(rdev);
2128         radeon_irq_kms_fini(rdev);
2129         r600_pcie_gart_fini(rdev);
2130         radeon_agp_fini(rdev);
2131         radeon_gem_fini(rdev);
2132         radeon_fence_driver_fini(rdev);
2133         radeon_clocks_fini(rdev);
2134         radeon_bo_fini(rdev);
2135         radeon_atombios_fini(rdev);
2136         kfree(rdev->bios);
2137         rdev->bios = NULL;
2138         radeon_dummy_page_fini(rdev);
2139 }
2140
2141
2142 /*
2143  * CS stuff
2144  */
2145 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2146 {
2147         /* FIXME: implement */
2148         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2149         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2150         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2151         radeon_ring_write(rdev, ib->length_dw);
2152 }
2153
2154 int r600_ib_test(struct radeon_device *rdev)
2155 {
2156         struct radeon_ib *ib;
2157         uint32_t scratch;
2158         uint32_t tmp = 0;
2159         unsigned i;
2160         int r;
2161
2162         r = radeon_scratch_get(rdev, &scratch);
2163         if (r) {
2164                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2165                 return r;
2166         }
2167         WREG32(scratch, 0xCAFEDEAD);
2168         r = radeon_ib_get(rdev, &ib);
2169         if (r) {
2170                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2171                 return r;
2172         }
2173         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2174         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2175         ib->ptr[2] = 0xDEADBEEF;
2176         ib->ptr[3] = PACKET2(0);
2177         ib->ptr[4] = PACKET2(0);
2178         ib->ptr[5] = PACKET2(0);
2179         ib->ptr[6] = PACKET2(0);
2180         ib->ptr[7] = PACKET2(0);
2181         ib->ptr[8] = PACKET2(0);
2182         ib->ptr[9] = PACKET2(0);
2183         ib->ptr[10] = PACKET2(0);
2184         ib->ptr[11] = PACKET2(0);
2185         ib->ptr[12] = PACKET2(0);
2186         ib->ptr[13] = PACKET2(0);
2187         ib->ptr[14] = PACKET2(0);
2188         ib->ptr[15] = PACKET2(0);
2189         ib->length_dw = 16;
2190         r = radeon_ib_schedule(rdev, ib);
2191         if (r) {
2192                 radeon_scratch_free(rdev, scratch);
2193                 radeon_ib_free(rdev, &ib);
2194                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2195                 return r;
2196         }
2197         r = radeon_fence_wait(ib->fence, false);
2198         if (r) {
2199                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2200                 return r;
2201         }
2202         for (i = 0; i < rdev->usec_timeout; i++) {
2203                 tmp = RREG32(scratch);
2204                 if (tmp == 0xDEADBEEF)
2205                         break;
2206                 DRM_UDELAY(1);
2207         }
2208         if (i < rdev->usec_timeout) {
2209                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2210         } else {
2211                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2212                           scratch, tmp);
2213                 r = -EINVAL;
2214         }
2215         radeon_scratch_free(rdev, scratch);
2216         radeon_ib_free(rdev, &ib);
2217         return r;
2218 }
2219
2220 /*
2221  * Interrupts
2222  *
2223  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2224  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2225  * writing to the ring and the GPU consuming, the GPU writes to the ring
2226  * and host consumes.  As the host irq handler processes interrupts, it
2227  * increments the rptr.  When the rptr catches up with the wptr, all the
2228  * current interrupts have been processed.
2229  */
2230
2231 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2232 {
2233         u32 rb_bufsz;
2234
2235         /* Align ring size */
2236         rb_bufsz = drm_order(ring_size / 4);
2237         ring_size = (1 << rb_bufsz) * 4;
2238         rdev->ih.ring_size = ring_size;
2239         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2240         rdev->ih.rptr = 0;
2241 }
2242
2243 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2244 {
2245         int r;
2246
2247         /* Allocate ring buffer */
2248         if (rdev->ih.ring_obj == NULL) {
2249                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2250                                      true,
2251                                      RADEON_GEM_DOMAIN_GTT,
2252                                      &rdev->ih.ring_obj);
2253                 if (r) {
2254                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2255                         return r;
2256                 }
2257                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2258                 if (unlikely(r != 0))
2259                         return r;
2260                 r = radeon_bo_pin(rdev->ih.ring_obj,
2261                                   RADEON_GEM_DOMAIN_GTT,
2262                                   &rdev->ih.gpu_addr);
2263                 if (r) {
2264                         radeon_bo_unreserve(rdev->ih.ring_obj);
2265                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2266                         return r;
2267                 }
2268                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2269                                    (void **)&rdev->ih.ring);
2270                 radeon_bo_unreserve(rdev->ih.ring_obj);
2271                 if (r) {
2272                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2273                         return r;
2274                 }
2275         }
2276         return 0;
2277 }
2278
2279 static void r600_ih_ring_fini(struct radeon_device *rdev)
2280 {
2281         int r;
2282         if (rdev->ih.ring_obj) {
2283                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2284                 if (likely(r == 0)) {
2285                         radeon_bo_kunmap(rdev->ih.ring_obj);
2286                         radeon_bo_unpin(rdev->ih.ring_obj);
2287                         radeon_bo_unreserve(rdev->ih.ring_obj);
2288                 }
2289                 radeon_bo_unref(&rdev->ih.ring_obj);
2290                 rdev->ih.ring = NULL;
2291                 rdev->ih.ring_obj = NULL;
2292         }
2293 }
2294
2295 static void r600_rlc_stop(struct radeon_device *rdev)
2296 {
2297
2298         if (rdev->family >= CHIP_RV770) {
2299                 /* r7xx asics need to soft reset RLC before halting */
2300                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2301                 RREG32(SRBM_SOFT_RESET);
2302                 udelay(15000);
2303                 WREG32(SRBM_SOFT_RESET, 0);
2304                 RREG32(SRBM_SOFT_RESET);
2305         }
2306
2307         WREG32(RLC_CNTL, 0);
2308 }
2309
2310 static void r600_rlc_start(struct radeon_device *rdev)
2311 {
2312         WREG32(RLC_CNTL, RLC_ENABLE);
2313 }
2314
2315 static int r600_rlc_init(struct radeon_device *rdev)
2316 {
2317         u32 i;
2318         const __be32 *fw_data;
2319
2320         if (!rdev->rlc_fw)
2321                 return -EINVAL;
2322
2323         r600_rlc_stop(rdev);
2324
2325         WREG32(RLC_HB_BASE, 0);
2326         WREG32(RLC_HB_CNTL, 0);
2327         WREG32(RLC_HB_RPTR, 0);
2328         WREG32(RLC_HB_WPTR, 0);
2329         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2330         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2331         WREG32(RLC_MC_CNTL, 0);
2332         WREG32(RLC_UCODE_CNTL, 0);
2333
2334         fw_data = (const __be32 *)rdev->rlc_fw->data;
2335         if (rdev->family >= CHIP_RV770) {
2336                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2337                         WREG32(RLC_UCODE_ADDR, i);
2338                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2339                 }
2340         } else {
2341                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2342                         WREG32(RLC_UCODE_ADDR, i);
2343                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2344                 }
2345         }
2346         WREG32(RLC_UCODE_ADDR, 0);
2347
2348         r600_rlc_start(rdev);
2349
2350         return 0;
2351 }
2352
2353 static void r600_enable_interrupts(struct radeon_device *rdev)
2354 {
2355         u32 ih_cntl = RREG32(IH_CNTL);
2356         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2357
2358         ih_cntl |= ENABLE_INTR;
2359         ih_rb_cntl |= IH_RB_ENABLE;
2360         WREG32(IH_CNTL, ih_cntl);
2361         WREG32(IH_RB_CNTL, ih_rb_cntl);
2362         rdev->ih.enabled = true;
2363 }
2364
2365 static void r600_disable_interrupts(struct radeon_device *rdev)
2366 {
2367         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2368         u32 ih_cntl = RREG32(IH_CNTL);
2369
2370         ih_rb_cntl &= ~IH_RB_ENABLE;
2371         ih_cntl &= ~ENABLE_INTR;
2372         WREG32(IH_RB_CNTL, ih_rb_cntl);
2373         WREG32(IH_CNTL, ih_cntl);
2374         /* set rptr, wptr to 0 */
2375         WREG32(IH_RB_RPTR, 0);
2376         WREG32(IH_RB_WPTR, 0);
2377         rdev->ih.enabled = false;
2378         rdev->ih.wptr = 0;
2379         rdev->ih.rptr = 0;
2380 }
2381
2382 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2383 {
2384         u32 tmp;
2385
2386         WREG32(CP_INT_CNTL, 0);
2387         WREG32(GRBM_INT_CNTL, 0);
2388         WREG32(DxMODE_INT_MASK, 0);
2389         if (ASIC_IS_DCE3(rdev)) {
2390                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2391                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2392                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2393                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2394                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2395                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2396                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2397                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2398                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2399                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2400                 if (ASIC_IS_DCE32(rdev)) {
2401                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2402                         WREG32(DC_HPD5_INT_CONTROL, 0);
2403                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2404                         WREG32(DC_HPD6_INT_CONTROL, 0);
2405                 }
2406         } else {
2407                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2408                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2409                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2410                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, 0);
2411                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2412                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, 0);
2413                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2414                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, 0);
2415         }
2416 }
2417
2418 int r600_irq_init(struct radeon_device *rdev)
2419 {
2420         int ret = 0;
2421         int rb_bufsz;
2422         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2423
2424         /* allocate ring */
2425         ret = r600_ih_ring_alloc(rdev);
2426         if (ret)
2427                 return ret;
2428
2429         /* disable irqs */
2430         r600_disable_interrupts(rdev);
2431
2432         /* init rlc */
2433         ret = r600_rlc_init(rdev);
2434         if (ret) {
2435                 r600_ih_ring_fini(rdev);
2436                 return ret;
2437         }
2438
2439         /* setup interrupt control */
2440         /* set dummy read address to ring address */
2441         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2442         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2443         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2444          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2445          */
2446         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2447         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2448         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2449         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2450
2451         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2452         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2453
2454         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2455                       IH_WPTR_OVERFLOW_CLEAR |
2456                       (rb_bufsz << 1));
2457         /* WPTR writeback, not yet */
2458         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2459         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2460         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2461
2462         WREG32(IH_RB_CNTL, ih_rb_cntl);
2463
2464         /* set rptr, wptr to 0 */
2465         WREG32(IH_RB_RPTR, 0);
2466         WREG32(IH_RB_WPTR, 0);
2467
2468         /* Default settings for IH_CNTL (disabled at first) */
2469         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2470         /* RPTR_REARM only works if msi's are enabled */
2471         if (rdev->msi_enabled)
2472                 ih_cntl |= RPTR_REARM;
2473
2474 #ifdef __BIG_ENDIAN
2475         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2476 #endif
2477         WREG32(IH_CNTL, ih_cntl);
2478
2479         /* force the active interrupt state to all disabled */
2480         r600_disable_interrupt_state(rdev);
2481
2482         /* enable irqs */
2483         r600_enable_interrupts(rdev);
2484
2485         return ret;
2486 }
2487
2488 void r600_irq_suspend(struct radeon_device *rdev)
2489 {
2490         r600_disable_interrupts(rdev);
2491         r600_rlc_stop(rdev);
2492 }
2493
2494 void r600_irq_fini(struct radeon_device *rdev)
2495 {
2496         r600_irq_suspend(rdev);
2497         r600_ih_ring_fini(rdev);
2498 }
2499
2500 int r600_irq_set(struct radeon_device *rdev)
2501 {
2502         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
2503         u32 mode_int = 0;
2504         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
2505
2506         if (!rdev->irq.installed) {
2507                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
2508                 return -EINVAL;
2509         }
2510         /* don't enable anything if the ih is disabled */
2511         if (!rdev->ih.enabled) {
2512                 r600_disable_interrupts(rdev);
2513                 /* force the active interrupt state to all disabled */
2514                 r600_disable_interrupt_state(rdev);
2515                 return 0;
2516         }
2517
2518         if (ASIC_IS_DCE3(rdev)) {
2519                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2520                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2521                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2522                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
2523                 if (ASIC_IS_DCE32(rdev)) {
2524                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
2525                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
2526                 }
2527         } else {
2528                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
2529                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
2530                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
2531         }
2532
2533         if (rdev->irq.sw_int) {
2534                 DRM_DEBUG("r600_irq_set: sw int\n");
2535                 cp_int_cntl |= RB_INT_ENABLE;
2536         }
2537         if (rdev->irq.crtc_vblank_int[0]) {
2538                 DRM_DEBUG("r600_irq_set: vblank 0\n");
2539                 mode_int |= D1MODE_VBLANK_INT_MASK;
2540         }
2541         if (rdev->irq.crtc_vblank_int[1]) {
2542                 DRM_DEBUG("r600_irq_set: vblank 1\n");
2543                 mode_int |= D2MODE_VBLANK_INT_MASK;
2544         }
2545         if (rdev->irq.hpd[0]) {
2546                 DRM_DEBUG("r600_irq_set: hpd 1\n");
2547                 hpd1 |= DC_HPDx_INT_EN;
2548         }
2549         if (rdev->irq.hpd[1]) {
2550                 DRM_DEBUG("r600_irq_set: hpd 2\n");
2551                 hpd2 |= DC_HPDx_INT_EN;
2552         }
2553         if (rdev->irq.hpd[2]) {
2554                 DRM_DEBUG("r600_irq_set: hpd 3\n");
2555                 hpd3 |= DC_HPDx_INT_EN;
2556         }
2557         if (rdev->irq.hpd[3]) {
2558                 DRM_DEBUG("r600_irq_set: hpd 4\n");
2559                 hpd4 |= DC_HPDx_INT_EN;
2560         }
2561         if (rdev->irq.hpd[4]) {
2562                 DRM_DEBUG("r600_irq_set: hpd 5\n");
2563                 hpd5 |= DC_HPDx_INT_EN;
2564         }
2565         if (rdev->irq.hpd[5]) {
2566                 DRM_DEBUG("r600_irq_set: hpd 6\n");
2567                 hpd6 |= DC_HPDx_INT_EN;
2568         }
2569
2570         WREG32(CP_INT_CNTL, cp_int_cntl);
2571         WREG32(DxMODE_INT_MASK, mode_int);
2572         if (ASIC_IS_DCE3(rdev)) {
2573                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
2574                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
2575                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
2576                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
2577                 if (ASIC_IS_DCE32(rdev)) {
2578                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
2579                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
2580                 }
2581         } else {
2582                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
2583                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
2584                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
2585         }
2586
2587         return 0;
2588 }
2589
2590 static inline void r600_irq_ack(struct radeon_device *rdev,
2591                                 u32 *disp_int,
2592                                 u32 *disp_int_cont,
2593                                 u32 *disp_int_cont2)
2594 {
2595         u32 tmp;
2596
2597         if (ASIC_IS_DCE3(rdev)) {
2598                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
2599                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
2600                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
2601         } else {
2602                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
2603                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
2604                 *disp_int_cont2 = 0;
2605         }
2606
2607         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
2608                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2609         if (*disp_int & LB_D1_VLINE_INTERRUPT)
2610                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2611         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
2612                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
2613         if (*disp_int & LB_D2_VLINE_INTERRUPT)
2614                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
2615         if (*disp_int & DC_HPD1_INTERRUPT) {
2616                 if (ASIC_IS_DCE3(rdev)) {
2617                         tmp = RREG32(DC_HPD1_INT_CONTROL);
2618                         tmp |= DC_HPDx_INT_ACK;
2619                         WREG32(DC_HPD1_INT_CONTROL, tmp);
2620                 } else {
2621                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
2622                         tmp |= DC_HPDx_INT_ACK;
2623                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2624                 }
2625         }
2626         if (*disp_int & DC_HPD2_INTERRUPT) {
2627                 if (ASIC_IS_DCE3(rdev)) {
2628                         tmp = RREG32(DC_HPD2_INT_CONTROL);
2629                         tmp |= DC_HPDx_INT_ACK;
2630                         WREG32(DC_HPD2_INT_CONTROL, tmp);
2631                 } else {
2632                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
2633                         tmp |= DC_HPDx_INT_ACK;
2634                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2635                 }
2636         }
2637         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
2638                 if (ASIC_IS_DCE3(rdev)) {
2639                         tmp = RREG32(DC_HPD3_INT_CONTROL);
2640                         tmp |= DC_HPDx_INT_ACK;
2641                         WREG32(DC_HPD3_INT_CONTROL, tmp);
2642                 } else {
2643                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
2644                         tmp |= DC_HPDx_INT_ACK;
2645                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2646                 }
2647         }
2648         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
2649                 tmp = RREG32(DC_HPD4_INT_CONTROL);
2650                 tmp |= DC_HPDx_INT_ACK;
2651                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2652         }
2653         if (ASIC_IS_DCE32(rdev)) {
2654                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
2655                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2656                         tmp |= DC_HPDx_INT_ACK;
2657                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2658                 }
2659                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
2660                         tmp = RREG32(DC_HPD5_INT_CONTROL);
2661                         tmp |= DC_HPDx_INT_ACK;
2662                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2663                 }
2664         }
2665 }
2666
2667 void r600_irq_disable(struct radeon_device *rdev)
2668 {
2669         u32 disp_int, disp_int_cont, disp_int_cont2;
2670
2671         r600_disable_interrupts(rdev);
2672         /* Wait and acknowledge irq */
2673         mdelay(1);
2674         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2675         r600_disable_interrupt_state(rdev);
2676 }
2677
2678 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
2679 {
2680         u32 wptr, tmp;
2681
2682         /* XXX use writeback */
2683         wptr = RREG32(IH_RB_WPTR);
2684
2685         if (wptr & RB_OVERFLOW) {
2686                 /* When a ring buffer overflow happen start parsing interrupt
2687                  * from the last not overwritten vector (wptr + 16). Hopefully
2688                  * this should allow us to catchup.
2689                  */
2690                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
2691                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
2692                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
2693                 tmp = RREG32(IH_RB_CNTL);
2694                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
2695                 WREG32(IH_RB_CNTL, tmp);
2696         }
2697         return (wptr & rdev->ih.ptr_mask);
2698 }
2699
2700 /*        r600 IV Ring
2701  * Each IV ring entry is 128 bits:
2702  * [7:0]    - interrupt source id
2703  * [31:8]   - reserved
2704  * [59:32]  - interrupt source data
2705  * [127:60]  - reserved
2706  *
2707  * The basic interrupt vector entries
2708  * are decoded as follows:
2709  * src_id  src_data  description
2710  *      1         0  D1 Vblank
2711  *      1         1  D1 Vline
2712  *      5         0  D2 Vblank
2713  *      5         1  D2 Vline
2714  *     19         0  FP Hot plug detection A
2715  *     19         1  FP Hot plug detection B
2716  *     19         2  DAC A auto-detection
2717  *     19         3  DAC B auto-detection
2718  *    176         -  CP_INT RB
2719  *    177         -  CP_INT IB1
2720  *    178         -  CP_INT IB2
2721  *    181         -  EOP Interrupt
2722  *    233         -  GUI Idle
2723  *
2724  * Note, these are based on r600 and may need to be
2725  * adjusted or added to on newer asics
2726  */
2727
2728 int r600_irq_process(struct radeon_device *rdev)
2729 {
2730         u32 wptr = r600_get_ih_wptr(rdev);
2731         u32 rptr = rdev->ih.rptr;
2732         u32 src_id, src_data;
2733         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
2734         unsigned long flags;
2735         bool queue_hotplug = false;
2736
2737         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
2738         if (!rdev->ih.enabled)
2739                 return IRQ_NONE;
2740
2741         spin_lock_irqsave(&rdev->ih.lock, flags);
2742
2743         if (rptr == wptr) {
2744                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2745                 return IRQ_NONE;
2746         }
2747         if (rdev->shutdown) {
2748                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
2749                 return IRQ_NONE;
2750         }
2751
2752 restart_ih:
2753         /* display interrupts */
2754         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
2755
2756         rdev->ih.wptr = wptr;
2757         while (rptr != wptr) {
2758                 /* wptr/rptr are in bytes! */
2759                 ring_index = rptr / 4;
2760                 src_id =  rdev->ih.ring[ring_index] & 0xff;
2761                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
2762
2763                 switch (src_id) {
2764                 case 1: /* D1 vblank/vline */
2765                         switch (src_data) {
2766                         case 0: /* D1 vblank */
2767                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
2768                                         drm_handle_vblank(rdev->ddev, 0);
2769                                         wake_up(&rdev->irq.vblank_queue);
2770                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
2771                                         DRM_DEBUG("IH: D1 vblank\n");
2772                                 }
2773                                 break;
2774                         case 1: /* D1 vline */
2775                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
2776                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
2777                                         DRM_DEBUG("IH: D1 vline\n");
2778                                 }
2779                                 break;
2780                         default:
2781                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2782                                 break;
2783                         }
2784                         break;
2785                 case 5: /* D2 vblank/vline */
2786                         switch (src_data) {
2787                         case 0: /* D2 vblank */
2788                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
2789                                         drm_handle_vblank(rdev->ddev, 1);
2790                                         wake_up(&rdev->irq.vblank_queue);
2791                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
2792                                         DRM_DEBUG("IH: D2 vblank\n");
2793                                 }
2794                                 break;
2795                         case 1: /* D1 vline */
2796                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
2797                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
2798                                         DRM_DEBUG("IH: D2 vline\n");
2799                                 }
2800                                 break;
2801                         default:
2802                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2803                                 break;
2804                         }
2805                         break;
2806                 case 19: /* HPD/DAC hotplug */
2807                         switch (src_data) {
2808                         case 0:
2809                                 if (disp_int & DC_HPD1_INTERRUPT) {
2810                                         disp_int &= ~DC_HPD1_INTERRUPT;
2811                                         queue_hotplug = true;
2812                                         DRM_DEBUG("IH: HPD1\n");
2813                                 }
2814                                 break;
2815                         case 1:
2816                                 if (disp_int & DC_HPD2_INTERRUPT) {
2817                                         disp_int &= ~DC_HPD2_INTERRUPT;
2818                                         queue_hotplug = true;
2819                                         DRM_DEBUG("IH: HPD2\n");
2820                                 }
2821                                 break;
2822                         case 4:
2823                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
2824                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
2825                                         queue_hotplug = true;
2826                                         DRM_DEBUG("IH: HPD3\n");
2827                                 }
2828                                 break;
2829                         case 5:
2830                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
2831                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
2832                                         queue_hotplug = true;
2833                                         DRM_DEBUG("IH: HPD4\n");
2834                                 }
2835                                 break;
2836                         case 10:
2837                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
2838                                         disp_int_cont &= ~DC_HPD5_INTERRUPT;
2839                                         queue_hotplug = true;
2840                                         DRM_DEBUG("IH: HPD5\n");
2841                                 }
2842                                 break;
2843                         case 12:
2844                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
2845                                         disp_int_cont &= ~DC_HPD6_INTERRUPT;
2846                                         queue_hotplug = true;
2847                                         DRM_DEBUG("IH: HPD6\n");
2848                                 }
2849                                 break;
2850                         default:
2851                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2852                                 break;
2853                         }
2854                         break;
2855                 case 176: /* CP_INT in ring buffer */
2856                 case 177: /* CP_INT in IB1 */
2857                 case 178: /* CP_INT in IB2 */
2858                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
2859                         radeon_fence_process(rdev);
2860                         break;
2861                 case 181: /* CP EOP event */
2862                         DRM_DEBUG("IH: CP EOP\n");
2863                         break;
2864                 default:
2865                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
2866                         break;
2867                 }
2868
2869                 /* wptr/rptr are in bytes! */
2870                 rptr += 16;
2871                 rptr &= rdev->ih.ptr_mask;
2872         }
2873         /* make sure wptr hasn't changed while processing */
2874         wptr = r600_get_ih_wptr(rdev);
2875         if (wptr != rdev->ih.wptr)
2876                 goto restart_ih;
2877         if (queue_hotplug)
2878                 queue_work(rdev->wq, &rdev->hotplug_work);
2879         rdev->ih.rptr = rptr;
2880         WREG32(IH_RB_RPTR, rdev->ih.rptr);
2881         spin_unlock_irqrestore(&rdev->ih.lock, flags);
2882         return IRQ_HANDLED;
2883 }
2884
2885 /*
2886  * Debugfs info
2887  */
2888 #if defined(CONFIG_DEBUG_FS)
2889
2890 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
2891 {
2892         struct drm_info_node *node = (struct drm_info_node *) m->private;
2893         struct drm_device *dev = node->minor->dev;
2894         struct radeon_device *rdev = dev->dev_private;
2895         unsigned count, i, j;
2896
2897         radeon_ring_free_size(rdev);
2898         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
2899         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
2900         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
2901         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
2902         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
2903         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
2904         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2905         seq_printf(m, "%u dwords in ring\n", count);
2906         i = rdev->cp.rptr;
2907         for (j = 0; j <= count; j++) {
2908                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2909                 i = (i + 1) & rdev->cp.ptr_mask;
2910         }
2911         return 0;
2912 }
2913
2914 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
2915 {
2916         struct drm_info_node *node = (struct drm_info_node *) m->private;
2917         struct drm_device *dev = node->minor->dev;
2918         struct radeon_device *rdev = dev->dev_private;
2919
2920         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
2921         DREG32_SYS(m, rdev, VM_L2_STATUS);
2922         return 0;
2923 }
2924
2925 static struct drm_info_list r600_mc_info_list[] = {
2926         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
2927         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
2928 };
2929 #endif
2930
2931 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
2932 {
2933 #if defined(CONFIG_DEBUG_FS)
2934         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
2935 #else
2936         return 0;
2937 #endif
2938 }
2939
2940 /**
2941  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
2942  * rdev: radeon device structure
2943  * bo: buffer object struct which userspace is waiting for idle
2944  *
2945  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
2946  * through ring buffer, this leads to corruption in rendering, see
2947  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
2948  * directly perform HDP flush by writing register through MMIO.
2949  */
2950 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
2951 {
2952         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
2953 }