SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/r600.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <linux/slab.h>
  29 #include <linux/seq_file.h>
  30 #include <linux/firmware.h>
  31 #include <linux/platform_device.h>
  32 #include "drmP.h"
  33 #include "radeon_drm.h"
  34 #include "radeon.h"
  35 #include "radeon_asic.h"
  36 #include "radeon_mode.h"
  37 #include "r600d.h"
  38 #include "atom.h"
  39 #include "avivod.h"
  40
  41 #define PFP_UCODE_SIZE 576
  42 #define PM4_UCODE_SIZE 1792
  43 #define RLC_UCODE_SIZE 768
  44 #define R700_PFP_UCODE_SIZE 848
  45 #define R700_PM4_UCODE_SIZE 1360
  46 #define R700_RLC_UCODE_SIZE 1024
  47 #define EVERGREEN_PFP_UCODE_SIZE 1120
  48 #define EVERGREEN_PM4_UCODE_SIZE 1376
  49 #define EVERGREEN_RLC_UCODE_SIZE 768
  50
  51 /* Firmware Names */
  52 MODULE_FIRMWARE("radeon/R600_pfp.bin");
  53 MODULE_FIRMWARE("radeon/R600_me.bin");
  54 MODULE_FIRMWARE("radeon/RV610_pfp.bin");
  55 MODULE_FIRMWARE("radeon/RV610_me.bin");
  56 MODULE_FIRMWARE("radeon/RV630_pfp.bin");
  57 MODULE_FIRMWARE("radeon/RV630_me.bin");
  58 MODULE_FIRMWARE("radeon/RV620_pfp.bin");
  59 MODULE_FIRMWARE("radeon/RV620_me.bin");
  60 MODULE_FIRMWARE("radeon/RV635_pfp.bin");
  61 MODULE_FIRMWARE("radeon/RV635_me.bin");
  62 MODULE_FIRMWARE("radeon/RV670_pfp.bin");
  63 MODULE_FIRMWARE("radeon/RV670_me.bin");
  64 MODULE_FIRMWARE("radeon/RS780_pfp.bin");
  65 MODULE_FIRMWARE("radeon/RS780_me.bin");
  66 MODULE_FIRMWARE("radeon/RV770_pfp.bin");
  67 MODULE_FIRMWARE("radeon/RV770_me.bin");
  68 MODULE_FIRMWARE("radeon/RV730_pfp.bin");
  69 MODULE_FIRMWARE("radeon/RV730_me.bin");
  70 MODULE_FIRMWARE("radeon/RV710_pfp.bin");
  71 MODULE_FIRMWARE("radeon/RV710_me.bin");
  72 MODULE_FIRMWARE("radeon/R600_rlc.bin");
  73 MODULE_FIRMWARE("radeon/R700_rlc.bin");
  74 MODULE_FIRMWARE("radeon/CEDAR_pfp.bin");
  75 MODULE_FIRMWARE("radeon/CEDAR_me.bin");
  76 MODULE_FIRMWARE("radeon/CEDAR_rlc.bin");
  77 MODULE_FIRMWARE("radeon/REDWOOD_pfp.bin");
  78 MODULE_FIRMWARE("radeon/REDWOOD_me.bin");
  79 MODULE_FIRMWARE("radeon/REDWOOD_rlc.bin");
  80 MODULE_FIRMWARE("radeon/JUNIPER_pfp.bin");
  81 MODULE_FIRMWARE("radeon/JUNIPER_me.bin");
  82 MODULE_FIRMWARE("radeon/JUNIPER_rlc.bin");
  83 MODULE_FIRMWARE("radeon/CYPRESS_pfp.bin");
  84 MODULE_FIRMWARE("radeon/CYPRESS_me.bin");
  85 MODULE_FIRMWARE("radeon/CYPRESS_rlc.bin");
  86
  87 int r600_debugfs_mc_info_init(struct radeon_device *rdev);
  88
  89 /* r600,rv610,rv630,rv620,rv635,rv670 */
  90 int r600_mc_wait_for_idle(struct radeon_device *rdev);
  91 void r600_gpu_init(struct radeon_device *rdev);
  92 void r600_fini(struct radeon_device *rdev);
  93 void r600_irq_disable(struct radeon_device *rdev);
  94
  95 void r600_pm_get_dynpm_state(struct radeon_device *rdev)
  96 {
  97         int i;
  98
  99         rdev->pm.dynpm_can_upclock = true;
 100         rdev->pm.dynpm_can_downclock = true;
 101
 102         /* power state array is low to high, default is first */
 103         if ((rdev->flags & RADEON_IS_IGP) || (rdev->family == CHIP_R600)) {
 104                 int min_power_state_index = 0;
 105
 106                 if (rdev->pm.num_power_states > 2)
 107                         min_power_state_index = 1;
 108
 109                 switch (rdev->pm.dynpm_planned_action) {
 110                 case DYNPM_ACTION_MINIMUM:
 111                         rdev->pm.requested_power_state_index = min_power_state_index;
 112                         rdev->pm.requested_clock_mode_index = 0;
 113                         rdev->pm.dynpm_can_downclock = false;
 114                         break;
 115                 case DYNPM_ACTION_DOWNCLOCK:
 116                         if (rdev->pm.current_power_state_index == min_power_state_index) {
 117                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 118                                 rdev->pm.dynpm_can_downclock = false;
 119                         } else {
 120                                 if (rdev->pm.active_crtc_count > 1) {
 121                                         for (i = 0; i < rdev->pm.num_power_states; i++) {
 122                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 123                                                         continue;
 124                                                 else if (i >= rdev->pm.current_power_state_index) {
 125                                                         rdev->pm.requested_power_state_index =
 126                                                                 rdev->pm.current_power_state_index;
 127                                                         break;
 128                                                 } else {
 129                                                         rdev->pm.requested_power_state_index = i;
 130                                                         break;
 131                                                 }
 132                                         }
 133                                 } else
 134                                         rdev->pm.requested_power_state_index =
 135                                                 rdev->pm.current_power_state_index - 1;
 136                         }
 137                         rdev->pm.requested_clock_mode_index = 0;
 138                         /* don't use the power state if crtcs are active and no display flag is set */
 139                         if ((rdev->pm.active_crtc_count > 0) &&
 140                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 141                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 142                              RADEON_PM_MODE_NO_DISPLAY)) {
 143                                 rdev->pm.requested_power_state_index++;
 144                         }
 145                         break;
 146                 case DYNPM_ACTION_UPCLOCK:
 147                         if (rdev->pm.current_power_state_index == (rdev->pm.num_power_states - 1)) {
 148                                 rdev->pm.requested_power_state_index = rdev->pm.current_power_state_index;
 149                                 rdev->pm.dynpm_can_upclock = false;
 150                         } else {
 151                                 if (rdev->pm.active_crtc_count > 1) {
 152                                         for (i = (rdev->pm.num_power_states - 1); i >= 0; i--) {
 153                                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 154                                                         continue;
 155                                                 else if (i <= rdev->pm.current_power_state_index) {
 156                                                         rdev->pm.requested_power_state_index =
 157                                                                 rdev->pm.current_power_state_index;
 158                                                         break;
 159                                                 } else {
 160                                                         rdev->pm.requested_power_state_index = i;
 161                                                         break;
 162                                                 }
 163                                         }
 164                                 } else
 165                                         rdev->pm.requested_power_state_index =
 166                                                 rdev->pm.current_power_state_index + 1;
 167                         }
 168                         rdev->pm.requested_clock_mode_index = 0;
 169                         break;
 170                 case DYNPM_ACTION_DEFAULT:
 171                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 172                         rdev->pm.requested_clock_mode_index = 0;
 173                         rdev->pm.dynpm_can_upclock = false;
 174                         break;
 175                 case DYNPM_ACTION_NONE:
 176                 default:
 177                         DRM_ERROR("Requested mode for not defined action\n");
 178                         return;
 179                 }
 180         } else {
 181                 /* XXX select a power state based on AC/DC, single/dualhead, etc. */
 182                 /* for now just select the first power state and switch between clock modes */
 183                 /* power state array is low to high, default is first (0) */
 184                 if (rdev->pm.active_crtc_count > 1) {
 185                         rdev->pm.requested_power_state_index = -1;
 186                         /* start at 1 as we don't want the default mode */
 187                         for (i = 1; i < rdev->pm.num_power_states; i++) {
 188                                 if (rdev->pm.power_state[i].flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 189                                         continue;
 190                                 else if ((rdev->pm.power_state[i].type == POWER_STATE_TYPE_PERFORMANCE) ||
 191                                          (rdev->pm.power_state[i].type == POWER_STATE_TYPE_BATTERY)) {
 192                                         rdev->pm.requested_power_state_index = i;
 193                                         break;
 194                                 }
 195                         }
 196                         /* if nothing selected, grab the default state. */
 197                         if (rdev->pm.requested_power_state_index == -1)
 198                                 rdev->pm.requested_power_state_index = 0;
 199                 } else
 200                         rdev->pm.requested_power_state_index = 1;
 201
 202                 switch (rdev->pm.dynpm_planned_action) {
 203                 case DYNPM_ACTION_MINIMUM:
 204                         rdev->pm.requested_clock_mode_index = 0;
 205                         rdev->pm.dynpm_can_downclock = false;
 206                         break;
 207                 case DYNPM_ACTION_DOWNCLOCK:
 208                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 209                                 if (rdev->pm.current_clock_mode_index == 0) {
 210                                         rdev->pm.requested_clock_mode_index = 0;
 211                                         rdev->pm.dynpm_can_downclock = false;
 212                                 } else
 213                                         rdev->pm.requested_clock_mode_index =
 214                                                 rdev->pm.current_clock_mode_index - 1;
 215                         } else {
 216                                 rdev->pm.requested_clock_mode_index = 0;
 217                                 rdev->pm.dynpm_can_downclock = false;
 218                         }
 219                         /* don't use the power state if crtcs are active and no display flag is set */
 220                         if ((rdev->pm.active_crtc_count > 0) &&
 221                             (rdev->pm.power_state[rdev->pm.requested_power_state_index].
 222                              clock_info[rdev->pm.requested_clock_mode_index].flags &
 223                              RADEON_PM_MODE_NO_DISPLAY)) {
 224                                 rdev->pm.requested_clock_mode_index++;
 225                         }
 226                         break;
 227                 case DYNPM_ACTION_UPCLOCK:
 228                         if (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index) {
 229                                 if (rdev->pm.current_clock_mode_index ==
 230                                     (rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1)) {
 231                                         rdev->pm.requested_clock_mode_index = rdev->pm.current_clock_mode_index;
 232                                         rdev->pm.dynpm_can_upclock = false;
 233                                 } else
 234                                         rdev->pm.requested_clock_mode_index =
 235                                                 rdev->pm.current_clock_mode_index + 1;
 236                         } else {
 237                                 rdev->pm.requested_clock_mode_index =
 238                                         rdev->pm.power_state[rdev->pm.requested_power_state_index].num_clock_modes - 1;
 239                                 rdev->pm.dynpm_can_upclock = false;
 240                         }
 241                         break;
 242                 case DYNPM_ACTION_DEFAULT:
 243                         rdev->pm.requested_power_state_index = rdev->pm.default_power_state_index;
 244                         rdev->pm.requested_clock_mode_index = 0;
 245                         rdev->pm.dynpm_can_upclock = false;
 246                         break;
 247                 case DYNPM_ACTION_NONE:
 248                 default:
 249                         DRM_ERROR("Requested mode for not defined action\n");
 250                         return;
 251                 }
 252         }
 253
 254         DRM_DEBUG("Requested: e: %d m: %d p: %d\n",
 255                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 256                   clock_info[rdev->pm.requested_clock_mode_index].sclk,
 257                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 258                   clock_info[rdev->pm.requested_clock_mode_index].mclk,
 259                   rdev->pm.power_state[rdev->pm.requested_power_state_index].
 260                   pcie_lanes);
 261 }
 262
 263 static int r600_pm_get_type_index(struct radeon_device *rdev,
 264                                   enum radeon_pm_state_type ps_type,
 265                                   int instance)
 266 {
 267         int i;
 268         int found_instance = -1;
 269
 270         for (i = 0; i < rdev->pm.num_power_states; i++) {
 271                 if (rdev->pm.power_state[i].type == ps_type) {
 272                         found_instance++;
 273                         if (found_instance == instance)
 274                                 return i;
 275                 }
 276         }
 277         /* return default if no match */
 278         return rdev->pm.default_power_state_index;
 279 }
 280
 281 void rs780_pm_init_profile(struct radeon_device *rdev)
 282 {
 283         if (rdev->pm.num_power_states == 2) {
 284                 /* default */
 285                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 286                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 287                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 288                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 289                 /* low sh */
 290                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 0;
 291                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 0;
 292                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 293                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 294                 /* mid sh */
 295                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 0;
 296                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 0;
 297                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 298                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 299                 /* high sh */
 300                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 0;
 301                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 302                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 303                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 304                 /* low mh */
 305                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 0;
 306                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 307                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 308                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 309                 /* mid mh */
 310                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 0;
 311                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 312                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 313                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 314                 /* high mh */
 315                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 0;
 316                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 1;
 317                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 318                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 319         } else if (rdev->pm.num_power_states == 3) {
 320                 /* default */
 321                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 322                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 323                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 324                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 325                 /* low sh */
 326                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 327                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 328                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 329                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 330                 /* mid sh */
 331                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 332                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 333                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 334                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 335                 /* high sh */
 336                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 337                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 2;
 338                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 339                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 340                 /* low mh */
 341                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 1;
 342                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 1;
 343                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 344                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 345                 /* mid mh */
 346                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 1;
 347                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 1;
 348                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 349                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 350                 /* high mh */
 351                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 1;
 352                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 353                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 354                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 355         } else {
 356                 /* default */
 357                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 358                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 359                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 360                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 361                 /* low sh */
 362                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 2;
 363                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 2;
 364                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 365                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 366                 /* mid sh */
 367                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 2;
 368                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 2;
 369                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 370                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 371                 /* high sh */
 372                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 2;
 373                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 3;
 374                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 375                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 376                 /* low mh */
 377                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 378                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 0;
 379                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 380                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 381                 /* mid mh */
 382                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 383                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 0;
 384                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 385                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 386                 /* high mh */
 387                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 388                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 3;
 389                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 390                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 391         }
 392 }
 393
 394 void r600_pm_init_profile(struct radeon_device *rdev)
 395 {
 396         if (rdev->family == CHIP_R600) {
 397                 /* XXX */
 398                 /* default */
 399                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 400                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 401                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 402                 rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 0;
 403                 /* low sh */
 404                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 405                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 406                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 407                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 408                 /* mid sh */
 409                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 410                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 411                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 412                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 0;
 413                 /* high sh */
 414                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 415                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 416                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 417                 rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 0;
 418                 /* low mh */
 419                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 420                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 421                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 422                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 423                 /* mid mh */
 424                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 425                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 426                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 427                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 0;
 428                 /* high mh */
 429                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 430                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 431                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 432                 rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 0;
 433         } else {
 434                 if (rdev->pm.num_power_states < 4) {
 435                         /* default */
 436                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 437                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 438                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 439                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 440                         /* low sh */
 441                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx = 1;
 442                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx = 1;
 443                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 444                         rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 445                         /* mid sh */
 446                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx = 1;
 447                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx = 1;
 448                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 449                         rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 450                         /* high sh */
 451                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx = 1;
 452                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx = 1;
 453                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 454                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 455                         /* low mh */
 456                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx = 2;
 457                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx = 2;
 458                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 459                         rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 460                         /* low mh */
 461                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx = 2;
 462                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx = 2;
 463                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 464                         rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 465                         /* high mh */
 466                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx = 2;
 467                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx = 2;
 468                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 469                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 470                 } else {
 471                         /* default */
 472                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_ps_idx = rdev->pm.default_power_state_index;
 473                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_ps_idx = rdev->pm.default_power_state_index;
 474                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_off_cm_idx = 0;
 475                         rdev->pm.profiles[PM_PROFILE_DEFAULT_IDX].dpms_on_cm_idx = 2;
 476                         /* low sh */
 477                         if (rdev->flags & RADEON_IS_MOBILITY) {
 478                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 479                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 480                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 481                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 482                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 483                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 484                         } else {
 485                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_ps_idx =
 486                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 487                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_ps_idx =
 488                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 489                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_off_cm_idx = 0;
 490                                 rdev->pm.profiles[PM_PROFILE_LOW_SH_IDX].dpms_on_cm_idx = 0;
 491                         }
 492                         /* mid sh */
 493                         if (rdev->flags & RADEON_IS_MOBILITY) {
 494                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 495                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 496                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 497                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 0);
 498                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 499                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 500                         } else {
 501                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_ps_idx =
 502                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 503                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_ps_idx =
 504                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 505                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_off_cm_idx = 0;
 506                                 rdev->pm.profiles[PM_PROFILE_MID_SH_IDX].dpms_on_cm_idx = 1;
 507                         }
 508                         /* high sh */
 509                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_ps_idx =
 510                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 511                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_ps_idx =
 512                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 0);
 513                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_off_cm_idx = 0;
 514                         rdev->pm.profiles[PM_PROFILE_HIGH_SH_IDX].dpms_on_cm_idx = 2;
 515                         /* low mh */
 516                         if (rdev->flags & RADEON_IS_MOBILITY) {
 517                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 518                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 519                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 520                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 521                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 522                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 523                         } else {
 524                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_ps_idx =
 525                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 526                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_ps_idx =
 527                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 528                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_off_cm_idx = 0;
 529                                 rdev->pm.profiles[PM_PROFILE_LOW_MH_IDX].dpms_on_cm_idx = 0;
 530                         }
 531                         /* mid mh */
 532                         if (rdev->flags & RADEON_IS_MOBILITY) {
 533                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 534                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 535                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 536                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_BATTERY, 1);
 537                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 538                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 539                         } else {
 540                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_ps_idx =
 541                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 542                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_ps_idx =
 543                                         r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 544                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_off_cm_idx = 0;
 545                                 rdev->pm.profiles[PM_PROFILE_MID_MH_IDX].dpms_on_cm_idx = 1;
 546                         }
 547                         /* high mh */
 548                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_ps_idx =
 549                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 550                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_ps_idx =
 551                                 r600_pm_get_type_index(rdev, POWER_STATE_TYPE_PERFORMANCE, 1);
 552                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_off_cm_idx = 0;
 553                         rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx = 2;
 554                 }
 555         }
 556 }
 557
 558 void r600_pm_misc(struct radeon_device *rdev)
 559 {
 560         int req_ps_idx = rdev->pm.requested_power_state_index;
 561         int req_cm_idx = rdev->pm.requested_clock_mode_index;
 562         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
 563         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
 564
 565         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
 566                 if (voltage->voltage != rdev->pm.current_vddc) {
 567                         radeon_atom_set_voltage(rdev, voltage->voltage);
 568                         rdev->pm.current_vddc = voltage->voltage;
 569                 }
 570         }
 571 }
 572
 573 bool r600_gui_idle(struct radeon_device *rdev)
 574 {
 575         if (RREG32(GRBM_STATUS) & GUI_ACTIVE)
 576                 return false;
 577         else
 578                 return true;
 579 }
 580
 581 /* hpd for digital panel detect/disconnect */
 582 bool r600_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
 583 {
 584         bool connected = false;
 585
 586         if (ASIC_IS_DCE3(rdev)) {
 587                 switch (hpd) {
 588                 case RADEON_HPD_1:
 589                         if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 590                                 connected = true;
 591                         break;
 592                 case RADEON_HPD_2:
 593                         if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 594                                 connected = true;
 595                         break;
 596                 case RADEON_HPD_3:
 597                         if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 598                                 connected = true;
 599                         break;
 600                 case RADEON_HPD_4:
 601                         if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 602                                 connected = true;
 603                         break;
 604                         /* DCE 3.2 */
 605                 case RADEON_HPD_5:
 606                         if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 607                                 connected = true;
 608                         break;
 609                 case RADEON_HPD_6:
 610                         if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 611                                 connected = true;
 612                         break;
 613                 default:
 614                         break;
 615                 }
 616         } else {
 617                 switch (hpd) {
 618                 case RADEON_HPD_1:
 619                         if (RREG32(DC_HOT_PLUG_DETECT1_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 620                                 connected = true;
 621                         break;
 622                 case RADEON_HPD_2:
 623                         if (RREG32(DC_HOT_PLUG_DETECT2_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 624                                 connected = true;
 625                         break;
 626                 case RADEON_HPD_3:
 627                         if (RREG32(DC_HOT_PLUG_DETECT3_INT_STATUS) & DC_HOT_PLUG_DETECTx_SENSE)
 628                                 connected = true;
 629                         break;
 630                 default:
 631                         break;
 632                 }
 633         }
 634         return connected;
 635 }
 636
 637 void r600_hpd_set_polarity(struct radeon_device *rdev,
 638                            enum radeon_hpd_id hpd)
 639 {
 640         u32 tmp;
 641         bool connected = r600_hpd_sense(rdev, hpd);
 642
 643         if (ASIC_IS_DCE3(rdev)) {
 644                 switch (hpd) {
 645                 case RADEON_HPD_1:
 646                         tmp = RREG32(DC_HPD1_INT_CONTROL);
 647                         if (connected)
 648                                 tmp &= ~DC_HPDx_INT_POLARITY;
 649                         else
 650                                 tmp |= DC_HPDx_INT_POLARITY;
 651                         WREG32(DC_HPD1_INT_CONTROL, tmp);
 652                         break;
 653                 case RADEON_HPD_2:
 654                         tmp = RREG32(DC_HPD2_INT_CONTROL);
 655                         if (connected)
 656                                 tmp &= ~DC_HPDx_INT_POLARITY;
 657                         else
 658                                 tmp |= DC_HPDx_INT_POLARITY;
 659                         WREG32(DC_HPD2_INT_CONTROL, tmp);
 660                         break;
 661                 case RADEON_HPD_3:
 662                         tmp = RREG32(DC_HPD3_INT_CONTROL);
 663                         if (connected)
 664                                 tmp &= ~DC_HPDx_INT_POLARITY;
 665                         else
 666                                 tmp |= DC_HPDx_INT_POLARITY;
 667                         WREG32(DC_HPD3_INT_CONTROL, tmp);
 668                         break;
 669                 case RADEON_HPD_4:
 670                         tmp = RREG32(DC_HPD4_INT_CONTROL);
 671                         if (connected)
 672                                 tmp &= ~DC_HPDx_INT_POLARITY;
 673                         else
 674                                 tmp |= DC_HPDx_INT_POLARITY;
 675                         WREG32(DC_HPD4_INT_CONTROL, tmp);
 676                         break;
 677                 case RADEON_HPD_5:
 678                         tmp = RREG32(DC_HPD5_INT_CONTROL);
 679                         if (connected)
 680                                 tmp &= ~DC_HPDx_INT_POLARITY;
 681                         else
 682                                 tmp |= DC_HPDx_INT_POLARITY;
 683                         WREG32(DC_HPD5_INT_CONTROL, tmp);
 684                         break;
 685                         /* DCE 3.2 */
 686                 case RADEON_HPD_6:
 687                         tmp = RREG32(DC_HPD6_INT_CONTROL);
 688                         if (connected)
 689                                 tmp &= ~DC_HPDx_INT_POLARITY;
 690                         else
 691                                 tmp |= DC_HPDx_INT_POLARITY;
 692                         WREG32(DC_HPD6_INT_CONTROL, tmp);
 693                         break;
 694                 default:
 695                         break;
 696                 }
 697         } else {
 698                 switch (hpd) {
 699                 case RADEON_HPD_1:
 700                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
 701                         if (connected)
 702                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 703                         else
 704                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 705                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
 706                         break;
 707                 case RADEON_HPD_2:
 708                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
 709                         if (connected)
 710                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 711                         else
 712                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 713                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
 714                         break;
 715                 case RADEON_HPD_3:
 716                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
 717                         if (connected)
 718                                 tmp &= ~DC_HOT_PLUG_DETECTx_INT_POLARITY;
 719                         else
 720                                 tmp |= DC_HOT_PLUG_DETECTx_INT_POLARITY;
 721                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
 722                         break;
 723                 default:
 724                         break;
 725                 }
 726         }
 727 }
 728
 729 void r600_hpd_init(struct radeon_device *rdev)
 730 {
 731         struct drm_device *dev = rdev->ddev;
 732         struct drm_connector *connector;
 733
 734         if (ASIC_IS_DCE3(rdev)) {
 735                 u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) | DC_HPDx_RX_INT_TIMER(0xfa);
 736                 if (ASIC_IS_DCE32(rdev))
 737                         tmp |= DC_HPDx_EN;
 738
 739                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 740                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 741                         switch (radeon_connector->hpd.hpd) {
 742                         case RADEON_HPD_1:
 743                                 WREG32(DC_HPD1_CONTROL, tmp);
 744                                 rdev->irq.hpd[0] = true;
 745                                 break;
 746                         case RADEON_HPD_2:
 747                                 WREG32(DC_HPD2_CONTROL, tmp);
 748                                 rdev->irq.hpd[1] = true;
 749                                 break;
 750                         case RADEON_HPD_3:
 751                                 WREG32(DC_HPD3_CONTROL, tmp);
 752                                 rdev->irq.hpd[2] = true;
 753                                 break;
 754                         case RADEON_HPD_4:
 755                                 WREG32(DC_HPD4_CONTROL, tmp);
 756                                 rdev->irq.hpd[3] = true;
 757                                 break;
 758                                 /* DCE 3.2 */
 759                         case RADEON_HPD_5:
 760                                 WREG32(DC_HPD5_CONTROL, tmp);
 761                                 rdev->irq.hpd[4] = true;
 762                                 break;
 763                         case RADEON_HPD_6:
 764                                 WREG32(DC_HPD6_CONTROL, tmp);
 765                                 rdev->irq.hpd[5] = true;
 766                                 break;
 767                         default:
 768                                 break;
 769                         }
 770                 }
 771         } else {
 772                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 773                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 774                         switch (radeon_connector->hpd.hpd) {
 775                         case RADEON_HPD_1:
 776                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 777                                 rdev->irq.hpd[0] = true;
 778                                 break;
 779                         case RADEON_HPD_2:
 780                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 781                                 rdev->irq.hpd[1] = true;
 782                                 break;
 783                         case RADEON_HPD_3:
 784                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, DC_HOT_PLUG_DETECTx_EN);
 785                                 rdev->irq.hpd[2] = true;
 786                                 break;
 787                         default:
 788                                 break;
 789                         }
 790                 }
 791         }
 792         if (rdev->irq.installed)
 793                 r600_irq_set(rdev);
 794 }
 795
 796 void r600_hpd_fini(struct radeon_device *rdev)
 797 {
 798         struct drm_device *dev = rdev->ddev;
 799         struct drm_connector *connector;
 800
 801         if (ASIC_IS_DCE3(rdev)) {
 802                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 803                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 804                         switch (radeon_connector->hpd.hpd) {
 805                         case RADEON_HPD_1:
 806                                 WREG32(DC_HPD1_CONTROL, 0);
 807                                 rdev->irq.hpd[0] = false;
 808                                 break;
 809                         case RADEON_HPD_2:
 810                                 WREG32(DC_HPD2_CONTROL, 0);
 811                                 rdev->irq.hpd[1] = false;
 812                                 break;
 813                         case RADEON_HPD_3:
 814                                 WREG32(DC_HPD3_CONTROL, 0);
 815                                 rdev->irq.hpd[2] = false;
 816                                 break;
 817                         case RADEON_HPD_4:
 818                                 WREG32(DC_HPD4_CONTROL, 0);
 819                                 rdev->irq.hpd[3] = false;
 820                                 break;
 821                                 /* DCE 3.2 */
 822                         case RADEON_HPD_5:
 823                                 WREG32(DC_HPD5_CONTROL, 0);
 824                                 rdev->irq.hpd[4] = false;
 825                                 break;
 826                         case RADEON_HPD_6:
 827                                 WREG32(DC_HPD6_CONTROL, 0);
 828                                 rdev->irq.hpd[5] = false;
 829                                 break;
 830                         default:
 831                                 break;
 832                         }
 833                 }
 834         } else {
 835                 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 836                         struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 837                         switch (radeon_connector->hpd.hpd) {
 838                         case RADEON_HPD_1:
 839                                 WREG32(DC_HOT_PLUG_DETECT1_CONTROL, 0);
 840                                 rdev->irq.hpd[0] = false;
 841                                 break;
 842                         case RADEON_HPD_2:
 843                                 WREG32(DC_HOT_PLUG_DETECT2_CONTROL, 0);
 844                                 rdev->irq.hpd[1] = false;
 845                                 break;
 846                         case RADEON_HPD_3:
 847                                 WREG32(DC_HOT_PLUG_DETECT3_CONTROL, 0);
 848                                 rdev->irq.hpd[2] = false;
 849                                 break;
 850                         default:
 851                                 break;
 852                         }
 853                 }
 854         }
 855 }
 856
 857 /*
 858  * R600 PCIE GART
 859  */
 860 void r600_pcie_gart_tlb_flush(struct radeon_device *rdev)
 861 {
 862         unsigned i;
 863         u32 tmp;
 864
 865         /* flush hdp cache so updates hit vram */
 866         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
 867
 868         WREG32(VM_CONTEXT0_INVALIDATION_LOW_ADDR, rdev->mc.gtt_start >> 12);
 869         WREG32(VM_CONTEXT0_INVALIDATION_HIGH_ADDR, (rdev->mc.gtt_end - 1) >> 12);
 870         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 871         for (i = 0; i < rdev->usec_timeout; i++) {
 872                 /* read MC_STATUS */
 873                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 874                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 875                 if (tmp == 2) {
 876                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 877                         return;
 878                 }
 879                 if (tmp) {
 880                         return;
 881                 }
 882                 udelay(1);
 883         }
 884 }
 885
 886 int r600_pcie_gart_init(struct radeon_device *rdev)
 887 {
 888         int r;
 889
 890         if (rdev->gart.table.vram.robj) {
 891                 WARN(1, "R600 PCIE GART already initialized.\n");
 892                 return 0;
 893         }
 894         /* Initialize common gart structure */
 895         r = radeon_gart_init(rdev);
 896         if (r)
 897                 return r;
 898         rdev->gart.table_size = rdev->gart.num_gpu_pages * 8;
 899         return radeon_gart_table_vram_alloc(rdev);
 900 }
 901
 902 int r600_pcie_gart_enable(struct radeon_device *rdev)
 903 {
 904         u32 tmp;
 905         int r, i;
 906
 907         if (rdev->gart.table.vram.robj == NULL) {
 908                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 909                 return -EINVAL;
 910         }
 911         r = radeon_gart_table_vram_pin(rdev);
 912         if (r)
 913                 return r;
 914         radeon_gart_restore(rdev);
 915
 916         /* Setup L2 cache */
 917         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 918                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 919                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 920         WREG32(VM_L2_CNTL2, 0);
 921         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 922         /* Setup TLB control */
 923         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 924                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 925                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 926                 ENABLE_WAIT_L2_QUERY;
 927         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 928         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 929         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
 930         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 931         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 932         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 933         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 934         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 935         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 936         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 937         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 938         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 939         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 940         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
 941         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 942         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 943         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 944         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 945                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 946         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 947                         (u32)(rdev->dummy_page.addr >> 12));
 948         for (i = 1; i < 7; i++)
 949                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 950
 951         r600_pcie_gart_tlb_flush(rdev);
 952         rdev->gart.ready = true;
 953         return 0;
 954 }
 955
 956 void r600_pcie_gart_disable(struct radeon_device *rdev)
 957 {
 958         u32 tmp;
 959         int i, r;
 960
 961         /* Disable all tables */
 962         for (i = 0; i < 7; i++)
 963                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
 964
 965         /* Disable L2 cache */
 966         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 967                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 968         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
 969         /* Setup L1 TLB control */
 970         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
 971                 ENABLE_WAIT_L2_QUERY;
 972         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
 973         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
 974         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
 975         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
 976         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
 977         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
 978         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
 979         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
 980         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp);
 981         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp);
 982         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
 983         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
 984         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp);
 985         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
 986         if (rdev->gart.table.vram.robj) {
 987                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 988                 if (likely(r == 0)) {
 989                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 990                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 991                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 992                 }
 993         }
 994 }
 995
 996 void r600_pcie_gart_fini(struct radeon_device *rdev)
 997 {
 998         radeon_gart_fini(rdev);
 999         r600_pcie_gart_disable(rdev);
1000         radeon_gart_table_vram_free(rdev);
1001 }
1002
1003 void r600_agp_enable(struct radeon_device *rdev)
1004 {
1005         u32 tmp;
1006         int i;
1007
1008         /* Setup L2 cache */
1009         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
1010                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
1011                                 EFFECTIVE_L2_QUEUE_SIZE(7));
1012         WREG32(VM_L2_CNTL2, 0);
1013         WREG32(VM_L2_CNTL3, BANK_SELECT_0(0) | BANK_SELECT_1(1));
1014         /* Setup TLB control */
1015         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
1016                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
1017                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5) |
1018                 ENABLE_WAIT_L2_QUERY;
1019         WREG32(MC_VM_L1_TLB_MCB_RD_SYS_CNTL, tmp);
1020         WREG32(MC_VM_L1_TLB_MCB_WR_SYS_CNTL, tmp);
1021         WREG32(MC_VM_L1_TLB_MCB_RD_HDP_CNTL, tmp | ENABLE_L1_STRICT_ORDERING);
1022         WREG32(MC_VM_L1_TLB_MCB_WR_HDP_CNTL, tmp);
1023         WREG32(MC_VM_L1_TLB_MCD_RD_A_CNTL, tmp);
1024         WREG32(MC_VM_L1_TLB_MCD_WR_A_CNTL, tmp);
1025         WREG32(MC_VM_L1_TLB_MCD_RD_B_CNTL, tmp);
1026         WREG32(MC_VM_L1_TLB_MCD_WR_B_CNTL, tmp);
1027         WREG32(MC_VM_L1_TLB_MCB_RD_GFX_CNTL, tmp);
1028         WREG32(MC_VM_L1_TLB_MCB_WR_GFX_CNTL, tmp);
1029         WREG32(MC_VM_L1_TLB_MCB_RD_PDMA_CNTL, tmp);
1030         WREG32(MC_VM_L1_TLB_MCB_WR_PDMA_CNTL, tmp);
1031         WREG32(MC_VM_L1_TLB_MCB_RD_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1032         WREG32(MC_VM_L1_TLB_MCB_WR_SEM_CNTL, tmp | ENABLE_SEMAPHORE_MODE);
1033         for (i = 0; i < 7; i++)
1034                 WREG32(VM_CONTEXT0_CNTL + (i * 4), 0);
1035 }
1036
1037 int r600_mc_wait_for_idle(struct radeon_device *rdev)
1038 {
1039         unsigned i;
1040         u32 tmp;
1041
1042         for (i = 0; i < rdev->usec_timeout; i++) {
1043                 /* read MC_STATUS */
1044                 tmp = RREG32(R_000E50_SRBM_STATUS) & 0x3F00;
1045                 if (!tmp)
1046                         return 0;
1047                 udelay(1);
1048         }
1049         return -1;
1050 }
1051
1052 static void r600_mc_program(struct radeon_device *rdev)
1053 {
1054         struct rv515_mc_save save;
1055         u32 tmp;
1056         int i, j;
1057
1058         /* Initialize HDP */
1059         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1060                 WREG32((0x2c14 + j), 0x00000000);
1061                 WREG32((0x2c18 + j), 0x00000000);
1062                 WREG32((0x2c1c + j), 0x00000000);
1063                 WREG32((0x2c20 + j), 0x00000000);
1064                 WREG32((0x2c24 + j), 0x00000000);
1065         }
1066         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
1067
1068         rv515_mc_stop(rdev, &save);
1069         if (r600_mc_wait_for_idle(rdev)) {
1070                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1071         }
1072         /* Lockout access through VGA aperture (doesn't exist before R600) */
1073         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
1074         /* Update configuration */
1075         if (rdev->flags & RADEON_IS_AGP) {
1076                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
1077                         /* VRAM before AGP */
1078                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1079                                 rdev->mc.vram_start >> 12);
1080                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1081                                 rdev->mc.gtt_end >> 12);
1082                 } else {
1083                         /* VRAM after AGP */
1084                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
1085                                 rdev->mc.gtt_start >> 12);
1086                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
1087                                 rdev->mc.vram_end >> 12);
1088                 }
1089         } else {
1090                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, rdev->mc.vram_start >> 12);
1091                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, rdev->mc.vram_end >> 12);
1092         }
1093         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
1094         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
1095         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
1096         WREG32(MC_VM_FB_LOCATION, tmp);
1097         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
1098         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
1099         WREG32(HDP_NONSURFACE_SIZE, rdev->mc.mc_vram_size | 0x3FF);
1100         if (rdev->flags & RADEON_IS_AGP) {
1101                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 22);
1102                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 22);
1103                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
1104         } else {
1105                 WREG32(MC_VM_AGP_BASE, 0);
1106                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
1107                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
1108         }
1109         if (r600_mc_wait_for_idle(rdev)) {
1110                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1111         }
1112         rv515_mc_resume(rdev, &save);
1113         /* we need to own VRAM, so turn off the VGA renderer here
1114          * to stop it overwriting our objects */
1115         rv515_vga_render_disable(rdev);
1116 }
1117
1118 /**
1119  * r600_vram_gtt_location - try to find VRAM & GTT location
1120  * @rdev: radeon device structure holding all necessary informations
1121  * @mc: memory controller structure holding memory informations
1122  *
1123  * Function will place try to place VRAM at same place as in CPU (PCI)
1124  * address space as some GPU seems to have issue when we reprogram at
1125  * different address space.
1126  *
1127  * If there is not enough space to fit the unvisible VRAM after the
1128  * aperture then we limit the VRAM size to the aperture.
1129  *
1130  * If we are using AGP then place VRAM adjacent to AGP aperture are we need
1131  * them to be in one from GPU point of view so that we can program GPU to
1132  * catch access outside them (weird GPU policy see ??).
1133  *
1134  * This function will never fails, worst case are limiting VRAM or GTT.
1135  *
1136  * Note: GTT start, end, size should be initialized before calling this
1137  * function on AGP platform.
1138  */
1139 void r600_vram_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
1140 {
1141         u64 size_bf, size_af;
1142
1143         if (mc->mc_vram_size > 0xE0000000) {
1144                 /* leave room for at least 512M GTT */
1145                 dev_warn(rdev->dev, "limiting VRAM\n");
1146                 mc->real_vram_size = 0xE0000000;
1147                 mc->mc_vram_size = 0xE0000000;
1148         }
1149         if (rdev->flags & RADEON_IS_AGP) {
1150                 size_bf = mc->gtt_start;
1151                 size_af = 0xFFFFFFFF - mc->gtt_end + 1;
1152                 if (size_bf > size_af) {
1153                         if (mc->mc_vram_size > size_bf) {
1154                                 dev_warn(rdev->dev, "limiting VRAM\n");
1155                                 mc->real_vram_size = size_bf;
1156                                 mc->mc_vram_size = size_bf;
1157                         }
1158                         mc->vram_start = mc->gtt_start - mc->mc_vram_size;
1159                 } else {
1160                         if (mc->mc_vram_size > size_af) {
1161                                 dev_warn(rdev->dev, "limiting VRAM\n");
1162                                 mc->real_vram_size = size_af;
1163                                 mc->mc_vram_size = size_af;
1164                         }
1165                         mc->vram_start = mc->gtt_end;
1166                 }
1167                 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
1168                 dev_info(rdev->dev, "VRAM: %lluM 0x%08llX - 0x%08llX (%lluM used)\n",
1169                                 mc->mc_vram_size >> 20, mc->vram_start,
1170                                 mc->vram_end, mc->real_vram_size >> 20);
1171         } else {
1172                 u64 base = 0;
1173                 if (rdev->flags & RADEON_IS_IGP)
1174                         base = (RREG32(MC_VM_FB_LOCATION) & 0xFFFF) << 24;
1175                 radeon_vram_location(rdev, &rdev->mc, base);
1176                 radeon_gtt_location(rdev, mc);
1177         }
1178 }
1179
1180 int r600_mc_init(struct radeon_device *rdev)
1181 {
1182         u32 tmp;
1183         int chansize, numchan;
1184
1185         /* Get VRAM informations */
1186         rdev->mc.vram_is_ddr = true;
1187         tmp = RREG32(RAMCFG);
1188         if (tmp & CHANSIZE_OVERRIDE) {
1189                 chansize = 16;
1190         } else if (tmp & CHANSIZE_MASK) {
1191                 chansize = 64;
1192         } else {
1193                 chansize = 32;
1194         }
1195         tmp = RREG32(CHMAP);
1196         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1197         case 0:
1198         default:
1199                 numchan = 1;
1200                 break;
1201         case 1:
1202                 numchan = 2;
1203                 break;
1204         case 2:
1205                 numchan = 4;
1206                 break;
1207         case 3:
1208                 numchan = 8;
1209                 break;
1210         }
1211         rdev->mc.vram_width = numchan * chansize;
1212         /* Could aper size report 0 ? */
1213         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1214         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1215         /* Setup GPU memory space */
1216         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE);
1217         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE);
1218         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1219         r600_vram_gtt_location(rdev, &rdev->mc);
1220
1221         if (rdev->flags & RADEON_IS_IGP)
1222                 rdev->mc.igp_sideport_enabled = radeon_atombios_sideport_present(rdev);
1223         radeon_update_bandwidth_info(rdev);
1224         return 0;
1225 }
1226
1227 /* We doesn't check that the GPU really needs a reset we simply do the
1228  * reset, it's up to the caller to determine if the GPU needs one. We
1229  * might add an helper function to check that.
1230  */
1231 int r600_gpu_soft_reset(struct radeon_device *rdev)
1232 {
1233         struct rv515_mc_save save;
1234         u32 grbm_busy_mask = S_008010_VC_BUSY(1) | S_008010_VGT_BUSY_NO_DMA(1) |
1235                                 S_008010_VGT_BUSY(1) | S_008010_TA03_BUSY(1) |
1236                                 S_008010_TC_BUSY(1) | S_008010_SX_BUSY(1) |
1237                                 S_008010_SH_BUSY(1) | S_008010_SPI03_BUSY(1) |
1238                                 S_008010_SMX_BUSY(1) | S_008010_SC_BUSY(1) |
1239                                 S_008010_PA_BUSY(1) | S_008010_DB03_BUSY(1) |
1240                                 S_008010_CR_BUSY(1) | S_008010_CB03_BUSY(1) |
1241                                 S_008010_GUI_ACTIVE(1);
1242         u32 grbm2_busy_mask = S_008014_SPI0_BUSY(1) | S_008014_SPI1_BUSY(1) |
1243                         S_008014_SPI2_BUSY(1) | S_008014_SPI3_BUSY(1) |
1244                         S_008014_TA0_BUSY(1) | S_008014_TA1_BUSY(1) |
1245                         S_008014_TA2_BUSY(1) | S_008014_TA3_BUSY(1) |
1246                         S_008014_DB0_BUSY(1) | S_008014_DB1_BUSY(1) |
1247                         S_008014_DB2_BUSY(1) | S_008014_DB3_BUSY(1) |
1248                         S_008014_CB0_BUSY(1) | S_008014_CB1_BUSY(1) |
1249                         S_008014_CB2_BUSY(1) | S_008014_CB3_BUSY(1);
1250         u32 tmp;
1251
1252         dev_info(rdev->dev, "GPU softreset \n");
1253         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1254                 RREG32(R_008010_GRBM_STATUS));
1255         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1256                 RREG32(R_008014_GRBM_STATUS2));
1257         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1258                 RREG32(R_000E50_SRBM_STATUS));
1259         rv515_mc_stop(rdev, &save);
1260         if (r600_mc_wait_for_idle(rdev)) {
1261                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1262         }
1263         /* Disable CP parsing/prefetching */
1264         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1265         /* Check if any of the rendering block is busy and reset it */
1266         if ((RREG32(R_008010_GRBM_STATUS) & grbm_busy_mask) ||
1267             (RREG32(R_008014_GRBM_STATUS2) & grbm2_busy_mask)) {
1268                 tmp = S_008020_SOFT_RESET_CR(1) |
1269                         S_008020_SOFT_RESET_DB(1) |
1270                         S_008020_SOFT_RESET_CB(1) |
1271                         S_008020_SOFT_RESET_PA(1) |
1272                         S_008020_SOFT_RESET_SC(1) |
1273                         S_008020_SOFT_RESET_SMX(1) |
1274                         S_008020_SOFT_RESET_SPI(1) |
1275                         S_008020_SOFT_RESET_SX(1) |
1276                         S_008020_SOFT_RESET_SH(1) |
1277                         S_008020_SOFT_RESET_TC(1) |
1278                         S_008020_SOFT_RESET_TA(1) |
1279                         S_008020_SOFT_RESET_VC(1) |
1280                         S_008020_SOFT_RESET_VGT(1);
1281                 dev_info(rdev->dev, "  R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1282                 WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1283                 RREG32(R_008020_GRBM_SOFT_RESET);
1284                 mdelay(15);
1285                 WREG32(R_008020_GRBM_SOFT_RESET, 0);
1286         }
1287         /* Reset CP (we always reset CP) */
1288         tmp = S_008020_SOFT_RESET_CP(1);
1289         dev_info(rdev->dev, "R_008020_GRBM_SOFT_RESET=0x%08X\n", tmp);
1290         WREG32(R_008020_GRBM_SOFT_RESET, tmp);
1291         RREG32(R_008020_GRBM_SOFT_RESET);
1292         mdelay(15);
1293         WREG32(R_008020_GRBM_SOFT_RESET, 0);
1294         /* Wait a little for things to settle down */
1295         mdelay(1);
1296         dev_info(rdev->dev, "  R_008010_GRBM_STATUS=0x%08X\n",
1297                 RREG32(R_008010_GRBM_STATUS));
1298         dev_info(rdev->dev, "  R_008014_GRBM_STATUS2=0x%08X\n",
1299                 RREG32(R_008014_GRBM_STATUS2));
1300         dev_info(rdev->dev, "  R_000E50_SRBM_STATUS=0x%08X\n",
1301                 RREG32(R_000E50_SRBM_STATUS));
1302         rv515_mc_resume(rdev, &save);
1303         return 0;
1304 }
1305
1306 bool r600_gpu_is_lockup(struct radeon_device *rdev)
1307 {
1308         u32 srbm_status;
1309         u32 grbm_status;
1310         u32 grbm_status2;
1311         int r;
1312
1313         srbm_status = RREG32(R_000E50_SRBM_STATUS);
1314         grbm_status = RREG32(R_008010_GRBM_STATUS);
1315         grbm_status2 = RREG32(R_008014_GRBM_STATUS2);
1316         if (!G_008010_GUI_ACTIVE(grbm_status)) {
1317                 r100_gpu_lockup_update(&rdev->config.r300.lockup, &rdev->cp);
1318                 return false;
1319         }
1320         /* force CP activities */
1321         r = radeon_ring_lock(rdev, 2);
1322         if (!r) {
1323                 /* PACKET2 NOP */
1324                 radeon_ring_write(rdev, 0x80000000);
1325                 radeon_ring_write(rdev, 0x80000000);
1326                 radeon_ring_unlock_commit(rdev);
1327         }
1328         rdev->cp.rptr = RREG32(R600_CP_RB_RPTR);
1329         return r100_gpu_cp_is_lockup(rdev, &rdev->config.r300.lockup, &rdev->cp);
1330 }
1331
1332 int r600_asic_reset(struct radeon_device *rdev)
1333 {
1334         return r600_gpu_soft_reset(rdev);
1335 }
1336
1337 static u32 r600_get_tile_pipe_to_backend_map(u32 num_tile_pipes,
1338                                              u32 num_backends,
1339                                              u32 backend_disable_mask)
1340 {
1341         u32 backend_map = 0;
1342         u32 enabled_backends_mask;
1343         u32 enabled_backends_count;
1344         u32 cur_pipe;
1345         u32 swizzle_pipe[R6XX_MAX_PIPES];
1346         u32 cur_backend;
1347         u32 i;
1348
1349         if (num_tile_pipes > R6XX_MAX_PIPES)
1350                 num_tile_pipes = R6XX_MAX_PIPES;
1351         if (num_tile_pipes < 1)
1352                 num_tile_pipes = 1;
1353         if (num_backends > R6XX_MAX_BACKENDS)
1354                 num_backends = R6XX_MAX_BACKENDS;
1355         if (num_backends < 1)
1356                 num_backends = 1;
1357
1358         enabled_backends_mask = 0;
1359         enabled_backends_count = 0;
1360         for (i = 0; i < R6XX_MAX_BACKENDS; ++i) {
1361                 if (((backend_disable_mask >> i) & 1) == 0) {
1362                         enabled_backends_mask |= (1 << i);
1363                         ++enabled_backends_count;
1364                 }
1365                 if (enabled_backends_count == num_backends)
1366                         break;
1367         }
1368
1369         if (enabled_backends_count == 0) {
1370                 enabled_backends_mask = 1;
1371                 enabled_backends_count = 1;
1372         }
1373
1374         if (enabled_backends_count != num_backends)
1375                 num_backends = enabled_backends_count;
1376
1377         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R6XX_MAX_PIPES);
1378         switch (num_tile_pipes) {
1379         case 1:
1380                 swizzle_pipe[0] = 0;
1381                 break;
1382         case 2:
1383                 swizzle_pipe[0] = 0;
1384                 swizzle_pipe[1] = 1;
1385                 break;
1386         case 3:
1387                 swizzle_pipe[0] = 0;
1388                 swizzle_pipe[1] = 1;
1389                 swizzle_pipe[2] = 2;
1390                 break;
1391         case 4:
1392                 swizzle_pipe[0] = 0;
1393                 swizzle_pipe[1] = 1;
1394                 swizzle_pipe[2] = 2;
1395                 swizzle_pipe[3] = 3;
1396                 break;
1397         case 5:
1398                 swizzle_pipe[0] = 0;
1399                 swizzle_pipe[1] = 1;
1400                 swizzle_pipe[2] = 2;
1401                 swizzle_pipe[3] = 3;
1402                 swizzle_pipe[4] = 4;
1403                 break;
1404         case 6:
1405                 swizzle_pipe[0] = 0;
1406                 swizzle_pipe[1] = 2;
1407                 swizzle_pipe[2] = 4;
1408                 swizzle_pipe[3] = 5;
1409                 swizzle_pipe[4] = 1;
1410                 swizzle_pipe[5] = 3;
1411                 break;
1412         case 7:
1413                 swizzle_pipe[0] = 0;
1414                 swizzle_pipe[1] = 2;
1415                 swizzle_pipe[2] = 4;
1416                 swizzle_pipe[3] = 6;
1417                 swizzle_pipe[4] = 1;
1418                 swizzle_pipe[5] = 3;
1419                 swizzle_pipe[6] = 5;
1420                 break;
1421         case 8:
1422                 swizzle_pipe[0] = 0;
1423                 swizzle_pipe[1] = 2;
1424                 swizzle_pipe[2] = 4;
1425                 swizzle_pipe[3] = 6;
1426                 swizzle_pipe[4] = 1;
1427                 swizzle_pipe[5] = 3;
1428                 swizzle_pipe[6] = 5;
1429                 swizzle_pipe[7] = 7;
1430                 break;
1431         }
1432
1433         cur_backend = 0;
1434         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
1435                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
1436                         cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1437
1438                 backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2)));
1439
1440                 cur_backend = (cur_backend + 1) % R6XX_MAX_BACKENDS;
1441         }
1442
1443         return backend_map;
1444 }
1445
1446 int r600_count_pipe_bits(uint32_t val)
1447 {
1448         int i, ret = 0;
1449
1450         for (i = 0; i < 32; i++) {
1451                 ret += val & 1;
1452                 val >>= 1;
1453         }
1454         return ret;
1455 }
1456
1457 void r600_gpu_init(struct radeon_device *rdev)
1458 {
1459         u32 tiling_config;
1460         u32 ramcfg;
1461         u32 backend_map;
1462         u32 cc_rb_backend_disable;
1463         u32 cc_gc_shader_pipe_config;
1464         u32 tmp;
1465         int i, j;
1466         u32 sq_config;
1467         u32 sq_gpr_resource_mgmt_1 = 0;
1468         u32 sq_gpr_resource_mgmt_2 = 0;
1469         u32 sq_thread_resource_mgmt = 0;
1470         u32 sq_stack_resource_mgmt_1 = 0;
1471         u32 sq_stack_resource_mgmt_2 = 0;
1472
1473         /* FIXME: implement */
1474         switch (rdev->family) {
1475         case CHIP_R600:
1476                 rdev->config.r600.max_pipes = 4;
1477                 rdev->config.r600.max_tile_pipes = 8;
1478                 rdev->config.r600.max_simds = 4;
1479                 rdev->config.r600.max_backends = 4;
1480                 rdev->config.r600.max_gprs = 256;
1481                 rdev->config.r600.max_threads = 192;
1482                 rdev->config.r600.max_stack_entries = 256;
1483                 rdev->config.r600.max_hw_contexts = 8;
1484                 rdev->config.r600.max_gs_threads = 16;
1485                 rdev->config.r600.sx_max_export_size = 128;
1486                 rdev->config.r600.sx_max_export_pos_size = 16;
1487                 rdev->config.r600.sx_max_export_smx_size = 128;
1488                 rdev->config.r600.sq_num_cf_insts = 2;
1489                 break;
1490         case CHIP_RV630:
1491         case CHIP_RV635:
1492                 rdev->config.r600.max_pipes = 2;
1493                 rdev->config.r600.max_tile_pipes = 2;
1494                 rdev->config.r600.max_simds = 3;
1495                 rdev->config.r600.max_backends = 1;
1496                 rdev->config.r600.max_gprs = 128;
1497                 rdev->config.r600.max_threads = 192;
1498                 rdev->config.r600.max_stack_entries = 128;
1499                 rdev->config.r600.max_hw_contexts = 8;
1500                 rdev->config.r600.max_gs_threads = 4;
1501                 rdev->config.r600.sx_max_export_size = 128;
1502                 rdev->config.r600.sx_max_export_pos_size = 16;
1503                 rdev->config.r600.sx_max_export_smx_size = 128;
1504                 rdev->config.r600.sq_num_cf_insts = 2;
1505                 break;
1506         case CHIP_RV610:
1507         case CHIP_RV620:
1508         case CHIP_RS780:
1509         case CHIP_RS880:
1510                 rdev->config.r600.max_pipes = 1;
1511                 rdev->config.r600.max_tile_pipes = 1;
1512                 rdev->config.r600.max_simds = 2;
1513                 rdev->config.r600.max_backends = 1;
1514                 rdev->config.r600.max_gprs = 128;
1515                 rdev->config.r600.max_threads = 192;
1516                 rdev->config.r600.max_stack_entries = 128;
1517                 rdev->config.r600.max_hw_contexts = 4;
1518                 rdev->config.r600.max_gs_threads = 4;
1519                 rdev->config.r600.sx_max_export_size = 128;
1520                 rdev->config.r600.sx_max_export_pos_size = 16;
1521                 rdev->config.r600.sx_max_export_smx_size = 128;
1522                 rdev->config.r600.sq_num_cf_insts = 1;
1523                 break;
1524         case CHIP_RV670:
1525                 rdev->config.r600.max_pipes = 4;
1526                 rdev->config.r600.max_tile_pipes = 4;
1527                 rdev->config.r600.max_simds = 4;
1528                 rdev->config.r600.max_backends = 4;
1529                 rdev->config.r600.max_gprs = 192;
1530                 rdev->config.r600.max_threads = 192;
1531                 rdev->config.r600.max_stack_entries = 256;
1532                 rdev->config.r600.max_hw_contexts = 8;
1533                 rdev->config.r600.max_gs_threads = 16;
1534                 rdev->config.r600.sx_max_export_size = 128;
1535                 rdev->config.r600.sx_max_export_pos_size = 16;
1536                 rdev->config.r600.sx_max_export_smx_size = 128;
1537                 rdev->config.r600.sq_num_cf_insts = 2;
1538                 break;
1539         default:
1540                 break;
1541         }
1542
1543         /* Initialize HDP */
1544         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
1545                 WREG32((0x2c14 + j), 0x00000000);
1546                 WREG32((0x2c18 + j), 0x00000000);
1547                 WREG32((0x2c1c + j), 0x00000000);
1548                 WREG32((0x2c20 + j), 0x00000000);
1549                 WREG32((0x2c24 + j), 0x00000000);
1550         }
1551
1552         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
1553
1554         /* Setup tiling */
1555         tiling_config = 0;
1556         ramcfg = RREG32(RAMCFG);
1557         switch (rdev->config.r600.max_tile_pipes) {
1558         case 1:
1559                 tiling_config |= PIPE_TILING(0);
1560                 break;
1561         case 2:
1562                 tiling_config |= PIPE_TILING(1);
1563                 break;
1564         case 4:
1565                 tiling_config |= PIPE_TILING(2);
1566                 break;
1567         case 8:
1568                 tiling_config |= PIPE_TILING(3);
1569                 break;
1570         default:
1571                 break;
1572         }
1573         rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes;
1574         rdev->config.r600.tiling_nbanks = 4 << ((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1575         tiling_config |= BANK_TILING((ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT);
1576         tiling_config |= GROUP_SIZE(0);
1577         rdev->config.r600.tiling_group_size = 256;
1578         tmp = (ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
1579         if (tmp > 3) {
1580                 tiling_config |= ROW_TILING(3);
1581                 tiling_config |= SAMPLE_SPLIT(3);
1582         } else {
1583                 tiling_config |= ROW_TILING(tmp);
1584                 tiling_config |= SAMPLE_SPLIT(tmp);
1585         }
1586         tiling_config |= BANK_SWAPS(1);
1587
1588         cc_rb_backend_disable = RREG32(CC_RB_BACKEND_DISABLE) & 0x00ff0000;
1589         cc_rb_backend_disable |=
1590                 BACKEND_DISABLE((R6XX_MAX_BACKENDS_MASK << rdev->config.r600.max_backends) & R6XX_MAX_BACKENDS_MASK);
1591
1592         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & 0xffffff00;
1593         cc_gc_shader_pipe_config |=
1594                 INACTIVE_QD_PIPES((R6XX_MAX_PIPES_MASK << rdev->config.r600.max_pipes) & R6XX_MAX_PIPES_MASK);
1595         cc_gc_shader_pipe_config |=
1596                 INACTIVE_SIMDS((R6XX_MAX_SIMDS_MASK << rdev->config.r600.max_simds) & R6XX_MAX_SIMDS_MASK);
1597
1598         backend_map = r600_get_tile_pipe_to_backend_map(rdev->config.r600.max_tile_pipes,
1599                                                         (R6XX_MAX_BACKENDS -
1600                                                          r600_count_pipe_bits((cc_rb_backend_disable &
1601                                                                                R6XX_MAX_BACKENDS_MASK) >> 16)),
1602                                                         (cc_rb_backend_disable >> 16));
1603
1604         tiling_config |= BACKEND_MAP(backend_map);
1605         WREG32(GB_TILING_CONFIG, tiling_config);
1606         WREG32(DCP_TILING_CONFIG, tiling_config & 0xffff);
1607         WREG32(HDP_TILING_CONFIG, tiling_config & 0xffff);
1608
1609         /* Setup pipes */
1610         WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable);
1611         WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1612         WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config);
1613
1614         tmp = R6XX_MAX_PIPES - r600_count_pipe_bits((cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK) >> 8);
1615         WREG32(VGT_OUT_DEALLOC_CNTL, (tmp * 4) & DEALLOC_DIST_MASK);
1616         WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((tmp * 4) - 2) & VTX_REUSE_DEPTH_MASK);
1617
1618         /* Setup some CP states */
1619         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | ROQ_IB2_START(0x2b)));
1620         WREG32(CP_MEQ_THRESHOLDS, (MEQ_END(0x40) | ROQ_END(0x40)));
1621
1622         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | SYNC_GRADIENT |
1623                              SYNC_WALKER | SYNC_ALIGNER));
1624         /* Setup various GPU states */
1625         if (rdev->family == CHIP_RV670)
1626                 WREG32(ARB_GDEC_RD_CNTL, 0x00000021);
1627
1628         tmp = RREG32(SX_DEBUG_1);
1629         tmp |= SMX_EVENT_RELEASE;
1630         if ((rdev->family > CHIP_R600))
1631                 tmp |= ENABLE_NEW_SMX_ADDRESS;
1632         WREG32(SX_DEBUG_1, tmp);
1633
1634         if (((rdev->family) == CHIP_R600) ||
1635             ((rdev->family) == CHIP_RV630) ||
1636             ((rdev->family) == CHIP_RV610) ||
1637             ((rdev->family) == CHIP_RV620) ||
1638             ((rdev->family) == CHIP_RS780) ||
1639             ((rdev->family) == CHIP_RS880)) {
1640                 WREG32(DB_DEBUG, PREZ_MUST_WAIT_FOR_POSTZ_DONE);
1641         } else {
1642                 WREG32(DB_DEBUG, 0);
1643         }
1644         WREG32(DB_WATERMARKS, (DEPTH_FREE(4) | DEPTH_CACHELINE_FREE(16) |
1645                                DEPTH_FLUSH(16) | DEPTH_PENDING_FREE(4)));
1646
1647         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1648         WREG32(VGT_NUM_INSTANCES, 0);
1649
1650         WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0));
1651         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(0));
1652
1653         tmp = RREG32(SQ_MS_FIFO_SIZES);
1654         if (((rdev->family) == CHIP_RV610) ||
1655             ((rdev->family) == CHIP_RV620) ||
1656             ((rdev->family) == CHIP_RS780) ||
1657             ((rdev->family) == CHIP_RS880)) {
1658                 tmp = (CACHE_FIFO_SIZE(0xa) |
1659                        FETCH_FIFO_HIWATER(0xa) |
1660                        DONE_FIFO_HIWATER(0xe0) |
1661                        ALU_UPDATE_FIFO_HIWATER(0x8));
1662         } else if (((rdev->family) == CHIP_R600) ||
1663                    ((rdev->family) == CHIP_RV630)) {
1664                 tmp &= ~DONE_FIFO_HIWATER(0xff);
1665                 tmp |= DONE_FIFO_HIWATER(0x4);
1666         }
1667         WREG32(SQ_MS_FIFO_SIZES, tmp);
1668
1669         /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT
1670          * should be adjusted as needed by the 2D/3D drivers.  This just sets default values
1671          */
1672         sq_config = RREG32(SQ_CONFIG);
1673         sq_config &= ~(PS_PRIO(3) |
1674                        VS_PRIO(3) |
1675                        GS_PRIO(3) |
1676                        ES_PRIO(3));
1677         sq_config |= (DX9_CONSTS |
1678                       VC_ENABLE |
1679                       PS_PRIO(0) |
1680                       VS_PRIO(1) |
1681                       GS_PRIO(2) |
1682                       ES_PRIO(3));
1683
1684         if ((rdev->family) == CHIP_R600) {
1685                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(124) |
1686                                           NUM_VS_GPRS(124) |
1687                                           NUM_CLAUSE_TEMP_GPRS(4));
1688                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(0) |
1689                                           NUM_ES_GPRS(0));
1690                 sq_thread_resource_mgmt = (NUM_PS_THREADS(136) |
1691                                            NUM_VS_THREADS(48) |
1692                                            NUM_GS_THREADS(4) |
1693                                            NUM_ES_THREADS(4));
1694                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(128) |
1695                                             NUM_VS_STACK_ENTRIES(128));
1696                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(0) |
1697                                             NUM_ES_STACK_ENTRIES(0));
1698         } else if (((rdev->family) == CHIP_RV610) ||
1699                    ((rdev->family) == CHIP_RV620) ||
1700                    ((rdev->family) == CHIP_RS780) ||
1701                    ((rdev->family) == CHIP_RS880)) {
1702                 /* no vertex cache */
1703                 sq_config &= ~VC_ENABLE;
1704
1705                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1706                                           NUM_VS_GPRS(44) |
1707                                           NUM_CLAUSE_TEMP_GPRS(2));
1708                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1709                                           NUM_ES_GPRS(17));
1710                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1711                                            NUM_VS_THREADS(78) |
1712                                            NUM_GS_THREADS(4) |
1713                                            NUM_ES_THREADS(31));
1714                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1715                                             NUM_VS_STACK_ENTRIES(40));
1716                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1717                                             NUM_ES_STACK_ENTRIES(16));
1718         } else if (((rdev->family) == CHIP_RV630) ||
1719                    ((rdev->family) == CHIP_RV635)) {
1720                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1721                                           NUM_VS_GPRS(44) |
1722                                           NUM_CLAUSE_TEMP_GPRS(2));
1723                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(18) |
1724                                           NUM_ES_GPRS(18));
1725                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1726                                            NUM_VS_THREADS(78) |
1727                                            NUM_GS_THREADS(4) |
1728                                            NUM_ES_THREADS(31));
1729                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(40) |
1730                                             NUM_VS_STACK_ENTRIES(40));
1731                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(32) |
1732                                             NUM_ES_STACK_ENTRIES(16));
1733         } else if ((rdev->family) == CHIP_RV670) {
1734                 sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(44) |
1735                                           NUM_VS_GPRS(44) |
1736                                           NUM_CLAUSE_TEMP_GPRS(2));
1737                 sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(17) |
1738                                           NUM_ES_GPRS(17));
1739                 sq_thread_resource_mgmt = (NUM_PS_THREADS(79) |
1740                                            NUM_VS_THREADS(78) |
1741                                            NUM_GS_THREADS(4) |
1742                                            NUM_ES_THREADS(31));
1743                 sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(64) |
1744                                             NUM_VS_STACK_ENTRIES(64));
1745                 sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(64) |
1746                                             NUM_ES_STACK_ENTRIES(64));
1747         }
1748
1749         WREG32(SQ_CONFIG, sq_config);
1750         WREG32(SQ_GPR_RESOURCE_MGMT_1,  sq_gpr_resource_mgmt_1);
1751         WREG32(SQ_GPR_RESOURCE_MGMT_2,  sq_gpr_resource_mgmt_2);
1752         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1753         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1754         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1755
1756         if (((rdev->family) == CHIP_RV610) ||
1757             ((rdev->family) == CHIP_RV620) ||
1758             ((rdev->family) == CHIP_RS780) ||
1759             ((rdev->family) == CHIP_RS880)) {
1760                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(TC_ONLY));
1761         } else {
1762                 WREG32(VGT_CACHE_INVALIDATION, CACHE_INVALIDATION(VC_AND_TC));
1763         }
1764
1765         /* More default values. 2D/3D driver should adjust as needed */
1766         WREG32(PA_SC_AA_SAMPLE_LOCS_2S, (S0_X(0xc) | S0_Y(0x4) |
1767                                          S1_X(0x4) | S1_Y(0xc)));
1768         WREG32(PA_SC_AA_SAMPLE_LOCS_4S, (S0_X(0xe) | S0_Y(0xe) |
1769                                          S1_X(0x2) | S1_Y(0x2) |
1770                                          S2_X(0xa) | S2_Y(0x6) |
1771                                          S3_X(0x6) | S3_Y(0xa)));
1772         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD0, (S0_X(0xe) | S0_Y(0xb) |
1773                                              S1_X(0x4) | S1_Y(0xc) |
1774                                              S2_X(0x1) | S2_Y(0x6) |
1775                                              S3_X(0xa) | S3_Y(0xe)));
1776         WREG32(PA_SC_AA_SAMPLE_LOCS_8S_WD1, (S4_X(0x6) | S4_Y(0x1) |
1777                                              S5_X(0x0) | S5_Y(0x0) |
1778                                              S6_X(0xb) | S6_Y(0x4) |
1779                                              S7_X(0x7) | S7_Y(0x8)));
1780
1781         WREG32(VGT_STRMOUT_EN, 0);
1782         tmp = rdev->config.r600.max_pipes * 16;
1783         switch (rdev->family) {
1784         case CHIP_RV610:
1785         case CHIP_RV620:
1786         case CHIP_RS780:
1787         case CHIP_RS880:
1788                 tmp += 32;
1789                 break;
1790         case CHIP_RV670:
1791                 tmp += 128;
1792                 break;
1793         default:
1794                 break;
1795         }
1796         if (tmp > 256) {
1797                 tmp = 256;
1798         }
1799         WREG32(VGT_ES_PER_GS, 128);
1800         WREG32(VGT_GS_PER_ES, tmp);
1801         WREG32(VGT_GS_PER_VS, 2);
1802         WREG32(VGT_GS_VERTEX_REUSE, 16);
1803
1804         /* more default values. 2D/3D driver should adjust as needed */
1805         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1806         WREG32(VGT_STRMOUT_EN, 0);
1807         WREG32(SX_MISC, 0);
1808         WREG32(PA_SC_MODE_CNTL, 0);
1809         WREG32(PA_SC_AA_CONFIG, 0);
1810         WREG32(PA_SC_LINE_STIPPLE, 0);
1811         WREG32(SPI_INPUT_Z, 0);
1812         WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2));
1813         WREG32(CB_COLOR7_FRAG, 0);
1814
1815         /* Clear render buffer base addresses */
1816         WREG32(CB_COLOR0_BASE, 0);
1817         WREG32(CB_COLOR1_BASE, 0);
1818         WREG32(CB_COLOR2_BASE, 0);
1819         WREG32(CB_COLOR3_BASE, 0);
1820         WREG32(CB_COLOR4_BASE, 0);
1821         WREG32(CB_COLOR5_BASE, 0);
1822         WREG32(CB_COLOR6_BASE, 0);
1823         WREG32(CB_COLOR7_BASE, 0);
1824         WREG32(CB_COLOR7_FRAG, 0);
1825
1826         switch (rdev->family) {
1827         case CHIP_RV610:
1828         case CHIP_RV620:
1829         case CHIP_RS780:
1830         case CHIP_RS880:
1831                 tmp = TC_L2_SIZE(8);
1832                 break;
1833         case CHIP_RV630:
1834         case CHIP_RV635:
1835                 tmp = TC_L2_SIZE(4);
1836                 break;
1837         case CHIP_R600:
1838                 tmp = TC_L2_SIZE(0) | L2_DISABLE_LATE_HIT;
1839                 break;
1840         default:
1841                 tmp = TC_L2_SIZE(0);
1842                 break;
1843         }
1844         WREG32(TC_CNTL, tmp);
1845
1846         tmp = RREG32(HDP_HOST_PATH_CNTL);
1847         WREG32(HDP_HOST_PATH_CNTL, tmp);
1848
1849         tmp = RREG32(ARB_POP);
1850         tmp |= ENABLE_TC128;
1851         WREG32(ARB_POP, tmp);
1852
1853         WREG32(PA_SC_MULTI_CHIP_CNTL, 0);
1854         WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA |
1855                                NUM_CLIP_SEQ(3)));
1856         WREG32(PA_SC_ENHANCE, FORCE_EOV_MAX_CLK_CNT(4095));
1857 }
1858
1859
1860 /*
1861  * Indirect registers accessor
1862  */
1863 u32 r600_pciep_rreg(struct radeon_device *rdev, u32 reg)
1864 {
1865         u32 r;
1866
1867         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1868         (void)RREG32(PCIE_PORT_INDEX);
1869         r = RREG32(PCIE_PORT_DATA);
1870         return r;
1871 }
1872
1873 void r600_pciep_wreg(struct radeon_device *rdev, u32 reg, u32 v)
1874 {
1875         WREG32(PCIE_PORT_INDEX, ((reg) & 0xff));
1876         (void)RREG32(PCIE_PORT_INDEX);
1877         WREG32(PCIE_PORT_DATA, (v));
1878         (void)RREG32(PCIE_PORT_DATA);
1879 }
1880
1881 /*
1882  * CP & Ring
1883  */
1884 void r600_cp_stop(struct radeon_device *rdev)
1885 {
1886         WREG32(R_0086D8_CP_ME_CNTL, S_0086D8_CP_ME_HALT(1));
1887 }
1888
1889 int r600_init_microcode(struct radeon_device *rdev)
1890 {
1891         struct platform_device *pdev;
1892         const char *chip_name;
1893         const char *rlc_chip_name;
1894         size_t pfp_req_size, me_req_size, rlc_req_size;
1895         char fw_name[30];
1896         int err;
1897
1898         DRM_DEBUG("\n");
1899
1900         pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
1901         err = IS_ERR(pdev);
1902         if (err) {
1903                 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
1904                 return -EINVAL;
1905         }
1906
1907         switch (rdev->family) {
1908         case CHIP_R600:
1909                 chip_name = "R600";
1910                 rlc_chip_name = "R600";
1911                 break;
1912         case CHIP_RV610:
1913                 chip_name = "RV610";
1914                 rlc_chip_name = "R600";
1915                 break;
1916         case CHIP_RV630:
1917                 chip_name = "RV630";
1918                 rlc_chip_name = "R600";
1919                 break;
1920         case CHIP_RV620:
1921                 chip_name = "RV620";
1922                 rlc_chip_name = "R600";
1923                 break;
1924         case CHIP_RV635:
1925                 chip_name = "RV635";
1926                 rlc_chip_name = "R600";
1927                 break;
1928         case CHIP_RV670:
1929                 chip_name = "RV670";
1930                 rlc_chip_name = "R600";
1931                 break;
1932         case CHIP_RS780:
1933         case CHIP_RS880:
1934                 chip_name = "RS780";
1935                 rlc_chip_name = "R600";
1936                 break;
1937         case CHIP_RV770:
1938                 chip_name = "RV770";
1939                 rlc_chip_name = "R700";
1940                 break;
1941         case CHIP_RV730:
1942         case CHIP_RV740:
1943                 chip_name = "RV730";
1944                 rlc_chip_name = "R700";
1945                 break;
1946         case CHIP_RV710:
1947                 chip_name = "RV710";
1948                 rlc_chip_name = "R700";
1949                 break;
1950         case CHIP_CEDAR:
1951                 chip_name = "CEDAR";
1952                 rlc_chip_name = "CEDAR";
1953                 break;
1954         case CHIP_REDWOOD:
1955                 chip_name = "REDWOOD";
1956                 rlc_chip_name = "REDWOOD";
1957                 break;
1958         case CHIP_JUNIPER:
1959                 chip_name = "JUNIPER";
1960                 rlc_chip_name = "JUNIPER";
1961                 break;
1962         case CHIP_CYPRESS:
1963         case CHIP_HEMLOCK:
1964                 chip_name = "CYPRESS";
1965                 rlc_chip_name = "CYPRESS";
1966                 break;
1967         default: BUG();
1968         }
1969
1970         if (rdev->family >= CHIP_CEDAR) {
1971                 pfp_req_size = EVERGREEN_PFP_UCODE_SIZE * 4;
1972                 me_req_size = EVERGREEN_PM4_UCODE_SIZE * 4;
1973                 rlc_req_size = EVERGREEN_RLC_UCODE_SIZE * 4;
1974         } else if (rdev->family >= CHIP_RV770) {
1975                 pfp_req_size = R700_PFP_UCODE_SIZE * 4;
1976                 me_req_size = R700_PM4_UCODE_SIZE * 4;
1977                 rlc_req_size = R700_RLC_UCODE_SIZE * 4;
1978         } else {
1979                 pfp_req_size = PFP_UCODE_SIZE * 4;
1980                 me_req_size = PM4_UCODE_SIZE * 12;
1981                 rlc_req_size = RLC_UCODE_SIZE * 4;
1982         }
1983
1984         DRM_INFO("Loading %s Microcode\n", chip_name);
1985
1986         snprintf(fw_name, sizeof(fw_name), "radeon/%s_pfp.bin", chip_name);
1987         err = request_firmware(&rdev->pfp_fw, fw_name, &pdev->dev);
1988         if (err)
1989                 goto out;
1990         if (rdev->pfp_fw->size != pfp_req_size) {
1991                 printk(KERN_ERR
1992                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
1993                        rdev->pfp_fw->size, fw_name);
1994                 err = -EINVAL;
1995                 goto out;
1996         }
1997
1998         snprintf(fw_name, sizeof(fw_name), "radeon/%s_me.bin", chip_name);
1999         err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
2000         if (err)
2001                 goto out;
2002         if (rdev->me_fw->size != me_req_size) {
2003                 printk(KERN_ERR
2004                        "r600_cp: Bogus length %zu in firmware \"%s\"\n",
2005                        rdev->me_fw->size, fw_name);
2006                 err = -EINVAL;
2007         }
2008
2009         snprintf(fw_name, sizeof(fw_name), "radeon/%s_rlc.bin", rlc_chip_name);
2010         err = request_firmware(&rdev->rlc_fw, fw_name, &pdev->dev);
2011         if (err)
2012                 goto out;
2013         if (rdev->rlc_fw->size != rlc_req_size) {
2014                 printk(KERN_ERR
2015                        "r600_rlc: Bogus length %zu in firmware \"%s\"\n",
2016                        rdev->rlc_fw->size, fw_name);
2017                 err = -EINVAL;
2018         }
2019
2020 out:
2021         platform_device_unregister(pdev);
2022
2023         if (err) {
2024                 if (err != -EINVAL)
2025                         printk(KERN_ERR
2026                                "r600_cp: Failed to load firmware \"%s\"\n",
2027                                fw_name);
2028                 release_firmware(rdev->pfp_fw);
2029                 rdev->pfp_fw = NULL;
2030                 release_firmware(rdev->me_fw);
2031                 rdev->me_fw = NULL;
2032                 release_firmware(rdev->rlc_fw);
2033                 rdev->rlc_fw = NULL;
2034         }
2035         return err;
2036 }
2037
2038 static int r600_cp_load_microcode(struct radeon_device *rdev)
2039 {
2040         const __be32 *fw_data;
2041         int i;
2042
2043         if (!rdev->me_fw || !rdev->pfp_fw)
2044                 return -EINVAL;
2045
2046         r600_cp_stop(rdev);
2047
2048         WREG32(CP_RB_CNTL, RB_NO_UPDATE | RB_BLKSZ(15) | RB_BUFSZ(3));
2049
2050         /* Reset cp */
2051         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2052         RREG32(GRBM_SOFT_RESET);
2053         mdelay(15);
2054         WREG32(GRBM_SOFT_RESET, 0);
2055
2056         WREG32(CP_ME_RAM_WADDR, 0);
2057
2058         fw_data = (const __be32 *)rdev->me_fw->data;
2059         WREG32(CP_ME_RAM_WADDR, 0);
2060         for (i = 0; i < PM4_UCODE_SIZE * 3; i++)
2061                 WREG32(CP_ME_RAM_DATA,
2062                        be32_to_cpup(fw_data++));
2063
2064         fw_data = (const __be32 *)rdev->pfp_fw->data;
2065         WREG32(CP_PFP_UCODE_ADDR, 0);
2066         for (i = 0; i < PFP_UCODE_SIZE; i++)
2067                 WREG32(CP_PFP_UCODE_DATA,
2068                        be32_to_cpup(fw_data++));
2069
2070         WREG32(CP_PFP_UCODE_ADDR, 0);
2071         WREG32(CP_ME_RAM_WADDR, 0);
2072         WREG32(CP_ME_RAM_RADDR, 0);
2073         return 0;
2074 }
2075
2076 int r600_cp_start(struct radeon_device *rdev)
2077 {
2078         int r;
2079         uint32_t cp_me;
2080
2081         r = radeon_ring_lock(rdev, 7);
2082         if (r) {
2083                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2084                 return r;
2085         }
2086         radeon_ring_write(rdev, PACKET3(PACKET3_ME_INITIALIZE, 5));
2087         radeon_ring_write(rdev, 0x1);
2088         if (rdev->family >= CHIP_CEDAR) {
2089                 radeon_ring_write(rdev, 0x0);
2090                 radeon_ring_write(rdev, rdev->config.evergreen.max_hw_contexts - 1);
2091         } else if (rdev->family >= CHIP_RV770) {
2092                 radeon_ring_write(rdev, 0x0);
2093                 radeon_ring_write(rdev, rdev->config.rv770.max_hw_contexts - 1);
2094         } else {
2095                 radeon_ring_write(rdev, 0x3);
2096                 radeon_ring_write(rdev, rdev->config.r600.max_hw_contexts - 1);
2097         }
2098         radeon_ring_write(rdev, PACKET3_ME_INITIALIZE_DEVICE_ID(1));
2099         radeon_ring_write(rdev, 0);
2100         radeon_ring_write(rdev, 0);
2101         radeon_ring_unlock_commit(rdev);
2102
2103         cp_me = 0xff;
2104         WREG32(R_0086D8_CP_ME_CNTL, cp_me);
2105         return 0;
2106 }
2107
2108 int r600_cp_resume(struct radeon_device *rdev)
2109 {
2110         u32 tmp;
2111         u32 rb_bufsz;
2112         int r;
2113
2114         /* Reset cp */
2115         WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP);
2116         RREG32(GRBM_SOFT_RESET);
2117         mdelay(15);
2118         WREG32(GRBM_SOFT_RESET, 0);
2119
2120         /* Set ring buffer size */
2121         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
2122         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
2123 #ifdef __BIG_ENDIAN
2124         tmp |= BUF_SWAP_32BIT;
2125 #endif
2126         WREG32(CP_RB_CNTL, tmp);
2127         WREG32(CP_SEM_WAIT_TIMER, 0x4);
2128
2129         /* Set the write pointer delay */
2130         WREG32(CP_RB_WPTR_DELAY, 0);
2131
2132         /* Initialize the ring buffer's read and write pointers */
2133         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
2134         WREG32(CP_RB_RPTR_WR, 0);
2135         WREG32(CP_RB_WPTR, 0);
2136         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
2137         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
2138         mdelay(1);
2139         WREG32(CP_RB_CNTL, tmp);
2140
2141         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
2142         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
2143
2144         rdev->cp.rptr = RREG32(CP_RB_RPTR);
2145         rdev->cp.wptr = RREG32(CP_RB_WPTR);
2146
2147         r600_cp_start(rdev);
2148         rdev->cp.ready = true;
2149         r = radeon_ring_test(rdev);
2150         if (r) {
2151                 rdev->cp.ready = false;
2152                 return r;
2153         }
2154         return 0;
2155 }
2156
2157 void r600_cp_commit(struct radeon_device *rdev)
2158 {
2159         WREG32(CP_RB_WPTR, rdev->cp.wptr);
2160         (void)RREG32(CP_RB_WPTR);
2161 }
2162
2163 void r600_ring_init(struct radeon_device *rdev, unsigned ring_size)
2164 {
2165         u32 rb_bufsz;
2166
2167         /* Align ring size */
2168         rb_bufsz = drm_order(ring_size / 8);
2169         ring_size = (1 << (rb_bufsz + 1)) * 4;
2170         rdev->cp.ring_size = ring_size;
2171         rdev->cp.align_mask = 16 - 1;
2172 }
2173
2174 void r600_cp_fini(struct radeon_device *rdev)
2175 {
2176         r600_cp_stop(rdev);
2177         radeon_ring_fini(rdev);
2178 }
2179
2180
2181 /*
2182  * GPU scratch registers helpers function.
2183  */
2184 void r600_scratch_init(struct radeon_device *rdev)
2185 {
2186         int i;
2187
2188         rdev->scratch.num_reg = 7;
2189         for (i = 0; i < rdev->scratch.num_reg; i++) {
2190                 rdev->scratch.free[i] = true;
2191                 rdev->scratch.reg[i] = SCRATCH_REG0 + (i * 4);
2192         }
2193 }
2194
2195 int r600_ring_test(struct radeon_device *rdev)
2196 {
2197         uint32_t scratch;
2198         uint32_t tmp = 0;
2199         unsigned i;
2200         int r;
2201
2202         r = radeon_scratch_get(rdev, &scratch);
2203         if (r) {
2204                 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
2205                 return r;
2206         }
2207         WREG32(scratch, 0xCAFEDEAD);
2208         r = radeon_ring_lock(rdev, 3);
2209         if (r) {
2210                 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
2211                 radeon_scratch_free(rdev, scratch);
2212                 return r;
2213         }
2214         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2215         radeon_ring_write(rdev, ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2216         radeon_ring_write(rdev, 0xDEADBEEF);
2217         radeon_ring_unlock_commit(rdev);
2218         for (i = 0; i < rdev->usec_timeout; i++) {
2219                 tmp = RREG32(scratch);
2220                 if (tmp == 0xDEADBEEF)
2221                         break;
2222                 DRM_UDELAY(1);
2223         }
2224         if (i < rdev->usec_timeout) {
2225                 DRM_INFO("ring test succeeded in %d usecs\n", i);
2226         } else {
2227                 DRM_ERROR("radeon: ring test failed (scratch(0x%04X)=0x%08X)\n",
2228                           scratch, tmp);
2229                 r = -EINVAL;
2230         }
2231         radeon_scratch_free(rdev, scratch);
2232         return r;
2233 }
2234
2235 void r600_wb_disable(struct radeon_device *rdev)
2236 {
2237         int r;
2238
2239         WREG32(SCRATCH_UMSK, 0);
2240         if (rdev->wb.wb_obj) {
2241                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2242                 if (unlikely(r != 0))
2243                         return;
2244                 radeon_bo_kunmap(rdev->wb.wb_obj);
2245                 radeon_bo_unpin(rdev->wb.wb_obj);
2246                 radeon_bo_unreserve(rdev->wb.wb_obj);
2247         }
2248 }
2249
2250 void r600_wb_fini(struct radeon_device *rdev)
2251 {
2252         r600_wb_disable(rdev);
2253         if (rdev->wb.wb_obj) {
2254                 radeon_bo_unref(&rdev->wb.wb_obj);
2255                 rdev->wb.wb = NULL;
2256                 rdev->wb.wb_obj = NULL;
2257         }
2258 }
2259
2260 int r600_wb_enable(struct radeon_device *rdev)
2261 {
2262         int r;
2263
2264         if (rdev->wb.wb_obj == NULL) {
2265                 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
2266                                 RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj);
2267                 if (r) {
2268                         dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
2269                         return r;
2270                 }
2271                 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
2272                 if (unlikely(r != 0)) {
2273                         r600_wb_fini(rdev);
2274                         return r;
2275                 }
2276                 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
2277                                 &rdev->wb.gpu_addr);
2278                 if (r) {
2279                         radeon_bo_unreserve(rdev->wb.wb_obj);
2280                         dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
2281                         r600_wb_fini(rdev);
2282                         return r;
2283                 }
2284                 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
2285                 radeon_bo_unreserve(rdev->wb.wb_obj);
2286                 if (r) {
2287                         dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
2288                         r600_wb_fini(rdev);
2289                         return r;
2290                 }
2291         }
2292         WREG32(SCRATCH_ADDR, (rdev->wb.gpu_addr >> 8) & 0xFFFFFFFF);
2293         WREG32(CP_RB_RPTR_ADDR, (rdev->wb.gpu_addr + 1024) & 0xFFFFFFFC);
2294         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->wb.gpu_addr + 1024) & 0xFF);
2295         WREG32(SCRATCH_UMSK, 0xff);
2296         return 0;
2297 }
2298
2299 void r600_fence_ring_emit(struct radeon_device *rdev,
2300                           struct radeon_fence *fence)
2301 {
2302         /* Also consider EVENT_WRITE_EOP.  it handles the interrupts + timestamps + events */
2303
2304         radeon_ring_write(rdev, PACKET3(PACKET3_EVENT_WRITE, 0));
2305         radeon_ring_write(rdev, CACHE_FLUSH_AND_INV_EVENT);
2306         /* wait for 3D idle clean */
2307         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2308         radeon_ring_write(rdev, (WAIT_UNTIL - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2309         radeon_ring_write(rdev, WAIT_3D_IDLE_bit | WAIT_3D_IDLECLEAN_bit);
2310         /* Emit fence sequence & fire IRQ */
2311         radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1));
2312         radeon_ring_write(rdev, ((rdev->fence_drv.scratch_reg - PACKET3_SET_CONFIG_REG_OFFSET) >> 2));
2313         radeon_ring_write(rdev, fence->seq);
2314         /* CP_INTERRUPT packet 3 no longer exists, use packet 0 */
2315         radeon_ring_write(rdev, PACKET0(CP_INT_STATUS, 0));
2316         radeon_ring_write(rdev, RB_INT_STAT);
2317 }
2318
2319 int r600_copy_blit(struct radeon_device *rdev,
2320                    uint64_t src_offset, uint64_t dst_offset,
2321                    unsigned num_pages, struct radeon_fence *fence)
2322 {
2323         int r;
2324
2325         mutex_lock(&rdev->r600_blit.mutex);
2326         rdev->r600_blit.vb_ib = NULL;
2327         r = r600_blit_prepare_copy(rdev, num_pages * RADEON_GPU_PAGE_SIZE);
2328         if (r) {
2329                 if (rdev->r600_blit.vb_ib)
2330                         radeon_ib_free(rdev, &rdev->r600_blit.vb_ib);
2331                 mutex_unlock(&rdev->r600_blit.mutex);
2332                 return r;
2333         }
2334         r600_kms_blit_copy(rdev, src_offset, dst_offset, num_pages * RADEON_GPU_PAGE_SIZE);
2335         r600_blit_done_copy(rdev, fence);
2336         mutex_unlock(&rdev->r600_blit.mutex);
2337         return 0;
2338 }
2339
2340 int r600_set_surface_reg(struct radeon_device *rdev, int reg,
2341                          uint32_t tiling_flags, uint32_t pitch,
2342                          uint32_t offset, uint32_t obj_size)
2343 {
2344         /* FIXME: implement */
2345         return 0;
2346 }
2347
2348 void r600_clear_surface_reg(struct radeon_device *rdev, int reg)
2349 {
2350         /* FIXME: implement */
2351 }
2352
2353
2354 bool r600_card_posted(struct radeon_device *rdev)
2355 {
2356         uint32_t reg;
2357
2358         /* first check CRTCs */
2359         reg = RREG32(D1CRTC_CONTROL) |
2360                 RREG32(D2CRTC_CONTROL);
2361         if (reg & CRTC_EN)
2362                 return true;
2363
2364         /* then check MEM_SIZE, in case the crtcs are off */
2365         if (RREG32(CONFIG_MEMSIZE))
2366                 return true;
2367
2368         return false;
2369 }
2370
2371 int r600_startup(struct radeon_device *rdev)
2372 {
2373         int r;
2374
2375         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
2376                 r = r600_init_microcode(rdev);
2377                 if (r) {
2378                         DRM_ERROR("Failed to load firmware!\n");
2379                         return r;
2380                 }
2381         }
2382
2383         r600_mc_program(rdev);
2384         if (rdev->flags & RADEON_IS_AGP) {
2385                 r600_agp_enable(rdev);
2386         } else {
2387                 r = r600_pcie_gart_enable(rdev);
2388                 if (r)
2389                         return r;
2390         }
2391         r600_gpu_init(rdev);
2392         r = r600_blit_init(rdev);
2393         if (r) {
2394                 r600_blit_fini(rdev);
2395                 rdev->asic->copy = NULL;
2396                 dev_warn(rdev->dev, "failed blitter (%d) falling back to memcpy\n", r);
2397         }
2398         /* pin copy shader into vram */
2399         if (rdev->r600_blit.shader_obj) {
2400                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2401                 if (unlikely(r != 0))
2402                         return r;
2403                 r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
2404                                 &rdev->r600_blit.shader_gpu_addr);
2405                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2406                 if (r) {
2407                         dev_err(rdev->dev, "(%d) pin blit object failed\n", r);
2408                         return r;
2409                 }
2410         }
2411         /* Enable IRQ */
2412         r = r600_irq_init(rdev);
2413         if (r) {
2414                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
2415                 radeon_irq_kms_fini(rdev);
2416                 return r;
2417         }
2418         r600_irq_set(rdev);
2419
2420         r = radeon_ring_init(rdev, rdev->cp.ring_size);
2421         if (r)
2422                 return r;
2423         r = r600_cp_load_microcode(rdev);
2424         if (r)
2425                 return r;
2426         r = r600_cp_resume(rdev);
2427         if (r)
2428                 return r;
2429         /* write back buffer are not vital so don't worry about failure */
2430         r600_wb_enable(rdev);
2431         return 0;
2432 }
2433
2434 void r600_vga_set_state(struct radeon_device *rdev, bool state)
2435 {
2436         uint32_t temp;
2437
2438         temp = RREG32(CONFIG_CNTL);
2439         if (state == false) {
2440                 temp &= ~(1<<0);
2441                 temp |= (1<<1);
2442         } else {
2443                 temp &= ~(1<<1);
2444         }
2445         WREG32(CONFIG_CNTL, temp);
2446 }
2447
2448 int r600_resume(struct radeon_device *rdev)
2449 {
2450         int r;
2451
2452         /* Do not reset GPU before posting, on r600 hw unlike on r500 hw,
2453          * posting will perform necessary task to bring back GPU into good
2454          * shape.
2455          */
2456         /* post card */
2457         atom_asic_init(rdev->mode_info.atom_context);
2458         /* Initialize clocks */
2459         r = radeon_clocks_init(rdev);
2460         if (r) {
2461                 return r;
2462         }
2463
2464         r = r600_startup(rdev);
2465         if (r) {
2466                 DRM_ERROR("r600 startup failed on resume\n");
2467                 return r;
2468         }
2469
2470         r = r600_ib_test(rdev);
2471         if (r) {
2472                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2473                 return r;
2474         }
2475
2476         r = r600_audio_init(rdev);
2477         if (r) {
2478                 DRM_ERROR("radeon: audio resume failed\n");
2479                 return r;
2480         }
2481
2482         return r;
2483 }
2484
2485 int r600_suspend(struct radeon_device *rdev)
2486 {
2487         int r;
2488
2489         r600_audio_fini(rdev);
2490         /* FIXME: we should wait for ring to be empty */
2491         r600_cp_stop(rdev);
2492         rdev->cp.ready = false;
2493         r600_irq_suspend(rdev);
2494         r600_wb_disable(rdev);
2495         r600_pcie_gart_disable(rdev);
2496         /* unpin shaders bo */
2497         if (rdev->r600_blit.shader_obj) {
2498                 r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2499                 if (!r) {
2500                         radeon_bo_unpin(rdev->r600_blit.shader_obj);
2501                         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2502                 }
2503         }
2504         return 0;
2505 }
2506
2507 /* Plan is to move initialization in that function and use
2508  * helper function so that radeon_device_init pretty much
2509  * do nothing more than calling asic specific function. This
2510  * should also allow to remove a bunch of callback function
2511  * like vram_info.
2512  */
2513 int r600_init(struct radeon_device *rdev)
2514 {
2515         int r;
2516
2517         r = radeon_dummy_page_init(rdev);
2518         if (r)
2519                 return r;
2520         if (r600_debugfs_mc_info_init(rdev)) {
2521                 DRM_ERROR("Failed to register debugfs file for mc !\n");
2522         }
2523         /* This don't do much */
2524         r = radeon_gem_init(rdev);
2525         if (r)
2526                 return r;
2527         /* Read BIOS */
2528         if (!radeon_get_bios(rdev)) {
2529                 if (ASIC_IS_AVIVO(rdev))
2530                         return -EINVAL;
2531         }
2532         /* Must be an ATOMBIOS */
2533         if (!rdev->is_atom_bios) {
2534                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2535                 return -EINVAL;
2536         }
2537         r = radeon_atombios_init(rdev);
2538         if (r)
2539                 return r;
2540         /* Post card if necessary */
2541         if (!r600_card_posted(rdev)) {
2542                 if (!rdev->bios) {
2543                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2544                         return -EINVAL;
2545                 }
2546                 DRM_INFO("GPU not posted. posting now...\n");
2547                 atom_asic_init(rdev->mode_info.atom_context);
2548         }
2549         /* Initialize scratch registers */
2550         r600_scratch_init(rdev);
2551         /* Initialize surface registers */
2552         radeon_surface_init(rdev);
2553         /* Initialize clocks */
2554         radeon_get_clock_info(rdev->ddev);
2555         r = radeon_clocks_init(rdev);
2556         if (r)
2557                 return r;
2558         /* Fence driver */
2559         r = radeon_fence_driver_init(rdev);
2560         if (r)
2561                 return r;
2562         if (rdev->flags & RADEON_IS_AGP) {
2563                 r = radeon_agp_init(rdev);
2564                 if (r)
2565                         radeon_agp_disable(rdev);
2566         }
2567         r = r600_mc_init(rdev);
2568         if (r)
2569                 return r;
2570         /* Memory manager */
2571         r = radeon_bo_init(rdev);
2572         if (r)
2573                 return r;
2574
2575         r = radeon_irq_kms_init(rdev);
2576         if (r)
2577                 return r;
2578
2579         rdev->cp.ring_obj = NULL;
2580         r600_ring_init(rdev, 1024 * 1024);
2581
2582         rdev->ih.ring_obj = NULL;
2583         r600_ih_ring_init(rdev, 64 * 1024);
2584
2585         r = r600_pcie_gart_init(rdev);
2586         if (r)
2587                 return r;
2588
2589         rdev->accel_working = true;
2590         r = r600_startup(rdev);
2591         if (r) {
2592                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2593                 r600_cp_fini(rdev);
2594                 r600_wb_fini(rdev);
2595                 r600_irq_fini(rdev);
2596                 radeon_irq_kms_fini(rdev);
2597                 r600_pcie_gart_fini(rdev);
2598                 rdev->accel_working = false;
2599         }
2600         if (rdev->accel_working) {
2601                 r = radeon_ib_pool_init(rdev);
2602                 if (r) {
2603                         dev_err(rdev->dev, "IB initialization failed (%d).\n", r);
2604                         rdev->accel_working = false;
2605                 } else {
2606                         r = r600_ib_test(rdev);
2607                         if (r) {
2608                                 dev_err(rdev->dev, "IB test failed (%d).\n", r);
2609                                 rdev->accel_working = false;
2610                         }
2611                 }
2612         }
2613
2614         r = r600_audio_init(rdev);
2615         if (r)
2616                 return r; /* TODO error handling */
2617         return 0;
2618 }
2619
2620 void r600_fini(struct radeon_device *rdev)
2621 {
2622         r600_audio_fini(rdev);
2623         r600_blit_fini(rdev);
2624         r600_cp_fini(rdev);
2625         r600_wb_fini(rdev);
2626         r600_irq_fini(rdev);
2627         radeon_irq_kms_fini(rdev);
2628         r600_pcie_gart_fini(rdev);
2629         radeon_agp_fini(rdev);
2630         radeon_gem_fini(rdev);
2631         radeon_fence_driver_fini(rdev);
2632         radeon_clocks_fini(rdev);
2633         radeon_bo_fini(rdev);
2634         radeon_atombios_fini(rdev);
2635         kfree(rdev->bios);
2636         rdev->bios = NULL;
2637         radeon_dummy_page_fini(rdev);
2638 }
2639
2640
2641 /*
2642  * CS stuff
2643  */
2644 void r600_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
2645 {
2646         /* FIXME: implement */
2647         radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
2648         radeon_ring_write(rdev, ib->gpu_addr & 0xFFFFFFFC);
2649         radeon_ring_write(rdev, upper_32_bits(ib->gpu_addr) & 0xFF);
2650         radeon_ring_write(rdev, ib->length_dw);
2651 }
2652
2653 int r600_ib_test(struct radeon_device *rdev)
2654 {
2655         struct radeon_ib *ib;
2656         uint32_t scratch;
2657         uint32_t tmp = 0;
2658         unsigned i;
2659         int r;
2660
2661         r = radeon_scratch_get(rdev, &scratch);
2662         if (r) {
2663                 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
2664                 return r;
2665         }
2666         WREG32(scratch, 0xCAFEDEAD);
2667         r = radeon_ib_get(rdev, &ib);
2668         if (r) {
2669                 DRM_ERROR("radeon: failed to get ib (%d).\n", r);
2670                 return r;
2671         }
2672         ib->ptr[0] = PACKET3(PACKET3_SET_CONFIG_REG, 1);
2673         ib->ptr[1] = ((scratch - PACKET3_SET_CONFIG_REG_OFFSET) >> 2);
2674         ib->ptr[2] = 0xDEADBEEF;
2675         ib->ptr[3] = PACKET2(0);
2676         ib->ptr[4] = PACKET2(0);
2677         ib->ptr[5] = PACKET2(0);
2678         ib->ptr[6] = PACKET2(0);
2679         ib->ptr[7] = PACKET2(0);
2680         ib->ptr[8] = PACKET2(0);
2681         ib->ptr[9] = PACKET2(0);
2682         ib->ptr[10] = PACKET2(0);
2683         ib->ptr[11] = PACKET2(0);
2684         ib->ptr[12] = PACKET2(0);
2685         ib->ptr[13] = PACKET2(0);
2686         ib->ptr[14] = PACKET2(0);
2687         ib->ptr[15] = PACKET2(0);
2688         ib->length_dw = 16;
2689         r = radeon_ib_schedule(rdev, ib);
2690         if (r) {
2691                 radeon_scratch_free(rdev, scratch);
2692                 radeon_ib_free(rdev, &ib);
2693                 DRM_ERROR("radeon: failed to schedule ib (%d).\n", r);
2694                 return r;
2695         }
2696         r = radeon_fence_wait(ib->fence, false);
2697         if (r) {
2698                 DRM_ERROR("radeon: fence wait failed (%d).\n", r);
2699                 return r;
2700         }
2701         for (i = 0; i < rdev->usec_timeout; i++) {
2702                 tmp = RREG32(scratch);
2703                 if (tmp == 0xDEADBEEF)
2704                         break;
2705                 DRM_UDELAY(1);
2706         }
2707         if (i < rdev->usec_timeout) {
2708                 DRM_INFO("ib test succeeded in %u usecs\n", i);
2709         } else {
2710                 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
2711                           scratch, tmp);
2712                 r = -EINVAL;
2713         }
2714         radeon_scratch_free(rdev, scratch);
2715         radeon_ib_free(rdev, &ib);
2716         return r;
2717 }
2718
2719 /*
2720  * Interrupts
2721  *
2722  * Interrupts use a ring buffer on r6xx/r7xx hardware.  It works pretty
2723  * the same as the CP ring buffer, but in reverse.  Rather than the CPU
2724  * writing to the ring and the GPU consuming, the GPU writes to the ring
2725  * and host consumes.  As the host irq handler processes interrupts, it
2726  * increments the rptr.  When the rptr catches up with the wptr, all the
2727  * current interrupts have been processed.
2728  */
2729
2730 void r600_ih_ring_init(struct radeon_device *rdev, unsigned ring_size)
2731 {
2732         u32 rb_bufsz;
2733
2734         /* Align ring size */
2735         rb_bufsz = drm_order(ring_size / 4);
2736         ring_size = (1 << rb_bufsz) * 4;
2737         rdev->ih.ring_size = ring_size;
2738         rdev->ih.ptr_mask = rdev->ih.ring_size - 1;
2739         rdev->ih.rptr = 0;
2740 }
2741
2742 static int r600_ih_ring_alloc(struct radeon_device *rdev)
2743 {
2744         int r;
2745
2746         /* Allocate ring buffer */
2747         if (rdev->ih.ring_obj == NULL) {
2748                 r = radeon_bo_create(rdev, NULL, rdev->ih.ring_size,
2749                                      true,
2750                                      RADEON_GEM_DOMAIN_GTT,
2751                                      &rdev->ih.ring_obj);
2752                 if (r) {
2753                         DRM_ERROR("radeon: failed to create ih ring buffer (%d).\n", r);
2754                         return r;
2755                 }
2756                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2757                 if (unlikely(r != 0))
2758                         return r;
2759                 r = radeon_bo_pin(rdev->ih.ring_obj,
2760                                   RADEON_GEM_DOMAIN_GTT,
2761                                   &rdev->ih.gpu_addr);
2762                 if (r) {
2763                         radeon_bo_unreserve(rdev->ih.ring_obj);
2764                         DRM_ERROR("radeon: failed to pin ih ring buffer (%d).\n", r);
2765                         return r;
2766                 }
2767                 r = radeon_bo_kmap(rdev->ih.ring_obj,
2768                                    (void **)&rdev->ih.ring);
2769                 radeon_bo_unreserve(rdev->ih.ring_obj);
2770                 if (r) {
2771                         DRM_ERROR("radeon: failed to map ih ring buffer (%d).\n", r);
2772                         return r;
2773                 }
2774         }
2775         return 0;
2776 }
2777
2778 static void r600_ih_ring_fini(struct radeon_device *rdev)
2779 {
2780         int r;
2781         if (rdev->ih.ring_obj) {
2782                 r = radeon_bo_reserve(rdev->ih.ring_obj, false);
2783                 if (likely(r == 0)) {
2784                         radeon_bo_kunmap(rdev->ih.ring_obj);
2785                         radeon_bo_unpin(rdev->ih.ring_obj);
2786                         radeon_bo_unreserve(rdev->ih.ring_obj);
2787                 }
2788                 radeon_bo_unref(&rdev->ih.ring_obj);
2789                 rdev->ih.ring = NULL;
2790                 rdev->ih.ring_obj = NULL;
2791         }
2792 }
2793
2794 void r600_rlc_stop(struct radeon_device *rdev)
2795 {
2796
2797         if ((rdev->family >= CHIP_RV770) &&
2798             (rdev->family <= CHIP_RV740)) {
2799                 /* r7xx asics need to soft reset RLC before halting */
2800                 WREG32(SRBM_SOFT_RESET, SOFT_RESET_RLC);
2801                 RREG32(SRBM_SOFT_RESET);
2802                 udelay(15000);
2803                 WREG32(SRBM_SOFT_RESET, 0);
2804                 RREG32(SRBM_SOFT_RESET);
2805         }
2806
2807         WREG32(RLC_CNTL, 0);
2808 }
2809
2810 static void r600_rlc_start(struct radeon_device *rdev)
2811 {
2812         WREG32(RLC_CNTL, RLC_ENABLE);
2813 }
2814
2815 static int r600_rlc_init(struct radeon_device *rdev)
2816 {
2817         u32 i;
2818         const __be32 *fw_data;
2819
2820         if (!rdev->rlc_fw)
2821                 return -EINVAL;
2822
2823         r600_rlc_stop(rdev);
2824
2825         WREG32(RLC_HB_BASE, 0);
2826         WREG32(RLC_HB_CNTL, 0);
2827         WREG32(RLC_HB_RPTR, 0);
2828         WREG32(RLC_HB_WPTR, 0);
2829         WREG32(RLC_HB_WPTR_LSB_ADDR, 0);
2830         WREG32(RLC_HB_WPTR_MSB_ADDR, 0);
2831         WREG32(RLC_MC_CNTL, 0);
2832         WREG32(RLC_UCODE_CNTL, 0);
2833
2834         fw_data = (const __be32 *)rdev->rlc_fw->data;
2835         if (rdev->family >= CHIP_CEDAR) {
2836                 for (i = 0; i < EVERGREEN_RLC_UCODE_SIZE; i++) {
2837                         WREG32(RLC_UCODE_ADDR, i);
2838                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2839                 }
2840         } else if (rdev->family >= CHIP_RV770) {
2841                 for (i = 0; i < R700_RLC_UCODE_SIZE; i++) {
2842                         WREG32(RLC_UCODE_ADDR, i);
2843                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2844                 }
2845         } else {
2846                 for (i = 0; i < RLC_UCODE_SIZE; i++) {
2847                         WREG32(RLC_UCODE_ADDR, i);
2848                         WREG32(RLC_UCODE_DATA, be32_to_cpup(fw_data++));
2849                 }
2850         }
2851         WREG32(RLC_UCODE_ADDR, 0);
2852
2853         r600_rlc_start(rdev);
2854
2855         return 0;
2856 }
2857
2858 static void r600_enable_interrupts(struct radeon_device *rdev)
2859 {
2860         u32 ih_cntl = RREG32(IH_CNTL);
2861         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2862
2863         ih_cntl |= ENABLE_INTR;
2864         ih_rb_cntl |= IH_RB_ENABLE;
2865         WREG32(IH_CNTL, ih_cntl);
2866         WREG32(IH_RB_CNTL, ih_rb_cntl);
2867         rdev->ih.enabled = true;
2868 }
2869
2870 void r600_disable_interrupts(struct radeon_device *rdev)
2871 {
2872         u32 ih_rb_cntl = RREG32(IH_RB_CNTL);
2873         u32 ih_cntl = RREG32(IH_CNTL);
2874
2875         ih_rb_cntl &= ~IH_RB_ENABLE;
2876         ih_cntl &= ~ENABLE_INTR;
2877         WREG32(IH_RB_CNTL, ih_rb_cntl);
2878         WREG32(IH_CNTL, ih_cntl);
2879         /* set rptr, wptr to 0 */
2880         WREG32(IH_RB_RPTR, 0);
2881         WREG32(IH_RB_WPTR, 0);
2882         rdev->ih.enabled = false;
2883         rdev->ih.wptr = 0;
2884         rdev->ih.rptr = 0;
2885 }
2886
2887 static void r600_disable_interrupt_state(struct radeon_device *rdev)
2888 {
2889         u32 tmp;
2890
2891         WREG32(CP_INT_CNTL, 0);
2892         WREG32(GRBM_INT_CNTL, 0);
2893         WREG32(DxMODE_INT_MASK, 0);
2894         if (ASIC_IS_DCE3(rdev)) {
2895                 WREG32(DCE3_DACA_AUTODETECT_INT_CONTROL, 0);
2896                 WREG32(DCE3_DACB_AUTODETECT_INT_CONTROL, 0);
2897                 tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2898                 WREG32(DC_HPD1_INT_CONTROL, tmp);
2899                 tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2900                 WREG32(DC_HPD2_INT_CONTROL, tmp);
2901                 tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2902                 WREG32(DC_HPD3_INT_CONTROL, tmp);
2903                 tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2904                 WREG32(DC_HPD4_INT_CONTROL, tmp);
2905                 if (ASIC_IS_DCE32(rdev)) {
2906                         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2907                         WREG32(DC_HPD5_INT_CONTROL, tmp);
2908                         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
2909                         WREG32(DC_HPD6_INT_CONTROL, tmp);
2910                 }
2911         } else {
2912                 WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
2913                 WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
2914                 tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2915                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
2916                 tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2917                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
2918                 tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & DC_HOT_PLUG_DETECTx_INT_POLARITY;
2919                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
2920         }
2921 }
2922
2923 int r600_irq_init(struct radeon_device *rdev)
2924 {
2925         int ret = 0;
2926         int rb_bufsz;
2927         u32 interrupt_cntl, ih_cntl, ih_rb_cntl;
2928
2929         /* allocate ring */
2930         ret = r600_ih_ring_alloc(rdev);
2931         if (ret)
2932                 return ret;
2933
2934         /* disable irqs */
2935         r600_disable_interrupts(rdev);
2936
2937         /* init rlc */
2938         ret = r600_rlc_init(rdev);
2939         if (ret) {
2940                 r600_ih_ring_fini(rdev);
2941                 return ret;
2942         }
2943
2944         /* setup interrupt control */
2945         /* set dummy read address to ring address */
2946         WREG32(INTERRUPT_CNTL2, rdev->ih.gpu_addr >> 8);
2947         interrupt_cntl = RREG32(INTERRUPT_CNTL);
2948         /* IH_DUMMY_RD_OVERRIDE=0 - dummy read disabled with msi, enabled without msi
2949          * IH_DUMMY_RD_OVERRIDE=1 - dummy read controlled by IH_DUMMY_RD_EN
2950          */
2951         interrupt_cntl &= ~IH_DUMMY_RD_OVERRIDE;
2952         /* IH_REQ_NONSNOOP_EN=1 if ring is in non-cacheable memory, e.g., vram */
2953         interrupt_cntl &= ~IH_REQ_NONSNOOP_EN;
2954         WREG32(INTERRUPT_CNTL, interrupt_cntl);
2955
2956         WREG32(IH_RB_BASE, rdev->ih.gpu_addr >> 8);
2957         rb_bufsz = drm_order(rdev->ih.ring_size / 4);
2958
2959         ih_rb_cntl = (IH_WPTR_OVERFLOW_ENABLE |
2960                       IH_WPTR_OVERFLOW_CLEAR |
2961                       (rb_bufsz << 1));
2962         /* WPTR writeback, not yet */
2963         /*ih_rb_cntl |= IH_WPTR_WRITEBACK_ENABLE;*/
2964         WREG32(IH_RB_WPTR_ADDR_LO, 0);
2965         WREG32(IH_RB_WPTR_ADDR_HI, 0);
2966
2967         WREG32(IH_RB_CNTL, ih_rb_cntl);
2968
2969         /* set rptr, wptr to 0 */
2970         WREG32(IH_RB_RPTR, 0);
2971         WREG32(IH_RB_WPTR, 0);
2972
2973         /* Default settings for IH_CNTL (disabled at first) */
2974         ih_cntl = MC_WRREQ_CREDIT(0x10) | MC_WR_CLEAN_CNT(0x10);
2975         /* RPTR_REARM only works if msi's are enabled */
2976         if (rdev->msi_enabled)
2977                 ih_cntl |= RPTR_REARM;
2978
2979 #ifdef __BIG_ENDIAN
2980         ih_cntl |= IH_MC_SWAP(IH_MC_SWAP_32BIT);
2981 #endif
2982         WREG32(IH_CNTL, ih_cntl);
2983
2984         /* force the active interrupt state to all disabled */
2985         if (rdev->family >= CHIP_CEDAR)
2986                 evergreen_disable_interrupt_state(rdev);
2987         else
2988                 r600_disable_interrupt_state(rdev);
2989
2990         /* enable irqs */
2991         r600_enable_interrupts(rdev);
2992
2993         return ret;
2994 }
2995
2996 void r600_irq_suspend(struct radeon_device *rdev)
2997 {
2998         r600_irq_disable(rdev);
2999         r600_rlc_stop(rdev);
3000 }
3001
3002 void r600_irq_fini(struct radeon_device *rdev)
3003 {
3004         r600_irq_suspend(rdev);
3005         r600_ih_ring_fini(rdev);
3006 }
3007
3008 int r600_irq_set(struct radeon_device *rdev)
3009 {
3010         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
3011         u32 mode_int = 0;
3012         u32 hpd1, hpd2, hpd3, hpd4 = 0, hpd5 = 0, hpd6 = 0;
3013         u32 grbm_int_cntl = 0;
3014         u32 hdmi1, hdmi2;
3015
3016         if (!rdev->irq.installed) {
3017                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
3018                 return -EINVAL;
3019         }
3020         /* don't enable anything if the ih is disabled */
3021         if (!rdev->ih.enabled) {
3022                 r600_disable_interrupts(rdev);
3023                 /* force the active interrupt state to all disabled */
3024                 r600_disable_interrupt_state(rdev);
3025                 return 0;
3026         }
3027
3028         hdmi1 = RREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3029         if (ASIC_IS_DCE3(rdev)) {
3030                 hdmi2 = RREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3031                 hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3032                 hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3033                 hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3034                 hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
3035                 if (ASIC_IS_DCE32(rdev)) {
3036                         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
3037                         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
3038                 }
3039         } else {
3040                 hdmi2 = RREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL) & ~R600_HDMI_INT_EN;
3041                 hpd1 = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL) & ~DC_HPDx_INT_EN;
3042                 hpd2 = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL) & ~DC_HPDx_INT_EN;
3043                 hpd3 = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL) & ~DC_HPDx_INT_EN;
3044         }
3045
3046         if (rdev->irq.sw_int) {
3047                 DRM_DEBUG("r600_irq_set: sw int\n");
3048                 cp_int_cntl |= RB_INT_ENABLE;
3049         }
3050         if (rdev->irq.crtc_vblank_int[0]) {
3051                 DRM_DEBUG("r600_irq_set: vblank 0\n");
3052                 mode_int |= D1MODE_VBLANK_INT_MASK;
3053         }
3054         if (rdev->irq.crtc_vblank_int[1]) {
3055                 DRM_DEBUG("r600_irq_set: vblank 1\n");
3056                 mode_int |= D2MODE_VBLANK_INT_MASK;
3057         }
3058         if (rdev->irq.hpd[0]) {
3059                 DRM_DEBUG("r600_irq_set: hpd 1\n");
3060                 hpd1 |= DC_HPDx_INT_EN;
3061         }
3062         if (rdev->irq.hpd[1]) {
3063                 DRM_DEBUG("r600_irq_set: hpd 2\n");
3064                 hpd2 |= DC_HPDx_INT_EN;
3065         }
3066         if (rdev->irq.hpd[2]) {
3067                 DRM_DEBUG("r600_irq_set: hpd 3\n");
3068                 hpd3 |= DC_HPDx_INT_EN;
3069         }
3070         if (rdev->irq.hpd[3]) {
3071                 DRM_DEBUG("r600_irq_set: hpd 4\n");
3072                 hpd4 |= DC_HPDx_INT_EN;
3073         }
3074         if (rdev->irq.hpd[4]) {
3075                 DRM_DEBUG("r600_irq_set: hpd 5\n");
3076                 hpd5 |= DC_HPDx_INT_EN;
3077         }
3078         if (rdev->irq.hpd[5]) {
3079                 DRM_DEBUG("r600_irq_set: hpd 6\n");
3080                 hpd6 |= DC_HPDx_INT_EN;
3081         }
3082         if (rdev->irq.hdmi[0]) {
3083                 DRM_DEBUG("r600_irq_set: hdmi 1\n");
3084                 hdmi1 |= R600_HDMI_INT_EN;
3085         }
3086         if (rdev->irq.hdmi[1]) {
3087                 DRM_DEBUG("r600_irq_set: hdmi 2\n");
3088                 hdmi2 |= R600_HDMI_INT_EN;
3089         }
3090         if (rdev->irq.gui_idle) {
3091                 DRM_DEBUG("gui idle\n");
3092                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
3093         }
3094
3095         WREG32(CP_INT_CNTL, cp_int_cntl);
3096         WREG32(DxMODE_INT_MASK, mode_int);
3097         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
3098         WREG32(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, hdmi1);
3099         if (ASIC_IS_DCE3(rdev)) {
3100                 WREG32(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, hdmi2);
3101                 WREG32(DC_HPD1_INT_CONTROL, hpd1);
3102                 WREG32(DC_HPD2_INT_CONTROL, hpd2);
3103                 WREG32(DC_HPD3_INT_CONTROL, hpd3);
3104                 WREG32(DC_HPD4_INT_CONTROL, hpd4);
3105                 if (ASIC_IS_DCE32(rdev)) {
3106                         WREG32(DC_HPD5_INT_CONTROL, hpd5);
3107                         WREG32(DC_HPD6_INT_CONTROL, hpd6);
3108                 }
3109         } else {
3110                 WREG32(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, hdmi2);
3111                 WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, hpd1);
3112                 WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, hpd2);
3113                 WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, hpd3);
3114         }
3115
3116         return 0;
3117 }
3118
3119 static inline void r600_irq_ack(struct radeon_device *rdev,
3120                                 u32 *disp_int,
3121                                 u32 *disp_int_cont,
3122                                 u32 *disp_int_cont2)
3123 {
3124         u32 tmp;
3125
3126         if (ASIC_IS_DCE3(rdev)) {
3127                 *disp_int = RREG32(DCE3_DISP_INTERRUPT_STATUS);
3128                 *disp_int_cont = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE);
3129                 *disp_int_cont2 = RREG32(DCE3_DISP_INTERRUPT_STATUS_CONTINUE2);
3130         } else {
3131                 *disp_int = RREG32(DISP_INTERRUPT_STATUS);
3132                 *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
3133                 *disp_int_cont2 = 0;
3134         }
3135
3136         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
3137                 WREG32(D1MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3138         if (*disp_int & LB_D1_VLINE_INTERRUPT)
3139                 WREG32(D1MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3140         if (*disp_int & LB_D2_VBLANK_INTERRUPT)
3141                 WREG32(D2MODE_VBLANK_STATUS, DxMODE_VBLANK_ACK);
3142         if (*disp_int & LB_D2_VLINE_INTERRUPT)
3143                 WREG32(D2MODE_VLINE_STATUS, DxMODE_VLINE_ACK);
3144         if (*disp_int & DC_HPD1_INTERRUPT) {
3145                 if (ASIC_IS_DCE3(rdev)) {
3146                         tmp = RREG32(DC_HPD1_INT_CONTROL);
3147                         tmp |= DC_HPDx_INT_ACK;
3148                         WREG32(DC_HPD1_INT_CONTROL, tmp);
3149                 } else {
3150                         tmp = RREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL);
3151                         tmp |= DC_HPDx_INT_ACK;
3152                         WREG32(DC_HOT_PLUG_DETECT1_INT_CONTROL, tmp);
3153                 }
3154         }
3155         if (*disp_int & DC_HPD2_INTERRUPT) {
3156                 if (ASIC_IS_DCE3(rdev)) {
3157                         tmp = RREG32(DC_HPD2_INT_CONTROL);
3158                         tmp |= DC_HPDx_INT_ACK;
3159                         WREG32(DC_HPD2_INT_CONTROL, tmp);
3160                 } else {
3161                         tmp = RREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL);
3162                         tmp |= DC_HPDx_INT_ACK;
3163                         WREG32(DC_HOT_PLUG_DETECT2_INT_CONTROL, tmp);
3164                 }
3165         }
3166         if (*disp_int_cont & DC_HPD3_INTERRUPT) {
3167                 if (ASIC_IS_DCE3(rdev)) {
3168                         tmp = RREG32(DC_HPD3_INT_CONTROL);
3169                         tmp |= DC_HPDx_INT_ACK;
3170                         WREG32(DC_HPD3_INT_CONTROL, tmp);
3171                 } else {
3172                         tmp = RREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL);
3173                         tmp |= DC_HPDx_INT_ACK;
3174                         WREG32(DC_HOT_PLUG_DETECT3_INT_CONTROL, tmp);
3175                 }
3176         }
3177         if (*disp_int_cont & DC_HPD4_INTERRUPT) {
3178                 tmp = RREG32(DC_HPD4_INT_CONTROL);
3179                 tmp |= DC_HPDx_INT_ACK;
3180                 WREG32(DC_HPD4_INT_CONTROL, tmp);
3181         }
3182         if (ASIC_IS_DCE32(rdev)) {
3183                 if (*disp_int_cont2 & DC_HPD5_INTERRUPT) {
3184                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3185                         tmp |= DC_HPDx_INT_ACK;
3186                         WREG32(DC_HPD5_INT_CONTROL, tmp);
3187                 }
3188                 if (*disp_int_cont2 & DC_HPD6_INTERRUPT) {
3189                         tmp = RREG32(DC_HPD5_INT_CONTROL);
3190                         tmp |= DC_HPDx_INT_ACK;
3191                         WREG32(DC_HPD6_INT_CONTROL, tmp);
3192                 }
3193         }
3194         if (RREG32(R600_HDMI_BLOCK1 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3195                 WREG32_P(R600_HDMI_BLOCK1 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3196         }
3197         if (ASIC_IS_DCE3(rdev)) {
3198                 if (RREG32(R600_HDMI_BLOCK3 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3199                         WREG32_P(R600_HDMI_BLOCK3 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3200                 }
3201         } else {
3202                 if (RREG32(R600_HDMI_BLOCK2 + R600_HDMI_STATUS) & R600_HDMI_INT_PENDING) {
3203                         WREG32_P(R600_HDMI_BLOCK2 + R600_HDMI_CNTL, R600_HDMI_INT_ACK, ~R600_HDMI_INT_ACK);
3204                 }
3205         }
3206 }
3207
3208 void r600_irq_disable(struct radeon_device *rdev)
3209 {
3210         u32 disp_int, disp_int_cont, disp_int_cont2;
3211
3212         r600_disable_interrupts(rdev);
3213         /* Wait and acknowledge irq */
3214         mdelay(1);
3215         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3216         r600_disable_interrupt_state(rdev);
3217 }
3218
3219 static inline u32 r600_get_ih_wptr(struct radeon_device *rdev)
3220 {
3221         u32 wptr, tmp;
3222
3223         /* XXX use writeback */
3224         wptr = RREG32(IH_RB_WPTR);
3225
3226         if (wptr & RB_OVERFLOW) {
3227                 /* When a ring buffer overflow happen start parsing interrupt
3228                  * from the last not overwritten vector (wptr + 16). Hopefully
3229                  * this should allow us to catchup.
3230                  */
3231                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
3232                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
3233                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
3234                 tmp = RREG32(IH_RB_CNTL);
3235                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
3236                 WREG32(IH_RB_CNTL, tmp);
3237         }
3238         return (wptr & rdev->ih.ptr_mask);
3239 }
3240
3241 /*        r600 IV Ring
3242  * Each IV ring entry is 128 bits:
3243  * [7:0]    - interrupt source id
3244  * [31:8]   - reserved
3245  * [59:32]  - interrupt source data
3246  * [127:60]  - reserved
3247  *
3248  * The basic interrupt vector entries
3249  * are decoded as follows:
3250  * src_id  src_data  description
3251  *      1         0  D1 Vblank
3252  *      1         1  D1 Vline
3253  *      5         0  D2 Vblank
3254  *      5         1  D2 Vline
3255  *     19         0  FP Hot plug detection A
3256  *     19         1  FP Hot plug detection B
3257  *     19         2  DAC A auto-detection
3258  *     19         3  DAC B auto-detection
3259  *     21         4  HDMI block A
3260  *     21         5  HDMI block B
3261  *    176         -  CP_INT RB
3262  *    177         -  CP_INT IB1
3263  *    178         -  CP_INT IB2
3264  *    181         -  EOP Interrupt
3265  *    233         -  GUI Idle
3266  *
3267  * Note, these are based on r600 and may need to be
3268  * adjusted or added to on newer asics
3269  */
3270
3271 int r600_irq_process(struct radeon_device *rdev)
3272 {
3273         u32 wptr = r600_get_ih_wptr(rdev);
3274         u32 rptr = rdev->ih.rptr;
3275         u32 src_id, src_data;
3276         u32 ring_index, disp_int, disp_int_cont, disp_int_cont2;
3277         unsigned long flags;
3278         bool queue_hotplug = false;
3279
3280         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
3281         if (!rdev->ih.enabled)
3282                 return IRQ_NONE;
3283
3284         spin_lock_irqsave(&rdev->ih.lock, flags);
3285
3286         if (rptr == wptr) {
3287                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3288                 return IRQ_NONE;
3289         }
3290         if (rdev->shutdown) {
3291                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
3292                 return IRQ_NONE;
3293         }
3294
3295 restart_ih:
3296         /* display interrupts */
3297         r600_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2);
3298
3299         rdev->ih.wptr = wptr;
3300         while (rptr != wptr) {
3301                 /* wptr/rptr are in bytes! */
3302                 ring_index = rptr / 4;
3303                 src_id =  rdev->ih.ring[ring_index] & 0xff;
3304                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
3305
3306                 switch (src_id) {
3307                 case 1: /* D1 vblank/vline */
3308                         switch (src_data) {
3309                         case 0: /* D1 vblank */
3310                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
3311                                         drm_handle_vblank(rdev->ddev, 0);
3312                                         rdev->pm.vblank_sync = true;
3313                                         wake_up(&rdev->irq.vblank_queue);
3314                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
3315                                         DRM_DEBUG("IH: D1 vblank\n");
3316                                 }
3317                                 break;
3318                         case 1: /* D1 vline */
3319                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
3320                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
3321                                         DRM_DEBUG("IH: D1 vline\n");
3322                                 }
3323                                 break;
3324                         default:
3325                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3326                                 break;
3327                         }
3328                         break;
3329                 case 5: /* D2 vblank/vline */
3330                         switch (src_data) {
3331                         case 0: /* D2 vblank */
3332                                 if (disp_int & LB_D2_VBLANK_INTERRUPT) {
3333                                         drm_handle_vblank(rdev->ddev, 1);
3334                                         rdev->pm.vblank_sync = true;
3335                                         wake_up(&rdev->irq.vblank_queue);
3336                                         disp_int &= ~LB_D2_VBLANK_INTERRUPT;
3337                                         DRM_DEBUG("IH: D2 vblank\n");
3338                                 }
3339                                 break;
3340                         case 1: /* D1 vline */
3341                                 if (disp_int & LB_D2_VLINE_INTERRUPT) {
3342                                         disp_int &= ~LB_D2_VLINE_INTERRUPT;
3343                                         DRM_DEBUG("IH: D2 vline\n");
3344                                 }
3345                                 break;
3346                         default:
3347                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3348                                 break;
3349                         }
3350                         break;
3351                 case 19: /* HPD/DAC hotplug */
3352                         switch (src_data) {
3353                         case 0:
3354                                 if (disp_int & DC_HPD1_INTERRUPT) {
3355                                         disp_int &= ~DC_HPD1_INTERRUPT;
3356                                         queue_hotplug = true;
3357                                         DRM_DEBUG("IH: HPD1\n");
3358                                 }
3359                                 break;
3360                         case 1:
3361                                 if (disp_int & DC_HPD2_INTERRUPT) {
3362                                         disp_int &= ~DC_HPD2_INTERRUPT;
3363                                         queue_hotplug = true;
3364                                         DRM_DEBUG("IH: HPD2\n");
3365                                 }
3366                                 break;
3367                         case 4:
3368                                 if (disp_int_cont & DC_HPD3_INTERRUPT) {
3369                                         disp_int_cont &= ~DC_HPD3_INTERRUPT;
3370                                         queue_hotplug = true;
3371                                         DRM_DEBUG("IH: HPD3\n");
3372                                 }
3373                                 break;
3374                         case 5:
3375                                 if (disp_int_cont & DC_HPD4_INTERRUPT) {
3376                                         disp_int_cont &= ~DC_HPD4_INTERRUPT;
3377                                         queue_hotplug = true;
3378                                         DRM_DEBUG("IH: HPD4\n");
3379                                 }
3380                                 break;
3381                         case 10:
3382                                 if (disp_int_cont2 & DC_HPD5_INTERRUPT) {
3383                                         disp_int_cont2 &= ~DC_HPD5_INTERRUPT;
3384                                         queue_hotplug = true;
3385                                         DRM_DEBUG("IH: HPD5\n");
3386                                 }
3387                                 break;
3388                         case 12:
3389                                 if (disp_int_cont2 & DC_HPD6_INTERRUPT) {
3390                                         disp_int_cont2 &= ~DC_HPD6_INTERRUPT;
3391                                         queue_hotplug = true;
3392                                         DRM_DEBUG("IH: HPD6\n");
3393                                 }
3394                                 break;
3395                         default:
3396                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3397                                 break;
3398                         }
3399                         break;
3400                 case 21: /* HDMI */
3401                         DRM_DEBUG("IH: HDMI: 0x%x\n", src_data);
3402                         r600_audio_schedule_polling(rdev);
3403                         break;
3404                 case 176: /* CP_INT in ring buffer */
3405                 case 177: /* CP_INT in IB1 */
3406                 case 178: /* CP_INT in IB2 */
3407                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
3408                         radeon_fence_process(rdev);
3409                         break;
3410                 case 181: /* CP EOP event */
3411                         DRM_DEBUG("IH: CP EOP\n");
3412                         break;
3413                 case 233: /* GUI IDLE */
3414                         DRM_DEBUG("IH: CP EOP\n");
3415                         rdev->pm.gui_idle = true;
3416                         wake_up(&rdev->irq.idle_queue);
3417                         break;
3418                 default:
3419                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
3420                         break;
3421                 }
3422
3423                 /* wptr/rptr are in bytes! */
3424                 rptr += 16;
3425                 rptr &= rdev->ih.ptr_mask;
3426         }
3427         /* make sure wptr hasn't changed while processing */
3428         wptr = r600_get_ih_wptr(rdev);
3429         if (wptr != rdev->ih.wptr)
3430                 goto restart_ih;
3431         if (queue_hotplug)
3432                 queue_work(rdev->wq, &rdev->hotplug_work);
3433         rdev->ih.rptr = rptr;
3434         WREG32(IH_RB_RPTR, rdev->ih.rptr);
3435         spin_unlock_irqrestore(&rdev->ih.lock, flags);
3436         return IRQ_HANDLED;
3437 }
3438
3439 /*
3440  * Debugfs info
3441  */
3442 #if defined(CONFIG_DEBUG_FS)
3443
3444 static int r600_debugfs_cp_ring_info(struct seq_file *m, void *data)
3445 {
3446         struct drm_info_node *node = (struct drm_info_node *) m->private;
3447         struct drm_device *dev = node->minor->dev;
3448         struct radeon_device *rdev = dev->dev_private;
3449         unsigned count, i, j;
3450
3451         radeon_ring_free_size(rdev);
3452         count = (rdev->cp.ring_size / 4) - rdev->cp.ring_free_dw;
3453         seq_printf(m, "CP_STAT 0x%08x\n", RREG32(CP_STAT));
3454         seq_printf(m, "CP_RB_WPTR 0x%08x\n", RREG32(CP_RB_WPTR));
3455         seq_printf(m, "CP_RB_RPTR 0x%08x\n", RREG32(CP_RB_RPTR));
3456         seq_printf(m, "driver's copy of the CP_RB_WPTR 0x%08x\n", rdev->cp.wptr);
3457         seq_printf(m, "driver's copy of the CP_RB_RPTR 0x%08x\n", rdev->cp.rptr);
3458         seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
3459         seq_printf(m, "%u dwords in ring\n", count);
3460         i = rdev->cp.rptr;
3461         for (j = 0; j <= count; j++) {
3462                 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
3463                 i = (i + 1) & rdev->cp.ptr_mask;
3464         }
3465         return 0;
3466 }
3467
3468 static int r600_debugfs_mc_info(struct seq_file *m, void *data)
3469 {
3470         struct drm_info_node *node = (struct drm_info_node *) m->private;
3471         struct drm_device *dev = node->minor->dev;
3472         struct radeon_device *rdev = dev->dev_private;
3473
3474         DREG32_SYS(m, rdev, R_000E50_SRBM_STATUS);
3475         DREG32_SYS(m, rdev, VM_L2_STATUS);
3476         return 0;
3477 }
3478
3479 static struct drm_info_list r600_mc_info_list[] = {
3480         {"r600_mc_info", r600_debugfs_mc_info, 0, NULL},
3481         {"r600_ring_info", r600_debugfs_cp_ring_info, 0, NULL},
3482 };
3483 #endif
3484
3485 int r600_debugfs_mc_info_init(struct radeon_device *rdev)
3486 {
3487 #if defined(CONFIG_DEBUG_FS)
3488         return radeon_debugfs_add_files(rdev, r600_mc_info_list, ARRAY_SIZE(r600_mc_info_list));
3489 #else
3490         return 0;
3491 #endif
3492 }
3493
3494 /**
3495  * r600_ioctl_wait_idle - flush host path cache on wait idle ioctl
3496  * rdev: radeon device structure
3497  * bo: buffer object struct which userspace is waiting for idle
3498  *
3499  * Some R6XX/R7XX doesn't seems to take into account HDP flush performed
3500  * through ring buffer, this leads to corruption in rendering, see
3501  * http://bugzilla.kernel.org/show_bug.cgi?id=15186 to avoid this we
3502  * directly perform HDP flush by writing register through MMIO.
3503  */
3504 void r600_ioctl_wait_idle(struct radeon_device *rdev, struct radeon_bo *bo)
3505 {
3506         WREG32(R_005480_HDP_MEM_COHERENCY_FLUSH_CNTL, 0x1);
3507 }