2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
28 #include <linux/seq_file.h>
29 #include <linux/slab.h>
32 #include "radeon_drm.h"
33 #include "radeon_reg.h"
40 #include <linux/firmware.h>
41 #include <linux/platform_device.h>
43 #include "r100_reg_safe.h"
44 #include "rn50_reg_safe.h"
47 #define FIRMWARE_R100 "radeon/R100_cp.bin"
48 #define FIRMWARE_R200 "radeon/R200_cp.bin"
49 #define FIRMWARE_R300 "radeon/R300_cp.bin"
50 #define FIRMWARE_R420 "radeon/R420_cp.bin"
51 #define FIRMWARE_RS690 "radeon/RS690_cp.bin"
52 #define FIRMWARE_RS600 "radeon/RS600_cp.bin"
53 #define FIRMWARE_R520 "radeon/R520_cp.bin"
55 MODULE_FIRMWARE(FIRMWARE_R100);
56 MODULE_FIRMWARE(FIRMWARE_R200);
57 MODULE_FIRMWARE(FIRMWARE_R300);
58 MODULE_FIRMWARE(FIRMWARE_R420);
59 MODULE_FIRMWARE(FIRMWARE_RS690);
60 MODULE_FIRMWARE(FIRMWARE_RS600);
61 MODULE_FIRMWARE(FIRMWARE_R520);
63 #include "r100_track.h"
65 /* This files gather functions specifics to:
66 * r100,rv100,rs100,rv200,rs200,r200,rv250,rs300,rv280
69 /* hpd for digital panel detect/disconnect */
70 bool r100_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
72 bool connected = false;
76 if (RREG32(RADEON_FP_GEN_CNTL) & RADEON_FP_DETECT_SENSE)
80 if (RREG32(RADEON_FP2_GEN_CNTL) & RADEON_FP2_DETECT_SENSE)
89 void r100_hpd_set_polarity(struct radeon_device *rdev,
90 enum radeon_hpd_id hpd)
93 bool connected = r100_hpd_sense(rdev, hpd);
97 tmp = RREG32(RADEON_FP_GEN_CNTL);
99 tmp &= ~RADEON_FP_DETECT_INT_POL;
101 tmp |= RADEON_FP_DETECT_INT_POL;
102 WREG32(RADEON_FP_GEN_CNTL, tmp);
105 tmp = RREG32(RADEON_FP2_GEN_CNTL);
107 tmp &= ~RADEON_FP2_DETECT_INT_POL;
109 tmp |= RADEON_FP2_DETECT_INT_POL;
110 WREG32(RADEON_FP2_GEN_CNTL, tmp);
117 void r100_hpd_init(struct radeon_device *rdev)
119 struct drm_device *dev = rdev->ddev;
120 struct drm_connector *connector;
122 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
123 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
124 switch (radeon_connector->hpd.hpd) {
126 rdev->irq.hpd[0] = true;
129 rdev->irq.hpd[1] = true;
135 if (rdev->irq.installed)
139 void r100_hpd_fini(struct radeon_device *rdev)
141 struct drm_device *dev = rdev->ddev;
142 struct drm_connector *connector;
144 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
145 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
146 switch (radeon_connector->hpd.hpd) {
148 rdev->irq.hpd[0] = false;
151 rdev->irq.hpd[1] = false;
162 void r100_pci_gart_tlb_flush(struct radeon_device *rdev)
164 /* TODO: can we do somethings here ? */
165 /* It seems hw only cache one entry so we should discard this
166 * entry otherwise if first GPU GART read hit this entry it
167 * could end up in wrong address. */
170 int r100_pci_gart_init(struct radeon_device *rdev)
174 if (rdev->gart.table.ram.ptr) {
175 WARN(1, "R100 PCI GART already initialized.\n");
178 /* Initialize common gart structure */
179 r = radeon_gart_init(rdev);
182 rdev->gart.table_size = rdev->gart.num_gpu_pages * 4;
183 rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush;
184 rdev->asic->gart_set_page = &r100_pci_gart_set_page;
185 return radeon_gart_table_ram_alloc(rdev);
188 /* required on r1xx, r2xx, r300, r(v)350, r420/r481, rs400/rs480 */
189 void r100_enable_bm(struct radeon_device *rdev)
192 /* Enable bus mastering */
193 tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS;
194 WREG32(RADEON_BUS_CNTL, tmp);
197 int r100_pci_gart_enable(struct radeon_device *rdev)
201 radeon_gart_restore(rdev);
202 /* discard memory request outside of configured range */
203 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
204 WREG32(RADEON_AIC_CNTL, tmp);
205 /* set address range for PCI address translate */
206 WREG32(RADEON_AIC_LO_ADDR, rdev->mc.gtt_start);
207 WREG32(RADEON_AIC_HI_ADDR, rdev->mc.gtt_end);
208 /* set PCI GART page-table base address */
209 WREG32(RADEON_AIC_PT_BASE, rdev->gart.table_addr);
210 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_PCIGART_TRANSLATE_EN;
211 WREG32(RADEON_AIC_CNTL, tmp);
212 r100_pci_gart_tlb_flush(rdev);
213 rdev->gart.ready = true;
217 void r100_pci_gart_disable(struct radeon_device *rdev)
221 /* discard memory request outside of configured range */
222 tmp = RREG32(RADEON_AIC_CNTL) | RADEON_DIS_OUT_OF_PCI_GART_ACCESS;
223 WREG32(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN);
224 WREG32(RADEON_AIC_LO_ADDR, 0);
225 WREG32(RADEON_AIC_HI_ADDR, 0);
228 int r100_pci_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr)
230 if (i < 0 || i > rdev->gart.num_gpu_pages) {
233 rdev->gart.table.ram.ptr[i] = cpu_to_le32(lower_32_bits(addr));
237 void r100_pci_gart_fini(struct radeon_device *rdev)
239 r100_pci_gart_disable(rdev);
240 radeon_gart_table_ram_free(rdev);
241 radeon_gart_fini(rdev);
244 int r100_irq_set(struct radeon_device *rdev)
248 if (!rdev->irq.installed) {
249 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
250 WREG32(R_000040_GEN_INT_CNTL, 0);
253 if (rdev->irq.sw_int) {
254 tmp |= RADEON_SW_INT_ENABLE;
256 if (rdev->irq.crtc_vblank_int[0]) {
257 tmp |= RADEON_CRTC_VBLANK_MASK;
259 if (rdev->irq.crtc_vblank_int[1]) {
260 tmp |= RADEON_CRTC2_VBLANK_MASK;
262 if (rdev->irq.hpd[0]) {
263 tmp |= RADEON_FP_DETECT_MASK;
265 if (rdev->irq.hpd[1]) {
266 tmp |= RADEON_FP2_DETECT_MASK;
268 WREG32(RADEON_GEN_INT_CNTL, tmp);
272 void r100_irq_disable(struct radeon_device *rdev)
276 WREG32(R_000040_GEN_INT_CNTL, 0);
277 /* Wait and acknowledge irq */
279 tmp = RREG32(R_000044_GEN_INT_STATUS);
280 WREG32(R_000044_GEN_INT_STATUS, tmp);
283 static inline uint32_t r100_irq_ack(struct radeon_device *rdev)
285 uint32_t irqs = RREG32(RADEON_GEN_INT_STATUS);
286 uint32_t irq_mask = RADEON_SW_INT_TEST |
287 RADEON_CRTC_VBLANK_STAT | RADEON_CRTC2_VBLANK_STAT |
288 RADEON_FP_DETECT_STAT | RADEON_FP2_DETECT_STAT;
291 WREG32(RADEON_GEN_INT_STATUS, irqs);
293 return irqs & irq_mask;
296 int r100_irq_process(struct radeon_device *rdev)
298 uint32_t status, msi_rearm;
299 bool queue_hotplug = false;
301 status = r100_irq_ack(rdev);
305 if (rdev->shutdown) {
310 if (status & RADEON_SW_INT_TEST) {
311 radeon_fence_process(rdev);
313 /* Vertical blank interrupts */
314 if (status & RADEON_CRTC_VBLANK_STAT) {
315 drm_handle_vblank(rdev->ddev, 0);
316 wake_up(&rdev->irq.vblank_queue);
318 if (status & RADEON_CRTC2_VBLANK_STAT) {
319 drm_handle_vblank(rdev->ddev, 1);
320 wake_up(&rdev->irq.vblank_queue);
322 if (status & RADEON_FP_DETECT_STAT) {
323 queue_hotplug = true;
326 if (status & RADEON_FP2_DETECT_STAT) {
327 queue_hotplug = true;
330 status = r100_irq_ack(rdev);
333 queue_work(rdev->wq, &rdev->hotplug_work);
334 if (rdev->msi_enabled) {
335 switch (rdev->family) {
338 msi_rearm = RREG32(RADEON_AIC_CNTL) & ~RS400_MSI_REARM;
339 WREG32(RADEON_AIC_CNTL, msi_rearm);
340 WREG32(RADEON_AIC_CNTL, msi_rearm | RS400_MSI_REARM);
343 msi_rearm = RREG32(RADEON_MSI_REARM_EN) & ~RV370_MSI_REARM_EN;
344 WREG32(RADEON_MSI_REARM_EN, msi_rearm);
345 WREG32(RADEON_MSI_REARM_EN, msi_rearm | RV370_MSI_REARM_EN);
352 u32 r100_get_vblank_counter(struct radeon_device *rdev, int crtc)
355 return RREG32(RADEON_CRTC_CRNT_FRAME);
357 return RREG32(RADEON_CRTC2_CRNT_FRAME);
360 /* Who ever call radeon_fence_emit should call ring_lock and ask
361 * for enough space (today caller are ib schedule and buffer move) */
362 void r100_fence_ring_emit(struct radeon_device *rdev,
363 struct radeon_fence *fence)
365 /* We have to make sure that caches are flushed before
366 * CPU might read something from VRAM. */
367 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_DSTCACHE_CTLSTAT, 0));
368 radeon_ring_write(rdev, RADEON_RB3D_DC_FLUSH_ALL);
369 radeon_ring_write(rdev, PACKET0(RADEON_RB3D_ZCACHE_CTLSTAT, 0));
370 radeon_ring_write(rdev, RADEON_RB3D_ZC_FLUSH_ALL);
371 /* Wait until IDLE & CLEAN */
372 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
373 radeon_ring_write(rdev, RADEON_WAIT_2D_IDLECLEAN | RADEON_WAIT_3D_IDLECLEAN);
374 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
375 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl |
376 RADEON_HDP_READ_BUFFER_INVALIDATE);
377 radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
378 radeon_ring_write(rdev, rdev->config.r100.hdp_cntl);
379 /* Emit fence sequence & fire IRQ */
380 radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
381 radeon_ring_write(rdev, fence->seq);
382 radeon_ring_write(rdev, PACKET0(RADEON_GEN_INT_STATUS, 0));
383 radeon_ring_write(rdev, RADEON_SW_INT_FIRE);
386 int r100_wb_init(struct radeon_device *rdev)
390 if (rdev->wb.wb_obj == NULL) {
391 r = radeon_bo_create(rdev, NULL, RADEON_GPU_PAGE_SIZE, true,
392 RADEON_GEM_DOMAIN_GTT,
395 dev_err(rdev->dev, "(%d) create WB buffer failed\n", r);
398 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
399 if (unlikely(r != 0))
401 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
404 dev_err(rdev->dev, "(%d) pin WB buffer failed\n", r);
405 radeon_bo_unreserve(rdev->wb.wb_obj);
408 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
409 radeon_bo_unreserve(rdev->wb.wb_obj);
411 dev_err(rdev->dev, "(%d) map WB buffer failed\n", r);
415 WREG32(R_000774_SCRATCH_ADDR, rdev->wb.gpu_addr);
416 WREG32(R_00070C_CP_RB_RPTR_ADDR,
417 S_00070C_RB_RPTR_ADDR((rdev->wb.gpu_addr + 1024) >> 2));
418 WREG32(R_000770_SCRATCH_UMSK, 0xff);
422 void r100_wb_disable(struct radeon_device *rdev)
424 WREG32(R_000770_SCRATCH_UMSK, 0);
427 void r100_wb_fini(struct radeon_device *rdev)
431 r100_wb_disable(rdev);
432 if (rdev->wb.wb_obj) {
433 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
434 if (unlikely(r != 0)) {
435 dev_err(rdev->dev, "(%d) can't finish WB\n", r);
438 radeon_bo_kunmap(rdev->wb.wb_obj);
439 radeon_bo_unpin(rdev->wb.wb_obj);
440 radeon_bo_unreserve(rdev->wb.wb_obj);
441 radeon_bo_unref(&rdev->wb.wb_obj);
443 rdev->wb.wb_obj = NULL;
447 int r100_copy_blit(struct radeon_device *rdev,
451 struct radeon_fence *fence)
454 uint32_t stride_bytes = PAGE_SIZE;
456 uint32_t stride_pixels;
461 /* radeon limited to 16k stride */
462 stride_bytes &= 0x3fff;
463 /* radeon pitch is /64 */
464 pitch = stride_bytes / 64;
465 stride_pixels = stride_bytes / 4;
466 num_loops = DIV_ROUND_UP(num_pages, 8191);
468 /* Ask for enough room for blit + flush + fence */
469 ndw = 64 + (10 * num_loops);
470 r = radeon_ring_lock(rdev, ndw);
472 DRM_ERROR("radeon: moving bo (%d) asking for %u dw.\n", r, ndw);
475 while (num_pages > 0) {
476 cur_pages = num_pages;
477 if (cur_pages > 8191) {
480 num_pages -= cur_pages;
482 /* pages are in Y direction - height
483 page width in X direction - width */
484 radeon_ring_write(rdev, PACKET3(PACKET3_BITBLT_MULTI, 8));
485 radeon_ring_write(rdev,
486 RADEON_GMC_SRC_PITCH_OFFSET_CNTL |
487 RADEON_GMC_DST_PITCH_OFFSET_CNTL |
488 RADEON_GMC_SRC_CLIPPING |
489 RADEON_GMC_DST_CLIPPING |
490 RADEON_GMC_BRUSH_NONE |
491 (RADEON_COLOR_FORMAT_ARGB8888 << 8) |
492 RADEON_GMC_SRC_DATATYPE_COLOR |
494 RADEON_DP_SRC_SOURCE_MEMORY |
495 RADEON_GMC_CLR_CMP_CNTL_DIS |
496 RADEON_GMC_WR_MSK_DIS);
497 radeon_ring_write(rdev, (pitch << 22) | (src_offset >> 10));
498 radeon_ring_write(rdev, (pitch << 22) | (dst_offset >> 10));
499 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
500 radeon_ring_write(rdev, 0);
501 radeon_ring_write(rdev, (0x1fff) | (0x1fff << 16));
502 radeon_ring_write(rdev, num_pages);
503 radeon_ring_write(rdev, num_pages);
504 radeon_ring_write(rdev, cur_pages | (stride_pixels << 16));
506 radeon_ring_write(rdev, PACKET0(RADEON_DSTCACHE_CTLSTAT, 0));
507 radeon_ring_write(rdev, RADEON_RB2D_DC_FLUSH_ALL);
508 radeon_ring_write(rdev, PACKET0(RADEON_WAIT_UNTIL, 0));
509 radeon_ring_write(rdev,
510 RADEON_WAIT_2D_IDLECLEAN |
511 RADEON_WAIT_HOST_IDLECLEAN |
512 RADEON_WAIT_DMA_GUI_IDLE);
514 r = radeon_fence_emit(rdev, fence);
516 radeon_ring_unlock_commit(rdev);
520 static int r100_cp_wait_for_idle(struct radeon_device *rdev)
525 for (i = 0; i < rdev->usec_timeout; i++) {
526 tmp = RREG32(R_000E40_RBBM_STATUS);
527 if (!G_000E40_CP_CMDSTRM_BUSY(tmp)) {
535 void r100_ring_start(struct radeon_device *rdev)
539 r = radeon_ring_lock(rdev, 2);
543 radeon_ring_write(rdev, PACKET0(RADEON_ISYNC_CNTL, 0));
544 radeon_ring_write(rdev,
545 RADEON_ISYNC_ANY2D_IDLE3D |
546 RADEON_ISYNC_ANY3D_IDLE2D |
547 RADEON_ISYNC_WAIT_IDLEGUI |
548 RADEON_ISYNC_CPSCRATCH_IDLEGUI);
549 radeon_ring_unlock_commit(rdev);
553 /* Load the microcode for the CP */
554 static int r100_cp_init_microcode(struct radeon_device *rdev)
556 struct platform_device *pdev;
557 const char *fw_name = NULL;
562 pdev = platform_device_register_simple("radeon_cp", 0, NULL, 0);
565 printk(KERN_ERR "radeon_cp: Failed to register firmware\n");
568 if ((rdev->family == CHIP_R100) || (rdev->family == CHIP_RV100) ||
569 (rdev->family == CHIP_RV200) || (rdev->family == CHIP_RS100) ||
570 (rdev->family == CHIP_RS200)) {
571 DRM_INFO("Loading R100 Microcode\n");
572 fw_name = FIRMWARE_R100;
573 } else if ((rdev->family == CHIP_R200) ||
574 (rdev->family == CHIP_RV250) ||
575 (rdev->family == CHIP_RV280) ||
576 (rdev->family == CHIP_RS300)) {
577 DRM_INFO("Loading R200 Microcode\n");
578 fw_name = FIRMWARE_R200;
579 } else if ((rdev->family == CHIP_R300) ||
580 (rdev->family == CHIP_R350) ||
581 (rdev->family == CHIP_RV350) ||
582 (rdev->family == CHIP_RV380) ||
583 (rdev->family == CHIP_RS400) ||
584 (rdev->family == CHIP_RS480)) {
585 DRM_INFO("Loading R300 Microcode\n");
586 fw_name = FIRMWARE_R300;
587 } else if ((rdev->family == CHIP_R420) ||
588 (rdev->family == CHIP_R423) ||
589 (rdev->family == CHIP_RV410)) {
590 DRM_INFO("Loading R400 Microcode\n");
591 fw_name = FIRMWARE_R420;
592 } else if ((rdev->family == CHIP_RS690) ||
593 (rdev->family == CHIP_RS740)) {
594 DRM_INFO("Loading RS690/RS740 Microcode\n");
595 fw_name = FIRMWARE_RS690;
596 } else if (rdev->family == CHIP_RS600) {
597 DRM_INFO("Loading RS600 Microcode\n");
598 fw_name = FIRMWARE_RS600;
599 } else if ((rdev->family == CHIP_RV515) ||
600 (rdev->family == CHIP_R520) ||
601 (rdev->family == CHIP_RV530) ||
602 (rdev->family == CHIP_R580) ||
603 (rdev->family == CHIP_RV560) ||
604 (rdev->family == CHIP_RV570)) {
605 DRM_INFO("Loading R500 Microcode\n");
606 fw_name = FIRMWARE_R520;
609 err = request_firmware(&rdev->me_fw, fw_name, &pdev->dev);
610 platform_device_unregister(pdev);
612 printk(KERN_ERR "radeon_cp: Failed to load firmware \"%s\"\n",
614 } else if (rdev->me_fw->size % 8) {
616 "radeon_cp: Bogus length %zu in firmware \"%s\"\n",
617 rdev->me_fw->size, fw_name);
619 release_firmware(rdev->me_fw);
625 static void r100_cp_load_microcode(struct radeon_device *rdev)
627 const __be32 *fw_data;
630 if (r100_gui_wait_for_idle(rdev)) {
631 printk(KERN_WARNING "Failed to wait GUI idle while "
632 "programming pipes. Bad things might happen.\n");
636 size = rdev->me_fw->size / 4;
637 fw_data = (const __be32 *)&rdev->me_fw->data[0];
638 WREG32(RADEON_CP_ME_RAM_ADDR, 0);
639 for (i = 0; i < size; i += 2) {
640 WREG32(RADEON_CP_ME_RAM_DATAH,
641 be32_to_cpup(&fw_data[i]));
642 WREG32(RADEON_CP_ME_RAM_DATAL,
643 be32_to_cpup(&fw_data[i + 1]));
648 int r100_cp_init(struct radeon_device *rdev, unsigned ring_size)
653 unsigned pre_write_timer;
654 unsigned pre_write_limit;
655 unsigned indirect2_start;
656 unsigned indirect1_start;
660 if (r100_debugfs_cp_init(rdev)) {
661 DRM_ERROR("Failed to register debugfs file for CP !\n");
664 tmp = RREG32(RADEON_CP_CSQ_STAT);
665 if ((tmp & (1 << 31))) {
666 DRM_INFO("radeon: cp busy (0x%08X) resetting\n", tmp);
667 WREG32(RADEON_CP_CSQ_MODE, 0);
668 WREG32(RADEON_CP_CSQ_CNTL, 0);
669 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
670 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
672 WREG32(RADEON_RBBM_SOFT_RESET, 0);
673 tmp = RREG32(RADEON_RBBM_SOFT_RESET);
675 tmp = RREG32(RADEON_CP_CSQ_STAT);
676 if ((tmp & (1 << 31))) {
677 DRM_INFO("radeon: cp reset failed (0x%08X)\n", tmp);
680 DRM_INFO("radeon: cp idle (0x%08X)\n", tmp);
684 r = r100_cp_init_microcode(rdev);
686 DRM_ERROR("Failed to load firmware!\n");
691 /* Align ring size */
692 rb_bufsz = drm_order(ring_size / 8);
693 ring_size = (1 << (rb_bufsz + 1)) * 4;
694 r100_cp_load_microcode(rdev);
695 r = radeon_ring_init(rdev, ring_size);
699 /* Each time the cp read 1024 bytes (16 dword/quadword) update
700 * the rptr copy in system ram */
702 /* cp will read 128bytes at a time (4 dwords) */
704 rdev->cp.align_mask = 16 - 1;
705 /* Write to CP_RB_WPTR will be delayed for pre_write_timer clocks */
706 pre_write_timer = 64;
707 /* Force CP_RB_WPTR write if written more than one time before the
711 /* Setup the cp cache like this (cache size is 96 dwords) :
715 * So ring cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
716 * indirect1 cache size is 64dwords (> (2 * max_fetch = 2 * 4dwords))
717 * indirect2 cache size is 16dwords (> (2 * max_fetch = 2 * 4dwords))
718 * Idea being that most of the gpu cmd will be through indirect1 buffer
719 * so it gets the bigger cache.
721 indirect2_start = 80;
722 indirect1_start = 16;
724 WREG32(0x718, pre_write_timer | (pre_write_limit << 28));
725 tmp = (REG_SET(RADEON_RB_BUFSZ, rb_bufsz) |
726 REG_SET(RADEON_RB_BLKSZ, rb_blksz) |
727 REG_SET(RADEON_MAX_FETCH, max_fetch) |
728 RADEON_RB_NO_UPDATE);
730 tmp |= RADEON_BUF_SWAP_32BIT;
732 WREG32(RADEON_CP_RB_CNTL, tmp);
734 /* Set ring address */
735 DRM_INFO("radeon: ring at 0x%016lX\n", (unsigned long)rdev->cp.gpu_addr);
736 WREG32(RADEON_CP_RB_BASE, rdev->cp.gpu_addr);
737 /* Force read & write ptr to 0 */
738 WREG32(RADEON_CP_RB_CNTL, tmp | RADEON_RB_RPTR_WR_ENA);
739 WREG32(RADEON_CP_RB_RPTR_WR, 0);
740 WREG32(RADEON_CP_RB_WPTR, 0);
741 WREG32(RADEON_CP_RB_CNTL, tmp);
743 rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR);
744 rdev->cp.wptr = RREG32(RADEON_CP_RB_WPTR);
745 /* Set cp mode to bus mastering & enable cp*/
746 WREG32(RADEON_CP_CSQ_MODE,
747 REG_SET(RADEON_INDIRECT2_START, indirect2_start) |
748 REG_SET(RADEON_INDIRECT1_START, indirect1_start));
750 WREG32(0x744, 0x00004D4D);
751 WREG32(RADEON_CP_CSQ_CNTL, RADEON_CSQ_PRIBM_INDBM);
752 radeon_ring_start(rdev);
753 r = radeon_ring_test(rdev);
755 DRM_ERROR("radeon: cp isn't working (%d).\n", r);
758 rdev->cp.ready = true;
762 void r100_cp_fini(struct radeon_device *rdev)
764 if (r100_cp_wait_for_idle(rdev)) {
765 DRM_ERROR("Wait for CP idle timeout, shutting down CP.\n");
768 r100_cp_disable(rdev);
769 radeon_ring_fini(rdev);
770 DRM_INFO("radeon: cp finalized\n");
773 void r100_cp_disable(struct radeon_device *rdev)
776 rdev->cp.ready = false;
777 WREG32(RADEON_CP_CSQ_MODE, 0);
778 WREG32(RADEON_CP_CSQ_CNTL, 0);
779 if (r100_gui_wait_for_idle(rdev)) {
780 printk(KERN_WARNING "Failed to wait GUI idle while "
781 "programming pipes. Bad things might happen.\n");
785 int r100_cp_reset(struct radeon_device *rdev)
791 reinit_cp = rdev->cp.ready;
792 rdev->cp.ready = false;
793 WREG32(RADEON_CP_CSQ_MODE, 0);
794 WREG32(RADEON_CP_CSQ_CNTL, 0);
795 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_CP);
796 (void)RREG32(RADEON_RBBM_SOFT_RESET);
798 WREG32(RADEON_RBBM_SOFT_RESET, 0);
799 /* Wait to prevent race in RBBM_STATUS */
801 for (i = 0; i < rdev->usec_timeout; i++) {
802 tmp = RREG32(RADEON_RBBM_STATUS);
803 if (!(tmp & (1 << 16))) {
804 DRM_INFO("CP reset succeed (RBBM_STATUS=0x%08X)\n",
807 return r100_cp_init(rdev, rdev->cp.ring_size);
813 tmp = RREG32(RADEON_RBBM_STATUS);
814 DRM_ERROR("Failed to reset CP (RBBM_STATUS=0x%08X)!\n", tmp);
818 void r100_cp_commit(struct radeon_device *rdev)
820 WREG32(RADEON_CP_RB_WPTR, rdev->cp.wptr);
821 (void)RREG32(RADEON_CP_RB_WPTR);
828 int r100_cs_parse_packet0(struct radeon_cs_parser *p,
829 struct radeon_cs_packet *pkt,
830 const unsigned *auth, unsigned n,
831 radeon_packet0_check_t check)
840 /* Check that register fall into register range
841 * determined by the number of entry (n) in the
842 * safe register bitmap.
844 if (pkt->one_reg_wr) {
845 if ((reg >> 7) > n) {
849 if (((reg + (pkt->count << 2)) >> 7) > n) {
853 for (i = 0; i <= pkt->count; i++, idx++) {
855 m = 1 << ((reg >> 2) & 31);
857 r = check(p, pkt, idx, reg);
862 if (pkt->one_reg_wr) {
863 if (!(auth[j] & m)) {
873 void r100_cs_dump_packet(struct radeon_cs_parser *p,
874 struct radeon_cs_packet *pkt)
876 volatile uint32_t *ib;
882 for (i = 0; i <= (pkt->count + 1); i++, idx++) {
883 DRM_INFO("ib[%d]=0x%08X\n", idx, ib[idx]);
888 * r100_cs_packet_parse() - parse cp packet and point ib index to next packet
889 * @parser: parser structure holding parsing context.
890 * @pkt: where to store packet informations
892 * Assume that chunk_ib_index is properly set. Will return -EINVAL
893 * if packet is bigger than remaining ib size. or if packets is unknown.
895 int r100_cs_packet_parse(struct radeon_cs_parser *p,
896 struct radeon_cs_packet *pkt,
899 struct radeon_cs_chunk *ib_chunk = &p->chunks[p->chunk_ib_idx];
902 if (idx >= ib_chunk->length_dw) {
903 DRM_ERROR("Can not parse packet at %d after CS end %d !\n",
904 idx, ib_chunk->length_dw);
907 header = radeon_get_ib_value(p, idx);
909 pkt->type = CP_PACKET_GET_TYPE(header);
910 pkt->count = CP_PACKET_GET_COUNT(header);
913 pkt->reg = CP_PACKET0_GET_REG(header);
914 pkt->one_reg_wr = CP_PACKET0_GET_ONE_REG_WR(header);
917 pkt->opcode = CP_PACKET3_GET_OPCODE(header);
923 DRM_ERROR("Unknown packet type %d at %d !\n", pkt->type, idx);
926 if ((pkt->count + 1 + pkt->idx) >= ib_chunk->length_dw) {
927 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n",
928 pkt->idx, pkt->type, pkt->count, ib_chunk->length_dw);
935 * r100_cs_packet_next_vline() - parse userspace VLINE packet
936 * @parser: parser structure holding parsing context.
938 * Userspace sends a special sequence for VLINE waits.
939 * PACKET0 - VLINE_START_END + value
940 * PACKET0 - WAIT_UNTIL +_value
941 * RELOC (P3) - crtc_id in reloc.
943 * This function parses this and relocates the VLINE START END
944 * and WAIT UNTIL packets to the correct crtc.
945 * It also detects a switched off crtc and nulls out the
948 int r100_cs_packet_parse_vline(struct radeon_cs_parser *p)
950 struct drm_mode_object *obj;
951 struct drm_crtc *crtc;
952 struct radeon_crtc *radeon_crtc;
953 struct radeon_cs_packet p3reloc, waitreloc;
956 uint32_t header, h_idx, reg;
957 volatile uint32_t *ib;
961 /* parse the wait until */
962 r = r100_cs_packet_parse(p, &waitreloc, p->idx);
966 /* check its a wait until and only 1 count */
967 if (waitreloc.reg != RADEON_WAIT_UNTIL ||
968 waitreloc.count != 0) {
969 DRM_ERROR("vline wait had illegal wait until segment\n");
974 if (radeon_get_ib_value(p, waitreloc.idx + 1) != RADEON_WAIT_CRTC_VLINE) {
975 DRM_ERROR("vline wait had illegal wait until\n");
980 /* jump over the NOP */
981 r = r100_cs_packet_parse(p, &p3reloc, p->idx + waitreloc.count + 2);
986 p->idx += waitreloc.count + 2;
987 p->idx += p3reloc.count + 2;
989 header = radeon_get_ib_value(p, h_idx);
990 crtc_id = radeon_get_ib_value(p, h_idx + 5);
991 reg = CP_PACKET0_GET_REG(header);
992 mutex_lock(&p->rdev->ddev->mode_config.mutex);
993 obj = drm_mode_object_find(p->rdev->ddev, crtc_id, DRM_MODE_OBJECT_CRTC);
995 DRM_ERROR("cannot find crtc %d\n", crtc_id);
999 crtc = obj_to_crtc(obj);
1000 radeon_crtc = to_radeon_crtc(crtc);
1001 crtc_id = radeon_crtc->crtc_id;
1003 if (!crtc->enabled) {
1004 /* if the CRTC isn't enabled - we need to nop out the wait until */
1005 ib[h_idx + 2] = PACKET2(0);
1006 ib[h_idx + 3] = PACKET2(0);
1007 } else if (crtc_id == 1) {
1009 case AVIVO_D1MODE_VLINE_START_END:
1010 header &= ~R300_CP_PACKET0_REG_MASK;
1011 header |= AVIVO_D2MODE_VLINE_START_END >> 2;
1013 case RADEON_CRTC_GUI_TRIG_VLINE:
1014 header &= ~R300_CP_PACKET0_REG_MASK;
1015 header |= RADEON_CRTC2_GUI_TRIG_VLINE >> 2;
1018 DRM_ERROR("unknown crtc reloc\n");
1023 ib[h_idx + 3] |= RADEON_ENG_DISPLAY_SELECT_CRTC1;
1026 mutex_unlock(&p->rdev->ddev->mode_config.mutex);
1031 * r100_cs_packet_next_reloc() - parse next packet which should be reloc packet3
1032 * @parser: parser structure holding parsing context.
1033 * @data: pointer to relocation data
1034 * @offset_start: starting offset
1035 * @offset_mask: offset mask (to align start offset on)
1036 * @reloc: reloc informations
1038 * Check next packet is relocation packet3, do bo validation and compute
1039 * GPU offset using the provided start.
1041 int r100_cs_packet_next_reloc(struct radeon_cs_parser *p,
1042 struct radeon_cs_reloc **cs_reloc)
1044 struct radeon_cs_chunk *relocs_chunk;
1045 struct radeon_cs_packet p3reloc;
1049 if (p->chunk_relocs_idx == -1) {
1050 DRM_ERROR("No relocation chunk !\n");
1054 relocs_chunk = &p->chunks[p->chunk_relocs_idx];
1055 r = r100_cs_packet_parse(p, &p3reloc, p->idx);
1059 p->idx += p3reloc.count + 2;
1060 if (p3reloc.type != PACKET_TYPE3 || p3reloc.opcode != PACKET3_NOP) {
1061 DRM_ERROR("No packet3 for relocation for packet at %d.\n",
1063 r100_cs_dump_packet(p, &p3reloc);
1066 idx = radeon_get_ib_value(p, p3reloc.idx + 1);
1067 if (idx >= relocs_chunk->length_dw) {
1068 DRM_ERROR("Relocs at %d after relocations chunk end %d !\n",
1069 idx, relocs_chunk->length_dw);
1070 r100_cs_dump_packet(p, &p3reloc);
1073 /* FIXME: we assume reloc size is 4 dwords */
1074 *cs_reloc = p->relocs_ptr[(idx / 4)];
1078 static int r100_get_vtx_size(uint32_t vtx_fmt)
1082 /* ordered according to bits in spec */
1083 if (vtx_fmt & RADEON_SE_VTX_FMT_W0)
1085 if (vtx_fmt & RADEON_SE_VTX_FMT_FPCOLOR)
1087 if (vtx_fmt & RADEON_SE_VTX_FMT_FPALPHA)
1089 if (vtx_fmt & RADEON_SE_VTX_FMT_PKCOLOR)
1091 if (vtx_fmt & RADEON_SE_VTX_FMT_FPSPEC)
1093 if (vtx_fmt & RADEON_SE_VTX_FMT_FPFOG)
1095 if (vtx_fmt & RADEON_SE_VTX_FMT_PKSPEC)
1097 if (vtx_fmt & RADEON_SE_VTX_FMT_ST0)
1099 if (vtx_fmt & RADEON_SE_VTX_FMT_ST1)
1101 if (vtx_fmt & RADEON_SE_VTX_FMT_Q1)
1103 if (vtx_fmt & RADEON_SE_VTX_FMT_ST2)
1105 if (vtx_fmt & RADEON_SE_VTX_FMT_Q2)
1107 if (vtx_fmt & RADEON_SE_VTX_FMT_ST3)
1109 if (vtx_fmt & RADEON_SE_VTX_FMT_Q3)
1111 if (vtx_fmt & RADEON_SE_VTX_FMT_Q0)
1114 if (vtx_fmt & (0x7 << 15))
1115 vtx_size += (vtx_fmt >> 15) & 0x7;
1116 if (vtx_fmt & RADEON_SE_VTX_FMT_N0)
1118 if (vtx_fmt & RADEON_SE_VTX_FMT_XY1)
1120 if (vtx_fmt & RADEON_SE_VTX_FMT_Z1)
1122 if (vtx_fmt & RADEON_SE_VTX_FMT_W1)
1124 if (vtx_fmt & RADEON_SE_VTX_FMT_N1)
1126 if (vtx_fmt & RADEON_SE_VTX_FMT_Z)
1131 static int r100_packet0_check(struct radeon_cs_parser *p,
1132 struct radeon_cs_packet *pkt,
1133 unsigned idx, unsigned reg)
1135 struct radeon_cs_reloc *reloc;
1136 struct r100_cs_track *track;
1137 volatile uint32_t *ib;
1145 track = (struct r100_cs_track *)p->track;
1147 idx_value = radeon_get_ib_value(p, idx);
1150 case RADEON_CRTC_GUI_TRIG_VLINE:
1151 r = r100_cs_packet_parse_vline(p);
1153 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1155 r100_cs_dump_packet(p, pkt);
1159 /* FIXME: only allow PACKET3 blit? easier to check for out of
1161 case RADEON_DST_PITCH_OFFSET:
1162 case RADEON_SRC_PITCH_OFFSET:
1163 r = r100_reloc_pitch_offset(p, pkt, idx, reg);
1167 case RADEON_RB3D_DEPTHOFFSET:
1168 r = r100_cs_packet_next_reloc(p, &reloc);
1170 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1172 r100_cs_dump_packet(p, pkt);
1175 track->zb.robj = reloc->robj;
1176 track->zb.offset = idx_value;
1177 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1179 case RADEON_RB3D_COLOROFFSET:
1180 r = r100_cs_packet_next_reloc(p, &reloc);
1182 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1184 r100_cs_dump_packet(p, pkt);
1187 track->cb[0].robj = reloc->robj;
1188 track->cb[0].offset = idx_value;
1189 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1191 case RADEON_PP_TXOFFSET_0:
1192 case RADEON_PP_TXOFFSET_1:
1193 case RADEON_PP_TXOFFSET_2:
1194 i = (reg - RADEON_PP_TXOFFSET_0) / 24;
1195 r = r100_cs_packet_next_reloc(p, &reloc);
1197 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1199 r100_cs_dump_packet(p, pkt);
1202 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1203 track->textures[i].robj = reloc->robj;
1205 case RADEON_PP_CUBIC_OFFSET_T0_0:
1206 case RADEON_PP_CUBIC_OFFSET_T0_1:
1207 case RADEON_PP_CUBIC_OFFSET_T0_2:
1208 case RADEON_PP_CUBIC_OFFSET_T0_3:
1209 case RADEON_PP_CUBIC_OFFSET_T0_4:
1210 i = (reg - RADEON_PP_CUBIC_OFFSET_T0_0) / 4;
1211 r = r100_cs_packet_next_reloc(p, &reloc);
1213 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1215 r100_cs_dump_packet(p, pkt);
1218 track->textures[0].cube_info[i].offset = idx_value;
1219 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1220 track->textures[0].cube_info[i].robj = reloc->robj;
1222 case RADEON_PP_CUBIC_OFFSET_T1_0:
1223 case RADEON_PP_CUBIC_OFFSET_T1_1:
1224 case RADEON_PP_CUBIC_OFFSET_T1_2:
1225 case RADEON_PP_CUBIC_OFFSET_T1_3:
1226 case RADEON_PP_CUBIC_OFFSET_T1_4:
1227 i = (reg - RADEON_PP_CUBIC_OFFSET_T1_0) / 4;
1228 r = r100_cs_packet_next_reloc(p, &reloc);
1230 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1232 r100_cs_dump_packet(p, pkt);
1235 track->textures[1].cube_info[i].offset = idx_value;
1236 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1237 track->textures[1].cube_info[i].robj = reloc->robj;
1239 case RADEON_PP_CUBIC_OFFSET_T2_0:
1240 case RADEON_PP_CUBIC_OFFSET_T2_1:
1241 case RADEON_PP_CUBIC_OFFSET_T2_2:
1242 case RADEON_PP_CUBIC_OFFSET_T2_3:
1243 case RADEON_PP_CUBIC_OFFSET_T2_4:
1244 i = (reg - RADEON_PP_CUBIC_OFFSET_T2_0) / 4;
1245 r = r100_cs_packet_next_reloc(p, &reloc);
1247 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1249 r100_cs_dump_packet(p, pkt);
1252 track->textures[2].cube_info[i].offset = idx_value;
1253 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1254 track->textures[2].cube_info[i].robj = reloc->robj;
1256 case RADEON_RE_WIDTH_HEIGHT:
1257 track->maxy = ((idx_value >> 16) & 0x7FF);
1259 case RADEON_RB3D_COLORPITCH:
1260 r = r100_cs_packet_next_reloc(p, &reloc);
1262 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1264 r100_cs_dump_packet(p, pkt);
1268 if (reloc->lobj.tiling_flags & RADEON_TILING_MACRO)
1269 tile_flags |= RADEON_COLOR_TILE_ENABLE;
1270 if (reloc->lobj.tiling_flags & RADEON_TILING_MICRO)
1271 tile_flags |= RADEON_COLOR_MICROTILE_ENABLE;
1273 tmp = idx_value & ~(0x7 << 16);
1277 track->cb[0].pitch = idx_value & RADEON_COLORPITCH_MASK;
1279 case RADEON_RB3D_DEPTHPITCH:
1280 track->zb.pitch = idx_value & RADEON_DEPTHPITCH_MASK;
1282 case RADEON_RB3D_CNTL:
1283 switch ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f) {
1289 track->cb[0].cpp = 1;
1294 track->cb[0].cpp = 2;
1297 track->cb[0].cpp = 4;
1300 DRM_ERROR("Invalid color buffer format (%d) !\n",
1301 ((idx_value >> RADEON_RB3D_COLOR_FORMAT_SHIFT) & 0x1f));
1304 track->z_enabled = !!(idx_value & RADEON_Z_ENABLE);
1306 case RADEON_RB3D_ZSTENCILCNTL:
1307 switch (idx_value & 0xf) {
1323 case RADEON_RB3D_ZPASS_ADDR:
1324 r = r100_cs_packet_next_reloc(p, &reloc);
1326 DRM_ERROR("No reloc for ib[%d]=0x%04X\n",
1328 r100_cs_dump_packet(p, pkt);
1331 ib[idx] = idx_value + ((u32)reloc->lobj.gpu_offset);
1333 case RADEON_PP_CNTL:
1335 uint32_t temp = idx_value >> 4;
1336 for (i = 0; i < track->num_texture; i++)
1337 track->textures[i].enabled = !!(temp & (1 << i));
1340 case RADEON_SE_VF_CNTL:
1341 track->vap_vf_cntl = idx_value;
1343 case RADEON_SE_VTX_FMT:
1344 track->vtx_size = r100_get_vtx_size(idx_value);
1346 case RADEON_PP_TEX_SIZE_0:
1347 case RADEON_PP_TEX_SIZE_1:
1348 case RADEON_PP_TEX_SIZE_2:
1349 i = (reg - RADEON_PP_TEX_SIZE_0) / 8;
1350 track->textures[i].width = (idx_value & RADEON_TEX_USIZE_MASK) + 1;
1351 track->textures[i].height = ((idx_value & RADEON_TEX_VSIZE_MASK) >> RADEON_TEX_VSIZE_SHIFT) + 1;
1353 case RADEON_PP_TEX_PITCH_0:
1354 case RADEON_PP_TEX_PITCH_1:
1355 case RADEON_PP_TEX_PITCH_2:
1356 i = (reg - RADEON_PP_TEX_PITCH_0) / 8;
1357 track->textures[i].pitch = idx_value + 32;
1359 case RADEON_PP_TXFILTER_0:
1360 case RADEON_PP_TXFILTER_1:
1361 case RADEON_PP_TXFILTER_2:
1362 i = (reg - RADEON_PP_TXFILTER_0) / 24;
1363 track->textures[i].num_levels = ((idx_value & RADEON_MAX_MIP_LEVEL_MASK)
1364 >> RADEON_MAX_MIP_LEVEL_SHIFT);
1365 tmp = (idx_value >> 23) & 0x7;
1366 if (tmp == 2 || tmp == 6)
1367 track->textures[i].roundup_w = false;
1368 tmp = (idx_value >> 27) & 0x7;
1369 if (tmp == 2 || tmp == 6)
1370 track->textures[i].roundup_h = false;
1372 case RADEON_PP_TXFORMAT_0:
1373 case RADEON_PP_TXFORMAT_1:
1374 case RADEON_PP_TXFORMAT_2:
1375 i = (reg - RADEON_PP_TXFORMAT_0) / 24;
1376 if (idx_value & RADEON_TXFORMAT_NON_POWER2) {
1377 track->textures[i].use_pitch = 1;
1379 track->textures[i].use_pitch = 0;
1380 track->textures[i].width = 1 << ((idx_value >> RADEON_TXFORMAT_WIDTH_SHIFT) & RADEON_TXFORMAT_WIDTH_MASK);
1381 track->textures[i].height = 1 << ((idx_value >> RADEON_TXFORMAT_HEIGHT_SHIFT) & RADEON_TXFORMAT_HEIGHT_MASK);
1383 if (idx_value & RADEON_TXFORMAT_CUBIC_MAP_ENABLE)
1384 track->textures[i].tex_coord_type = 2;
1385 switch ((idx_value & RADEON_TXFORMAT_FORMAT_MASK)) {
1386 case RADEON_TXFORMAT_I8:
1387 case RADEON_TXFORMAT_RGB332:
1388 case RADEON_TXFORMAT_Y8:
1389 track->textures[i].cpp = 1;
1391 case RADEON_TXFORMAT_AI88:
1392 case RADEON_TXFORMAT_ARGB1555:
1393 case RADEON_TXFORMAT_RGB565:
1394 case RADEON_TXFORMAT_ARGB4444:
1395 case RADEON_TXFORMAT_VYUY422:
1396 case RADEON_TXFORMAT_YVYU422:
1397 case RADEON_TXFORMAT_SHADOW16:
1398 case RADEON_TXFORMAT_LDUDV655:
1399 case RADEON_TXFORMAT_DUDV88:
1400 track->textures[i].cpp = 2;
1402 case RADEON_TXFORMAT_ARGB8888:
1403 case RADEON_TXFORMAT_RGBA8888:
1404 case RADEON_TXFORMAT_SHADOW32:
1405 case RADEON_TXFORMAT_LDUDUV8888:
1406 track->textures[i].cpp = 4;
1408 case RADEON_TXFORMAT_DXT1:
1409 track->textures[i].cpp = 1;
1410 track->textures[i].compress_format = R100_TRACK_COMP_DXT1;
1412 case RADEON_TXFORMAT_DXT23:
1413 case RADEON_TXFORMAT_DXT45:
1414 track->textures[i].cpp = 1;
1415 track->textures[i].compress_format = R100_TRACK_COMP_DXT35;
1418 track->textures[i].cube_info[4].width = 1 << ((idx_value >> 16) & 0xf);
1419 track->textures[i].cube_info[4].height = 1 << ((idx_value >> 20) & 0xf);
1421 case RADEON_PP_CUBIC_FACES_0:
1422 case RADEON_PP_CUBIC_FACES_1:
1423 case RADEON_PP_CUBIC_FACES_2:
1425 i = (reg - RADEON_PP_CUBIC_FACES_0) / 4;
1426 for (face = 0; face < 4; face++) {
1427 track->textures[i].cube_info[face].width = 1 << ((tmp >> (face * 8)) & 0xf);
1428 track->textures[i].cube_info[face].height = 1 << ((tmp >> ((face * 8) + 4)) & 0xf);
1432 printk(KERN_ERR "Forbidden register 0x%04X in cs at %d\n",
1439 int r100_cs_track_check_pkt3_indx_buffer(struct radeon_cs_parser *p,
1440 struct radeon_cs_packet *pkt,
1441 struct radeon_bo *robj)
1446 value = radeon_get_ib_value(p, idx + 2);
1447 if ((value + 1) > radeon_bo_size(robj)) {
1448 DRM_ERROR("[drm] Buffer too small for PACKET3 INDX_BUFFER "
1449 "(need %u have %lu) !\n",
1451 radeon_bo_size(robj));
1457 static int r100_packet3_check(struct radeon_cs_parser *p,
1458 struct radeon_cs_packet *pkt)
1460 struct radeon_cs_reloc *reloc;
1461 struct r100_cs_track *track;
1463 volatile uint32_t *ib;
1468 track = (struct r100_cs_track *)p->track;
1469 switch (pkt->opcode) {
1470 case PACKET3_3D_LOAD_VBPNTR:
1471 r = r100_packet3_load_vbpntr(p, pkt, idx);
1475 case PACKET3_INDX_BUFFER:
1476 r = r100_cs_packet_next_reloc(p, &reloc);
1478 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1479 r100_cs_dump_packet(p, pkt);
1482 ib[idx+1] = radeon_get_ib_value(p, idx+1) + ((u32)reloc->lobj.gpu_offset);
1483 r = r100_cs_track_check_pkt3_indx_buffer(p, pkt, reloc->robj);
1489 /* 3D_RNDR_GEN_INDX_PRIM on r100/r200 */
1490 r = r100_cs_packet_next_reloc(p, &reloc);
1492 DRM_ERROR("No reloc for packet3 %d\n", pkt->opcode);
1493 r100_cs_dump_packet(p, pkt);
1496 ib[idx] = radeon_get_ib_value(p, idx) + ((u32)reloc->lobj.gpu_offset);
1497 track->num_arrays = 1;
1498 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 2));
1500 track->arrays[0].robj = reloc->robj;
1501 track->arrays[0].esize = track->vtx_size;
1503 track->max_indx = radeon_get_ib_value(p, idx+1);
1505 track->vap_vf_cntl = radeon_get_ib_value(p, idx+3);
1506 track->immd_dwords = pkt->count - 1;
1507 r = r100_cs_track_check(p->rdev, track);
1511 case PACKET3_3D_DRAW_IMMD:
1512 if (((radeon_get_ib_value(p, idx + 1) >> 4) & 0x3) != 3) {
1513 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1516 track->vtx_size = r100_get_vtx_size(radeon_get_ib_value(p, idx + 0));
1517 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1518 track->immd_dwords = pkt->count - 1;
1519 r = r100_cs_track_check(p->rdev, track);
1523 /* triggers drawing using in-packet vertex data */
1524 case PACKET3_3D_DRAW_IMMD_2:
1525 if (((radeon_get_ib_value(p, idx) >> 4) & 0x3) != 3) {
1526 DRM_ERROR("PRIM_WALK must be 3 for IMMD draw\n");
1529 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1530 track->immd_dwords = pkt->count;
1531 r = r100_cs_track_check(p->rdev, track);
1535 /* triggers drawing using in-packet vertex data */
1536 case PACKET3_3D_DRAW_VBUF_2:
1537 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1538 r = r100_cs_track_check(p->rdev, track);
1542 /* triggers drawing of vertex buffers setup elsewhere */
1543 case PACKET3_3D_DRAW_INDX_2:
1544 track->vap_vf_cntl = radeon_get_ib_value(p, idx);
1545 r = r100_cs_track_check(p->rdev, track);
1549 /* triggers drawing using indices to vertex buffer */
1550 case PACKET3_3D_DRAW_VBUF:
1551 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1552 r = r100_cs_track_check(p->rdev, track);
1556 /* triggers drawing of vertex buffers setup elsewhere */
1557 case PACKET3_3D_DRAW_INDX:
1558 track->vap_vf_cntl = radeon_get_ib_value(p, idx + 1);
1559 r = r100_cs_track_check(p->rdev, track);
1563 /* triggers drawing using indices to vertex buffer */
1567 DRM_ERROR("Packet3 opcode %x not supported\n", pkt->opcode);
1573 int r100_cs_parse(struct radeon_cs_parser *p)
1575 struct radeon_cs_packet pkt;
1576 struct r100_cs_track *track;
1579 track = kzalloc(sizeof(*track), GFP_KERNEL);
1580 r100_cs_track_clear(p->rdev, track);
1583 r = r100_cs_packet_parse(p, &pkt, p->idx);
1587 p->idx += pkt.count + 2;
1590 if (p->rdev->family >= CHIP_R200)
1591 r = r100_cs_parse_packet0(p, &pkt,
1592 p->rdev->config.r100.reg_safe_bm,
1593 p->rdev->config.r100.reg_safe_bm_size,
1594 &r200_packet0_check);
1596 r = r100_cs_parse_packet0(p, &pkt,
1597 p->rdev->config.r100.reg_safe_bm,
1598 p->rdev->config.r100.reg_safe_bm_size,
1599 &r100_packet0_check);
1604 r = r100_packet3_check(p, &pkt);
1607 DRM_ERROR("Unknown packet type %d !\n",
1614 } while (p->idx < p->chunks[p->chunk_ib_idx].length_dw);
1620 * Global GPU functions
1622 void r100_errata(struct radeon_device *rdev)
1624 rdev->pll_errata = 0;
1626 if (rdev->family == CHIP_RV200 || rdev->family == CHIP_RS200) {
1627 rdev->pll_errata |= CHIP_ERRATA_PLL_DUMMYREADS;
1630 if (rdev->family == CHIP_RV100 ||
1631 rdev->family == CHIP_RS100 ||
1632 rdev->family == CHIP_RS200) {
1633 rdev->pll_errata |= CHIP_ERRATA_PLL_DELAY;
1637 /* Wait for vertical sync on primary CRTC */
1638 void r100_gpu_wait_for_vsync(struct radeon_device *rdev)
1640 uint32_t crtc_gen_cntl, tmp;
1643 crtc_gen_cntl = RREG32(RADEON_CRTC_GEN_CNTL);
1644 if ((crtc_gen_cntl & RADEON_CRTC_DISP_REQ_EN_B) ||
1645 !(crtc_gen_cntl & RADEON_CRTC_EN)) {
1648 /* Clear the CRTC_VBLANK_SAVE bit */
1649 WREG32(RADEON_CRTC_STATUS, RADEON_CRTC_VBLANK_SAVE_CLEAR);
1650 for (i = 0; i < rdev->usec_timeout; i++) {
1651 tmp = RREG32(RADEON_CRTC_STATUS);
1652 if (tmp & RADEON_CRTC_VBLANK_SAVE) {
1659 /* Wait for vertical sync on secondary CRTC */
1660 void r100_gpu_wait_for_vsync2(struct radeon_device *rdev)
1662 uint32_t crtc2_gen_cntl, tmp;
1665 crtc2_gen_cntl = RREG32(RADEON_CRTC2_GEN_CNTL);
1666 if ((crtc2_gen_cntl & RADEON_CRTC2_DISP_REQ_EN_B) ||
1667 !(crtc2_gen_cntl & RADEON_CRTC2_EN))
1670 /* Clear the CRTC_VBLANK_SAVE bit */
1671 WREG32(RADEON_CRTC2_STATUS, RADEON_CRTC2_VBLANK_SAVE_CLEAR);
1672 for (i = 0; i < rdev->usec_timeout; i++) {
1673 tmp = RREG32(RADEON_CRTC2_STATUS);
1674 if (tmp & RADEON_CRTC2_VBLANK_SAVE) {
1681 int r100_rbbm_fifo_wait_for_entry(struct radeon_device *rdev, unsigned n)
1686 for (i = 0; i < rdev->usec_timeout; i++) {
1687 tmp = RREG32(RADEON_RBBM_STATUS) & RADEON_RBBM_FIFOCNT_MASK;
1696 int r100_gui_wait_for_idle(struct radeon_device *rdev)
1701 if (r100_rbbm_fifo_wait_for_entry(rdev, 64)) {
1702 printk(KERN_WARNING "radeon: wait for empty RBBM fifo failed !"
1703 " Bad things might happen.\n");
1705 for (i = 0; i < rdev->usec_timeout; i++) {
1706 tmp = RREG32(RADEON_RBBM_STATUS);
1707 if (!(tmp & RADEON_RBBM_ACTIVE)) {
1715 int r100_mc_wait_for_idle(struct radeon_device *rdev)
1720 for (i = 0; i < rdev->usec_timeout; i++) {
1721 /* read MC_STATUS */
1722 tmp = RREG32(RADEON_MC_STATUS);
1723 if (tmp & RADEON_MC_IDLE) {
1731 void r100_gpu_init(struct radeon_device *rdev)
1733 /* TODO: anythings to do here ? pipes ? */
1734 r100_hdp_reset(rdev);
1737 void r100_hdp_reset(struct radeon_device *rdev)
1741 tmp = RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL;
1743 WREG32(RADEON_HOST_PATH_CNTL, tmp | RADEON_HDP_SOFT_RESET | RADEON_HDP_READ_BUFFER_INVALIDATE);
1744 (void)RREG32(RADEON_HOST_PATH_CNTL);
1746 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1747 WREG32(RADEON_HOST_PATH_CNTL, tmp);
1748 (void)RREG32(RADEON_HOST_PATH_CNTL);
1751 int r100_rb2d_reset(struct radeon_device *rdev)
1756 WREG32(RADEON_RBBM_SOFT_RESET, RADEON_SOFT_RESET_E2);
1757 (void)RREG32(RADEON_RBBM_SOFT_RESET);
1759 WREG32(RADEON_RBBM_SOFT_RESET, 0);
1760 /* Wait to prevent race in RBBM_STATUS */
1762 for (i = 0; i < rdev->usec_timeout; i++) {
1763 tmp = RREG32(RADEON_RBBM_STATUS);
1764 if (!(tmp & (1 << 26))) {
1765 DRM_INFO("RB2D reset succeed (RBBM_STATUS=0x%08X)\n",
1771 tmp = RREG32(RADEON_RBBM_STATUS);
1772 DRM_ERROR("Failed to reset RB2D (RBBM_STATUS=0x%08X)!\n", tmp);
1776 int r100_gpu_reset(struct radeon_device *rdev)
1780 /* reset order likely matter */
1781 status = RREG32(RADEON_RBBM_STATUS);
1783 r100_hdp_reset(rdev);
1785 if (status & ((1 << 17) | (1 << 18) | (1 << 27))) {
1786 r100_rb2d_reset(rdev);
1788 /* TODO: reset 3D engine */
1790 status = RREG32(RADEON_RBBM_STATUS);
1791 if (status & (1 << 16)) {
1792 r100_cp_reset(rdev);
1794 /* Check if GPU is idle */
1795 status = RREG32(RADEON_RBBM_STATUS);
1796 if (status & RADEON_RBBM_ACTIVE) {
1797 DRM_ERROR("Failed to reset GPU (RBBM_STATUS=0x%08X)\n", status);
1800 DRM_INFO("GPU reset succeed (RBBM_STATUS=0x%08X)\n", status);
1804 void r100_set_common_regs(struct radeon_device *rdev)
1806 struct drm_device *dev = rdev->ddev;
1807 bool force_dac2 = false;
1809 /* set these so they don't interfere with anything */
1810 WREG32(RADEON_OV0_SCALE_CNTL, 0);
1811 WREG32(RADEON_SUBPIC_CNTL, 0);
1812 WREG32(RADEON_VIPH_CONTROL, 0);
1813 WREG32(RADEON_I2C_CNTL_1, 0);
1814 WREG32(RADEON_DVI_I2C_CNTL_1, 0);
1815 WREG32(RADEON_CAP0_TRIG_CNTL, 0);
1816 WREG32(RADEON_CAP1_TRIG_CNTL, 0);
1818 /* always set up dac2 on rn50 and some rv100 as lots
1819 * of servers seem to wire it up to a VGA port but
1820 * don't report it in the bios connector
1823 switch (dev->pdev->device) {
1832 /* DELL triple head servers */
1833 if ((dev->pdev->subsystem_vendor == 0x1028 /* DELL */) &&
1834 ((dev->pdev->subsystem_device == 0x016c) ||
1835 (dev->pdev->subsystem_device == 0x016d) ||
1836 (dev->pdev->subsystem_device == 0x016e) ||
1837 (dev->pdev->subsystem_device == 0x016f) ||
1838 (dev->pdev->subsystem_device == 0x0170) ||
1839 (dev->pdev->subsystem_device == 0x017d) ||
1840 (dev->pdev->subsystem_device == 0x017e) ||
1841 (dev->pdev->subsystem_device == 0x0183) ||
1842 (dev->pdev->subsystem_device == 0x018a) ||
1843 (dev->pdev->subsystem_device == 0x019a)))
1849 u32 disp_hw_debug = RREG32(RADEON_DISP_HW_DEBUG);
1850 u32 tv_dac_cntl = RREG32(RADEON_TV_DAC_CNTL);
1851 u32 dac2_cntl = RREG32(RADEON_DAC_CNTL2);
1853 /* For CRT on DAC2, don't turn it on if BIOS didn't
1854 enable it, even it's detected.
1857 /* force it to crtc0 */
1858 dac2_cntl &= ~RADEON_DAC2_DAC_CLK_SEL;
1859 dac2_cntl |= RADEON_DAC2_DAC2_CLK_SEL;
1860 disp_hw_debug |= RADEON_CRT2_DISP1_SEL;
1862 /* set up the TV DAC */
1863 tv_dac_cntl &= ~(RADEON_TV_DAC_PEDESTAL |
1864 RADEON_TV_DAC_STD_MASK |
1865 RADEON_TV_DAC_RDACPD |
1866 RADEON_TV_DAC_GDACPD |
1867 RADEON_TV_DAC_BDACPD |
1868 RADEON_TV_DAC_BGADJ_MASK |
1869 RADEON_TV_DAC_DACADJ_MASK);
1870 tv_dac_cntl |= (RADEON_TV_DAC_NBLANK |
1871 RADEON_TV_DAC_NHOLD |
1872 RADEON_TV_DAC_STD_PS2 |
1875 WREG32(RADEON_TV_DAC_CNTL, tv_dac_cntl);
1876 WREG32(RADEON_DISP_HW_DEBUG, disp_hw_debug);
1877 WREG32(RADEON_DAC_CNTL2, dac2_cntl);
1884 static void r100_vram_get_type(struct radeon_device *rdev)
1888 rdev->mc.vram_is_ddr = false;
1889 if (rdev->flags & RADEON_IS_IGP)
1890 rdev->mc.vram_is_ddr = true;
1891 else if (RREG32(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR)
1892 rdev->mc.vram_is_ddr = true;
1893 if ((rdev->family == CHIP_RV100) ||
1894 (rdev->family == CHIP_RS100) ||
1895 (rdev->family == CHIP_RS200)) {
1896 tmp = RREG32(RADEON_MEM_CNTL);
1897 if (tmp & RV100_HALF_MODE) {
1898 rdev->mc.vram_width = 32;
1900 rdev->mc.vram_width = 64;
1902 if (rdev->flags & RADEON_SINGLE_CRTC) {
1903 rdev->mc.vram_width /= 4;
1904 rdev->mc.vram_is_ddr = true;
1906 } else if (rdev->family <= CHIP_RV280) {
1907 tmp = RREG32(RADEON_MEM_CNTL);
1908 if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) {
1909 rdev->mc.vram_width = 128;
1911 rdev->mc.vram_width = 64;
1915 rdev->mc.vram_width = 128;
1919 static u32 r100_get_accessible_vram(struct radeon_device *rdev)
1924 aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1926 /* Set HDP_APER_CNTL only on cards that are known not to be broken,
1927 * that is has the 2nd generation multifunction PCI interface
1929 if (rdev->family == CHIP_RV280 ||
1930 rdev->family >= CHIP_RV350) {
1931 WREG32_P(RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL,
1932 ~RADEON_HDP_APER_CNTL);
1933 DRM_INFO("Generation 2 PCI interface, using max accessible memory\n");
1934 return aper_size * 2;
1937 /* Older cards have all sorts of funny issues to deal with. First
1938 * check if it's a multifunction card by reading the PCI config
1939 * header type... Limit those to one aperture size
1941 pci_read_config_byte(rdev->pdev, 0xe, &byte);
1943 DRM_INFO("Generation 1 PCI interface in multifunction mode\n");
1944 DRM_INFO("Limiting VRAM to one aperture\n");
1948 /* Single function older card. We read HDP_APER_CNTL to see how the BIOS
1949 * have set it up. We don't write this as it's broken on some ASICs but
1950 * we expect the BIOS to have done the right thing (might be too optimistic...)
1952 if (RREG32(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL)
1953 return aper_size * 2;
1957 void r100_vram_init_sizes(struct radeon_device *rdev)
1959 u64 config_aper_size;
1961 /* work out accessible VRAM */
1962 rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1963 rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1964 rdev->mc.visible_vram_size = r100_get_accessible_vram(rdev);
1965 /* FIXME we don't use the second aperture yet when we could use it */
1966 if (rdev->mc.visible_vram_size > rdev->mc.aper_size)
1967 rdev->mc.visible_vram_size = rdev->mc.aper_size;
1968 config_aper_size = RREG32(RADEON_CONFIG_APER_SIZE);
1969 if (rdev->flags & RADEON_IS_IGP) {
1971 /* read NB_TOM to get the amount of ram stolen for the GPU */
1972 tom = RREG32(RADEON_NB_TOM);
1973 rdev->mc.real_vram_size = (((tom >> 16) - (tom & 0xffff) + 1) << 16);
1974 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1975 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1977 rdev->mc.real_vram_size = RREG32(RADEON_CONFIG_MEMSIZE);
1978 /* Some production boards of m6 will report 0
1981 if (rdev->mc.real_vram_size == 0) {
1982 rdev->mc.real_vram_size = 8192 * 1024;
1983 WREG32(RADEON_CONFIG_MEMSIZE, rdev->mc.real_vram_size);
1985 /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM -
1986 * Novell bug 204882 + along with lots of ubuntu ones
1988 if (config_aper_size > rdev->mc.real_vram_size)
1989 rdev->mc.mc_vram_size = config_aper_size;
1991 rdev->mc.mc_vram_size = rdev->mc.real_vram_size;
1993 /* FIXME remove this once we support unmappable VRAM */
1994 if (rdev->mc.mc_vram_size > rdev->mc.aper_size) {
1995 rdev->mc.mc_vram_size = rdev->mc.aper_size;
1996 rdev->mc.real_vram_size = rdev->mc.aper_size;
2000 void r100_vga_set_state(struct radeon_device *rdev, bool state)
2004 temp = RREG32(RADEON_CONFIG_CNTL);
2005 if (state == false) {
2011 WREG32(RADEON_CONFIG_CNTL, temp);
2014 void r100_mc_init(struct radeon_device *rdev)
2018 r100_vram_get_type(rdev);
2019 r100_vram_init_sizes(rdev);
2020 base = rdev->mc.aper_base;
2021 if (rdev->flags & RADEON_IS_IGP)
2022 base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16;
2023 radeon_vram_location(rdev, &rdev->mc, base);
2024 if (!(rdev->flags & RADEON_IS_AGP))
2025 radeon_gtt_location(rdev, &rdev->mc);
2030 * Indirect registers accessor
2032 void r100_pll_errata_after_index(struct radeon_device *rdev)
2034 if (!(rdev->pll_errata & CHIP_ERRATA_PLL_DUMMYREADS)) {
2037 (void)RREG32(RADEON_CLOCK_CNTL_DATA);
2038 (void)RREG32(RADEON_CRTC_GEN_CNTL);
2041 static void r100_pll_errata_after_data(struct radeon_device *rdev)
2043 /* This workarounds is necessary on RV100, RS100 and RS200 chips
2044 * or the chip could hang on a subsequent access
2046 if (rdev->pll_errata & CHIP_ERRATA_PLL_DELAY) {
2050 /* This function is required to workaround a hardware bug in some (all?)
2051 * revisions of the R300. This workaround should be called after every
2052 * CLOCK_CNTL_INDEX register access. If not, register reads afterward
2053 * may not be correct.
2055 if (rdev->pll_errata & CHIP_ERRATA_R300_CG) {
2058 save = RREG32(RADEON_CLOCK_CNTL_INDEX);
2059 tmp = save & ~(0x3f | RADEON_PLL_WR_EN);
2060 WREG32(RADEON_CLOCK_CNTL_INDEX, tmp);
2061 tmp = RREG32(RADEON_CLOCK_CNTL_DATA);
2062 WREG32(RADEON_CLOCK_CNTL_INDEX, save);
2066 uint32_t r100_pll_rreg(struct radeon_device *rdev, uint32_t reg)
2070 WREG8(RADEON_CLOCK_CNTL_INDEX, reg & 0x3f);
2071 r100_pll_errata_after_index(rdev);
2072 data = RREG32(RADEON_CLOCK_CNTL_DATA);
2073 r100_pll_errata_after_data(rdev);
2077 void r100_pll_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
2079 WREG8(RADEON_CLOCK_CNTL_INDEX, ((reg & 0x3f) | RADEON_PLL_WR_EN));
2080 r100_pll_errata_after_index(rdev);
2081 WREG32(RADEON_CLOCK_CNTL_DATA, v);
2082 r100_pll_errata_after_data(rdev);
2085 void r100_set_safe_registers(struct radeon_device *rdev)
2087 if (ASIC_IS_RN50(rdev)) {
2088 rdev->config.r100.reg_safe_bm = rn50_reg_safe_bm;
2089 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(rn50_reg_safe_bm);
2090 } else if (rdev->family < CHIP_R200) {
2091 rdev->config.r100.reg_safe_bm = r100_reg_safe_bm;
2092 rdev->config.r100.reg_safe_bm_size = ARRAY_SIZE(r100_reg_safe_bm);
2094 r200_set_safe_registers(rdev);
2101 #if defined(CONFIG_DEBUG_FS)
2102 static int r100_debugfs_rbbm_info(struct seq_file *m, void *data)
2104 struct drm_info_node *node = (struct drm_info_node *) m->private;
2105 struct drm_device *dev = node->minor->dev;
2106 struct radeon_device *rdev = dev->dev_private;
2107 uint32_t reg, value;
2110 seq_printf(m, "RBBM_STATUS 0x%08x\n", RREG32(RADEON_RBBM_STATUS));
2111 seq_printf(m, "RBBM_CMDFIFO_STAT 0x%08x\n", RREG32(0xE7C));
2112 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2113 for (i = 0; i < 64; i++) {
2114 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i | 0x100);
2115 reg = (RREG32(RADEON_RBBM_CMDFIFO_DATA) - 1) >> 2;
2116 WREG32(RADEON_RBBM_CMDFIFO_ADDR, i);
2117 value = RREG32(RADEON_RBBM_CMDFIFO_DATA);
2118 seq_printf(m, "[0x%03X] 0x%04X=0x%08X\n", i, reg, value);
2123 static int r100_debugfs_cp_ring_info(struct seq_file *m, void *data)
2125 struct drm_info_node *node = (struct drm_info_node *) m->private;
2126 struct drm_device *dev = node->minor->dev;
2127 struct radeon_device *rdev = dev->dev_private;
2129 unsigned count, i, j;
2131 radeon_ring_free_size(rdev);
2132 rdp = RREG32(RADEON_CP_RB_RPTR);
2133 wdp = RREG32(RADEON_CP_RB_WPTR);
2134 count = (rdp + rdev->cp.ring_size - wdp) & rdev->cp.ptr_mask;
2135 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2136 seq_printf(m, "CP_RB_WPTR 0x%08x\n", wdp);
2137 seq_printf(m, "CP_RB_RPTR 0x%08x\n", rdp);
2138 seq_printf(m, "%u free dwords in ring\n", rdev->cp.ring_free_dw);
2139 seq_printf(m, "%u dwords in ring\n", count);
2140 for (j = 0; j <= count; j++) {
2141 i = (rdp + j) & rdev->cp.ptr_mask;
2142 seq_printf(m, "r[%04d]=0x%08x\n", i, rdev->cp.ring[i]);
2148 static int r100_debugfs_cp_csq_fifo(struct seq_file *m, void *data)
2150 struct drm_info_node *node = (struct drm_info_node *) m->private;
2151 struct drm_device *dev = node->minor->dev;
2152 struct radeon_device *rdev = dev->dev_private;
2153 uint32_t csq_stat, csq2_stat, tmp;
2154 unsigned r_rptr, r_wptr, ib1_rptr, ib1_wptr, ib2_rptr, ib2_wptr;
2157 seq_printf(m, "CP_STAT 0x%08x\n", RREG32(RADEON_CP_STAT));
2158 seq_printf(m, "CP_CSQ_MODE 0x%08x\n", RREG32(RADEON_CP_CSQ_MODE));
2159 csq_stat = RREG32(RADEON_CP_CSQ_STAT);
2160 csq2_stat = RREG32(RADEON_CP_CSQ2_STAT);
2161 r_rptr = (csq_stat >> 0) & 0x3ff;
2162 r_wptr = (csq_stat >> 10) & 0x3ff;
2163 ib1_rptr = (csq_stat >> 20) & 0x3ff;
2164 ib1_wptr = (csq2_stat >> 0) & 0x3ff;
2165 ib2_rptr = (csq2_stat >> 10) & 0x3ff;
2166 ib2_wptr = (csq2_stat >> 20) & 0x3ff;
2167 seq_printf(m, "CP_CSQ_STAT 0x%08x\n", csq_stat);
2168 seq_printf(m, "CP_CSQ2_STAT 0x%08x\n", csq2_stat);
2169 seq_printf(m, "Ring rptr %u\n", r_rptr);
2170 seq_printf(m, "Ring wptr %u\n", r_wptr);
2171 seq_printf(m, "Indirect1 rptr %u\n", ib1_rptr);
2172 seq_printf(m, "Indirect1 wptr %u\n", ib1_wptr);
2173 seq_printf(m, "Indirect2 rptr %u\n", ib2_rptr);
2174 seq_printf(m, "Indirect2 wptr %u\n", ib2_wptr);
2175 /* FIXME: 0, 128, 640 depends on fifo setup see cp_init_kms
2176 * 128 = indirect1_start * 8 & 640 = indirect2_start * 8 */
2177 seq_printf(m, "Ring fifo:\n");
2178 for (i = 0; i < 256; i++) {
2179 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2180 tmp = RREG32(RADEON_CP_CSQ_DATA);
2181 seq_printf(m, "rfifo[%04d]=0x%08X\n", i, tmp);
2183 seq_printf(m, "Indirect1 fifo:\n");
2184 for (i = 256; i <= 512; i++) {
2185 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2186 tmp = RREG32(RADEON_CP_CSQ_DATA);
2187 seq_printf(m, "ib1fifo[%04d]=0x%08X\n", i, tmp);
2189 seq_printf(m, "Indirect2 fifo:\n");
2190 for (i = 640; i < ib1_wptr; i++) {
2191 WREG32(RADEON_CP_CSQ_ADDR, i << 2);
2192 tmp = RREG32(RADEON_CP_CSQ_DATA);
2193 seq_printf(m, "ib2fifo[%04d]=0x%08X\n", i, tmp);
2198 static int r100_debugfs_mc_info(struct seq_file *m, void *data)
2200 struct drm_info_node *node = (struct drm_info_node *) m->private;
2201 struct drm_device *dev = node->minor->dev;
2202 struct radeon_device *rdev = dev->dev_private;
2205 tmp = RREG32(RADEON_CONFIG_MEMSIZE);
2206 seq_printf(m, "CONFIG_MEMSIZE 0x%08x\n", tmp);
2207 tmp = RREG32(RADEON_MC_FB_LOCATION);
2208 seq_printf(m, "MC_FB_LOCATION 0x%08x\n", tmp);
2209 tmp = RREG32(RADEON_BUS_CNTL);
2210 seq_printf(m, "BUS_CNTL 0x%08x\n", tmp);
2211 tmp = RREG32(RADEON_MC_AGP_LOCATION);
2212 seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp);
2213 tmp = RREG32(RADEON_AGP_BASE);
2214 seq_printf(m, "AGP_BASE 0x%08x\n", tmp);
2215 tmp = RREG32(RADEON_HOST_PATH_CNTL);
2216 seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp);
2217 tmp = RREG32(0x01D0);
2218 seq_printf(m, "AIC_CTRL 0x%08x\n", tmp);
2219 tmp = RREG32(RADEON_AIC_LO_ADDR);
2220 seq_printf(m, "AIC_LO_ADDR 0x%08x\n", tmp);
2221 tmp = RREG32(RADEON_AIC_HI_ADDR);
2222 seq_printf(m, "AIC_HI_ADDR 0x%08x\n", tmp);
2223 tmp = RREG32(0x01E4);
2224 seq_printf(m, "AIC_TLB_ADDR 0x%08x\n", tmp);
2228 static struct drm_info_list r100_debugfs_rbbm_list[] = {
2229 {"r100_rbbm_info", r100_debugfs_rbbm_info, 0, NULL},
2232 static struct drm_info_list r100_debugfs_cp_list[] = {
2233 {"r100_cp_ring_info", r100_debugfs_cp_ring_info, 0, NULL},
2234 {"r100_cp_csq_fifo", r100_debugfs_cp_csq_fifo, 0, NULL},
2237 static struct drm_info_list r100_debugfs_mc_info_list[] = {
2238 {"r100_mc_info", r100_debugfs_mc_info, 0, NULL},
2242 int r100_debugfs_rbbm_init(struct radeon_device *rdev)
2244 #if defined(CONFIG_DEBUG_FS)
2245 return radeon_debugfs_add_files(rdev, r100_debugfs_rbbm_list, 1);
2251 int r100_debugfs_cp_init(struct radeon_device *rdev)
2253 #if defined(CONFIG_DEBUG_FS)
2254 return radeon_debugfs_add_files(rdev, r100_debugfs_cp_list, 2);
2260 int r100_debugfs_mc_info_init(struct radeon_device *rdev)
2262 #if defined(CONFIG_DEBUG_FS)
2263 return radeon_debugfs_add_files(rdev, r100_debugfs_mc_info_list, 1);
2269 int r100_set_surface_reg(struct radeon_device *rdev, int reg,
2270 uint32_t tiling_flags, uint32_t pitch,
2271 uint32_t offset, uint32_t obj_size)
2273 int surf_index = reg * 16;
2276 /* r100/r200 divide by 16 */
2277 if (rdev->family < CHIP_R300)
2282 if (rdev->family <= CHIP_RS200) {
2283 if ((tiling_flags & (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2284 == (RADEON_TILING_MACRO|RADEON_TILING_MICRO))
2285 flags |= RADEON_SURF_TILE_COLOR_BOTH;
2286 if (tiling_flags & RADEON_TILING_MACRO)
2287 flags |= RADEON_SURF_TILE_COLOR_MACRO;
2288 } else if (rdev->family <= CHIP_RV280) {
2289 if (tiling_flags & (RADEON_TILING_MACRO))
2290 flags |= R200_SURF_TILE_COLOR_MACRO;
2291 if (tiling_flags & RADEON_TILING_MICRO)
2292 flags |= R200_SURF_TILE_COLOR_MICRO;
2294 if (tiling_flags & RADEON_TILING_MACRO)
2295 flags |= R300_SURF_TILE_MACRO;
2296 if (tiling_flags & RADEON_TILING_MICRO)
2297 flags |= R300_SURF_TILE_MICRO;
2300 if (tiling_flags & RADEON_TILING_SWAP_16BIT)
2301 flags |= RADEON_SURF_AP0_SWP_16BPP | RADEON_SURF_AP1_SWP_16BPP;
2302 if (tiling_flags & RADEON_TILING_SWAP_32BIT)
2303 flags |= RADEON_SURF_AP0_SWP_32BPP | RADEON_SURF_AP1_SWP_32BPP;
2305 DRM_DEBUG("writing surface %d %d %x %x\n", reg, flags, offset, offset+obj_size-1);
2306 WREG32(RADEON_SURFACE0_INFO + surf_index, flags);
2307 WREG32(RADEON_SURFACE0_LOWER_BOUND + surf_index, offset);
2308 WREG32(RADEON_SURFACE0_UPPER_BOUND + surf_index, offset + obj_size - 1);
2312 void r100_clear_surface_reg(struct radeon_device *rdev, int reg)
2314 int surf_index = reg * 16;
2315 WREG32(RADEON_SURFACE0_INFO + surf_index, 0);
2318 void r100_bandwidth_update(struct radeon_device *rdev)
2320 fixed20_12 trcd_ff, trp_ff, tras_ff, trbs_ff, tcas_ff;
2321 fixed20_12 sclk_ff, mclk_ff, sclk_eff_ff, sclk_delay_ff;
2322 fixed20_12 peak_disp_bw, mem_bw, pix_clk, pix_clk2, temp_ff, crit_point_ff;
2323 uint32_t temp, data, mem_trcd, mem_trp, mem_tras;
2324 fixed20_12 memtcas_ff[8] = {
2333 fixed20_12 memtcas_rs480_ff[8] = {
2343 fixed20_12 memtcas2_ff[8] = {
2353 fixed20_12 memtrbs[8] = {
2363 fixed20_12 memtrbs_r4xx[8] = {
2373 fixed20_12 min_mem_eff;
2374 fixed20_12 mc_latency_sclk, mc_latency_mclk, k1;
2375 fixed20_12 cur_latency_mclk, cur_latency_sclk;
2376 fixed20_12 disp_latency, disp_latency_overhead, disp_drain_rate,
2377 disp_drain_rate2, read_return_rate;
2378 fixed20_12 time_disp1_drop_priority;
2380 int cur_size = 16; /* in octawords */
2381 int critical_point = 0, critical_point2;
2382 /* uint32_t read_return_rate, time_disp1_drop_priority; */
2383 int stop_req, max_stop_req;
2384 struct drm_display_mode *mode1 = NULL;
2385 struct drm_display_mode *mode2 = NULL;
2386 uint32_t pixel_bytes1 = 0;
2387 uint32_t pixel_bytes2 = 0;
2389 if (rdev->mode_info.crtcs[0]->base.enabled) {
2390 mode1 = &rdev->mode_info.crtcs[0]->base.mode;
2391 pixel_bytes1 = rdev->mode_info.crtcs[0]->base.fb->bits_per_pixel / 8;
2393 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
2394 if (rdev->mode_info.crtcs[1]->base.enabled) {
2395 mode2 = &rdev->mode_info.crtcs[1]->base.mode;
2396 pixel_bytes2 = rdev->mode_info.crtcs[1]->base.fb->bits_per_pixel / 8;
2400 min_mem_eff.full = rfixed_const_8(0);
2402 if ((rdev->disp_priority == 2) && ASIC_IS_R300(rdev)) {
2403 uint32_t mc_init_misc_lat_timer = RREG32(R300_MC_INIT_MISC_LAT_TIMER);
2404 mc_init_misc_lat_timer &= ~(R300_MC_DISP1R_INIT_LAT_MASK << R300_MC_DISP1R_INIT_LAT_SHIFT);
2405 mc_init_misc_lat_timer &= ~(R300_MC_DISP0R_INIT_LAT_MASK << R300_MC_DISP0R_INIT_LAT_SHIFT);
2406 /* check crtc enables */
2408 mc_init_misc_lat_timer |= (1 << R300_MC_DISP1R_INIT_LAT_SHIFT);
2410 mc_init_misc_lat_timer |= (1 << R300_MC_DISP0R_INIT_LAT_SHIFT);
2411 WREG32(R300_MC_INIT_MISC_LAT_TIMER, mc_init_misc_lat_timer);
2415 * determine is there is enough bw for current mode
2417 mclk_ff.full = rfixed_const(rdev->clock.default_mclk);
2418 temp_ff.full = rfixed_const(100);
2419 mclk_ff.full = rfixed_div(mclk_ff, temp_ff);
2420 sclk_ff.full = rfixed_const(rdev->clock.default_sclk);
2421 sclk_ff.full = rfixed_div(sclk_ff, temp_ff);
2423 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1);
2424 temp_ff.full = rfixed_const(temp);
2425 mem_bw.full = rfixed_mul(mclk_ff, temp_ff);
2429 peak_disp_bw.full = 0;
2431 temp_ff.full = rfixed_const(1000);
2432 pix_clk.full = rfixed_const(mode1->clock); /* convert to fixed point */
2433 pix_clk.full = rfixed_div(pix_clk, temp_ff);
2434 temp_ff.full = rfixed_const(pixel_bytes1);
2435 peak_disp_bw.full += rfixed_mul(pix_clk, temp_ff);
2438 temp_ff.full = rfixed_const(1000);
2439 pix_clk2.full = rfixed_const(mode2->clock); /* convert to fixed point */
2440 pix_clk2.full = rfixed_div(pix_clk2, temp_ff);
2441 temp_ff.full = rfixed_const(pixel_bytes2);
2442 peak_disp_bw.full += rfixed_mul(pix_clk2, temp_ff);
2445 mem_bw.full = rfixed_mul(mem_bw, min_mem_eff);
2446 if (peak_disp_bw.full >= mem_bw.full) {
2447 DRM_ERROR("You may not have enough display bandwidth for current mode\n"
2448 "If you have flickering problem, try to lower resolution, refresh rate, or color depth\n");
2451 /* Get values from the EXT_MEM_CNTL register...converting its contents. */
2452 temp = RREG32(RADEON_MEM_TIMING_CNTL);
2453 if ((rdev->family == CHIP_RV100) || (rdev->flags & RADEON_IS_IGP)) { /* RV100, M6, IGPs */
2454 mem_trcd = ((temp >> 2) & 0x3) + 1;
2455 mem_trp = ((temp & 0x3)) + 1;
2456 mem_tras = ((temp & 0x70) >> 4) + 1;
2457 } else if (rdev->family == CHIP_R300 ||
2458 rdev->family == CHIP_R350) { /* r300, r350 */
2459 mem_trcd = (temp & 0x7) + 1;
2460 mem_trp = ((temp >> 8) & 0x7) + 1;
2461 mem_tras = ((temp >> 11) & 0xf) + 4;
2462 } else if (rdev->family == CHIP_RV350 ||
2463 rdev->family <= CHIP_RV380) {
2465 mem_trcd = (temp & 0x7) + 3;
2466 mem_trp = ((temp >> 8) & 0x7) + 3;
2467 mem_tras = ((temp >> 11) & 0xf) + 6;
2468 } else if (rdev->family == CHIP_R420 ||
2469 rdev->family == CHIP_R423 ||
2470 rdev->family == CHIP_RV410) {
2472 mem_trcd = (temp & 0xf) + 3;
2475 mem_trp = ((temp >> 8) & 0xf) + 3;
2478 mem_tras = ((temp >> 12) & 0x1f) + 6;
2481 } else { /* RV200, R200 */
2482 mem_trcd = (temp & 0x7) + 1;
2483 mem_trp = ((temp >> 8) & 0x7) + 1;
2484 mem_tras = ((temp >> 12) & 0xf) + 4;
2487 trcd_ff.full = rfixed_const(mem_trcd);
2488 trp_ff.full = rfixed_const(mem_trp);
2489 tras_ff.full = rfixed_const(mem_tras);
2491 /* Get values from the MEM_SDRAM_MODE_REG register...converting its */
2492 temp = RREG32(RADEON_MEM_SDRAM_MODE_REG);
2493 data = (temp & (7 << 20)) >> 20;
2494 if ((rdev->family == CHIP_RV100) || rdev->flags & RADEON_IS_IGP) {
2495 if (rdev->family == CHIP_RS480) /* don't think rs400 */
2496 tcas_ff = memtcas_rs480_ff[data];
2498 tcas_ff = memtcas_ff[data];
2500 tcas_ff = memtcas2_ff[data];
2502 if (rdev->family == CHIP_RS400 ||
2503 rdev->family == CHIP_RS480) {
2504 /* extra cas latency stored in bits 23-25 0-4 clocks */
2505 data = (temp >> 23) & 0x7;
2507 tcas_ff.full += rfixed_const(data);
2510 if (ASIC_IS_R300(rdev) && !(rdev->flags & RADEON_IS_IGP)) {
2511 /* on the R300, Tcas is included in Trbs.
2513 temp = RREG32(RADEON_MEM_CNTL);
2514 data = (R300_MEM_NUM_CHANNELS_MASK & temp);
2516 if (R300_MEM_USE_CD_CH_ONLY & temp) {
2517 temp = RREG32(R300_MC_IND_INDEX);
2518 temp &= ~R300_MC_IND_ADDR_MASK;
2519 temp |= R300_MC_READ_CNTL_CD_mcind;
2520 WREG32(R300_MC_IND_INDEX, temp);
2521 temp = RREG32(R300_MC_IND_DATA);
2522 data = (R300_MEM_RBS_POSITION_C_MASK & temp);
2524 temp = RREG32(R300_MC_READ_CNTL_AB);
2525 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2528 temp = RREG32(R300_MC_READ_CNTL_AB);
2529 data = (R300_MEM_RBS_POSITION_A_MASK & temp);
2531 if (rdev->family == CHIP_RV410 ||
2532 rdev->family == CHIP_R420 ||
2533 rdev->family == CHIP_R423)
2534 trbs_ff = memtrbs_r4xx[data];
2536 trbs_ff = memtrbs[data];
2537 tcas_ff.full += trbs_ff.full;
2540 sclk_eff_ff.full = sclk_ff.full;
2542 if (rdev->flags & RADEON_IS_AGP) {
2543 fixed20_12 agpmode_ff;
2544 agpmode_ff.full = rfixed_const(radeon_agpmode);
2545 temp_ff.full = rfixed_const_666(16);
2546 sclk_eff_ff.full -= rfixed_mul(agpmode_ff, temp_ff);
2548 /* TODO PCIE lanes may affect this - agpmode == 16?? */
2550 if (ASIC_IS_R300(rdev)) {
2551 sclk_delay_ff.full = rfixed_const(250);
2553 if ((rdev->family == CHIP_RV100) ||
2554 rdev->flags & RADEON_IS_IGP) {
2555 if (rdev->mc.vram_is_ddr)
2556 sclk_delay_ff.full = rfixed_const(41);
2558 sclk_delay_ff.full = rfixed_const(33);
2560 if (rdev->mc.vram_width == 128)
2561 sclk_delay_ff.full = rfixed_const(57);
2563 sclk_delay_ff.full = rfixed_const(41);
2567 mc_latency_sclk.full = rfixed_div(sclk_delay_ff, sclk_eff_ff);
2569 if (rdev->mc.vram_is_ddr) {
2570 if (rdev->mc.vram_width == 32) {
2571 k1.full = rfixed_const(40);
2574 k1.full = rfixed_const(20);
2578 k1.full = rfixed_const(40);
2582 temp_ff.full = rfixed_const(2);
2583 mc_latency_mclk.full = rfixed_mul(trcd_ff, temp_ff);
2584 temp_ff.full = rfixed_const(c);
2585 mc_latency_mclk.full += rfixed_mul(tcas_ff, temp_ff);
2586 temp_ff.full = rfixed_const(4);
2587 mc_latency_mclk.full += rfixed_mul(tras_ff, temp_ff);
2588 mc_latency_mclk.full += rfixed_mul(trp_ff, temp_ff);
2589 mc_latency_mclk.full += k1.full;
2591 mc_latency_mclk.full = rfixed_div(mc_latency_mclk, mclk_ff);
2592 mc_latency_mclk.full += rfixed_div(temp_ff, sclk_eff_ff);
2595 HW cursor time assuming worst case of full size colour cursor.
2597 temp_ff.full = rfixed_const((2 * (cur_size - (rdev->mc.vram_is_ddr + 1))));
2598 temp_ff.full += trcd_ff.full;
2599 if (temp_ff.full < tras_ff.full)
2600 temp_ff.full = tras_ff.full;
2601 cur_latency_mclk.full = rfixed_div(temp_ff, mclk_ff);
2603 temp_ff.full = rfixed_const(cur_size);
2604 cur_latency_sclk.full = rfixed_div(temp_ff, sclk_eff_ff);
2606 Find the total latency for the display data.
2608 disp_latency_overhead.full = rfixed_const(8);
2609 disp_latency_overhead.full = rfixed_div(disp_latency_overhead, sclk_ff);
2610 mc_latency_mclk.full += disp_latency_overhead.full + cur_latency_mclk.full;
2611 mc_latency_sclk.full += disp_latency_overhead.full + cur_latency_sclk.full;
2613 if (mc_latency_mclk.full > mc_latency_sclk.full)
2614 disp_latency.full = mc_latency_mclk.full;
2616 disp_latency.full = mc_latency_sclk.full;
2618 /* setup Max GRPH_STOP_REQ default value */
2619 if (ASIC_IS_RV100(rdev))
2620 max_stop_req = 0x5c;
2622 max_stop_req = 0x7c;
2626 Set GRPH_BUFFER_CNTL register using h/w defined optimal values.
2627 GRPH_STOP_REQ <= MIN[ 0x7C, (CRTC_H_DISP + 1) * (bit depth) / 0x10 ]
2629 stop_req = mode1->hdisplay * pixel_bytes1 / 16;
2631 if (stop_req > max_stop_req)
2632 stop_req = max_stop_req;
2635 Find the drain rate of the display buffer.
2637 temp_ff.full = rfixed_const((16/pixel_bytes1));
2638 disp_drain_rate.full = rfixed_div(pix_clk, temp_ff);
2641 Find the critical point of the display buffer.
2643 crit_point_ff.full = rfixed_mul(disp_drain_rate, disp_latency);
2644 crit_point_ff.full += rfixed_const_half(0);
2646 critical_point = rfixed_trunc(crit_point_ff);
2648 if (rdev->disp_priority == 2) {
2653 The critical point should never be above max_stop_req-4. Setting
2654 GRPH_CRITICAL_CNTL = 0 will thus force high priority all the time.
2656 if (max_stop_req - critical_point < 4)
2659 if (critical_point == 0 && mode2 && rdev->family == CHIP_R300) {
2660 /* some R300 cards have problem with this set to 0, when CRTC2 is enabled.*/
2661 critical_point = 0x10;
2664 temp = RREG32(RADEON_GRPH_BUFFER_CNTL);
2665 temp &= ~(RADEON_GRPH_STOP_REQ_MASK);
2666 temp |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2667 temp &= ~(RADEON_GRPH_START_REQ_MASK);
2668 if ((rdev->family == CHIP_R350) &&
2669 (stop_req > 0x15)) {
2672 temp |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2673 temp |= RADEON_GRPH_BUFFER_SIZE;
2674 temp &= ~(RADEON_GRPH_CRITICAL_CNTL |
2675 RADEON_GRPH_CRITICAL_AT_SOF |
2676 RADEON_GRPH_STOP_CNTL);
2678 Write the result into the register.
2680 WREG32(RADEON_GRPH_BUFFER_CNTL, ((temp & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2681 (critical_point << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2684 if ((rdev->family == CHIP_RS400) ||
2685 (rdev->family == CHIP_RS480)) {
2686 /* attempt to program RS400 disp regs correctly ??? */
2687 temp = RREG32(RS400_DISP1_REG_CNTL);
2688 temp &= ~(RS400_DISP1_START_REQ_LEVEL_MASK |
2689 RS400_DISP1_STOP_REQ_LEVEL_MASK);
2690 WREG32(RS400_DISP1_REQ_CNTL1, (temp |
2691 (critical_point << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2692 (critical_point << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2693 temp = RREG32(RS400_DMIF_MEM_CNTL1);
2694 temp &= ~(RS400_DISP1_CRITICAL_POINT_START_MASK |
2695 RS400_DISP1_CRITICAL_POINT_STOP_MASK);
2696 WREG32(RS400_DMIF_MEM_CNTL1, (temp |
2697 (critical_point << RS400_DISP1_CRITICAL_POINT_START_SHIFT) |
2698 (critical_point << RS400_DISP1_CRITICAL_POINT_STOP_SHIFT)));
2702 DRM_DEBUG("GRPH_BUFFER_CNTL from to %x\n",
2703 /* (unsigned int)info->SavedReg->grph_buffer_cntl, */
2704 (unsigned int)RREG32(RADEON_GRPH_BUFFER_CNTL));
2709 stop_req = mode2->hdisplay * pixel_bytes2 / 16;
2711 if (stop_req > max_stop_req)
2712 stop_req = max_stop_req;
2715 Find the drain rate of the display buffer.
2717 temp_ff.full = rfixed_const((16/pixel_bytes2));
2718 disp_drain_rate2.full = rfixed_div(pix_clk2, temp_ff);
2720 grph2_cntl = RREG32(RADEON_GRPH2_BUFFER_CNTL);
2721 grph2_cntl &= ~(RADEON_GRPH_STOP_REQ_MASK);
2722 grph2_cntl |= (stop_req << RADEON_GRPH_STOP_REQ_SHIFT);
2723 grph2_cntl &= ~(RADEON_GRPH_START_REQ_MASK);
2724 if ((rdev->family == CHIP_R350) &&
2725 (stop_req > 0x15)) {
2728 grph2_cntl |= (stop_req << RADEON_GRPH_START_REQ_SHIFT);
2729 grph2_cntl |= RADEON_GRPH_BUFFER_SIZE;
2730 grph2_cntl &= ~(RADEON_GRPH_CRITICAL_CNTL |
2731 RADEON_GRPH_CRITICAL_AT_SOF |
2732 RADEON_GRPH_STOP_CNTL);
2734 if ((rdev->family == CHIP_RS100) ||
2735 (rdev->family == CHIP_RS200))
2736 critical_point2 = 0;
2738 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128;
2739 temp_ff.full = rfixed_const(temp);
2740 temp_ff.full = rfixed_mul(mclk_ff, temp_ff);
2741 if (sclk_ff.full < temp_ff.full)
2742 temp_ff.full = sclk_ff.full;
2744 read_return_rate.full = temp_ff.full;
2747 temp_ff.full = read_return_rate.full - disp_drain_rate.full;
2748 time_disp1_drop_priority.full = rfixed_div(crit_point_ff, temp_ff);
2750 time_disp1_drop_priority.full = 0;
2752 crit_point_ff.full = disp_latency.full + time_disp1_drop_priority.full + disp_latency.full;
2753 crit_point_ff.full = rfixed_mul(crit_point_ff, disp_drain_rate2);
2754 crit_point_ff.full += rfixed_const_half(0);
2756 critical_point2 = rfixed_trunc(crit_point_ff);
2758 if (rdev->disp_priority == 2) {
2759 critical_point2 = 0;
2762 if (max_stop_req - critical_point2 < 4)
2763 critical_point2 = 0;
2767 if (critical_point2 == 0 && rdev->family == CHIP_R300) {
2768 /* some R300 cards have problem with this set to 0 */
2769 critical_point2 = 0x10;
2772 WREG32(RADEON_GRPH2_BUFFER_CNTL, ((grph2_cntl & ~RADEON_GRPH_CRITICAL_POINT_MASK) |
2773 (critical_point2 << RADEON_GRPH_CRITICAL_POINT_SHIFT)));
2775 if ((rdev->family == CHIP_RS400) ||
2776 (rdev->family == CHIP_RS480)) {
2778 /* attempt to program RS400 disp2 regs correctly ??? */
2779 temp = RREG32(RS400_DISP2_REQ_CNTL1);
2780 temp &= ~(RS400_DISP2_START_REQ_LEVEL_MASK |
2781 RS400_DISP2_STOP_REQ_LEVEL_MASK);
2782 WREG32(RS400_DISP2_REQ_CNTL1, (temp |
2783 (critical_point2 << RS400_DISP1_START_REQ_LEVEL_SHIFT) |
2784 (critical_point2 << RS400_DISP1_STOP_REQ_LEVEL_SHIFT)));
2785 temp = RREG32(RS400_DISP2_REQ_CNTL2);
2786 temp &= ~(RS400_DISP2_CRITICAL_POINT_START_MASK |
2787 RS400_DISP2_CRITICAL_POINT_STOP_MASK);
2788 WREG32(RS400_DISP2_REQ_CNTL2, (temp |
2789 (critical_point2 << RS400_DISP2_CRITICAL_POINT_START_SHIFT) |
2790 (critical_point2 << RS400_DISP2_CRITICAL_POINT_STOP_SHIFT)));
2792 WREG32(RS400_DISP2_REQ_CNTL1, 0x105DC1CC);
2793 WREG32(RS400_DISP2_REQ_CNTL2, 0x2749D000);
2794 WREG32(RS400_DMIF_MEM_CNTL1, 0x29CA71DC);
2795 WREG32(RS400_DISP1_REQ_CNTL1, 0x28FBC3AC);
2798 DRM_DEBUG("GRPH2_BUFFER_CNTL from to %x\n",
2799 (unsigned int)RREG32(RADEON_GRPH2_BUFFER_CNTL));
2803 static inline void r100_cs_track_texture_print(struct r100_cs_track_texture *t)
2805 DRM_ERROR("pitch %d\n", t->pitch);
2806 DRM_ERROR("use_pitch %d\n", t->use_pitch);
2807 DRM_ERROR("width %d\n", t->width);
2808 DRM_ERROR("width_11 %d\n", t->width_11);
2809 DRM_ERROR("height %d\n", t->height);
2810 DRM_ERROR("height_11 %d\n", t->height_11);
2811 DRM_ERROR("num levels %d\n", t->num_levels);
2812 DRM_ERROR("depth %d\n", t->txdepth);
2813 DRM_ERROR("bpp %d\n", t->cpp);
2814 DRM_ERROR("coordinate type %d\n", t->tex_coord_type);
2815 DRM_ERROR("width round to power of 2 %d\n", t->roundup_w);
2816 DRM_ERROR("height round to power of 2 %d\n", t->roundup_h);
2817 DRM_ERROR("compress format %d\n", t->compress_format);
2820 static int r100_cs_track_cube(struct radeon_device *rdev,
2821 struct r100_cs_track *track, unsigned idx)
2823 unsigned face, w, h;
2824 struct radeon_bo *cube_robj;
2827 for (face = 0; face < 5; face++) {
2828 cube_robj = track->textures[idx].cube_info[face].robj;
2829 w = track->textures[idx].cube_info[face].width;
2830 h = track->textures[idx].cube_info[face].height;
2833 size *= track->textures[idx].cpp;
2835 size += track->textures[idx].cube_info[face].offset;
2837 if (size > radeon_bo_size(cube_robj)) {
2838 DRM_ERROR("Cube texture offset greater than object size %lu %lu\n",
2839 size, radeon_bo_size(cube_robj));
2840 r100_cs_track_texture_print(&track->textures[idx]);
2847 static int r100_track_compress_size(int compress_format, int w, int h)
2849 int block_width, block_height, block_bytes;
2850 int wblocks, hblocks;
2857 switch (compress_format) {
2858 case R100_TRACK_COMP_DXT1:
2863 case R100_TRACK_COMP_DXT35:
2869 hblocks = (h + block_height - 1) / block_height;
2870 wblocks = (w + block_width - 1) / block_width;
2871 if (wblocks < min_wblocks)
2872 wblocks = min_wblocks;
2873 sz = wblocks * hblocks * block_bytes;
2877 static int r100_cs_track_texture_check(struct radeon_device *rdev,
2878 struct r100_cs_track *track)
2880 struct radeon_bo *robj;
2882 unsigned u, i, w, h;
2885 for (u = 0; u < track->num_texture; u++) {
2886 if (!track->textures[u].enabled)
2888 robj = track->textures[u].robj;
2890 DRM_ERROR("No texture bound to unit %u\n", u);
2894 for (i = 0; i <= track->textures[u].num_levels; i++) {
2895 if (track->textures[u].use_pitch) {
2896 if (rdev->family < CHIP_R300)
2897 w = (track->textures[u].pitch / track->textures[u].cpp) / (1 << i);
2899 w = track->textures[u].pitch / (1 << i);
2901 w = track->textures[u].width;
2902 if (rdev->family >= CHIP_RV515)
2903 w |= track->textures[u].width_11;
2905 if (track->textures[u].roundup_w)
2906 w = roundup_pow_of_two(w);
2908 h = track->textures[u].height;
2909 if (rdev->family >= CHIP_RV515)
2910 h |= track->textures[u].height_11;
2912 if (track->textures[u].roundup_h)
2913 h = roundup_pow_of_two(h);
2914 if (track->textures[u].compress_format) {
2916 size += r100_track_compress_size(track->textures[u].compress_format, w, h);
2917 /* compressed textures are block based */
2921 size *= track->textures[u].cpp;
2923 switch (track->textures[u].tex_coord_type) {
2927 size *= (1 << track->textures[u].txdepth);
2930 if (track->separate_cube) {
2931 ret = r100_cs_track_cube(rdev, track, u);
2938 DRM_ERROR("Invalid texture coordinate type %u for unit "
2939 "%u\n", track->textures[u].tex_coord_type, u);
2942 if (size > radeon_bo_size(robj)) {
2943 DRM_ERROR("Texture of unit %u needs %lu bytes but is "
2944 "%lu\n", u, size, radeon_bo_size(robj));
2945 r100_cs_track_texture_print(&track->textures[u]);
2952 int r100_cs_track_check(struct radeon_device *rdev, struct r100_cs_track *track)
2959 for (i = 0; i < track->num_cb; i++) {
2960 if (track->cb[i].robj == NULL) {
2961 if (!(track->fastfill || track->color_channel_mask ||
2962 track->blend_read_enable)) {
2965 DRM_ERROR("[drm] No buffer for color buffer %d !\n", i);
2968 size = track->cb[i].pitch * track->cb[i].cpp * track->maxy;
2969 size += track->cb[i].offset;
2970 if (size > radeon_bo_size(track->cb[i].robj)) {
2971 DRM_ERROR("[drm] Buffer too small for color buffer %d "
2972 "(need %lu have %lu) !\n", i, size,
2973 radeon_bo_size(track->cb[i].robj));
2974 DRM_ERROR("[drm] color buffer %d (%u %u %u %u)\n",
2975 i, track->cb[i].pitch, track->cb[i].cpp,
2976 track->cb[i].offset, track->maxy);
2980 if (track->z_enabled) {
2981 if (track->zb.robj == NULL) {
2982 DRM_ERROR("[drm] No buffer for z buffer !\n");
2985 size = track->zb.pitch * track->zb.cpp * track->maxy;
2986 size += track->zb.offset;
2987 if (size > radeon_bo_size(track->zb.robj)) {
2988 DRM_ERROR("[drm] Buffer too small for z buffer "
2989 "(need %lu have %lu) !\n", size,
2990 radeon_bo_size(track->zb.robj));
2991 DRM_ERROR("[drm] zbuffer (%u %u %u %u)\n",
2992 track->zb.pitch, track->zb.cpp,
2993 track->zb.offset, track->maxy);
2997 prim_walk = (track->vap_vf_cntl >> 4) & 0x3;
2998 nverts = (track->vap_vf_cntl >> 16) & 0xFFFF;
2999 switch (prim_walk) {
3001 for (i = 0; i < track->num_arrays; i++) {
3002 size = track->arrays[i].esize * track->max_indx * 4;
3003 if (track->arrays[i].robj == NULL) {
3004 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3005 "bound\n", prim_walk, i);
3008 if (size > radeon_bo_size(track->arrays[i].robj)) {
3009 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3010 "need %lu dwords have %lu dwords\n",
3011 prim_walk, i, size >> 2,
3012 radeon_bo_size(track->arrays[i].robj)
3014 DRM_ERROR("Max indices %u\n", track->max_indx);
3020 for (i = 0; i < track->num_arrays; i++) {
3021 size = track->arrays[i].esize * (nverts - 1) * 4;
3022 if (track->arrays[i].robj == NULL) {
3023 DRM_ERROR("(PW %u) Vertex array %u no buffer "
3024 "bound\n", prim_walk, i);
3027 if (size > radeon_bo_size(track->arrays[i].robj)) {
3028 dev_err(rdev->dev, "(PW %u) Vertex array %u "
3029 "need %lu dwords have %lu dwords\n",
3030 prim_walk, i, size >> 2,
3031 radeon_bo_size(track->arrays[i].robj)
3038 size = track->vtx_size * nverts;
3039 if (size != track->immd_dwords) {
3040 DRM_ERROR("IMMD draw %u dwors but needs %lu dwords\n",
3041 track->immd_dwords, size);
3042 DRM_ERROR("VAP_VF_CNTL.NUM_VERTICES %u, VTX_SIZE %u\n",
3043 nverts, track->vtx_size);
3048 DRM_ERROR("[drm] Invalid primitive walk %d for VAP_VF_CNTL\n",
3052 return r100_cs_track_texture_check(rdev, track);
3055 void r100_cs_track_clear(struct radeon_device *rdev, struct r100_cs_track *track)
3059 if (rdev->family < CHIP_R300) {
3061 if (rdev->family <= CHIP_RS200)
3062 track->num_texture = 3;
3064 track->num_texture = 6;
3066 track->separate_cube = 1;
3069 track->num_texture = 16;
3071 track->separate_cube = 0;
3074 for (i = 0; i < track->num_cb; i++) {
3075 track->cb[i].robj = NULL;
3076 track->cb[i].pitch = 8192;
3077 track->cb[i].cpp = 16;
3078 track->cb[i].offset = 0;
3080 track->z_enabled = true;
3081 track->zb.robj = NULL;
3082 track->zb.pitch = 8192;
3084 track->zb.offset = 0;
3085 track->vtx_size = 0x7F;
3086 track->immd_dwords = 0xFFFFFFFFUL;
3087 track->num_arrays = 11;
3088 track->max_indx = 0x00FFFFFFUL;
3089 for (i = 0; i < track->num_arrays; i++) {
3090 track->arrays[i].robj = NULL;
3091 track->arrays[i].esize = 0x7F;
3093 for (i = 0; i < track->num_texture; i++) {
3094 track->textures[i].compress_format = R100_TRACK_COMP_NONE;
3095 track->textures[i].pitch = 16536;
3096 track->textures[i].width = 16536;
3097 track->textures[i].height = 16536;
3098 track->textures[i].width_11 = 1 << 11;
3099 track->textures[i].height_11 = 1 << 11;
3100 track->textures[i].num_levels = 12;
3101 if (rdev->family <= CHIP_RS200) {
3102 track->textures[i].tex_coord_type = 0;
3103 track->textures[i].txdepth = 0;
3105 track->textures[i].txdepth = 16;
3106 track->textures[i].tex_coord_type = 1;
3108 track->textures[i].cpp = 64;
3109 track->textures[i].robj = NULL;
3110 /* CS IB emission code makes sure texture unit are disabled */
3111 track->textures[i].enabled = false;
3112 track->textures[i].roundup_w = true;
3113 track->textures[i].roundup_h = true;
3114 if (track->separate_cube)
3115 for (face = 0; face < 5; face++) {
3116 track->textures[i].cube_info[face].robj = NULL;
3117 track->textures[i].cube_info[face].width = 16536;
3118 track->textures[i].cube_info[face].height = 16536;
3119 track->textures[i].cube_info[face].offset = 0;
3124 int r100_ring_test(struct radeon_device *rdev)
3131 r = radeon_scratch_get(rdev, &scratch);
3133 DRM_ERROR("radeon: cp failed to get scratch reg (%d).\n", r);
3136 WREG32(scratch, 0xCAFEDEAD);
3137 r = radeon_ring_lock(rdev, 2);
3139 DRM_ERROR("radeon: cp failed to lock ring (%d).\n", r);
3140 radeon_scratch_free(rdev, scratch);
3143 radeon_ring_write(rdev, PACKET0(scratch, 0));
3144 radeon_ring_write(rdev, 0xDEADBEEF);
3145 radeon_ring_unlock_commit(rdev);
3146 for (i = 0; i < rdev->usec_timeout; i++) {
3147 tmp = RREG32(scratch);
3148 if (tmp == 0xDEADBEEF) {
3153 if (i < rdev->usec_timeout) {
3154 DRM_INFO("ring test succeeded in %d usecs\n", i);
3156 DRM_ERROR("radeon: ring test failed (sracth(0x%04X)=0x%08X)\n",
3160 radeon_scratch_free(rdev, scratch);
3164 void r100_ring_ib_execute(struct radeon_device *rdev, struct radeon_ib *ib)
3166 radeon_ring_write(rdev, PACKET0(RADEON_CP_IB_BASE, 1));
3167 radeon_ring_write(rdev, ib->gpu_addr);
3168 radeon_ring_write(rdev, ib->length_dw);
3171 int r100_ib_test(struct radeon_device *rdev)
3173 struct radeon_ib *ib;
3179 r = radeon_scratch_get(rdev, &scratch);
3181 DRM_ERROR("radeon: failed to get scratch reg (%d).\n", r);
3184 WREG32(scratch, 0xCAFEDEAD);
3185 r = radeon_ib_get(rdev, &ib);
3189 ib->ptr[0] = PACKET0(scratch, 0);
3190 ib->ptr[1] = 0xDEADBEEF;
3191 ib->ptr[2] = PACKET2(0);
3192 ib->ptr[3] = PACKET2(0);
3193 ib->ptr[4] = PACKET2(0);
3194 ib->ptr[5] = PACKET2(0);
3195 ib->ptr[6] = PACKET2(0);
3196 ib->ptr[7] = PACKET2(0);
3198 r = radeon_ib_schedule(rdev, ib);
3200 radeon_scratch_free(rdev, scratch);
3201 radeon_ib_free(rdev, &ib);
3204 r = radeon_fence_wait(ib->fence, false);
3208 for (i = 0; i < rdev->usec_timeout; i++) {
3209 tmp = RREG32(scratch);
3210 if (tmp == 0xDEADBEEF) {
3215 if (i < rdev->usec_timeout) {
3216 DRM_INFO("ib test succeeded in %u usecs\n", i);
3218 DRM_ERROR("radeon: ib test failed (sracth(0x%04X)=0x%08X)\n",
3222 radeon_scratch_free(rdev, scratch);
3223 radeon_ib_free(rdev, &ib);
3227 void r100_ib_fini(struct radeon_device *rdev)
3229 radeon_ib_pool_fini(rdev);
3232 int r100_ib_init(struct radeon_device *rdev)
3236 r = radeon_ib_pool_init(rdev);
3238 dev_err(rdev->dev, "failled initializing IB pool (%d).\n", r);
3242 r = r100_ib_test(rdev);
3244 dev_err(rdev->dev, "failled testing IB (%d).\n", r);
3251 void r100_mc_stop(struct radeon_device *rdev, struct r100_mc_save *save)
3253 /* Shutdown CP we shouldn't need to do that but better be safe than
3256 rdev->cp.ready = false;
3257 WREG32(R_000740_CP_CSQ_CNTL, 0);
3259 /* Save few CRTC registers */
3260 save->GENMO_WT = RREG8(R_0003C2_GENMO_WT);
3261 save->CRTC_EXT_CNTL = RREG32(R_000054_CRTC_EXT_CNTL);
3262 save->CRTC_GEN_CNTL = RREG32(R_000050_CRTC_GEN_CNTL);
3263 save->CUR_OFFSET = RREG32(R_000260_CUR_OFFSET);
3264 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3265 save->CRTC2_GEN_CNTL = RREG32(R_0003F8_CRTC2_GEN_CNTL);
3266 save->CUR2_OFFSET = RREG32(R_000360_CUR2_OFFSET);
3269 /* Disable VGA aperture access */
3270 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & save->GENMO_WT);
3271 /* Disable cursor, overlay, crtc */
3272 WREG32(R_000260_CUR_OFFSET, save->CUR_OFFSET | S_000260_CUR_LOCK(1));
3273 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL |
3274 S_000054_CRTC_DISPLAY_DIS(1));
3275 WREG32(R_000050_CRTC_GEN_CNTL,
3276 (C_000050_CRTC_CUR_EN & save->CRTC_GEN_CNTL) |
3277 S_000050_CRTC_DISP_REQ_EN_B(1));
3278 WREG32(R_000420_OV0_SCALE_CNTL,
3279 C_000420_OV0_OVERLAY_EN & RREG32(R_000420_OV0_SCALE_CNTL));
3280 WREG32(R_000260_CUR_OFFSET, C_000260_CUR_LOCK & save->CUR_OFFSET);
3281 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3282 WREG32(R_000360_CUR2_OFFSET, save->CUR2_OFFSET |
3283 S_000360_CUR2_LOCK(1));
3284 WREG32(R_0003F8_CRTC2_GEN_CNTL,
3285 (C_0003F8_CRTC2_CUR_EN & save->CRTC2_GEN_CNTL) |
3286 S_0003F8_CRTC2_DISPLAY_DIS(1) |
3287 S_0003F8_CRTC2_DISP_REQ_EN_B(1));
3288 WREG32(R_000360_CUR2_OFFSET,
3289 C_000360_CUR2_LOCK & save->CUR2_OFFSET);
3293 void r100_mc_resume(struct radeon_device *rdev, struct r100_mc_save *save)
3295 /* Update base address for crtc */
3296 WREG32(R_00023C_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3297 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3298 WREG32(R_00033C_CRTC2_DISPLAY_BASE_ADDR, rdev->mc.vram_start);
3300 /* Restore CRTC registers */
3301 WREG8(R_0003C2_GENMO_WT, save->GENMO_WT);
3302 WREG32(R_000054_CRTC_EXT_CNTL, save->CRTC_EXT_CNTL);
3303 WREG32(R_000050_CRTC_GEN_CNTL, save->CRTC_GEN_CNTL);
3304 if (!(rdev->flags & RADEON_SINGLE_CRTC)) {
3305 WREG32(R_0003F8_CRTC2_GEN_CNTL, save->CRTC2_GEN_CNTL);
3309 void r100_vga_render_disable(struct radeon_device *rdev)
3313 tmp = RREG8(R_0003C2_GENMO_WT);
3314 WREG8(R_0003C2_GENMO_WT, C_0003C2_VGA_RAM_EN & tmp);
3317 static void r100_debugfs(struct radeon_device *rdev)
3321 r = r100_debugfs_mc_info_init(rdev);
3323 dev_warn(rdev->dev, "Failed to create r100_mc debugfs file.\n");
3326 static void r100_mc_program(struct radeon_device *rdev)
3328 struct r100_mc_save save;
3330 /* Stops all mc clients */
3331 r100_mc_stop(rdev, &save);
3332 if (rdev->flags & RADEON_IS_AGP) {
3333 WREG32(R_00014C_MC_AGP_LOCATION,
3334 S_00014C_MC_AGP_START(rdev->mc.gtt_start >> 16) |
3335 S_00014C_MC_AGP_TOP(rdev->mc.gtt_end >> 16));
3336 WREG32(R_000170_AGP_BASE, lower_32_bits(rdev->mc.agp_base));
3337 if (rdev->family > CHIP_RV200)
3338 WREG32(R_00015C_AGP_BASE_2,
3339 upper_32_bits(rdev->mc.agp_base) & 0xff);
3341 WREG32(R_00014C_MC_AGP_LOCATION, 0x0FFFFFFF);
3342 WREG32(R_000170_AGP_BASE, 0);
3343 if (rdev->family > CHIP_RV200)
3344 WREG32(R_00015C_AGP_BASE_2, 0);
3346 /* Wait for mc idle */
3347 if (r100_mc_wait_for_idle(rdev))
3348 dev_warn(rdev->dev, "Wait for MC idle timeout.\n");
3349 /* Program MC, should be a 32bits limited address space */
3350 WREG32(R_000148_MC_FB_LOCATION,
3351 S_000148_MC_FB_START(rdev->mc.vram_start >> 16) |
3352 S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16));
3353 r100_mc_resume(rdev, &save);
3356 void r100_clock_startup(struct radeon_device *rdev)
3360 if (radeon_dynclks != -1 && radeon_dynclks)
3361 radeon_legacy_set_clock_gating(rdev, 1);
3362 /* We need to force on some of the block */
3363 tmp = RREG32_PLL(R_00000D_SCLK_CNTL);
3364 tmp |= S_00000D_FORCE_CP(1) | S_00000D_FORCE_VIP(1);
3365 if ((rdev->family == CHIP_RV250) || (rdev->family == CHIP_RV280))
3366 tmp |= S_00000D_FORCE_DISP1(1) | S_00000D_FORCE_DISP2(1);
3367 WREG32_PLL(R_00000D_SCLK_CNTL, tmp);
3370 static int r100_startup(struct radeon_device *rdev)
3374 /* set common regs */
3375 r100_set_common_regs(rdev);
3377 r100_mc_program(rdev);
3379 r100_clock_startup(rdev);
3380 /* Initialize GPU configuration (# pipes, ...) */
3381 r100_gpu_init(rdev);
3382 /* Initialize GART (initialize after TTM so we can allocate
3383 * memory through TTM but finalize after TTM) */
3384 r100_enable_bm(rdev);
3385 if (rdev->flags & RADEON_IS_PCI) {
3386 r = r100_pci_gart_enable(rdev);
3392 rdev->config.r100.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
3393 /* 1M ring buffer */
3394 r = r100_cp_init(rdev, 1024 * 1024);
3396 dev_err(rdev->dev, "failled initializing CP (%d).\n", r);
3399 r = r100_wb_init(rdev);
3401 dev_err(rdev->dev, "failled initializing WB (%d).\n", r);
3402 r = r100_ib_init(rdev);
3404 dev_err(rdev->dev, "failled initializing IB (%d).\n", r);
3410 int r100_resume(struct radeon_device *rdev)
3412 /* Make sur GART are not working */
3413 if (rdev->flags & RADEON_IS_PCI)
3414 r100_pci_gart_disable(rdev);
3415 /* Resume clock before doing reset */
3416 r100_clock_startup(rdev);
3417 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3418 if (radeon_gpu_reset(rdev)) {
3419 dev_warn(rdev->dev, "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3420 RREG32(R_000E40_RBBM_STATUS),
3421 RREG32(R_0007C0_CP_STAT));
3424 radeon_combios_asic_init(rdev->ddev);
3425 /* Resume clock after posting */
3426 r100_clock_startup(rdev);
3427 /* Initialize surface registers */
3428 radeon_surface_init(rdev);
3429 return r100_startup(rdev);
3432 int r100_suspend(struct radeon_device *rdev)
3434 r100_cp_disable(rdev);
3435 r100_wb_disable(rdev);
3436 r100_irq_disable(rdev);
3437 if (rdev->flags & RADEON_IS_PCI)
3438 r100_pci_gart_disable(rdev);
3442 void r100_fini(struct radeon_device *rdev)
3447 radeon_gem_fini(rdev);
3448 if (rdev->flags & RADEON_IS_PCI)
3449 r100_pci_gart_fini(rdev);
3450 radeon_agp_fini(rdev);
3451 radeon_irq_kms_fini(rdev);
3452 radeon_fence_driver_fini(rdev);
3453 radeon_bo_fini(rdev);
3454 radeon_atombios_fini(rdev);
3459 int r100_init(struct radeon_device *rdev)
3463 /* Register debugfs file specific to this group of asics */
3466 r100_vga_render_disable(rdev);
3467 /* Initialize scratch registers */
3468 radeon_scratch_init(rdev);
3469 /* Initialize surface registers */
3470 radeon_surface_init(rdev);
3471 /* TODO: disable VGA need to use VGA request */
3473 if (!radeon_get_bios(rdev)) {
3474 if (ASIC_IS_AVIVO(rdev))
3477 if (rdev->is_atom_bios) {
3478 dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n");
3481 r = radeon_combios_init(rdev);
3485 /* Reset gpu before posting otherwise ATOM will enter infinite loop */
3486 if (radeon_gpu_reset(rdev)) {
3488 "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n",
3489 RREG32(R_000E40_RBBM_STATUS),
3490 RREG32(R_0007C0_CP_STAT));
3492 /* check if cards are posted or not */
3493 if (radeon_boot_test_post_card(rdev) == false)
3495 /* Set asic errata */
3497 /* Initialize clocks */
3498 radeon_get_clock_info(rdev->ddev);
3499 /* Initialize power management */
3500 radeon_pm_init(rdev);
3501 /* initialize AGP */
3502 if (rdev->flags & RADEON_IS_AGP) {
3503 r = radeon_agp_init(rdev);
3505 radeon_agp_disable(rdev);
3508 /* initialize VRAM */
3511 r = radeon_fence_driver_init(rdev);
3514 r = radeon_irq_kms_init(rdev);
3517 /* Memory manager */
3518 r = radeon_bo_init(rdev);
3521 if (rdev->flags & RADEON_IS_PCI) {
3522 r = r100_pci_gart_init(rdev);
3526 r100_set_safe_registers(rdev);
3527 rdev->accel_working = true;
3528 r = r100_startup(rdev);
3530 /* Somethings want wront with the accel init stop accel */
3531 dev_err(rdev->dev, "Disabling GPU acceleration\n");
3535 radeon_irq_kms_fini(rdev);
3536 if (rdev->flags & RADEON_IS_PCI)
3537 r100_pci_gart_fini(rdev);
3538 rdev->accel_working = false;