SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/radeon/evergreen.c

   1 /*
   2  * Copyright 2010 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  * Authors: Alex Deucher
  23  */
  24 #include <linux/firmware.h>
  25 #include <linux/platform_device.h>
  26 #include <linux/slab.h>
  27 #include "drmP.h"
  28 #include "radeon.h"
  29 #include "radeon_asic.h"
  30 #include "radeon_drm.h"
  31 #include "evergreend.h"
  32 #include "atom.h"
  33 #include "avivod.h"
  34 #include "evergreen_reg.h"
  35
  36 #define EVERGREEN_PFP_UCODE_SIZE 1120
  37 #define EVERGREEN_PM4_UCODE_SIZE 1376
  38
  39 static void evergreen_gpu_init(struct radeon_device *rdev);
  40 void evergreen_fini(struct radeon_device *rdev);
  41
  42 void evergreen_pm_misc(struct radeon_device *rdev)
  43 {
  44         int req_ps_idx = rdev->pm.requested_power_state_index;
  45         int req_cm_idx = rdev->pm.requested_clock_mode_index;
  46         struct radeon_power_state *ps = &rdev->pm.power_state[req_ps_idx];
  47         struct radeon_voltage *voltage = &ps->clock_info[req_cm_idx].voltage;
  48
  49         if ((voltage->type == VOLTAGE_SW) && voltage->voltage) {
  50                 if (voltage->voltage != rdev->pm.current_vddc) {
  51                         radeon_atom_set_voltage(rdev, voltage->voltage);
  52                         rdev->pm.current_vddc = voltage->voltage;
  53                 }
  54         }
  55 }
  56
  57 void evergreen_pm_prepare(struct radeon_device *rdev)
  58 {
  59         struct drm_device *ddev = rdev->ddev;
  60         struct drm_crtc *crtc;
  61         struct radeon_crtc *radeon_crtc;
  62         u32 tmp;
  63
  64         /* disable any active CRTCs */
  65         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  66                 radeon_crtc = to_radeon_crtc(crtc);
  67                 if (radeon_crtc->enabled) {
  68                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
  69                         tmp |= EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
  70                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  71                 }
  72         }
  73 }
  74
  75 void evergreen_pm_finish(struct radeon_device *rdev)
  76 {
  77         struct drm_device *ddev = rdev->ddev;
  78         struct drm_crtc *crtc;
  79         struct radeon_crtc *radeon_crtc;
  80         u32 tmp;
  81
  82         /* enable any active CRTCs */
  83         list_for_each_entry(crtc, &ddev->mode_config.crtc_list, head) {
  84                 radeon_crtc = to_radeon_crtc(crtc);
  85                 if (radeon_crtc->enabled) {
  86                         tmp = RREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset);
  87                         tmp &= ~EVERGREEN_CRTC_DISP_READ_REQUEST_DISABLE;
  88                         WREG32(EVERGREEN_CRTC_CONTROL + radeon_crtc->crtc_offset, tmp);
  89                 }
  90         }
  91 }
  92
  93 bool evergreen_hpd_sense(struct radeon_device *rdev, enum radeon_hpd_id hpd)
  94 {
  95         bool connected = false;
  96
  97         switch (hpd) {
  98         case RADEON_HPD_1:
  99                 if (RREG32(DC_HPD1_INT_STATUS) & DC_HPDx_SENSE)
 100                         connected = true;
 101                 break;
 102         case RADEON_HPD_2:
 103                 if (RREG32(DC_HPD2_INT_STATUS) & DC_HPDx_SENSE)
 104                         connected = true;
 105                 break;
 106         case RADEON_HPD_3:
 107                 if (RREG32(DC_HPD3_INT_STATUS) & DC_HPDx_SENSE)
 108                         connected = true;
 109                 break;
 110         case RADEON_HPD_4:
 111                 if (RREG32(DC_HPD4_INT_STATUS) & DC_HPDx_SENSE)
 112                         connected = true;
 113                 break;
 114         case RADEON_HPD_5:
 115                 if (RREG32(DC_HPD5_INT_STATUS) & DC_HPDx_SENSE)
 116                         connected = true;
 117                 break;
 118         case RADEON_HPD_6:
 119                 if (RREG32(DC_HPD6_INT_STATUS) & DC_HPDx_SENSE)
 120                         connected = true;
 121                         break;
 122         default:
 123                 break;
 124         }
 125
 126         return connected;
 127 }
 128
 129 void evergreen_hpd_set_polarity(struct radeon_device *rdev,
 130                                 enum radeon_hpd_id hpd)
 131 {
 132         u32 tmp;
 133         bool connected = evergreen_hpd_sense(rdev, hpd);
 134
 135         switch (hpd) {
 136         case RADEON_HPD_1:
 137                 tmp = RREG32(DC_HPD1_INT_CONTROL);
 138                 if (connected)
 139                         tmp &= ~DC_HPDx_INT_POLARITY;
 140                 else
 141                         tmp |= DC_HPDx_INT_POLARITY;
 142                 WREG32(DC_HPD1_INT_CONTROL, tmp);
 143                 break;
 144         case RADEON_HPD_2:
 145                 tmp = RREG32(DC_HPD2_INT_CONTROL);
 146                 if (connected)
 147                         tmp &= ~DC_HPDx_INT_POLARITY;
 148                 else
 149                         tmp |= DC_HPDx_INT_POLARITY;
 150                 WREG32(DC_HPD2_INT_CONTROL, tmp);
 151                 break;
 152         case RADEON_HPD_3:
 153                 tmp = RREG32(DC_HPD3_INT_CONTROL);
 154                 if (connected)
 155                         tmp &= ~DC_HPDx_INT_POLARITY;
 156                 else
 157                         tmp |= DC_HPDx_INT_POLARITY;
 158                 WREG32(DC_HPD3_INT_CONTROL, tmp);
 159                 break;
 160         case RADEON_HPD_4:
 161                 tmp = RREG32(DC_HPD4_INT_CONTROL);
 162                 if (connected)
 163                         tmp &= ~DC_HPDx_INT_POLARITY;
 164                 else
 165                         tmp |= DC_HPDx_INT_POLARITY;
 166                 WREG32(DC_HPD4_INT_CONTROL, tmp);
 167                 break;
 168         case RADEON_HPD_5:
 169                 tmp = RREG32(DC_HPD5_INT_CONTROL);
 170                 if (connected)
 171                         tmp &= ~DC_HPDx_INT_POLARITY;
 172                 else
 173                         tmp |= DC_HPDx_INT_POLARITY;
 174                 WREG32(DC_HPD5_INT_CONTROL, tmp);
 175                         break;
 176         case RADEON_HPD_6:
 177                 tmp = RREG32(DC_HPD6_INT_CONTROL);
 178                 if (connected)
 179                         tmp &= ~DC_HPDx_INT_POLARITY;
 180                 else
 181                         tmp |= DC_HPDx_INT_POLARITY;
 182                 WREG32(DC_HPD6_INT_CONTROL, tmp);
 183                 break;
 184         default:
 185                 break;
 186         }
 187 }
 188
 189 void evergreen_hpd_init(struct radeon_device *rdev)
 190 {
 191         struct drm_device *dev = rdev->ddev;
 192         struct drm_connector *connector;
 193         u32 tmp = DC_HPDx_CONNECTION_TIMER(0x9c4) |
 194                 DC_HPDx_RX_INT_TIMER(0xfa) | DC_HPDx_EN;
 195
 196         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 197                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 198                 switch (radeon_connector->hpd.hpd) {
 199                 case RADEON_HPD_1:
 200                         WREG32(DC_HPD1_CONTROL, tmp);
 201                         rdev->irq.hpd[0] = true;
 202                         break;
 203                 case RADEON_HPD_2:
 204                         WREG32(DC_HPD2_CONTROL, tmp);
 205                         rdev->irq.hpd[1] = true;
 206                         break;
 207                 case RADEON_HPD_3:
 208                         WREG32(DC_HPD3_CONTROL, tmp);
 209                         rdev->irq.hpd[2] = true;
 210                         break;
 211                 case RADEON_HPD_4:
 212                         WREG32(DC_HPD4_CONTROL, tmp);
 213                         rdev->irq.hpd[3] = true;
 214                         break;
 215                 case RADEON_HPD_5:
 216                         WREG32(DC_HPD5_CONTROL, tmp);
 217                         rdev->irq.hpd[4] = true;
 218                         break;
 219                 case RADEON_HPD_6:
 220                         WREG32(DC_HPD6_CONTROL, tmp);
 221                         rdev->irq.hpd[5] = true;
 222                         break;
 223                 default:
 224                         break;
 225                 }
 226         }
 227         if (rdev->irq.installed)
 228                 evergreen_irq_set(rdev);
 229 }
 230
 231 void evergreen_hpd_fini(struct radeon_device *rdev)
 232 {
 233         struct drm_device *dev = rdev->ddev;
 234         struct drm_connector *connector;
 235
 236         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
 237                 struct radeon_connector *radeon_connector = to_radeon_connector(connector);
 238                 switch (radeon_connector->hpd.hpd) {
 239                 case RADEON_HPD_1:
 240                         WREG32(DC_HPD1_CONTROL, 0);
 241                         rdev->irq.hpd[0] = false;
 242                         break;
 243                 case RADEON_HPD_2:
 244                         WREG32(DC_HPD2_CONTROL, 0);
 245                         rdev->irq.hpd[1] = false;
 246                         break;
 247                 case RADEON_HPD_3:
 248                         WREG32(DC_HPD3_CONTROL, 0);
 249                         rdev->irq.hpd[2] = false;
 250                         break;
 251                 case RADEON_HPD_4:
 252                         WREG32(DC_HPD4_CONTROL, 0);
 253                         rdev->irq.hpd[3] = false;
 254                         break;
 255                 case RADEON_HPD_5:
 256                         WREG32(DC_HPD5_CONTROL, 0);
 257                         rdev->irq.hpd[4] = false;
 258                         break;
 259                 case RADEON_HPD_6:
 260                         WREG32(DC_HPD6_CONTROL, 0);
 261                         rdev->irq.hpd[5] = false;
 262                         break;
 263                 default:
 264                         break;
 265                 }
 266         }
 267 }
 268
 269 void evergreen_bandwidth_update(struct radeon_device *rdev)
 270 {
 271         /* XXX */
 272 }
 273
 274 static int evergreen_mc_wait_for_idle(struct radeon_device *rdev)
 275 {
 276         unsigned i;
 277         u32 tmp;
 278
 279         for (i = 0; i < rdev->usec_timeout; i++) {
 280                 /* read MC_STATUS */
 281                 tmp = RREG32(SRBM_STATUS) & 0x1F00;
 282                 if (!tmp)
 283                         return 0;
 284                 udelay(1);
 285         }
 286         return -1;
 287 }
 288
 289 /*
 290  * GART
 291  */
 292 void evergreen_pcie_gart_tlb_flush(struct radeon_device *rdev)
 293 {
 294         unsigned i;
 295         u32 tmp;
 296
 297         WREG32(VM_CONTEXT0_REQUEST_RESPONSE, REQUEST_TYPE(1));
 298         for (i = 0; i < rdev->usec_timeout; i++) {
 299                 /* read MC_STATUS */
 300                 tmp = RREG32(VM_CONTEXT0_REQUEST_RESPONSE);
 301                 tmp = (tmp & RESPONSE_TYPE_MASK) >> RESPONSE_TYPE_SHIFT;
 302                 if (tmp == 2) {
 303                         printk(KERN_WARNING "[drm] r600 flush TLB failed\n");
 304                         return;
 305                 }
 306                 if (tmp) {
 307                         return;
 308                 }
 309                 udelay(1);
 310         }
 311 }
 312
 313 int evergreen_pcie_gart_enable(struct radeon_device *rdev)
 314 {
 315         u32 tmp;
 316         int r;
 317
 318         if (rdev->gart.table.vram.robj == NULL) {
 319                 dev_err(rdev->dev, "No VRAM object for PCIE GART.\n");
 320                 return -EINVAL;
 321         }
 322         r = radeon_gart_table_vram_pin(rdev);
 323         if (r)
 324                 return r;
 325         radeon_gart_restore(rdev);
 326         /* Setup L2 cache */
 327         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 328                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 329                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 330         WREG32(VM_L2_CNTL2, 0);
 331         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 332         /* Setup TLB control */
 333         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 334                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 335                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 336                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 337         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 338         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 339         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 340         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 341         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 342         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 343         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 344         WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12);
 345         WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12);
 346         WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12);
 347         WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) |
 348                                 RANGE_PROTECTION_FAULT_ENABLE_DEFAULT);
 349         WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR,
 350                         (u32)(rdev->dummy_page.addr >> 12));
 351         WREG32(VM_CONTEXT1_CNTL, 0);
 352
 353         evergreen_pcie_gart_tlb_flush(rdev);
 354         rdev->gart.ready = true;
 355         return 0;
 356 }
 357
 358 void evergreen_pcie_gart_disable(struct radeon_device *rdev)
 359 {
 360         u32 tmp;
 361         int r;
 362
 363         /* Disable all tables */
 364         WREG32(VM_CONTEXT0_CNTL, 0);
 365         WREG32(VM_CONTEXT1_CNTL, 0);
 366
 367         /* Setup L2 cache */
 368         WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING |
 369                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 370         WREG32(VM_L2_CNTL2, 0);
 371         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 372         /* Setup TLB control */
 373         tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 374         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 375         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 376         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 377         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 378         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 379         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 380         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 381         if (rdev->gart.table.vram.robj) {
 382                 r = radeon_bo_reserve(rdev->gart.table.vram.robj, false);
 383                 if (likely(r == 0)) {
 384                         radeon_bo_kunmap(rdev->gart.table.vram.robj);
 385                         radeon_bo_unpin(rdev->gart.table.vram.robj);
 386                         radeon_bo_unreserve(rdev->gart.table.vram.robj);
 387                 }
 388         }
 389 }
 390
 391 void evergreen_pcie_gart_fini(struct radeon_device *rdev)
 392 {
 393         evergreen_pcie_gart_disable(rdev);
 394         radeon_gart_table_vram_free(rdev);
 395         radeon_gart_fini(rdev);
 396 }
 397
 398
 399 void evergreen_agp_enable(struct radeon_device *rdev)
 400 {
 401         u32 tmp;
 402
 403         /* Setup L2 cache */
 404         WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING |
 405                                 ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE |
 406                                 EFFECTIVE_L2_QUEUE_SIZE(7));
 407         WREG32(VM_L2_CNTL2, 0);
 408         WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2));
 409         /* Setup TLB control */
 410         tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING |
 411                 SYSTEM_ACCESS_MODE_NOT_IN_SYS |
 412                 SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU |
 413                 EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5);
 414         WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp);
 415         WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp);
 416         WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp);
 417         WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp);
 418         WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp);
 419         WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp);
 420         WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp);
 421         WREG32(VM_CONTEXT0_CNTL, 0);
 422         WREG32(VM_CONTEXT1_CNTL, 0);
 423 }
 424
 425 static void evergreen_mc_stop(struct radeon_device *rdev, struct evergreen_mc_save *save)
 426 {
 427         save->vga_control[0] = RREG32(D1VGA_CONTROL);
 428         save->vga_control[1] = RREG32(D2VGA_CONTROL);
 429         save->vga_control[2] = RREG32(EVERGREEN_D3VGA_CONTROL);
 430         save->vga_control[3] = RREG32(EVERGREEN_D4VGA_CONTROL);
 431         save->vga_control[4] = RREG32(EVERGREEN_D5VGA_CONTROL);
 432         save->vga_control[5] = RREG32(EVERGREEN_D6VGA_CONTROL);
 433         save->vga_render_control = RREG32(VGA_RENDER_CONTROL);
 434         save->vga_hdp_control = RREG32(VGA_HDP_CONTROL);
 435         save->crtc_control[0] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET);
 436         save->crtc_control[1] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
 437         save->crtc_control[2] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET);
 438         save->crtc_control[3] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
 439         save->crtc_control[4] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET);
 440         save->crtc_control[5] = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
 441
 442         /* Stop all video */
 443         WREG32(VGA_RENDER_CONTROL, 0);
 444         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 445         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 446         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 447         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 448         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 449         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 450         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 451         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 452         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 453         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 454         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 455         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 456         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 457         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 458         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 459         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 460         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 461         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 462
 463         WREG32(D1VGA_CONTROL, 0);
 464         WREG32(D2VGA_CONTROL, 0);
 465         WREG32(EVERGREEN_D3VGA_CONTROL, 0);
 466         WREG32(EVERGREEN_D4VGA_CONTROL, 0);
 467         WREG32(EVERGREEN_D5VGA_CONTROL, 0);
 468         WREG32(EVERGREEN_D6VGA_CONTROL, 0);
 469 }
 470
 471 static void evergreen_mc_resume(struct radeon_device *rdev, struct evergreen_mc_save *save)
 472 {
 473         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
 474                upper_32_bits(rdev->mc.vram_start));
 475         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC0_REGISTER_OFFSET,
 476                upper_32_bits(rdev->mc.vram_start));
 477         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
 478                (u32)rdev->mc.vram_start);
 479         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC0_REGISTER_OFFSET,
 480                (u32)rdev->mc.vram_start);
 481
 482         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
 483                upper_32_bits(rdev->mc.vram_start));
 484         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC1_REGISTER_OFFSET,
 485                upper_32_bits(rdev->mc.vram_start));
 486         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
 487                (u32)rdev->mc.vram_start);
 488         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC1_REGISTER_OFFSET,
 489                (u32)rdev->mc.vram_start);
 490
 491         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
 492                upper_32_bits(rdev->mc.vram_start));
 493         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC2_REGISTER_OFFSET,
 494                upper_32_bits(rdev->mc.vram_start));
 495         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
 496                (u32)rdev->mc.vram_start);
 497         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC2_REGISTER_OFFSET,
 498                (u32)rdev->mc.vram_start);
 499
 500         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
 501                upper_32_bits(rdev->mc.vram_start));
 502         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC3_REGISTER_OFFSET,
 503                upper_32_bits(rdev->mc.vram_start));
 504         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
 505                (u32)rdev->mc.vram_start);
 506         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC3_REGISTER_OFFSET,
 507                (u32)rdev->mc.vram_start);
 508
 509         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
 510                upper_32_bits(rdev->mc.vram_start));
 511         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC4_REGISTER_OFFSET,
 512                upper_32_bits(rdev->mc.vram_start));
 513         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
 514                (u32)rdev->mc.vram_start);
 515         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC4_REGISTER_OFFSET,
 516                (u32)rdev->mc.vram_start);
 517
 518         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
 519                upper_32_bits(rdev->mc.vram_start));
 520         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS_HIGH + EVERGREEN_CRTC5_REGISTER_OFFSET,
 521                upper_32_bits(rdev->mc.vram_start));
 522         WREG32(EVERGREEN_GRPH_PRIMARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
 523                (u32)rdev->mc.vram_start);
 524         WREG32(EVERGREEN_GRPH_SECONDARY_SURFACE_ADDRESS + EVERGREEN_CRTC5_REGISTER_OFFSET,
 525                (u32)rdev->mc.vram_start);
 526
 527         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS_HIGH, upper_32_bits(rdev->mc.vram_start));
 528         WREG32(EVERGREEN_VGA_MEMORY_BASE_ADDRESS, (u32)rdev->mc.vram_start);
 529         /* Unlock host access */
 530         WREG32(VGA_HDP_CONTROL, save->vga_hdp_control);
 531         mdelay(1);
 532         /* Restore video state */
 533         WREG32(D1VGA_CONTROL, save->vga_control[0]);
 534         WREG32(D2VGA_CONTROL, save->vga_control[1]);
 535         WREG32(EVERGREEN_D3VGA_CONTROL, save->vga_control[2]);
 536         WREG32(EVERGREEN_D4VGA_CONTROL, save->vga_control[3]);
 537         WREG32(EVERGREEN_D5VGA_CONTROL, save->vga_control[4]);
 538         WREG32(EVERGREEN_D6VGA_CONTROL, save->vga_control[5]);
 539         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 1);
 540         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 1);
 541         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 1);
 542         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 1);
 543         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 1);
 544         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 1);
 545         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, save->crtc_control[0]);
 546         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, save->crtc_control[1]);
 547         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, save->crtc_control[2]);
 548         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, save->crtc_control[3]);
 549         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, save->crtc_control[4]);
 550         WREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, save->crtc_control[5]);
 551         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
 552         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
 553         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
 554         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
 555         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
 556         WREG32(EVERGREEN_CRTC_UPDATE_LOCK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
 557         WREG32(VGA_RENDER_CONTROL, save->vga_render_control);
 558 }
 559
 560 static void evergreen_mc_program(struct radeon_device *rdev)
 561 {
 562         struct evergreen_mc_save save;
 563         u32 tmp;
 564         int i, j;
 565
 566         /* Initialize HDP */
 567         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 568                 WREG32((0x2c14 + j), 0x00000000);
 569                 WREG32((0x2c18 + j), 0x00000000);
 570                 WREG32((0x2c1c + j), 0x00000000);
 571                 WREG32((0x2c20 + j), 0x00000000);
 572                 WREG32((0x2c24 + j), 0x00000000);
 573         }
 574         WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0);
 575
 576         evergreen_mc_stop(rdev, &save);
 577         if (evergreen_mc_wait_for_idle(rdev)) {
 578                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 579         }
 580         /* Lockout access through VGA aperture*/
 581         WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
 582         /* Update configuration */
 583         if (rdev->flags & RADEON_IS_AGP) {
 584                 if (rdev->mc.vram_start < rdev->mc.gtt_start) {
 585                         /* VRAM before AGP */
 586                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 587                                 rdev->mc.vram_start >> 12);
 588                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 589                                 rdev->mc.gtt_end >> 12);
 590                 } else {
 591                         /* VRAM after AGP */
 592                         WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 593                                 rdev->mc.gtt_start >> 12);
 594                         WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 595                                 rdev->mc.vram_end >> 12);
 596                 }
 597         } else {
 598                 WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR,
 599                         rdev->mc.vram_start >> 12);
 600                 WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR,
 601                         rdev->mc.vram_end >> 12);
 602         }
 603         WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0);
 604         tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16;
 605         tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF);
 606         WREG32(MC_VM_FB_LOCATION, tmp);
 607         WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8));
 608         WREG32(HDP_NONSURFACE_INFO, (2 << 7));
 609         WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF);
 610         if (rdev->flags & RADEON_IS_AGP) {
 611                 WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16);
 612                 WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16);
 613                 WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22);
 614         } else {
 615                 WREG32(MC_VM_AGP_BASE, 0);
 616                 WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF);
 617                 WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF);
 618         }
 619         if (evergreen_mc_wait_for_idle(rdev)) {
 620                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
 621         }
 622         evergreen_mc_resume(rdev, &save);
 623         /* we need to own VRAM, so turn off the VGA renderer here
 624          * to stop it overwriting our objects */
 625         rv515_vga_render_disable(rdev);
 626 }
 627
 628 /*
 629  * CP.
 630  */
 631
 632 static int evergreen_cp_load_microcode(struct radeon_device *rdev)
 633 {
 634         const __be32 *fw_data;
 635         int i;
 636
 637         if (!rdev->me_fw || !rdev->pfp_fw)
 638                 return -EINVAL;
 639
 640         r700_cp_stop(rdev);
 641         WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0));
 642
 643         fw_data = (const __be32 *)rdev->pfp_fw->data;
 644         WREG32(CP_PFP_UCODE_ADDR, 0);
 645         for (i = 0; i < EVERGREEN_PFP_UCODE_SIZE; i++)
 646                 WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++));
 647         WREG32(CP_PFP_UCODE_ADDR, 0);
 648
 649         fw_data = (const __be32 *)rdev->me_fw->data;
 650         WREG32(CP_ME_RAM_WADDR, 0);
 651         for (i = 0; i < EVERGREEN_PM4_UCODE_SIZE; i++)
 652                 WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++));
 653
 654         WREG32(CP_PFP_UCODE_ADDR, 0);
 655         WREG32(CP_ME_RAM_WADDR, 0);
 656         WREG32(CP_ME_RAM_RADDR, 0);
 657         return 0;
 658 }
 659
 660 int evergreen_cp_resume(struct radeon_device *rdev)
 661 {
 662         u32 tmp;
 663         u32 rb_bufsz;
 664         int r;
 665
 666         /* Reset cp; if cp is reset, then PA, SH, VGT also need to be reset */
 667         WREG32(GRBM_SOFT_RESET, (SOFT_RESET_CP |
 668                                  SOFT_RESET_PA |
 669                                  SOFT_RESET_SH |
 670                                  SOFT_RESET_VGT |
 671                                  SOFT_RESET_SX));
 672         RREG32(GRBM_SOFT_RESET);
 673         mdelay(15);
 674         WREG32(GRBM_SOFT_RESET, 0);
 675         RREG32(GRBM_SOFT_RESET);
 676
 677         /* Set ring buffer size */
 678         rb_bufsz = drm_order(rdev->cp.ring_size / 8);
 679         tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz;
 680 #ifdef __BIG_ENDIAN
 681         tmp |= BUF_SWAP_32BIT;
 682 #endif
 683         WREG32(CP_RB_CNTL, tmp);
 684         WREG32(CP_SEM_WAIT_TIMER, 0x4);
 685
 686         /* Set the write pointer delay */
 687         WREG32(CP_RB_WPTR_DELAY, 0);
 688
 689         /* Initialize the ring buffer's read and write pointers */
 690         WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA);
 691         WREG32(CP_RB_RPTR_WR, 0);
 692         WREG32(CP_RB_WPTR, 0);
 693         WREG32(CP_RB_RPTR_ADDR, rdev->cp.gpu_addr & 0xFFFFFFFF);
 694         WREG32(CP_RB_RPTR_ADDR_HI, upper_32_bits(rdev->cp.gpu_addr));
 695         mdelay(1);
 696         WREG32(CP_RB_CNTL, tmp);
 697
 698         WREG32(CP_RB_BASE, rdev->cp.gpu_addr >> 8);
 699         WREG32(CP_DEBUG, (1 << 27) | (1 << 28));
 700
 701         rdev->cp.rptr = RREG32(CP_RB_RPTR);
 702         rdev->cp.wptr = RREG32(CP_RB_WPTR);
 703
 704         r600_cp_start(rdev);
 705         rdev->cp.ready = true;
 706         r = radeon_ring_test(rdev);
 707         if (r) {
 708                 rdev->cp.ready = false;
 709                 return r;
 710         }
 711         return 0;
 712 }
 713
 714 /*
 715  * Core functions
 716  */
 717 static u32 evergreen_get_tile_pipe_to_backend_map(struct radeon_device *rdev,
 718                                                   u32 num_tile_pipes,
 719                                                   u32 num_backends,
 720                                                   u32 backend_disable_mask)
 721 {
 722         u32 backend_map = 0;
 723         u32 enabled_backends_mask = 0;
 724         u32 enabled_backends_count = 0;
 725         u32 cur_pipe;
 726         u32 swizzle_pipe[EVERGREEN_MAX_PIPES];
 727         u32 cur_backend = 0;
 728         u32 i;
 729         bool force_no_swizzle;
 730
 731         if (num_tile_pipes > EVERGREEN_MAX_PIPES)
 732                 num_tile_pipes = EVERGREEN_MAX_PIPES;
 733         if (num_tile_pipes < 1)
 734                 num_tile_pipes = 1;
 735         if (num_backends > EVERGREEN_MAX_BACKENDS)
 736                 num_backends = EVERGREEN_MAX_BACKENDS;
 737         if (num_backends < 1)
 738                 num_backends = 1;
 739
 740         for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
 741                 if (((backend_disable_mask >> i) & 1) == 0) {
 742                         enabled_backends_mask |= (1 << i);
 743                         ++enabled_backends_count;
 744                 }
 745                 if (enabled_backends_count == num_backends)
 746                         break;
 747         }
 748
 749         if (enabled_backends_count == 0) {
 750                 enabled_backends_mask = 1;
 751                 enabled_backends_count = 1;
 752         }
 753
 754         if (enabled_backends_count != num_backends)
 755                 num_backends = enabled_backends_count;
 756
 757         memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * EVERGREEN_MAX_PIPES);
 758         switch (rdev->family) {
 759         case CHIP_CEDAR:
 760         case CHIP_REDWOOD:
 761                 force_no_swizzle = false;
 762                 break;
 763         case CHIP_CYPRESS:
 764         case CHIP_HEMLOCK:
 765         case CHIP_JUNIPER:
 766         default:
 767                 force_no_swizzle = true;
 768                 break;
 769         }
 770         if (force_no_swizzle) {
 771                 bool last_backend_enabled = false;
 772
 773                 force_no_swizzle = false;
 774                 for (i = 0; i < EVERGREEN_MAX_BACKENDS; ++i) {
 775                         if (((enabled_backends_mask >> i) & 1) == 1) {
 776                                 if (last_backend_enabled)
 777                                         force_no_swizzle = true;
 778                                 last_backend_enabled = true;
 779                         } else
 780                                 last_backend_enabled = false;
 781                 }
 782         }
 783
 784         switch (num_tile_pipes) {
 785         case 1:
 786         case 3:
 787         case 5:
 788         case 7:
 789                 DRM_ERROR("odd number of pipes!\n");
 790                 break;
 791         case 2:
 792                 swizzle_pipe[0] = 0;
 793                 swizzle_pipe[1] = 1;
 794                 break;
 795         case 4:
 796                 if (force_no_swizzle) {
 797                         swizzle_pipe[0] = 0;
 798                         swizzle_pipe[1] = 1;
 799                         swizzle_pipe[2] = 2;
 800                         swizzle_pipe[3] = 3;
 801                 } else {
 802                         swizzle_pipe[0] = 0;
 803                         swizzle_pipe[1] = 2;
 804                         swizzle_pipe[2] = 1;
 805                         swizzle_pipe[3] = 3;
 806                 }
 807                 break;
 808         case 6:
 809                 if (force_no_swizzle) {
 810                         swizzle_pipe[0] = 0;
 811                         swizzle_pipe[1] = 1;
 812                         swizzle_pipe[2] = 2;
 813                         swizzle_pipe[3] = 3;
 814                         swizzle_pipe[4] = 4;
 815                         swizzle_pipe[5] = 5;
 816                 } else {
 817                         swizzle_pipe[0] = 0;
 818                         swizzle_pipe[1] = 2;
 819                         swizzle_pipe[2] = 4;
 820                         swizzle_pipe[3] = 1;
 821                         swizzle_pipe[4] = 3;
 822                         swizzle_pipe[5] = 5;
 823                 }
 824                 break;
 825         case 8:
 826                 if (force_no_swizzle) {
 827                         swizzle_pipe[0] = 0;
 828                         swizzle_pipe[1] = 1;
 829                         swizzle_pipe[2] = 2;
 830                         swizzle_pipe[3] = 3;
 831                         swizzle_pipe[4] = 4;
 832                         swizzle_pipe[5] = 5;
 833                         swizzle_pipe[6] = 6;
 834                         swizzle_pipe[7] = 7;
 835                 } else {
 836                         swizzle_pipe[0] = 0;
 837                         swizzle_pipe[1] = 2;
 838                         swizzle_pipe[2] = 4;
 839                         swizzle_pipe[3] = 6;
 840                         swizzle_pipe[4] = 1;
 841                         swizzle_pipe[5] = 3;
 842                         swizzle_pipe[6] = 5;
 843                         swizzle_pipe[7] = 7;
 844                 }
 845                 break;
 846         }
 847
 848         for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) {
 849                 while (((1 << cur_backend) & enabled_backends_mask) == 0)
 850                         cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
 851
 852                 backend_map |= (((cur_backend & 0xf) << (swizzle_pipe[cur_pipe] * 4)));
 853
 854                 cur_backend = (cur_backend + 1) % EVERGREEN_MAX_BACKENDS;
 855         }
 856
 857         return backend_map;
 858 }
 859
 860 static void evergreen_gpu_init(struct radeon_device *rdev)
 861 {
 862         u32 cc_rb_backend_disable = 0;
 863         u32 cc_gc_shader_pipe_config;
 864         u32 gb_addr_config = 0;
 865         u32 mc_shared_chmap, mc_arb_ramcfg;
 866         u32 gb_backend_map;
 867         u32 grbm_gfx_index;
 868         u32 sx_debug_1;
 869         u32 smx_dc_ctl0;
 870         u32 sq_config;
 871         u32 sq_lds_resource_mgmt;
 872         u32 sq_gpr_resource_mgmt_1;
 873         u32 sq_gpr_resource_mgmt_2;
 874         u32 sq_gpr_resource_mgmt_3;
 875         u32 sq_thread_resource_mgmt;
 876         u32 sq_thread_resource_mgmt_2;
 877         u32 sq_stack_resource_mgmt_1;
 878         u32 sq_stack_resource_mgmt_2;
 879         u32 sq_stack_resource_mgmt_3;
 880         u32 vgt_cache_invalidation;
 881         u32 hdp_host_path_cntl;
 882         int i, j, num_shader_engines, ps_thread_count;
 883
 884         switch (rdev->family) {
 885         case CHIP_CYPRESS:
 886         case CHIP_HEMLOCK:
 887                 rdev->config.evergreen.num_ses = 2;
 888                 rdev->config.evergreen.max_pipes = 4;
 889                 rdev->config.evergreen.max_tile_pipes = 8;
 890                 rdev->config.evergreen.max_simds = 10;
 891                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
 892                 rdev->config.evergreen.max_gprs = 256;
 893                 rdev->config.evergreen.max_threads = 248;
 894                 rdev->config.evergreen.max_gs_threads = 32;
 895                 rdev->config.evergreen.max_stack_entries = 512;
 896                 rdev->config.evergreen.sx_num_of_sets = 4;
 897                 rdev->config.evergreen.sx_max_export_size = 256;
 898                 rdev->config.evergreen.sx_max_export_pos_size = 64;
 899                 rdev->config.evergreen.sx_max_export_smx_size = 192;
 900                 rdev->config.evergreen.max_hw_contexts = 8;
 901                 rdev->config.evergreen.sq_num_cf_insts = 2;
 902
 903                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
 904                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
 905                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
 906                 break;
 907         case CHIP_JUNIPER:
 908                 rdev->config.evergreen.num_ses = 1;
 909                 rdev->config.evergreen.max_pipes = 4;
 910                 rdev->config.evergreen.max_tile_pipes = 4;
 911                 rdev->config.evergreen.max_simds = 10;
 912                 rdev->config.evergreen.max_backends = 4 * rdev->config.evergreen.num_ses;
 913                 rdev->config.evergreen.max_gprs = 256;
 914                 rdev->config.evergreen.max_threads = 248;
 915                 rdev->config.evergreen.max_gs_threads = 32;
 916                 rdev->config.evergreen.max_stack_entries = 512;
 917                 rdev->config.evergreen.sx_num_of_sets = 4;
 918                 rdev->config.evergreen.sx_max_export_size = 256;
 919                 rdev->config.evergreen.sx_max_export_pos_size = 64;
 920                 rdev->config.evergreen.sx_max_export_smx_size = 192;
 921                 rdev->config.evergreen.max_hw_contexts = 8;
 922                 rdev->config.evergreen.sq_num_cf_insts = 2;
 923
 924                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
 925                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
 926                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
 927                 break;
 928         case CHIP_REDWOOD:
 929                 rdev->config.evergreen.num_ses = 1;
 930                 rdev->config.evergreen.max_pipes = 4;
 931                 rdev->config.evergreen.max_tile_pipes = 4;
 932                 rdev->config.evergreen.max_simds = 5;
 933                 rdev->config.evergreen.max_backends = 2 * rdev->config.evergreen.num_ses;
 934                 rdev->config.evergreen.max_gprs = 256;
 935                 rdev->config.evergreen.max_threads = 248;
 936                 rdev->config.evergreen.max_gs_threads = 32;
 937                 rdev->config.evergreen.max_stack_entries = 256;
 938                 rdev->config.evergreen.sx_num_of_sets = 4;
 939                 rdev->config.evergreen.sx_max_export_size = 256;
 940                 rdev->config.evergreen.sx_max_export_pos_size = 64;
 941                 rdev->config.evergreen.sx_max_export_smx_size = 192;
 942                 rdev->config.evergreen.max_hw_contexts = 8;
 943                 rdev->config.evergreen.sq_num_cf_insts = 2;
 944
 945                 rdev->config.evergreen.sc_prim_fifo_size = 0x100;
 946                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
 947                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
 948                 break;
 949         case CHIP_CEDAR:
 950         default:
 951                 rdev->config.evergreen.num_ses = 1;
 952                 rdev->config.evergreen.max_pipes = 2;
 953                 rdev->config.evergreen.max_tile_pipes = 2;
 954                 rdev->config.evergreen.max_simds = 2;
 955                 rdev->config.evergreen.max_backends = 1 * rdev->config.evergreen.num_ses;
 956                 rdev->config.evergreen.max_gprs = 256;
 957                 rdev->config.evergreen.max_threads = 192;
 958                 rdev->config.evergreen.max_gs_threads = 16;
 959                 rdev->config.evergreen.max_stack_entries = 256;
 960                 rdev->config.evergreen.sx_num_of_sets = 4;
 961                 rdev->config.evergreen.sx_max_export_size = 128;
 962                 rdev->config.evergreen.sx_max_export_pos_size = 32;
 963                 rdev->config.evergreen.sx_max_export_smx_size = 96;
 964                 rdev->config.evergreen.max_hw_contexts = 4;
 965                 rdev->config.evergreen.sq_num_cf_insts = 1;
 966
 967                 rdev->config.evergreen.sc_prim_fifo_size = 0x40;
 968                 rdev->config.evergreen.sc_hiz_tile_fifo_size = 0x30;
 969                 rdev->config.evergreen.sc_earlyz_tile_fifo_size = 0x130;
 970                 break;
 971         }
 972
 973         /* Initialize HDP */
 974         for (i = 0, j = 0; i < 32; i++, j += 0x18) {
 975                 WREG32((0x2c14 + j), 0x00000000);
 976                 WREG32((0x2c18 + j), 0x00000000);
 977                 WREG32((0x2c1c + j), 0x00000000);
 978                 WREG32((0x2c20 + j), 0x00000000);
 979                 WREG32((0x2c24 + j), 0x00000000);
 980         }
 981
 982         WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff));
 983
 984         cc_gc_shader_pipe_config = RREG32(CC_GC_SHADER_PIPE_CONFIG) & ~2;
 985
 986         cc_gc_shader_pipe_config |=
 987                 INACTIVE_QD_PIPES((EVERGREEN_MAX_PIPES_MASK << rdev->config.evergreen.max_pipes)
 988                                   & EVERGREEN_MAX_PIPES_MASK);
 989         cc_gc_shader_pipe_config |=
 990                 INACTIVE_SIMDS((EVERGREEN_MAX_SIMDS_MASK << rdev->config.evergreen.max_simds)
 991                                & EVERGREEN_MAX_SIMDS_MASK);
 992
 993         cc_rb_backend_disable =
 994                 BACKEND_DISABLE((EVERGREEN_MAX_BACKENDS_MASK << rdev->config.evergreen.max_backends)
 995                                 & EVERGREEN_MAX_BACKENDS_MASK);
 996
 997
 998         mc_shared_chmap = RREG32(MC_SHARED_CHMAP);
 999         mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG);
1000
1001         switch (rdev->config.evergreen.max_tile_pipes) {
1002         case 1:
1003         default:
1004                 gb_addr_config |= NUM_PIPES(0);
1005                 break;
1006         case 2:
1007                 gb_addr_config |= NUM_PIPES(1);
1008                 break;
1009         case 4:
1010                 gb_addr_config |= NUM_PIPES(2);
1011                 break;
1012         case 8:
1013                 gb_addr_config |= NUM_PIPES(3);
1014                 break;
1015         }
1016
1017         gb_addr_config |= PIPE_INTERLEAVE_SIZE((mc_arb_ramcfg & BURSTLENGTH_MASK) >> BURSTLENGTH_SHIFT);
1018         gb_addr_config |= BANK_INTERLEAVE_SIZE(0);
1019         gb_addr_config |= NUM_SHADER_ENGINES(rdev->config.evergreen.num_ses - 1);
1020         gb_addr_config |= SHADER_ENGINE_TILE_SIZE(1);
1021         gb_addr_config |= NUM_GPUS(0); /* Hemlock? */
1022         gb_addr_config |= MULTI_GPU_TILE_SIZE(2);
1023
1024         if (((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) > 2)
1025                 gb_addr_config |= ROW_SIZE(2);
1026         else
1027                 gb_addr_config |= ROW_SIZE((mc_arb_ramcfg & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT);
1028
1029         if (rdev->ddev->pdev->device == 0x689e) {
1030                 u32 efuse_straps_4;
1031                 u32 efuse_straps_3;
1032                 u8 efuse_box_bit_131_124;
1033
1034                 WREG32(RCU_IND_INDEX, 0x204);
1035                 efuse_straps_4 = RREG32(RCU_IND_DATA);
1036                 WREG32(RCU_IND_INDEX, 0x203);
1037                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1038                 efuse_box_bit_131_124 = (u8)(((efuse_straps_4 & 0xf) << 4) | ((efuse_straps_3 & 0xf0000000) >> 28));
1039
1040                 switch(efuse_box_bit_131_124) {
1041                 case 0x00:
1042                         gb_backend_map = 0x76543210;
1043                         break;
1044                 case 0x55:
1045                         gb_backend_map = 0x77553311;
1046                         break;
1047                 case 0x56:
1048                         gb_backend_map = 0x77553300;
1049                         break;
1050                 case 0x59:
1051                         gb_backend_map = 0x77552211;
1052                         break;
1053                 case 0x66:
1054                         gb_backend_map = 0x77443300;
1055                         break;
1056                 case 0x99:
1057                         gb_backend_map = 0x66552211;
1058                         break;
1059                 case 0x5a:
1060                         gb_backend_map = 0x77552200;
1061                         break;
1062                 case 0xaa:
1063                         gb_backend_map = 0x66442200;
1064                         break;
1065                 case 0x95:
1066                         gb_backend_map = 0x66553311;
1067                         break;
1068                 default:
1069                         DRM_ERROR("bad backend map, using default\n");
1070                         gb_backend_map =
1071                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1072                                                                        rdev->config.evergreen.max_tile_pipes,
1073                                                                        rdev->config.evergreen.max_backends,
1074                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1075                                                                    rdev->config.evergreen.max_backends) &
1076                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1077                         break;
1078                 }
1079         } else if (rdev->ddev->pdev->device == 0x68b9) {
1080                 u32 efuse_straps_3;
1081                 u8 efuse_box_bit_127_124;
1082
1083                 WREG32(RCU_IND_INDEX, 0x203);
1084                 efuse_straps_3 = RREG32(RCU_IND_DATA);
1085                 efuse_box_bit_127_124 = (u8)(efuse_straps_3 & 0xF0000000) >> 28;
1086
1087                 switch(efuse_box_bit_127_124) {
1088                 case 0x0:
1089                         gb_backend_map = 0x00003210;
1090                         break;
1091                 case 0x5:
1092                 case 0x6:
1093                 case 0x9:
1094                 case 0xa:
1095                         gb_backend_map = 0x00003311;
1096                         break;
1097                 default:
1098                         DRM_ERROR("bad backend map, using default\n");
1099                         gb_backend_map =
1100                                 evergreen_get_tile_pipe_to_backend_map(rdev,
1101                                                                        rdev->config.evergreen.max_tile_pipes,
1102                                                                        rdev->config.evergreen.max_backends,
1103                                                                        ((EVERGREEN_MAX_BACKENDS_MASK <<
1104                                                                    rdev->config.evergreen.max_backends) &
1105                                                                         EVERGREEN_MAX_BACKENDS_MASK));
1106                         break;
1107                 }
1108         } else
1109                 gb_backend_map =
1110                         evergreen_get_tile_pipe_to_backend_map(rdev,
1111                                                                rdev->config.evergreen.max_tile_pipes,
1112                                                                rdev->config.evergreen.max_backends,
1113                                                                ((EVERGREEN_MAX_BACKENDS_MASK <<
1114                                                                  rdev->config.evergreen.max_backends) &
1115                                                                 EVERGREEN_MAX_BACKENDS_MASK));
1116
1117         WREG32(GB_BACKEND_MAP, gb_backend_map);
1118         WREG32(GB_ADDR_CONFIG, gb_addr_config);
1119         WREG32(DMIF_ADDR_CONFIG, gb_addr_config);
1120         WREG32(HDP_ADDR_CONFIG, gb_addr_config);
1121
1122         num_shader_engines = ((RREG32(GB_ADDR_CONFIG) & NUM_SHADER_ENGINES(3)) >> 12) + 1;
1123         grbm_gfx_index = INSTANCE_BROADCAST_WRITES;
1124
1125         for (i = 0; i < rdev->config.evergreen.num_ses; i++) {
1126                 u32 rb = cc_rb_backend_disable | (0xf0 << 16);
1127                 u32 sp = cc_gc_shader_pipe_config;
1128                 u32 gfx = grbm_gfx_index | SE_INDEX(i);
1129
1130                 if (i == num_shader_engines) {
1131                         rb |= BACKEND_DISABLE(EVERGREEN_MAX_BACKENDS_MASK);
1132                         sp |= INACTIVE_SIMDS(EVERGREEN_MAX_SIMDS_MASK);
1133                 }
1134
1135                 WREG32(GRBM_GFX_INDEX, gfx);
1136                 WREG32(RLC_GFX_INDEX, gfx);
1137
1138                 WREG32(CC_RB_BACKEND_DISABLE, rb);
1139                 WREG32(CC_SYS_RB_BACKEND_DISABLE, rb);
1140                 WREG32(GC_USER_RB_BACKEND_DISABLE, rb);
1141                 WREG32(CC_GC_SHADER_PIPE_CONFIG, sp);
1142         }
1143
1144         grbm_gfx_index |= SE_BROADCAST_WRITES;
1145         WREG32(GRBM_GFX_INDEX, grbm_gfx_index);
1146         WREG32(RLC_GFX_INDEX, grbm_gfx_index);
1147
1148         WREG32(CGTS_SYS_TCC_DISABLE, 0);
1149         WREG32(CGTS_TCC_DISABLE, 0);
1150         WREG32(CGTS_USER_SYS_TCC_DISABLE, 0);
1151         WREG32(CGTS_USER_TCC_DISABLE, 0);
1152
1153         /* set HW defaults for 3D engine */
1154         WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) |
1155                                      ROQ_IB2_START(0x2b)));
1156
1157         WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30));
1158
1159         WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO |
1160                              SYNC_GRADIENT |
1161                              SYNC_WALKER |
1162                              SYNC_ALIGNER));
1163
1164         sx_debug_1 = RREG32(SX_DEBUG_1);
1165         sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS;
1166         WREG32(SX_DEBUG_1, sx_debug_1);
1167
1168
1169         smx_dc_ctl0 = RREG32(SMX_DC_CTL0);
1170         smx_dc_ctl0 &= ~NUMBER_OF_SETS(0x1ff);
1171         smx_dc_ctl0 |= NUMBER_OF_SETS(rdev->config.evergreen.sx_num_of_sets);
1172         WREG32(SMX_DC_CTL0, smx_dc_ctl0);
1173
1174         WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_size / 4) - 1) |
1175                                         POSITION_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_pos_size / 4) - 1) |
1176                                         SMX_BUFFER_SIZE((rdev->config.evergreen.sx_max_export_smx_size / 4) - 1)));
1177
1178         WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.evergreen.sc_prim_fifo_size) |
1179                                  SC_HIZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_hiz_tile_fifo_size) |
1180                                  SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.evergreen.sc_earlyz_tile_fifo_size)));
1181
1182         WREG32(VGT_NUM_INSTANCES, 1);
1183         WREG32(SPI_CONFIG_CNTL, 0);
1184         WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4));
1185         WREG32(CP_PERFMON_CNTL, 0);
1186
1187         WREG32(SQ_MS_FIFO_SIZES, (CACHE_FIFO_SIZE(16 * rdev->config.evergreen.sq_num_cf_insts) |
1188                                   FETCH_FIFO_HIWATER(0x4) |
1189                                   DONE_FIFO_HIWATER(0xe0) |
1190                                   ALU_UPDATE_FIFO_HIWATER(0x8)));
1191
1192         sq_config = RREG32(SQ_CONFIG);
1193         sq_config &= ~(PS_PRIO(3) |
1194                        VS_PRIO(3) |
1195                        GS_PRIO(3) |
1196                        ES_PRIO(3));
1197         sq_config |= (VC_ENABLE |
1198                       EXPORT_SRC_C |
1199                       PS_PRIO(0) |
1200                       VS_PRIO(1) |
1201                       GS_PRIO(2) |
1202                       ES_PRIO(3));
1203
1204         if (rdev->family == CHIP_CEDAR)
1205                 /* no vertex cache */
1206                 sq_config &= ~VC_ENABLE;
1207
1208         sq_lds_resource_mgmt = RREG32(SQ_LDS_RESOURCE_MGMT);
1209
1210         sq_gpr_resource_mgmt_1 = NUM_PS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2))* 12 / 32);
1211         sq_gpr_resource_mgmt_1 |= NUM_VS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 6 / 32);
1212         sq_gpr_resource_mgmt_1 |= NUM_CLAUSE_TEMP_GPRS(4);
1213         sq_gpr_resource_mgmt_2 = NUM_GS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1214         sq_gpr_resource_mgmt_2 |= NUM_ES_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 4 / 32);
1215         sq_gpr_resource_mgmt_3 = NUM_HS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1216         sq_gpr_resource_mgmt_3 |= NUM_LS_GPRS((rdev->config.evergreen.max_gprs - (4 * 2)) * 3 / 32);
1217
1218         if (rdev->family == CHIP_CEDAR)
1219                 ps_thread_count = 96;
1220         else
1221                 ps_thread_count = 128;
1222
1223         sq_thread_resource_mgmt = NUM_PS_THREADS(ps_thread_count);
1224         sq_thread_resource_mgmt |= NUM_VS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1225         sq_thread_resource_mgmt |= NUM_GS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1226         sq_thread_resource_mgmt |= NUM_ES_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1227         sq_thread_resource_mgmt_2 = NUM_HS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1228         sq_thread_resource_mgmt_2 |= NUM_LS_THREADS(((rdev->config.evergreen.max_threads - ps_thread_count) / 6) / 8) * 8;
1229
1230         sq_stack_resource_mgmt_1 = NUM_PS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1231         sq_stack_resource_mgmt_1 |= NUM_VS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1232         sq_stack_resource_mgmt_2 = NUM_GS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1233         sq_stack_resource_mgmt_2 |= NUM_ES_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1234         sq_stack_resource_mgmt_3 = NUM_HS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1235         sq_stack_resource_mgmt_3 |= NUM_LS_STACK_ENTRIES((rdev->config.evergreen.max_stack_entries * 1) / 6);
1236
1237         WREG32(SQ_CONFIG, sq_config);
1238         WREG32(SQ_GPR_RESOURCE_MGMT_1, sq_gpr_resource_mgmt_1);
1239         WREG32(SQ_GPR_RESOURCE_MGMT_2, sq_gpr_resource_mgmt_2);
1240         WREG32(SQ_GPR_RESOURCE_MGMT_3, sq_gpr_resource_mgmt_3);
1241         WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt);
1242         WREG32(SQ_THREAD_RESOURCE_MGMT_2, sq_thread_resource_mgmt_2);
1243         WREG32(SQ_STACK_RESOURCE_MGMT_1, sq_stack_resource_mgmt_1);
1244         WREG32(SQ_STACK_RESOURCE_MGMT_2, sq_stack_resource_mgmt_2);
1245         WREG32(SQ_STACK_RESOURCE_MGMT_3, sq_stack_resource_mgmt_3);
1246         WREG32(SQ_DYN_GPR_CNTL_PS_FLUSH_REQ, 0);
1247         WREG32(SQ_LDS_RESOURCE_MGMT, sq_lds_resource_mgmt);
1248
1249         WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) |
1250                                           FORCE_EOV_MAX_REZ_CNT(255)));
1251
1252         if (rdev->family == CHIP_CEDAR)
1253                 vgt_cache_invalidation = CACHE_INVALIDATION(TC_ONLY);
1254         else
1255                 vgt_cache_invalidation = CACHE_INVALIDATION(VC_AND_TC);
1256         vgt_cache_invalidation |= AUTO_INVLD_EN(ES_AND_GS_AUTO);
1257         WREG32(VGT_CACHE_INVALIDATION, vgt_cache_invalidation);
1258
1259         WREG32(VGT_GS_VERTEX_REUSE, 16);
1260         WREG32(PA_SC_LINE_STIPPLE_STATE, 0);
1261
1262         WREG32(CB_PERF_CTR0_SEL_0, 0);
1263         WREG32(CB_PERF_CTR0_SEL_1, 0);
1264         WREG32(CB_PERF_CTR1_SEL_0, 0);
1265         WREG32(CB_PERF_CTR1_SEL_1, 0);
1266         WREG32(CB_PERF_CTR2_SEL_0, 0);
1267         WREG32(CB_PERF_CTR2_SEL_1, 0);
1268         WREG32(CB_PERF_CTR3_SEL_0, 0);
1269         WREG32(CB_PERF_CTR3_SEL_1, 0);
1270
1271         hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL);
1272         WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl);
1273
1274         WREG32(PA_CL_ENHANCE, CLIP_VTX_REORDER_ENA | NUM_CLIP_SEQ(3));
1275
1276         udelay(50);
1277
1278 }
1279
1280 int evergreen_mc_init(struct radeon_device *rdev)
1281 {
1282         u32 tmp;
1283         int chansize, numchan;
1284
1285         /* Get VRAM informations */
1286         rdev->mc.vram_is_ddr = true;
1287         tmp = RREG32(MC_ARB_RAMCFG);
1288         if (tmp & CHANSIZE_OVERRIDE) {
1289                 chansize = 16;
1290         } else if (tmp & CHANSIZE_MASK) {
1291                 chansize = 64;
1292         } else {
1293                 chansize = 32;
1294         }
1295         tmp = RREG32(MC_SHARED_CHMAP);
1296         switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) {
1297         case 0:
1298         default:
1299                 numchan = 1;
1300                 break;
1301         case 1:
1302                 numchan = 2;
1303                 break;
1304         case 2:
1305                 numchan = 4;
1306                 break;
1307         case 3:
1308                 numchan = 8;
1309                 break;
1310         }
1311         rdev->mc.vram_width = numchan * chansize;
1312         /* Could aper size report 0 ? */
1313         rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0);
1314         rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0);
1315         /* Setup GPU memory space */
1316         /* size in MB on evergreen */
1317         rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1318         rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE) * 1024 * 1024;
1319         rdev->mc.visible_vram_size = rdev->mc.aper_size;
1320         r600_vram_gtt_location(rdev, &rdev->mc);
1321         radeon_update_bandwidth_info(rdev);
1322
1323         return 0;
1324 }
1325
1326 bool evergreen_gpu_is_lockup(struct radeon_device *rdev)
1327 {
1328         /* FIXME: implement for evergreen */
1329         return false;
1330 }
1331
1332 static int evergreen_gpu_soft_reset(struct radeon_device *rdev)
1333 {
1334         struct evergreen_mc_save save;
1335         u32 srbm_reset = 0;
1336         u32 grbm_reset = 0;
1337
1338         dev_info(rdev->dev, "GPU softreset \n");
1339         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1340                 RREG32(GRBM_STATUS));
1341         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1342                 RREG32(GRBM_STATUS_SE0));
1343         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1344                 RREG32(GRBM_STATUS_SE1));
1345         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1346                 RREG32(SRBM_STATUS));
1347         evergreen_mc_stop(rdev, &save);
1348         if (evergreen_mc_wait_for_idle(rdev)) {
1349                 dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
1350         }
1351         /* Disable CP parsing/prefetching */
1352         WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT);
1353
1354         /* reset all the gfx blocks */
1355         grbm_reset = (SOFT_RESET_CP |
1356                       SOFT_RESET_CB |
1357                       SOFT_RESET_DB |
1358                       SOFT_RESET_PA |
1359                       SOFT_RESET_SC |
1360                       SOFT_RESET_SPI |
1361                       SOFT_RESET_SH |
1362                       SOFT_RESET_SX |
1363                       SOFT_RESET_TC |
1364                       SOFT_RESET_TA |
1365                       SOFT_RESET_VC |
1366                       SOFT_RESET_VGT);
1367
1368         dev_info(rdev->dev, "  GRBM_SOFT_RESET=0x%08X\n", grbm_reset);
1369         WREG32(GRBM_SOFT_RESET, grbm_reset);
1370         (void)RREG32(GRBM_SOFT_RESET);
1371         udelay(50);
1372         WREG32(GRBM_SOFT_RESET, 0);
1373         (void)RREG32(GRBM_SOFT_RESET);
1374
1375         /* reset all the system blocks */
1376         srbm_reset = SRBM_SOFT_RESET_ALL_MASK;
1377
1378         dev_info(rdev->dev, "  SRBM_SOFT_RESET=0x%08X\n", srbm_reset);
1379         WREG32(SRBM_SOFT_RESET, srbm_reset);
1380         (void)RREG32(SRBM_SOFT_RESET);
1381         udelay(50);
1382         WREG32(SRBM_SOFT_RESET, 0);
1383         (void)RREG32(SRBM_SOFT_RESET);
1384         /* Wait a little for things to settle down */
1385         udelay(50);
1386         dev_info(rdev->dev, "  GRBM_STATUS=0x%08X\n",
1387                 RREG32(GRBM_STATUS));
1388         dev_info(rdev->dev, "  GRBM_STATUS_SE0=0x%08X\n",
1389                 RREG32(GRBM_STATUS_SE0));
1390         dev_info(rdev->dev, "  GRBM_STATUS_SE1=0x%08X\n",
1391                 RREG32(GRBM_STATUS_SE1));
1392         dev_info(rdev->dev, "  SRBM_STATUS=0x%08X\n",
1393                 RREG32(SRBM_STATUS));
1394         /* After reset we need to reinit the asic as GPU often endup in an
1395          * incoherent state.
1396          */
1397         atom_asic_init(rdev->mode_info.atom_context);
1398         evergreen_mc_resume(rdev, &save);
1399         return 0;
1400 }
1401
1402 int evergreen_asic_reset(struct radeon_device *rdev)
1403 {
1404         return evergreen_gpu_soft_reset(rdev);
1405 }
1406
1407 /* Interrupts */
1408
1409 u32 evergreen_get_vblank_counter(struct radeon_device *rdev, int crtc)
1410 {
1411         switch (crtc) {
1412         case 0:
1413                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC0_REGISTER_OFFSET);
1414         case 1:
1415                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC1_REGISTER_OFFSET);
1416         case 2:
1417                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC2_REGISTER_OFFSET);
1418         case 3:
1419                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC3_REGISTER_OFFSET);
1420         case 4:
1421                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC4_REGISTER_OFFSET);
1422         case 5:
1423                 return RREG32(CRTC_STATUS_FRAME_COUNT + EVERGREEN_CRTC5_REGISTER_OFFSET);
1424         default:
1425                 return 0;
1426         }
1427 }
1428
1429 void evergreen_disable_interrupt_state(struct radeon_device *rdev)
1430 {
1431         u32 tmp;
1432
1433         WREG32(CP_INT_CNTL, 0);
1434         WREG32(GRBM_INT_CNTL, 0);
1435         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1436         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1437         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1438         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1439         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1440         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1441
1442         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET, 0);
1443         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET, 0);
1444         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET, 0);
1445         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET, 0);
1446         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET, 0);
1447         WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0);
1448
1449         WREG32(DACA_AUTODETECT_INT_CONTROL, 0);
1450         WREG32(DACB_AUTODETECT_INT_CONTROL, 0);
1451
1452         tmp = RREG32(DC_HPD1_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1453         WREG32(DC_HPD1_INT_CONTROL, tmp);
1454         tmp = RREG32(DC_HPD2_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1455         WREG32(DC_HPD2_INT_CONTROL, tmp);
1456         tmp = RREG32(DC_HPD3_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1457         WREG32(DC_HPD3_INT_CONTROL, tmp);
1458         tmp = RREG32(DC_HPD4_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1459         WREG32(DC_HPD4_INT_CONTROL, tmp);
1460         tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1461         WREG32(DC_HPD5_INT_CONTROL, tmp);
1462         tmp = RREG32(DC_HPD6_INT_CONTROL) & DC_HPDx_INT_POLARITY;
1463         WREG32(DC_HPD6_INT_CONTROL, tmp);
1464
1465 }
1466
1467 int evergreen_irq_set(struct radeon_device *rdev)
1468 {
1469         u32 cp_int_cntl = CNTX_BUSY_INT_ENABLE | CNTX_EMPTY_INT_ENABLE;
1470         u32 crtc1 = 0, crtc2 = 0, crtc3 = 0, crtc4 = 0, crtc5 = 0, crtc6 = 0;
1471         u32 hpd1, hpd2, hpd3, hpd4, hpd5, hpd6;
1472         u32 grbm_int_cntl = 0;
1473
1474         if (!rdev->irq.installed) {
1475                 WARN(1, "Can't enable IRQ/MSI because no handler is installed.\n");
1476                 return -EINVAL;
1477         }
1478         /* don't enable anything if the ih is disabled */
1479         if (!rdev->ih.enabled) {
1480                 r600_disable_interrupts(rdev);
1481                 /* force the active interrupt state to all disabled */
1482                 evergreen_disable_interrupt_state(rdev);
1483                 return 0;
1484         }
1485
1486         hpd1 = RREG32(DC_HPD1_INT_CONTROL) & ~DC_HPDx_INT_EN;
1487         hpd2 = RREG32(DC_HPD2_INT_CONTROL) & ~DC_HPDx_INT_EN;
1488         hpd3 = RREG32(DC_HPD3_INT_CONTROL) & ~DC_HPDx_INT_EN;
1489         hpd4 = RREG32(DC_HPD4_INT_CONTROL) & ~DC_HPDx_INT_EN;
1490         hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN;
1491         hpd6 = RREG32(DC_HPD6_INT_CONTROL) & ~DC_HPDx_INT_EN;
1492
1493         if (rdev->irq.sw_int) {
1494                 DRM_DEBUG("evergreen_irq_set: sw int\n");
1495                 cp_int_cntl |= RB_INT_ENABLE;
1496         }
1497         if (rdev->irq.crtc_vblank_int[0]) {
1498                 DRM_DEBUG("evergreen_irq_set: vblank 0\n");
1499                 crtc1 |= VBLANK_INT_MASK;
1500         }
1501         if (rdev->irq.crtc_vblank_int[1]) {
1502                 DRM_DEBUG("evergreen_irq_set: vblank 1\n");
1503                 crtc2 |= VBLANK_INT_MASK;
1504         }
1505         if (rdev->irq.crtc_vblank_int[2]) {
1506                 DRM_DEBUG("evergreen_irq_set: vblank 2\n");
1507                 crtc3 |= VBLANK_INT_MASK;
1508         }
1509         if (rdev->irq.crtc_vblank_int[3]) {
1510                 DRM_DEBUG("evergreen_irq_set: vblank 3\n");
1511                 crtc4 |= VBLANK_INT_MASK;
1512         }
1513         if (rdev->irq.crtc_vblank_int[4]) {
1514                 DRM_DEBUG("evergreen_irq_set: vblank 4\n");
1515                 crtc5 |= VBLANK_INT_MASK;
1516         }
1517         if (rdev->irq.crtc_vblank_int[5]) {
1518                 DRM_DEBUG("evergreen_irq_set: vblank 5\n");
1519                 crtc6 |= VBLANK_INT_MASK;
1520         }
1521         if (rdev->irq.hpd[0]) {
1522                 DRM_DEBUG("evergreen_irq_set: hpd 1\n");
1523                 hpd1 |= DC_HPDx_INT_EN;
1524         }
1525         if (rdev->irq.hpd[1]) {
1526                 DRM_DEBUG("evergreen_irq_set: hpd 2\n");
1527                 hpd2 |= DC_HPDx_INT_EN;
1528         }
1529         if (rdev->irq.hpd[2]) {
1530                 DRM_DEBUG("evergreen_irq_set: hpd 3\n");
1531                 hpd3 |= DC_HPDx_INT_EN;
1532         }
1533         if (rdev->irq.hpd[3]) {
1534                 DRM_DEBUG("evergreen_irq_set: hpd 4\n");
1535                 hpd4 |= DC_HPDx_INT_EN;
1536         }
1537         if (rdev->irq.hpd[4]) {
1538                 DRM_DEBUG("evergreen_irq_set: hpd 5\n");
1539                 hpd5 |= DC_HPDx_INT_EN;
1540         }
1541         if (rdev->irq.hpd[5]) {
1542                 DRM_DEBUG("evergreen_irq_set: hpd 6\n");
1543                 hpd6 |= DC_HPDx_INT_EN;
1544         }
1545         if (rdev->irq.gui_idle) {
1546                 DRM_DEBUG("gui idle\n");
1547                 grbm_int_cntl |= GUI_IDLE_INT_ENABLE;
1548         }
1549
1550         WREG32(CP_INT_CNTL, cp_int_cntl);
1551         WREG32(GRBM_INT_CNTL, grbm_int_cntl);
1552
1553         WREG32(INT_MASK + EVERGREEN_CRTC0_REGISTER_OFFSET, crtc1);
1554         WREG32(INT_MASK + EVERGREEN_CRTC1_REGISTER_OFFSET, crtc2);
1555         WREG32(INT_MASK + EVERGREEN_CRTC2_REGISTER_OFFSET, crtc3);
1556         WREG32(INT_MASK + EVERGREEN_CRTC3_REGISTER_OFFSET, crtc4);
1557         WREG32(INT_MASK + EVERGREEN_CRTC4_REGISTER_OFFSET, crtc5);
1558         WREG32(INT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6);
1559
1560         WREG32(DC_HPD1_INT_CONTROL, hpd1);
1561         WREG32(DC_HPD2_INT_CONTROL, hpd2);
1562         WREG32(DC_HPD3_INT_CONTROL, hpd3);
1563         WREG32(DC_HPD4_INT_CONTROL, hpd4);
1564         WREG32(DC_HPD5_INT_CONTROL, hpd5);
1565         WREG32(DC_HPD6_INT_CONTROL, hpd6);
1566
1567         return 0;
1568 }
1569
1570 static inline void evergreen_irq_ack(struct radeon_device *rdev,
1571                                      u32 *disp_int,
1572                                      u32 *disp_int_cont,
1573                                      u32 *disp_int_cont2,
1574                                      u32 *disp_int_cont3,
1575                                      u32 *disp_int_cont4,
1576                                      u32 *disp_int_cont5)
1577 {
1578         u32 tmp;
1579
1580         *disp_int = RREG32(DISP_INTERRUPT_STATUS);
1581         *disp_int_cont = RREG32(DISP_INTERRUPT_STATUS_CONTINUE);
1582         *disp_int_cont2 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE2);
1583         *disp_int_cont3 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE3);
1584         *disp_int_cont4 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE4);
1585         *disp_int_cont5 = RREG32(DISP_INTERRUPT_STATUS_CONTINUE5);
1586
1587         if (*disp_int & LB_D1_VBLANK_INTERRUPT)
1588                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VBLANK_ACK);
1589         if (*disp_int & LB_D1_VLINE_INTERRUPT)
1590                 WREG32(VLINE_STATUS + EVERGREEN_CRTC0_REGISTER_OFFSET, VLINE_ACK);
1591
1592         if (*disp_int_cont & LB_D2_VBLANK_INTERRUPT)
1593                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VBLANK_ACK);
1594         if (*disp_int_cont & LB_D2_VLINE_INTERRUPT)
1595                 WREG32(VLINE_STATUS + EVERGREEN_CRTC1_REGISTER_OFFSET, VLINE_ACK);
1596
1597         if (*disp_int_cont2 & LB_D3_VBLANK_INTERRUPT)
1598                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VBLANK_ACK);
1599         if (*disp_int_cont2 & LB_D3_VLINE_INTERRUPT)
1600                 WREG32(VLINE_STATUS + EVERGREEN_CRTC2_REGISTER_OFFSET, VLINE_ACK);
1601
1602         if (*disp_int_cont3 & LB_D4_VBLANK_INTERRUPT)
1603                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VBLANK_ACK);
1604         if (*disp_int_cont3 & LB_D4_VLINE_INTERRUPT)
1605                 WREG32(VLINE_STATUS + EVERGREEN_CRTC3_REGISTER_OFFSET, VLINE_ACK);
1606
1607         if (*disp_int_cont4 & LB_D5_VBLANK_INTERRUPT)
1608                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VBLANK_ACK);
1609         if (*disp_int_cont4 & LB_D5_VLINE_INTERRUPT)
1610                 WREG32(VLINE_STATUS + EVERGREEN_CRTC4_REGISTER_OFFSET, VLINE_ACK);
1611
1612         if (*disp_int_cont5 & LB_D6_VBLANK_INTERRUPT)
1613                 WREG32(VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK);
1614         if (*disp_int_cont5 & LB_D6_VLINE_INTERRUPT)
1615                 WREG32(VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK);
1616
1617         if (*disp_int & DC_HPD1_INTERRUPT) {
1618                 tmp = RREG32(DC_HPD1_INT_CONTROL);
1619                 tmp |= DC_HPDx_INT_ACK;
1620                 WREG32(DC_HPD1_INT_CONTROL, tmp);
1621         }
1622         if (*disp_int_cont & DC_HPD2_INTERRUPT) {
1623                 tmp = RREG32(DC_HPD2_INT_CONTROL);
1624                 tmp |= DC_HPDx_INT_ACK;
1625                 WREG32(DC_HPD2_INT_CONTROL, tmp);
1626         }
1627         if (*disp_int_cont2 & DC_HPD3_INTERRUPT) {
1628                 tmp = RREG32(DC_HPD3_INT_CONTROL);
1629                 tmp |= DC_HPDx_INT_ACK;
1630                 WREG32(DC_HPD3_INT_CONTROL, tmp);
1631         }
1632         if (*disp_int_cont3 & DC_HPD4_INTERRUPT) {
1633                 tmp = RREG32(DC_HPD4_INT_CONTROL);
1634                 tmp |= DC_HPDx_INT_ACK;
1635                 WREG32(DC_HPD4_INT_CONTROL, tmp);
1636         }
1637         if (*disp_int_cont4 & DC_HPD5_INTERRUPT) {
1638                 tmp = RREG32(DC_HPD5_INT_CONTROL);
1639                 tmp |= DC_HPDx_INT_ACK;
1640                 WREG32(DC_HPD5_INT_CONTROL, tmp);
1641         }
1642         if (*disp_int_cont5 & DC_HPD6_INTERRUPT) {
1643                 tmp = RREG32(DC_HPD5_INT_CONTROL);
1644                 tmp |= DC_HPDx_INT_ACK;
1645                 WREG32(DC_HPD6_INT_CONTROL, tmp);
1646         }
1647 }
1648
1649 void evergreen_irq_disable(struct radeon_device *rdev)
1650 {
1651         u32 disp_int, disp_int_cont, disp_int_cont2;
1652         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1653
1654         r600_disable_interrupts(rdev);
1655         /* Wait and acknowledge irq */
1656         mdelay(1);
1657         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1658                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1659         evergreen_disable_interrupt_state(rdev);
1660 }
1661
1662 static void evergreen_irq_suspend(struct radeon_device *rdev)
1663 {
1664         evergreen_irq_disable(rdev);
1665         r600_rlc_stop(rdev);
1666 }
1667
1668 static inline u32 evergreen_get_ih_wptr(struct radeon_device *rdev)
1669 {
1670         u32 wptr, tmp;
1671
1672         /* XXX use writeback */
1673         wptr = RREG32(IH_RB_WPTR);
1674
1675         if (wptr & RB_OVERFLOW) {
1676                 /* When a ring buffer overflow happen start parsing interrupt
1677                  * from the last not overwritten vector (wptr + 16). Hopefully
1678                  * this should allow us to catchup.
1679                  */
1680                 dev_warn(rdev->dev, "IH ring buffer overflow (0x%08X, %d, %d)\n",
1681                         wptr, rdev->ih.rptr, (wptr + 16) + rdev->ih.ptr_mask);
1682                 rdev->ih.rptr = (wptr + 16) & rdev->ih.ptr_mask;
1683                 tmp = RREG32(IH_RB_CNTL);
1684                 tmp |= IH_WPTR_OVERFLOW_CLEAR;
1685                 WREG32(IH_RB_CNTL, tmp);
1686         }
1687         return (wptr & rdev->ih.ptr_mask);
1688 }
1689
1690 int evergreen_irq_process(struct radeon_device *rdev)
1691 {
1692         u32 wptr = evergreen_get_ih_wptr(rdev);
1693         u32 rptr = rdev->ih.rptr;
1694         u32 src_id, src_data;
1695         u32 ring_index;
1696         u32 disp_int, disp_int_cont, disp_int_cont2;
1697         u32 disp_int_cont3, disp_int_cont4, disp_int_cont5;
1698         unsigned long flags;
1699         bool queue_hotplug = false;
1700
1701         DRM_DEBUG("r600_irq_process start: rptr %d, wptr %d\n", rptr, wptr);
1702         if (!rdev->ih.enabled)
1703                 return IRQ_NONE;
1704
1705         spin_lock_irqsave(&rdev->ih.lock, flags);
1706
1707         if (rptr == wptr) {
1708                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1709                 return IRQ_NONE;
1710         }
1711         if (rdev->shutdown) {
1712                 spin_unlock_irqrestore(&rdev->ih.lock, flags);
1713                 return IRQ_NONE;
1714         }
1715
1716 restart_ih:
1717         /* display interrupts */
1718         evergreen_irq_ack(rdev, &disp_int, &disp_int_cont, &disp_int_cont2,
1719                           &disp_int_cont3, &disp_int_cont4, &disp_int_cont5);
1720
1721         rdev->ih.wptr = wptr;
1722         while (rptr != wptr) {
1723                 /* wptr/rptr are in bytes! */
1724                 ring_index = rptr / 4;
1725                 src_id =  rdev->ih.ring[ring_index] & 0xff;
1726                 src_data = rdev->ih.ring[ring_index + 1] & 0xfffffff;
1727
1728                 switch (src_id) {
1729                 case 1: /* D1 vblank/vline */
1730                         switch (src_data) {
1731                         case 0: /* D1 vblank */
1732                                 if (disp_int & LB_D1_VBLANK_INTERRUPT) {
1733                                         drm_handle_vblank(rdev->ddev, 0);
1734                                         wake_up(&rdev->irq.vblank_queue);
1735                                         disp_int &= ~LB_D1_VBLANK_INTERRUPT;
1736                                         DRM_DEBUG("IH: D1 vblank\n");
1737                                 }
1738                                 break;
1739                         case 1: /* D1 vline */
1740                                 if (disp_int & LB_D1_VLINE_INTERRUPT) {
1741                                         disp_int &= ~LB_D1_VLINE_INTERRUPT;
1742                                         DRM_DEBUG("IH: D1 vline\n");
1743                                 }
1744                                 break;
1745                         default:
1746                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1747                                 break;
1748                         }
1749                         break;
1750                 case 2: /* D2 vblank/vline */
1751                         switch (src_data) {
1752                         case 0: /* D2 vblank */
1753                                 if (disp_int_cont & LB_D2_VBLANK_INTERRUPT) {
1754                                         drm_handle_vblank(rdev->ddev, 1);
1755                                         wake_up(&rdev->irq.vblank_queue);
1756                                         disp_int_cont &= ~LB_D2_VBLANK_INTERRUPT;
1757                                         DRM_DEBUG("IH: D2 vblank\n");
1758                                 }
1759                                 break;
1760                         case 1: /* D2 vline */
1761                                 if (disp_int_cont & LB_D2_VLINE_INTERRUPT) {
1762                                         disp_int_cont &= ~LB_D2_VLINE_INTERRUPT;
1763                                         DRM_DEBUG("IH: D2 vline\n");
1764                                 }
1765                                 break;
1766                         default:
1767                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1768                                 break;
1769                         }
1770                         break;
1771                 case 3: /* D3 vblank/vline */
1772                         switch (src_data) {
1773                         case 0: /* D3 vblank */
1774                                 if (disp_int_cont2 & LB_D3_VBLANK_INTERRUPT) {
1775                                         drm_handle_vblank(rdev->ddev, 2);
1776                                         wake_up(&rdev->irq.vblank_queue);
1777                                         disp_int_cont2 &= ~LB_D3_VBLANK_INTERRUPT;
1778                                         DRM_DEBUG("IH: D3 vblank\n");
1779                                 }
1780                                 break;
1781                         case 1: /* D3 vline */
1782                                 if (disp_int_cont2 & LB_D3_VLINE_INTERRUPT) {
1783                                         disp_int_cont2 &= ~LB_D3_VLINE_INTERRUPT;
1784                                         DRM_DEBUG("IH: D3 vline\n");
1785                                 }
1786                                 break;
1787                         default:
1788                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1789                                 break;
1790                         }
1791                         break;
1792                 case 4: /* D4 vblank/vline */
1793                         switch (src_data) {
1794                         case 0: /* D4 vblank */
1795                                 if (disp_int_cont3 & LB_D4_VBLANK_INTERRUPT) {
1796                                         drm_handle_vblank(rdev->ddev, 3);
1797                                         wake_up(&rdev->irq.vblank_queue);
1798                                         disp_int_cont3 &= ~LB_D4_VBLANK_INTERRUPT;
1799                                         DRM_DEBUG("IH: D4 vblank\n");
1800                                 }
1801                                 break;
1802                         case 1: /* D4 vline */
1803                                 if (disp_int_cont3 & LB_D4_VLINE_INTERRUPT) {
1804                                         disp_int_cont3 &= ~LB_D4_VLINE_INTERRUPT;
1805                                         DRM_DEBUG("IH: D4 vline\n");
1806                                 }
1807                                 break;
1808                         default:
1809                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1810                                 break;
1811                         }
1812                         break;
1813                 case 5: /* D5 vblank/vline */
1814                         switch (src_data) {
1815                         case 0: /* D5 vblank */
1816                                 if (disp_int_cont4 & LB_D5_VBLANK_INTERRUPT) {
1817                                         drm_handle_vblank(rdev->ddev, 4);
1818                                         wake_up(&rdev->irq.vblank_queue);
1819                                         disp_int_cont4 &= ~LB_D5_VBLANK_INTERRUPT;
1820                                         DRM_DEBUG("IH: D5 vblank\n");
1821                                 }
1822                                 break;
1823                         case 1: /* D5 vline */
1824                                 if (disp_int_cont4 & LB_D5_VLINE_INTERRUPT) {
1825                                         disp_int_cont4 &= ~LB_D5_VLINE_INTERRUPT;
1826                                         DRM_DEBUG("IH: D5 vline\n");
1827                                 }
1828                                 break;
1829                         default:
1830                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1831                                 break;
1832                         }
1833                         break;
1834                 case 6: /* D6 vblank/vline */
1835                         switch (src_data) {
1836                         case 0: /* D6 vblank */
1837                                 if (disp_int_cont5 & LB_D6_VBLANK_INTERRUPT) {
1838                                         drm_handle_vblank(rdev->ddev, 5);
1839                                         wake_up(&rdev->irq.vblank_queue);
1840                                         disp_int_cont5 &= ~LB_D6_VBLANK_INTERRUPT;
1841                                         DRM_DEBUG("IH: D6 vblank\n");
1842                                 }
1843                                 break;
1844                         case 1: /* D6 vline */
1845                                 if (disp_int_cont5 & LB_D6_VLINE_INTERRUPT) {
1846                                         disp_int_cont5 &= ~LB_D6_VLINE_INTERRUPT;
1847                                         DRM_DEBUG("IH: D6 vline\n");
1848                                 }
1849                                 break;
1850                         default:
1851                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1852                                 break;
1853                         }
1854                         break;
1855                 case 42: /* HPD hotplug */
1856                         switch (src_data) {
1857                         case 0:
1858                                 if (disp_int & DC_HPD1_INTERRUPT) {
1859                                         disp_int &= ~DC_HPD1_INTERRUPT;
1860                                         queue_hotplug = true;
1861                                         DRM_DEBUG("IH: HPD1\n");
1862                                 }
1863                                 break;
1864                         case 1:
1865                                 if (disp_int_cont & DC_HPD2_INTERRUPT) {
1866                                         disp_int_cont &= ~DC_HPD2_INTERRUPT;
1867                                         queue_hotplug = true;
1868                                         DRM_DEBUG("IH: HPD2\n");
1869                                 }
1870                                 break;
1871                         case 2:
1872                                 if (disp_int_cont2 & DC_HPD3_INTERRUPT) {
1873                                         disp_int_cont2 &= ~DC_HPD3_INTERRUPT;
1874                                         queue_hotplug = true;
1875                                         DRM_DEBUG("IH: HPD3\n");
1876                                 }
1877                                 break;
1878                         case 3:
1879                                 if (disp_int_cont3 & DC_HPD4_INTERRUPT) {
1880                                         disp_int_cont3 &= ~DC_HPD4_INTERRUPT;
1881                                         queue_hotplug = true;
1882                                         DRM_DEBUG("IH: HPD4\n");
1883                                 }
1884                                 break;
1885                         case 4:
1886                                 if (disp_int_cont4 & DC_HPD5_INTERRUPT) {
1887                                         disp_int_cont4 &= ~DC_HPD5_INTERRUPT;
1888                                         queue_hotplug = true;
1889                                         DRM_DEBUG("IH: HPD5\n");
1890                                 }
1891                                 break;
1892                         case 5:
1893                                 if (disp_int_cont5 & DC_HPD6_INTERRUPT) {
1894                                         disp_int_cont5 &= ~DC_HPD6_INTERRUPT;
1895                                         queue_hotplug = true;
1896                                         DRM_DEBUG("IH: HPD6\n");
1897                                 }
1898                                 break;
1899                         default:
1900                                 DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1901                                 break;
1902                         }
1903                         break;
1904                 case 176: /* CP_INT in ring buffer */
1905                 case 177: /* CP_INT in IB1 */
1906                 case 178: /* CP_INT in IB2 */
1907                         DRM_DEBUG("IH: CP int: 0x%08x\n", src_data);
1908                         radeon_fence_process(rdev);
1909                         break;
1910                 case 181: /* CP EOP event */
1911                         DRM_DEBUG("IH: CP EOP\n");
1912                         break;
1913                 case 233: /* GUI IDLE */
1914                         DRM_DEBUG("IH: CP EOP\n");
1915                         rdev->pm.gui_idle = true;
1916                         wake_up(&rdev->irq.idle_queue);
1917                         break;
1918                 default:
1919                         DRM_DEBUG("Unhandled interrupt: %d %d\n", src_id, src_data);
1920                         break;
1921                 }
1922
1923                 /* wptr/rptr are in bytes! */
1924                 rptr += 16;
1925                 rptr &= rdev->ih.ptr_mask;
1926         }
1927         /* make sure wptr hasn't changed while processing */
1928         wptr = evergreen_get_ih_wptr(rdev);
1929         if (wptr != rdev->ih.wptr)
1930                 goto restart_ih;
1931         if (queue_hotplug)
1932                 queue_work(rdev->wq, &rdev->hotplug_work);
1933         rdev->ih.rptr = rptr;
1934         WREG32(IH_RB_RPTR, rdev->ih.rptr);
1935         spin_unlock_irqrestore(&rdev->ih.lock, flags);
1936         return IRQ_HANDLED;
1937 }
1938
1939 static int evergreen_startup(struct radeon_device *rdev)
1940 {
1941         int r;
1942
1943         if (!rdev->me_fw || !rdev->pfp_fw || !rdev->rlc_fw) {
1944                 r = r600_init_microcode(rdev);
1945                 if (r) {
1946                         DRM_ERROR("Failed to load firmware!\n");
1947                         return r;
1948                 }
1949         }
1950
1951         evergreen_mc_program(rdev);
1952         if (rdev->flags & RADEON_IS_AGP) {
1953                 evergreen_agp_enable(rdev);
1954         } else {
1955                 r = evergreen_pcie_gart_enable(rdev);
1956                 if (r)
1957                         return r;
1958         }
1959         evergreen_gpu_init(rdev);
1960 #if 0
1961         if (!rdev->r600_blit.shader_obj) {
1962                 r = r600_blit_init(rdev);
1963                 if (r) {
1964                         DRM_ERROR("radeon: failed blitter (%d).\n", r);
1965                         return r;
1966                 }
1967         }
1968
1969         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
1970         if (unlikely(r != 0))
1971                 return r;
1972         r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM,
1973                         &rdev->r600_blit.shader_gpu_addr);
1974         radeon_bo_unreserve(rdev->r600_blit.shader_obj);
1975         if (r) {
1976                 DRM_ERROR("failed to pin blit object %d\n", r);
1977                 return r;
1978         }
1979 #endif
1980
1981         /* Enable IRQ */
1982         r = r600_irq_init(rdev);
1983         if (r) {
1984                 DRM_ERROR("radeon: IH init failed (%d).\n", r);
1985                 radeon_irq_kms_fini(rdev);
1986                 return r;
1987         }
1988         evergreen_irq_set(rdev);
1989
1990         r = radeon_ring_init(rdev, rdev->cp.ring_size);
1991         if (r)
1992                 return r;
1993         r = evergreen_cp_load_microcode(rdev);
1994         if (r)
1995                 return r;
1996         r = evergreen_cp_resume(rdev);
1997         if (r)
1998                 return r;
1999         /* write back buffer are not vital so don't worry about failure */
2000         r600_wb_enable(rdev);
2001
2002         return 0;
2003 }
2004
2005 int evergreen_resume(struct radeon_device *rdev)
2006 {
2007         int r;
2008
2009         /* Do not reset GPU before posting, on rv770 hw unlike on r500 hw,
2010          * posting will perform necessary task to bring back GPU into good
2011          * shape.
2012          */
2013         /* post card */
2014         atom_asic_init(rdev->mode_info.atom_context);
2015         /* Initialize clocks */
2016         r = radeon_clocks_init(rdev);
2017         if (r) {
2018                 return r;
2019         }
2020
2021         r = evergreen_startup(rdev);
2022         if (r) {
2023                 DRM_ERROR("r600 startup failed on resume\n");
2024                 return r;
2025         }
2026
2027         r = r600_ib_test(rdev);
2028         if (r) {
2029                 DRM_ERROR("radeon: failled testing IB (%d).\n", r);
2030                 return r;
2031         }
2032
2033         return r;
2034
2035 }
2036
2037 int evergreen_suspend(struct radeon_device *rdev)
2038 {
2039 #if 0
2040         int r;
2041 #endif
2042         /* FIXME: we should wait for ring to be empty */
2043         r700_cp_stop(rdev);
2044         rdev->cp.ready = false;
2045         evergreen_irq_suspend(rdev);
2046         r600_wb_disable(rdev);
2047         evergreen_pcie_gart_disable(rdev);
2048 #if 0
2049         /* unpin shaders bo */
2050         r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false);
2051         if (likely(r == 0)) {
2052                 radeon_bo_unpin(rdev->r600_blit.shader_obj);
2053                 radeon_bo_unreserve(rdev->r600_blit.shader_obj);
2054         }
2055 #endif
2056         return 0;
2057 }
2058
2059 static bool evergreen_card_posted(struct radeon_device *rdev)
2060 {
2061         u32 reg;
2062
2063         /* first check CRTCs */
2064         reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
2065                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) |
2066                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
2067                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) |
2068                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
2069                 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
2070         if (reg & EVERGREEN_CRTC_MASTER_EN)
2071                 return true;
2072
2073         /* then check MEM_SIZE, in case the crtcs are off */
2074         if (RREG32(CONFIG_MEMSIZE))
2075                 return true;
2076
2077         return false;
2078 }
2079
2080 /* Plan is to move initialization in that function and use
2081  * helper function so that radeon_device_init pretty much
2082  * do nothing more than calling asic specific function. This
2083  * should also allow to remove a bunch of callback function
2084  * like vram_info.
2085  */
2086 int evergreen_init(struct radeon_device *rdev)
2087 {
2088         int r;
2089
2090         r = radeon_dummy_page_init(rdev);
2091         if (r)
2092                 return r;
2093         /* This don't do much */
2094         r = radeon_gem_init(rdev);
2095         if (r)
2096                 return r;
2097         /* Read BIOS */
2098         if (!radeon_get_bios(rdev)) {
2099                 if (ASIC_IS_AVIVO(rdev))
2100                         return -EINVAL;
2101         }
2102         /* Must be an ATOMBIOS */
2103         if (!rdev->is_atom_bios) {
2104                 dev_err(rdev->dev, "Expecting atombios for R600 GPU\n");
2105                 return -EINVAL;
2106         }
2107         r = radeon_atombios_init(rdev);
2108         if (r)
2109                 return r;
2110         /* Post card if necessary */
2111         if (!evergreen_card_posted(rdev)) {
2112                 if (!rdev->bios) {
2113                         dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
2114                         return -EINVAL;
2115                 }
2116                 DRM_INFO("GPU not posted. posting now...\n");
2117                 atom_asic_init(rdev->mode_info.atom_context);
2118         }
2119         /* Initialize scratch registers */
2120         r600_scratch_init(rdev);
2121         /* Initialize surface registers */
2122         radeon_surface_init(rdev);
2123         /* Initialize clocks */
2124         radeon_get_clock_info(rdev->ddev);
2125         r = radeon_clocks_init(rdev);
2126         if (r)
2127                 return r;
2128         /* Fence driver */
2129         r = radeon_fence_driver_init(rdev);
2130         if (r)
2131                 return r;
2132         /* initialize AGP */
2133         if (rdev->flags & RADEON_IS_AGP) {
2134                 r = radeon_agp_init(rdev);
2135                 if (r)
2136                         radeon_agp_disable(rdev);
2137         }
2138         /* initialize memory controller */
2139         r = evergreen_mc_init(rdev);
2140         if (r)
2141                 return r;
2142         /* Memory manager */
2143         r = radeon_bo_init(rdev);
2144         if (r)
2145                 return r;
2146
2147         r = radeon_irq_kms_init(rdev);
2148         if (r)
2149                 return r;
2150
2151         rdev->cp.ring_obj = NULL;
2152         r600_ring_init(rdev, 1024 * 1024);
2153
2154         rdev->ih.ring_obj = NULL;
2155         r600_ih_ring_init(rdev, 64 * 1024);
2156
2157         r = r600_pcie_gart_init(rdev);
2158         if (r)
2159                 return r;
2160
2161         rdev->accel_working = true;
2162         r = evergreen_startup(rdev);
2163         if (r) {
2164                 dev_err(rdev->dev, "disabling GPU acceleration\n");
2165                 r700_cp_fini(rdev);
2166                 r600_wb_fini(rdev);
2167                 r600_irq_fini(rdev);
2168                 radeon_irq_kms_fini(rdev);
2169                 evergreen_pcie_gart_fini(rdev);
2170                 rdev->accel_working = false;
2171         }
2172         if (rdev->accel_working) {
2173                 r = radeon_ib_pool_init(rdev);
2174                 if (r) {
2175                         DRM_ERROR("radeon: failed initializing IB pool (%d).\n", r);
2176                         rdev->accel_working = false;
2177                 }
2178                 r = r600_ib_test(rdev);
2179                 if (r) {
2180                         DRM_ERROR("radeon: failed testing IB (%d).\n", r);
2181                         rdev->accel_working = false;
2182                 }
2183         }
2184         return 0;
2185 }
2186
2187 void evergreen_fini(struct radeon_device *rdev)
2188 {
2189         /*r600_blit_fini(rdev);*/
2190         r700_cp_fini(rdev);
2191         r600_wb_fini(rdev);
2192         r600_irq_fini(rdev);
2193         radeon_irq_kms_fini(rdev);
2194         evergreen_pcie_gart_fini(rdev);
2195         radeon_gem_fini(rdev);
2196         radeon_fence_driver_fini(rdev);
2197         radeon_clocks_fini(rdev);
2198         radeon_agp_fini(rdev);
2199         radeon_bo_fini(rdev);
2200         radeon_atombios_fini(rdev);
2201         kfree(rdev->bios);
2202         rdev->bios = NULL;
2203         radeon_dummy_page_fini(rdev);
2204 }