SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/nouveau/nouveau_irq.c

   1 /*
   2  * Copyright (C) 2006 Ben Skeggs.
   3  *
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining
   7  * a copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sublicense, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial
  16  * portions of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  19  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  20  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
  21  * IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
  22  * LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
  23  * OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
  24  * WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  */
  27
  28 /*
  29  * Authors:
  30  *   Ben Skeggs <darktama@iinet.net.au>
  31  */
  32
  33 #include "drmP.h"
  34 #include "drm.h"
  35 #include "nouveau_drm.h"
  36 #include "nouveau_drv.h"
  37 #include "nouveau_reg.h"
  38 #include <linux/ratelimit.h>
  39
  40 /* needed for hotplug irq */
  41 #include "nouveau_connector.h"
  42 #include "nv50_display.h"
  43
  44 void
  45 nouveau_irq_preinstall(struct drm_device *dev)
  46 {
  47         struct drm_nouveau_private *dev_priv = dev->dev_private;
  48
  49         /* Master disable */
  50         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
  51
  52         if (dev_priv->card_type == NV_50) {
  53                 INIT_WORK(&dev_priv->irq_work, nv50_display_irq_handler_bh);
  54                 INIT_LIST_HEAD(&dev_priv->vbl_waiting);
  55         }
  56 }
  57
  58 int
  59 nouveau_irq_postinstall(struct drm_device *dev)
  60 {
  61         /* Master enable */
  62         nv_wr32(dev, NV03_PMC_INTR_EN_0, NV_PMC_INTR_EN_0_MASTER_ENABLE);
  63         return 0;
  64 }
  65
  66 void
  67 nouveau_irq_uninstall(struct drm_device *dev)
  68 {
  69         /* Master disable */
  70         nv_wr32(dev, NV03_PMC_INTR_EN_0, 0);
  71 }
  72
  73 static int
  74 nouveau_call_method(struct nouveau_channel *chan, int class, int mthd, int data)
  75 {
  76         struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
  77         struct nouveau_pgraph_object_method *grm;
  78         struct nouveau_pgraph_object_class *grc;
  79
  80         grc = dev_priv->engine.graph.grclass;
  81         while (grc->id) {
  82                 if (grc->id == class)
  83                         break;
  84                 grc++;
  85         }
  86
  87         if (grc->id != class || !grc->methods)
  88                 return -ENOENT;
  89
  90         grm = grc->methods;
  91         while (grm->id) {
  92                 if (grm->id == mthd)
  93                         return grm->exec(chan, class, mthd, data);
  94                 grm++;
  95         }
  96
  97         return -ENOENT;
  98 }
  99
 100 static bool
 101 nouveau_fifo_swmthd(struct nouveau_channel *chan, uint32_t addr, uint32_t data)
 102 {
 103         struct drm_device *dev = chan->dev;
 104         const int subc = (addr >> 13) & 0x7;
 105         const int mthd = addr & 0x1ffc;
 106
 107         if (mthd == 0x0000) {
 108                 struct nouveau_gpuobj_ref *ref = NULL;
 109
 110                 if (nouveau_gpuobj_ref_find(chan, data, &ref))
 111                         return false;
 112
 113                 if (ref->gpuobj->engine != NVOBJ_ENGINE_SW)
 114                         return false;
 115
 116                 chan->sw_subchannel[subc] = ref->gpuobj->class;
 117                 nv_wr32(dev, NV04_PFIFO_CACHE1_ENGINE, nv_rd32(dev,
 118                         NV04_PFIFO_CACHE1_ENGINE) & ~(0xf << subc * 4));
 119                 return true;
 120         }
 121
 122         /* hw object */
 123         if (nv_rd32(dev, NV04_PFIFO_CACHE1_ENGINE) & (1 << (subc*4)))
 124                 return false;
 125
 126         if (nouveau_call_method(chan, chan->sw_subchannel[subc], mthd, data))
 127                 return false;
 128
 129         return true;
 130 }
 131
 132 static void
 133 nouveau_fifo_irq_handler(struct drm_device *dev)
 134 {
 135         struct drm_nouveau_private *dev_priv = dev->dev_private;
 136         struct nouveau_engine *engine = &dev_priv->engine;
 137         uint32_t status, reassign;
 138         int cnt = 0;
 139
 140         reassign = nv_rd32(dev, NV03_PFIFO_CACHES) & 1;
 141         while ((status = nv_rd32(dev, NV03_PFIFO_INTR_0)) && (cnt++ < 100)) {
 142                 struct nouveau_channel *chan = NULL;
 143                 uint32_t chid, get;
 144
 145                 nv_wr32(dev, NV03_PFIFO_CACHES, 0);
 146
 147                 chid = engine->fifo.channel_id(dev);
 148                 if (chid >= 0 && chid < engine->fifo.channels)
 149                         chan = dev_priv->fifos[chid];
 150                 get  = nv_rd32(dev, NV03_PFIFO_CACHE1_GET);
 151
 152                 if (status & NV_PFIFO_INTR_CACHE_ERROR) {
 153                         uint32_t mthd, data;
 154                         int ptr;
 155
 156                         /* NV_PFIFO_CACHE1_GET actually goes to 0xffc before
 157                          * wrapping on my G80 chips, but CACHE1 isn't big
 158                          * enough for this much data.. Tests show that it
 159                          * wraps around to the start at GET=0x800.. No clue
 160                          * as to why..
 161                          */
 162                         ptr = (get & 0x7ff) >> 2;
 163
 164                         if (dev_priv->card_type < NV_40) {
 165                                 mthd = nv_rd32(dev,
 166                                         NV04_PFIFO_CACHE1_METHOD(ptr));
 167                                 data = nv_rd32(dev,
 168                                         NV04_PFIFO_CACHE1_DATA(ptr));
 169                         } else {
 170                                 mthd = nv_rd32(dev,
 171                                         NV40_PFIFO_CACHE1_METHOD(ptr));
 172                                 data = nv_rd32(dev,
 173                                         NV40_PFIFO_CACHE1_DATA(ptr));
 174                         }
 175
 176                         if (!chan || !nouveau_fifo_swmthd(chan, mthd, data)) {
 177                                 NV_INFO(dev, "PFIFO_CACHE_ERROR - Ch %d/%d "
 178                                              "Mthd 0x%04x Data 0x%08x\n",
 179                                         chid, (mthd >> 13) & 7, mthd & 0x1ffc,
 180                                         data);
 181                         }
 182
 183                         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH, 0);
 184                         nv_wr32(dev, NV03_PFIFO_INTR_0,
 185                                                 NV_PFIFO_INTR_CACHE_ERROR);
 186
 187                         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
 188                                 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) & ~1);
 189                         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
 190                         nv_wr32(dev, NV03_PFIFO_CACHE1_PUSH0,
 191                                 nv_rd32(dev, NV03_PFIFO_CACHE1_PUSH0) | 1);
 192                         nv_wr32(dev, NV04_PFIFO_CACHE1_HASH, 0);
 193
 194                         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_PUSH,
 195                                 nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUSH) | 1);
 196                         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
 197
 198                         status &= ~NV_PFIFO_INTR_CACHE_ERROR;
 199                 }
 200
 201                 if (status & NV_PFIFO_INTR_DMA_PUSHER) {
 202                         NV_INFO(dev, "PFIFO_DMA_PUSHER - Ch %d\n", chid);
 203
 204                         status &= ~NV_PFIFO_INTR_DMA_PUSHER;
 205                         nv_wr32(dev, NV03_PFIFO_INTR_0,
 206                                                 NV_PFIFO_INTR_DMA_PUSHER);
 207
 208                         nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_STATE, 0x00000000);
 209                         if (nv_rd32(dev, NV04_PFIFO_CACHE1_DMA_PUT) != get)
 210                                 nv_wr32(dev, NV04_PFIFO_CACHE1_DMA_GET,
 211                                                                 get + 4);
 212                 }
 213
 214                 if (status & NV_PFIFO_INTR_SEMAPHORE) {
 215                         uint32_t sem;
 216
 217                         status &= ~NV_PFIFO_INTR_SEMAPHORE;
 218                         nv_wr32(dev, NV03_PFIFO_INTR_0,
 219                                 NV_PFIFO_INTR_SEMAPHORE);
 220
 221                         sem = nv_rd32(dev, NV10_PFIFO_CACHE1_SEMAPHORE);
 222                         nv_wr32(dev, NV10_PFIFO_CACHE1_SEMAPHORE, sem | 0x1);
 223
 224                         nv_wr32(dev, NV03_PFIFO_CACHE1_GET, get + 4);
 225                         nv_wr32(dev, NV04_PFIFO_CACHE1_PULL0, 1);
 226                 }
 227
 228                 if (status) {
 229                         NV_INFO(dev, "PFIFO_INTR 0x%08x - Ch %d\n",
 230                                 status, chid);
 231                         nv_wr32(dev, NV03_PFIFO_INTR_0, status);
 232                         status = 0;
 233                 }
 234
 235                 nv_wr32(dev, NV03_PFIFO_CACHES, reassign);
 236         }
 237
 238         if (status) {
 239                 NV_INFO(dev, "PFIFO still angry after %d spins, halt\n", cnt);
 240                 nv_wr32(dev, 0x2140, 0);
 241                 nv_wr32(dev, 0x140, 0);
 242         }
 243
 244         nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PFIFO_PENDING);
 245 }
 246
 247 struct nouveau_bitfield_names {
 248         uint32_t mask;
 249         const char *name;
 250 };
 251
 252 static struct nouveau_bitfield_names nstatus_names[] =
 253 {
 254         { NV04_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 255         { NV04_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 256         { NV04_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 257         { NV04_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 258 };
 259
 260 static struct nouveau_bitfield_names nstatus_names_nv10[] =
 261 {
 262         { NV10_PGRAPH_NSTATUS_STATE_IN_USE,       "STATE_IN_USE" },
 263         { NV10_PGRAPH_NSTATUS_INVALID_STATE,      "INVALID_STATE" },
 264         { NV10_PGRAPH_NSTATUS_BAD_ARGUMENT,       "BAD_ARGUMENT" },
 265         { NV10_PGRAPH_NSTATUS_PROTECTION_FAULT,   "PROTECTION_FAULT" }
 266 };
 267
 268 static struct nouveau_bitfield_names nsource_names[] =
 269 {
 270         { NV03_PGRAPH_NSOURCE_NOTIFICATION,       "NOTIFICATION" },
 271         { NV03_PGRAPH_NSOURCE_DATA_ERROR,         "DATA_ERROR" },
 272         { NV03_PGRAPH_NSOURCE_PROTECTION_ERROR,   "PROTECTION_ERROR" },
 273         { NV03_PGRAPH_NSOURCE_RANGE_EXCEPTION,    "RANGE_EXCEPTION" },
 274         { NV03_PGRAPH_NSOURCE_LIMIT_COLOR,        "LIMIT_COLOR" },
 275         { NV03_PGRAPH_NSOURCE_LIMIT_ZETA,         "LIMIT_ZETA" },
 276         { NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD,       "ILLEGAL_MTHD" },
 277         { NV03_PGRAPH_NSOURCE_DMA_R_PROTECTION,   "DMA_R_PROTECTION" },
 278         { NV03_PGRAPH_NSOURCE_DMA_W_PROTECTION,   "DMA_W_PROTECTION" },
 279         { NV03_PGRAPH_NSOURCE_FORMAT_EXCEPTION,   "FORMAT_EXCEPTION" },
 280         { NV03_PGRAPH_NSOURCE_PATCH_EXCEPTION,    "PATCH_EXCEPTION" },
 281         { NV03_PGRAPH_NSOURCE_STATE_INVALID,      "STATE_INVALID" },
 282         { NV03_PGRAPH_NSOURCE_DOUBLE_NOTIFY,      "DOUBLE_NOTIFY" },
 283         { NV03_PGRAPH_NSOURCE_NOTIFY_IN_USE,      "NOTIFY_IN_USE" },
 284         { NV03_PGRAPH_NSOURCE_METHOD_CNT,         "METHOD_CNT" },
 285         { NV03_PGRAPH_NSOURCE_BFR_NOTIFICATION,   "BFR_NOTIFICATION" },
 286         { NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION, "DMA_VTX_PROTECTION" },
 287         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_A,        "DMA_WIDTH_A" },
 288         { NV03_PGRAPH_NSOURCE_DMA_WIDTH_B,        "DMA_WIDTH_B" },
 289 };
 290
 291 static void
 292 nouveau_print_bitfield_names_(uint32_t value,
 293                                 const struct nouveau_bitfield_names *namelist,
 294                                 const int namelist_len)
 295 {
 296         /*
 297          * Caller must have already printed the KERN_* log level for us.
 298          * Also the caller is responsible for adding the newline.
 299          */
 300         int i;
 301         for (i = 0; i < namelist_len; ++i) {
 302                 uint32_t mask = namelist[i].mask;
 303                 if (value & mask) {
 304                         printk(" %s", namelist[i].name);
 305                         value &= ~mask;
 306                 }
 307         }
 308         if (value)
 309                 printk(" (unknown bits 0x%08x)", value);
 310 }
 311 #define nouveau_print_bitfield_names(val, namelist) \
 312         nouveau_print_bitfield_names_((val), (namelist), ARRAY_SIZE(namelist))
 313
 314 struct nouveau_enum_names {
 315         uint32_t value;
 316         const char *name;
 317 };
 318
 319 static void
 320 nouveau_print_enum_names_(uint32_t value,
 321                                 const struct nouveau_enum_names *namelist,
 322                                 const int namelist_len)
 323 {
 324         /*
 325          * Caller must have already printed the KERN_* log level for us.
 326          * Also the caller is responsible for adding the newline.
 327          */
 328         int i;
 329         for (i = 0; i < namelist_len; ++i) {
 330                 if (value == namelist[i].value) {
 331                         printk("%s", namelist[i].name);
 332                         return;
 333                 }
 334         }
 335         printk("unknown value 0x%08x", value);
 336 }
 337 #define nouveau_print_enum_names(val, namelist) \
 338         nouveau_print_enum_names_((val), (namelist), ARRAY_SIZE(namelist))
 339
 340 static int
 341 nouveau_graph_chid_from_grctx(struct drm_device *dev)
 342 {
 343         struct drm_nouveau_private *dev_priv = dev->dev_private;
 344         uint32_t inst;
 345         int i;
 346
 347         if (dev_priv->card_type < NV_40)
 348                 return dev_priv->engine.fifo.channels;
 349         else
 350         if (dev_priv->card_type < NV_50) {
 351                 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 4;
 352
 353                 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 354                         struct nouveau_channel *chan = dev_priv->fifos[i];
 355
 356                         if (!chan || !chan->ramin_grctx)
 357                                 continue;
 358
 359                         if (inst == chan->ramin_grctx->instance)
 360                                 break;
 361                 }
 362         } else {
 363                 inst = (nv_rd32(dev, 0x40032c) & 0xfffff) << 12;
 364
 365                 for (i = 0; i < dev_priv->engine.fifo.channels; i++) {
 366                         struct nouveau_channel *chan = dev_priv->fifos[i];
 367
 368                         if (!chan || !chan->ramin)
 369                                 continue;
 370
 371                         if (inst == chan->ramin->instance)
 372                                 break;
 373                 }
 374         }
 375
 376
 377         return i;
 378 }
 379
 380 static int
 381 nouveau_graph_trapped_channel(struct drm_device *dev, int *channel_ret)
 382 {
 383         struct drm_nouveau_private *dev_priv = dev->dev_private;
 384         struct nouveau_engine *engine = &dev_priv->engine;
 385         int channel;
 386
 387         if (dev_priv->card_type < NV_10)
 388                 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 24) & 0xf;
 389         else
 390         if (dev_priv->card_type < NV_40)
 391                 channel = (nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR) >> 20) & 0x1f;
 392         else
 393                 channel = nouveau_graph_chid_from_grctx(dev);
 394
 395         if (channel >= engine->fifo.channels || !dev_priv->fifos[channel]) {
 396                 NV_ERROR(dev, "AIII, invalid/inactive channel id %d\n", channel);
 397                 return -EINVAL;
 398         }
 399
 400         *channel_ret = channel;
 401         return 0;
 402 }
 403
 404 struct nouveau_pgraph_trap {
 405         int channel;
 406         int class;
 407         int subc, mthd, size;
 408         uint32_t data, data2;
 409         uint32_t nsource, nstatus;
 410 };
 411
 412 static void
 413 nouveau_graph_trap_info(struct drm_device *dev,
 414                         struct nouveau_pgraph_trap *trap)
 415 {
 416         struct drm_nouveau_private *dev_priv = dev->dev_private;
 417         uint32_t address;
 418
 419         trap->nsource = trap->nstatus = 0;
 420         if (dev_priv->card_type < NV_50) {
 421                 trap->nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 422                 trap->nstatus = nv_rd32(dev, NV03_PGRAPH_NSTATUS);
 423         }
 424
 425         if (nouveau_graph_trapped_channel(dev, &trap->channel))
 426                 trap->channel = -1;
 427         address = nv_rd32(dev, NV04_PGRAPH_TRAPPED_ADDR);
 428
 429         trap->mthd = address & 0x1FFC;
 430         trap->data = nv_rd32(dev, NV04_PGRAPH_TRAPPED_DATA);
 431         if (dev_priv->card_type < NV_10) {
 432                 trap->subc  = (address >> 13) & 0x7;
 433         } else {
 434                 trap->subc  = (address >> 16) & 0x7;
 435                 trap->data2 = nv_rd32(dev, NV10_PGRAPH_TRAPPED_DATA_HIGH);
 436         }
 437
 438         if (dev_priv->card_type < NV_10)
 439                 trap->class = nv_rd32(dev, 0x400180 + trap->subc*4) & 0xFF;
 440         else if (dev_priv->card_type < NV_40)
 441                 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFF;
 442         else if (dev_priv->card_type < NV_50)
 443                 trap->class = nv_rd32(dev, 0x400160 + trap->subc*4) & 0xFFFF;
 444         else
 445                 trap->class = nv_rd32(dev, 0x400814);
 446 }
 447
 448 static void
 449 nouveau_graph_dump_trap_info(struct drm_device *dev, const char *id,
 450                              struct nouveau_pgraph_trap *trap)
 451 {
 452         struct drm_nouveau_private *dev_priv = dev->dev_private;
 453         uint32_t nsource = trap->nsource, nstatus = trap->nstatus;
 454
 455         if (dev_priv->card_type < NV_50) {
 456                 NV_INFO(dev, "%s - nSource:", id);
 457                 nouveau_print_bitfield_names(nsource, nsource_names);
 458                 printk(", nStatus:");
 459                 if (dev_priv->card_type < NV_10)
 460                         nouveau_print_bitfield_names(nstatus, nstatus_names);
 461                 else
 462                         nouveau_print_bitfield_names(nstatus, nstatus_names_nv10);
 463                 printk("\n");
 464         }
 465
 466         NV_INFO(dev, "%s - Ch %d/%d Class 0x%04x Mthd 0x%04x "
 467                                         "Data 0x%08x:0x%08x\n",
 468                                         id, trap->channel, trap->subc,
 469                                         trap->class, trap->mthd,
 470                                         trap->data2, trap->data);
 471 }
 472
 473 static int
 474 nouveau_pgraph_intr_swmthd(struct drm_device *dev,
 475                            struct nouveau_pgraph_trap *trap)
 476 {
 477         struct drm_nouveau_private *dev_priv = dev->dev_private;
 478
 479         if (trap->channel < 0 ||
 480             trap->channel >= dev_priv->engine.fifo.channels ||
 481             !dev_priv->fifos[trap->channel])
 482                 return -ENODEV;
 483
 484         return nouveau_call_method(dev_priv->fifos[trap->channel],
 485                                    trap->class, trap->mthd, trap->data);
 486 }
 487
 488 static inline void
 489 nouveau_pgraph_intr_notify(struct drm_device *dev, uint32_t nsource)
 490 {
 491         struct nouveau_pgraph_trap trap;
 492         int unhandled = 0;
 493
 494         nouveau_graph_trap_info(dev, &trap);
 495
 496         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 497                 if (nouveau_pgraph_intr_swmthd(dev, &trap))
 498                         unhandled = 1;
 499         } else {
 500                 unhandled = 1;
 501         }
 502
 503         if (unhandled)
 504                 nouveau_graph_dump_trap_info(dev, "PGRAPH_NOTIFY", &trap);
 505 }
 506
 507 static DEFINE_RATELIMIT_STATE(nouveau_ratelimit_state, 3 * HZ, 20);
 508
 509 static int nouveau_ratelimit(void)
 510 {
 511         return __ratelimit(&nouveau_ratelimit_state);
 512 }
 513
 514
 515 static inline void
 516 nouveau_pgraph_intr_error(struct drm_device *dev, uint32_t nsource)
 517 {
 518         struct nouveau_pgraph_trap trap;
 519         int unhandled = 0;
 520
 521         nouveau_graph_trap_info(dev, &trap);
 522         trap.nsource = nsource;
 523
 524         if (nsource & NV03_PGRAPH_NSOURCE_ILLEGAL_MTHD) {
 525                 if (nouveau_pgraph_intr_swmthd(dev, &trap))
 526                         unhandled = 1;
 527         } else if (nsource & NV03_PGRAPH_NSOURCE_DMA_VTX_PROTECTION) {
 528                 uint32_t v = nv_rd32(dev, 0x402000);
 529                 nv_wr32(dev, 0x402000, v);
 530
 531                 /* dump the error anyway for now: it's useful for
 532                    Gallium development */
 533                 unhandled = 1;
 534         } else {
 535                 unhandled = 1;
 536         }
 537
 538         if (unhandled && nouveau_ratelimit())
 539                 nouveau_graph_dump_trap_info(dev, "PGRAPH_ERROR", &trap);
 540 }
 541
 542 static inline void
 543 nouveau_pgraph_intr_context_switch(struct drm_device *dev)
 544 {
 545         struct drm_nouveau_private *dev_priv = dev->dev_private;
 546         struct nouveau_engine *engine = &dev_priv->engine;
 547         uint32_t chid;
 548
 549         chid = engine->fifo.channel_id(dev);
 550         NV_DEBUG(dev, "PGRAPH context switch interrupt channel %x\n", chid);
 551
 552         switch (dev_priv->card_type) {
 553         case NV_04:
 554                 nv04_graph_context_switch(dev);
 555                 break;
 556         case NV_10:
 557                 nv10_graph_context_switch(dev);
 558                 break;
 559         default:
 560                 NV_ERROR(dev, "Context switch not implemented\n");
 561                 break;
 562         }
 563 }
 564
 565 static void
 566 nouveau_pgraph_irq_handler(struct drm_device *dev)
 567 {
 568         uint32_t status;
 569
 570         while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
 571                 uint32_t nsource = nv_rd32(dev, NV03_PGRAPH_NSOURCE);
 572
 573                 if (status & NV_PGRAPH_INTR_NOTIFY) {
 574                         nouveau_pgraph_intr_notify(dev, nsource);
 575
 576                         status &= ~NV_PGRAPH_INTR_NOTIFY;
 577                         nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_NOTIFY);
 578                 }
 579
 580                 if (status & NV_PGRAPH_INTR_ERROR) {
 581                         nouveau_pgraph_intr_error(dev, nsource);
 582
 583                         status &= ~NV_PGRAPH_INTR_ERROR;
 584                         nv_wr32(dev, NV03_PGRAPH_INTR, NV_PGRAPH_INTR_ERROR);
 585                 }
 586
 587                 if (status & NV_PGRAPH_INTR_CONTEXT_SWITCH) {
 588                         nouveau_pgraph_intr_context_switch(dev);
 589
 590                         status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
 591                         nv_wr32(dev, NV03_PGRAPH_INTR,
 592                                  NV_PGRAPH_INTR_CONTEXT_SWITCH);
 593                 }
 594
 595                 if (status) {
 596                         NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n", status);
 597                         nv_wr32(dev, NV03_PGRAPH_INTR, status);
 598                 }
 599
 600                 if ((nv_rd32(dev, NV04_PGRAPH_FIFO) & (1 << 0)) == 0)
 601                         nv_wr32(dev, NV04_PGRAPH_FIFO, 1);
 602         }
 603
 604         nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
 605 }
 606
 607 static void
 608 nv50_pfb_vm_trap(struct drm_device *dev, int display, const char *name)
 609 {
 610         struct drm_nouveau_private *dev_priv = dev->dev_private;
 611         uint32_t trap[6];
 612         int i, ch;
 613         uint32_t idx = nv_rd32(dev, 0x100c90);
 614         if (idx & 0x80000000) {
 615                 idx &= 0xffffff;
 616                 if (display) {
 617                         for (i = 0; i < 6; i++) {
 618                                 nv_wr32(dev, 0x100c90, idx | i << 24);
 619                                 trap[i] = nv_rd32(dev, 0x100c94);
 620                         }
 621                         for (ch = 0; ch < dev_priv->engine.fifo.channels; ch++) {
 622                                 struct nouveau_channel *chan = dev_priv->fifos[ch];
 623
 624                                 if (!chan || !chan->ramin)
 625                                         continue;
 626
 627                                 if (trap[1] == chan->ramin->instance >> 12)
 628                                         break;
 629                         }
 630                         NV_INFO(dev, "%s - VM: Trapped %s at %02x%04x%04x status %08x %08x channel %d\n",
 631                                         name, (trap[5]&0x100?"read":"write"),
 632                                         trap[5]&0xff, trap[4]&0xffff,
 633                                         trap[3]&0xffff, trap[0], trap[2], ch);
 634                 }
 635                 nv_wr32(dev, 0x100c90, idx | 0x80000000);
 636         } else if (display) {
 637                 NV_INFO(dev, "%s - no VM fault?\n", name);
 638         }
 639 }
 640
 641 static struct nouveau_enum_names nv50_mp_exec_error_names[] =
 642 {
 643         { 3, "STACK_UNDERFLOW" },
 644         { 4, "QUADON_ACTIVE" },
 645         { 8, "TIMEOUT" },
 646         { 0x10, "INVALID_OPCODE" },
 647         { 0x40, "BREAKPOINT" },
 648 };
 649
 650 static void
 651 nv50_pgraph_mp_trap(struct drm_device *dev, int tpid, int display)
 652 {
 653         struct drm_nouveau_private *dev_priv = dev->dev_private;
 654         uint32_t units = nv_rd32(dev, 0x1540);
 655         uint32_t addr, mp10, status, pc, oplow, ophigh;
 656         int i;
 657         int mps = 0;
 658         for (i = 0; i < 4; i++) {
 659                 if (!(units & 1 << (i+24)))
 660                         continue;
 661                 if (dev_priv->chipset < 0xa0)
 662                         addr = 0x408200 + (tpid << 12) + (i << 7);
 663                 else
 664                         addr = 0x408100 + (tpid << 11) + (i << 7);
 665                 mp10 = nv_rd32(dev, addr + 0x10);
 666                 status = nv_rd32(dev, addr + 0x14);
 667                 if (!status)
 668                         continue;
 669                 if (display) {
 670                         nv_rd32(dev, addr + 0x20);
 671                         pc = nv_rd32(dev, addr + 0x24);
 672                         oplow = nv_rd32(dev, addr + 0x70);
 673                         ophigh= nv_rd32(dev, addr + 0x74);
 674                         NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - "
 675                                         "TP %d MP %d: ", tpid, i);
 676                         nouveau_print_enum_names(status,
 677                                         nv50_mp_exec_error_names);
 678                         printk(" at %06x warp %d, opcode %08x %08x\n",
 679                                         pc&0xffffff, pc >> 24,
 680                                         oplow, ophigh);
 681                 }
 682                 nv_wr32(dev, addr + 0x10, mp10);
 683                 nv_wr32(dev, addr + 0x14, 0);
 684                 mps++;
 685         }
 686         if (!mps && display)
 687                 NV_INFO(dev, "PGRAPH_TRAP_MP_EXEC - TP %d: "
 688                                 "No MPs claiming errors?\n", tpid);
 689 }
 690
 691 static void
 692 nv50_pgraph_tp_trap(struct drm_device *dev, int type, uint32_t ustatus_old,
 693                 uint32_t ustatus_new, int display, const char *name)
 694 {
 695         struct drm_nouveau_private *dev_priv = dev->dev_private;
 696         int tps = 0;
 697         uint32_t units = nv_rd32(dev, 0x1540);
 698         int i, r;
 699         uint32_t ustatus_addr, ustatus;
 700         for (i = 0; i < 16; i++) {
 701                 if (!(units & (1 << i)))
 702                         continue;
 703                 if (dev_priv->chipset < 0xa0)
 704                         ustatus_addr = ustatus_old + (i << 12);
 705                 else
 706                         ustatus_addr = ustatus_new + (i << 11);
 707                 ustatus = nv_rd32(dev, ustatus_addr) & 0x7fffffff;
 708                 if (!ustatus)
 709                         continue;
 710                 tps++;
 711                 switch (type) {
 712                 case 6: /* texture error... unknown for now */
 713                         nv50_pfb_vm_trap(dev, display, name);
 714                         if (display) {
 715                                 NV_ERROR(dev, "magic set %d:\n", i);
 716                                 for (r = ustatus_addr + 4; r <= ustatus_addr + 0x10; r += 4)
 717                                         NV_ERROR(dev, "\t0x%08x: 0x%08x\n", r,
 718                                                 nv_rd32(dev, r));
 719                         }
 720                         break;
 721                 case 7: /* MP error */
 722                         if (ustatus & 0x00010000) {
 723                                 nv50_pgraph_mp_trap(dev, i, display);
 724                                 ustatus &= ~0x00010000;
 725                         }
 726                         break;
 727                 case 8: /* TPDMA error */
 728                         {
 729                         uint32_t e0c = nv_rd32(dev, ustatus_addr + 4);
 730                         uint32_t e10 = nv_rd32(dev, ustatus_addr + 8);
 731                         uint32_t e14 = nv_rd32(dev, ustatus_addr + 0xc);
 732                         uint32_t e18 = nv_rd32(dev, ustatus_addr + 0x10);
 733                         uint32_t e1c = nv_rd32(dev, ustatus_addr + 0x14);
 734                         uint32_t e20 = nv_rd32(dev, ustatus_addr + 0x18);
 735                         uint32_t e24 = nv_rd32(dev, ustatus_addr + 0x1c);
 736                         nv50_pfb_vm_trap(dev, display, name);
 737                         /* 2d engine destination */
 738                         if (ustatus & 0x00000010) {
 739                                 if (display) {
 740                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - Unknown fault at address %02x%08x\n",
 741                                                         i, e14, e10);
 742                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_2D - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 743                                                         i, e0c, e18, e1c, e20, e24);
 744                                 }
 745                                 ustatus &= ~0x00000010;
 746                         }
 747                         /* Render target */
 748                         if (ustatus & 0x00000040) {
 749                                 if (display) {
 750                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - Unknown fault at address %02x%08x\n",
 751                                                         i, e14, e10);
 752                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA_RT - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 753                                                         i, e0c, e18, e1c, e20, e24);
 754                                 }
 755                                 ustatus &= ~0x00000040;
 756                         }
 757                         /* CUDA memory: l[], g[] or stack. */
 758                         if (ustatus & 0x00000080) {
 759                                 if (display) {
 760                                         if (e18 & 0x80000000) {
 761                                                 /* g[] read fault? */
 762                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global read fault at address %02x%08x\n",
 763                                                                 i, e14, e10 | ((e18 >> 24) & 0x1f));
 764                                                 e18 &= ~0x1f000000;
 765                                         } else if (e18 & 0xc) {
 766                                                 /* g[] write fault? */
 767                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Global write fault at address %02x%08x\n",
 768                                                                 i, e14, e10 | ((e18 >> 7) & 0x1f));
 769                                                 e18 &= ~0x00000f80;
 770                                         } else {
 771                                                 NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - Unknown CUDA fault at address %02x%08x\n",
 772                                                                 i, e14, e10);
 773                                         }
 774                                         NV_INFO(dev, "PGRAPH_TRAP_TPDMA - TP %d - e0c: %08x, e18: %08x, e1c: %08x, e20: %08x, e24: %08x\n",
 775                                                         i, e0c, e18, e1c, e20, e24);
 776                                 }
 777                                 ustatus &= ~0x00000080;
 778                         }
 779                         }
 780                         break;
 781                 }
 782                 if (ustatus) {
 783                         if (display)
 784                                 NV_INFO(dev, "%s - TP%d: Unhandled ustatus 0x%08x\n", name, i, ustatus);
 785                 }
 786                 nv_wr32(dev, ustatus_addr, 0xc0000000);
 787         }
 788
 789         if (!tps && display)
 790                 NV_INFO(dev, "%s - No TPs claiming errors?\n", name);
 791 }
 792
 793 static void
 794 nv50_pgraph_trap_handler(struct drm_device *dev)
 795 {
 796         struct nouveau_pgraph_trap trap;
 797         uint32_t status = nv_rd32(dev, 0x400108);
 798         uint32_t ustatus;
 799         int display = nouveau_ratelimit();
 800
 801
 802         if (!status && display) {
 803                 nouveau_graph_trap_info(dev, &trap);
 804                 nouveau_graph_dump_trap_info(dev, "PGRAPH_TRAP", &trap);
 805                 NV_INFO(dev, "PGRAPH_TRAP - no units reporting traps?\n");
 806         }
 807
 808         /* DISPATCH: Relays commands to other units and handles NOTIFY,
 809          * COND, QUERY. If you get a trap from it, the command is still stuck
 810          * in DISPATCH and you need to do something about it. */
 811         if (status & 0x001) {
 812                 ustatus = nv_rd32(dev, 0x400804) & 0x7fffffff;
 813                 if (!ustatus && display) {
 814                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - no ustatus?\n");
 815                 }
 816
 817                 /* Known to be triggered by screwed up NOTIFY and COND... */
 818                 if (ustatus & 0x00000001) {
 819                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_FAULT");
 820                         nv_wr32(dev, 0x400500, 0);
 821                         if (nv_rd32(dev, 0x400808) & 0x80000000) {
 822                                 if (display) {
 823                                         if (nouveau_graph_trapped_channel(dev, &trap.channel))
 824                                                 trap.channel = -1;
 825                                         trap.class = nv_rd32(dev, 0x400814);
 826                                         trap.mthd = nv_rd32(dev, 0x400808) & 0x1ffc;
 827                                         trap.subc = (nv_rd32(dev, 0x400808) >> 16) & 0x7;
 828                                         trap.data = nv_rd32(dev, 0x40080c);
 829                                         trap.data2 = nv_rd32(dev, 0x400810);
 830                                         nouveau_graph_dump_trap_info(dev,
 831                                                         "PGRAPH_TRAP_DISPATCH_FAULT", &trap);
 832                                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400808: %08x\n", nv_rd32(dev, 0x400808));
 833                                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - 400848: %08x\n", nv_rd32(dev, 0x400848));
 834                                 }
 835                                 nv_wr32(dev, 0x400808, 0);
 836                         } else if (display) {
 837                                 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_FAULT - No stuck command?\n");
 838                         }
 839                         nv_wr32(dev, 0x4008e8, nv_rd32(dev, 0x4008e8) & 3);
 840                         nv_wr32(dev, 0x400848, 0);
 841                         ustatus &= ~0x00000001;
 842                 }
 843                 if (ustatus & 0x00000002) {
 844                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_DISPATCH_QUERY");
 845                         nv_wr32(dev, 0x400500, 0);
 846                         if (nv_rd32(dev, 0x40084c) & 0x80000000) {
 847                                 if (display) {
 848                                         if (nouveau_graph_trapped_channel(dev, &trap.channel))
 849                                                 trap.channel = -1;
 850                                         trap.class = nv_rd32(dev, 0x400814);
 851                                         trap.mthd = nv_rd32(dev, 0x40084c) & 0x1ffc;
 852                                         trap.subc = (nv_rd32(dev, 0x40084c) >> 16) & 0x7;
 853                                         trap.data = nv_rd32(dev, 0x40085c);
 854                                         trap.data2 = 0;
 855                                         nouveau_graph_dump_trap_info(dev,
 856                                                         "PGRAPH_TRAP_DISPATCH_QUERY", &trap);
 857                                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - 40084c: %08x\n", nv_rd32(dev, 0x40084c));
 858                                 }
 859                                 nv_wr32(dev, 0x40084c, 0);
 860                         } else if (display) {
 861                                 NV_INFO(dev, "PGRAPH_TRAP_DISPATCH_QUERY - No stuck command?\n");
 862                         }
 863                         ustatus &= ~0x00000002;
 864                 }
 865                 if (ustatus && display)
 866                         NV_INFO(dev, "PGRAPH_TRAP_DISPATCH - Unhandled ustatus 0x%08x\n", ustatus);
 867                 nv_wr32(dev, 0x400804, 0xc0000000);
 868                 nv_wr32(dev, 0x400108, 0x001);
 869                 status &= ~0x001;
 870         }
 871
 872         /* TRAPs other than dispatch use the "normal" trap regs. */
 873         if (status && display) {
 874                 nouveau_graph_trap_info(dev, &trap);
 875                 nouveau_graph_dump_trap_info(dev,
 876                                 "PGRAPH_TRAP", &trap);
 877         }
 878
 879         /* M2MF: Memory to memory copy engine. */
 880         if (status & 0x002) {
 881                 ustatus = nv_rd32(dev, 0x406800) & 0x7fffffff;
 882                 if (!ustatus && display) {
 883                         NV_INFO(dev, "PGRAPH_TRAP_M2MF - no ustatus?\n");
 884                 }
 885                 if (ustatus & 0x00000001) {
 886                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_NOTIFY");
 887                         ustatus &= ~0x00000001;
 888                 }
 889                 if (ustatus & 0x00000002) {
 890                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_IN");
 891                         ustatus &= ~0x00000002;
 892                 }
 893                 if (ustatus & 0x00000004) {
 894                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_M2MF_OUT");
 895                         ustatus &= ~0x00000004;
 896                 }
 897                 NV_INFO (dev, "PGRAPH_TRAP_M2MF - %08x %08x %08x %08x\n",
 898                                 nv_rd32(dev, 0x406804),
 899                                 nv_rd32(dev, 0x406808),
 900                                 nv_rd32(dev, 0x40680c),
 901                                 nv_rd32(dev, 0x406810));
 902                 if (ustatus && display)
 903                         NV_INFO(dev, "PGRAPH_TRAP_M2MF - Unhandled ustatus 0x%08x\n", ustatus);
 904                 /* No sane way found yet -- just reset the bugger. */
 905                 nv_wr32(dev, 0x400040, 2);
 906                 nv_wr32(dev, 0x400040, 0);
 907                 nv_wr32(dev, 0x406800, 0xc0000000);
 908                 nv_wr32(dev, 0x400108, 0x002);
 909                 status &= ~0x002;
 910         }
 911
 912         /* VFETCH: Fetches data from vertex buffers. */
 913         if (status & 0x004) {
 914                 ustatus = nv_rd32(dev, 0x400c04) & 0x7fffffff;
 915                 if (!ustatus && display) {
 916                         NV_INFO(dev, "PGRAPH_TRAP_VFETCH - no ustatus?\n");
 917                 }
 918                 if (ustatus & 0x00000001) {
 919                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_VFETCH_FAULT");
 920                         NV_INFO (dev, "PGRAPH_TRAP_VFETCH_FAULT - %08x %08x %08x %08x\n",
 921                                         nv_rd32(dev, 0x400c00),
 922                                         nv_rd32(dev, 0x400c08),
 923                                         nv_rd32(dev, 0x400c0c),
 924                                         nv_rd32(dev, 0x400c10));
 925                         ustatus &= ~0x00000001;
 926                 }
 927                 if (ustatus && display)
 928                         NV_INFO(dev, "PGRAPH_TRAP_VFETCH - Unhandled ustatus 0x%08x\n", ustatus);
 929                 nv_wr32(dev, 0x400c04, 0xc0000000);
 930                 nv_wr32(dev, 0x400108, 0x004);
 931                 status &= ~0x004;
 932         }
 933
 934         /* STRMOUT: DirectX streamout / OpenGL transform feedback. */
 935         if (status & 0x008) {
 936                 ustatus = nv_rd32(dev, 0x401800) & 0x7fffffff;
 937                 if (!ustatus && display) {
 938                         NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - no ustatus?\n");
 939                 }
 940                 if (ustatus & 0x00000001) {
 941                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_STRMOUT_FAULT");
 942                         NV_INFO (dev, "PGRAPH_TRAP_STRMOUT_FAULT - %08x %08x %08x %08x\n",
 943                                         nv_rd32(dev, 0x401804),
 944                                         nv_rd32(dev, 0x401808),
 945                                         nv_rd32(dev, 0x40180c),
 946                                         nv_rd32(dev, 0x401810));
 947                         ustatus &= ~0x00000001;
 948                 }
 949                 if (ustatus && display)
 950                         NV_INFO(dev, "PGRAPH_TRAP_STRMOUT - Unhandled ustatus 0x%08x\n", ustatus);
 951                 /* No sane way found yet -- just reset the bugger. */
 952                 nv_wr32(dev, 0x400040, 0x80);
 953                 nv_wr32(dev, 0x400040, 0);
 954                 nv_wr32(dev, 0x401800, 0xc0000000);
 955                 nv_wr32(dev, 0x400108, 0x008);
 956                 status &= ~0x008;
 957         }
 958
 959         /* CCACHE: Handles code and c[] caches and fills them. */
 960         if (status & 0x010) {
 961                 ustatus = nv_rd32(dev, 0x405018) & 0x7fffffff;
 962                 if (!ustatus && display) {
 963                         NV_INFO(dev, "PGRAPH_TRAP_CCACHE - no ustatus?\n");
 964                 }
 965                 if (ustatus & 0x00000001) {
 966                         nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_CCACHE_FAULT");
 967                         NV_INFO (dev, "PGRAPH_TRAP_CCACHE_FAULT - %08x %08x %08x %08x %08x %08x %08x\n",
 968                                         nv_rd32(dev, 0x405800),
 969                                         nv_rd32(dev, 0x405804),
 970                                         nv_rd32(dev, 0x405808),
 971                                         nv_rd32(dev, 0x40580c),
 972                                         nv_rd32(dev, 0x405810),
 973                                         nv_rd32(dev, 0x405814),
 974                                         nv_rd32(dev, 0x40581c));
 975                         ustatus &= ~0x00000001;
 976                 }
 977                 if (ustatus && display)
 978                         NV_INFO(dev, "PGRAPH_TRAP_CCACHE - Unhandled ustatus 0x%08x\n", ustatus);
 979                 nv_wr32(dev, 0x405018, 0xc0000000);
 980                 nv_wr32(dev, 0x400108, 0x010);
 981                 status &= ~0x010;
 982         }
 983
 984         /* Unknown, not seen yet... 0x402000 is the only trap status reg
 985          * remaining, so try to handle it anyway. Perhaps related to that
 986          * unknown DMA slot on tesla? */
 987         if (status & 0x20) {
 988                 nv50_pfb_vm_trap(dev, display, "PGRAPH_TRAP_UNKC04");
 989                 ustatus = nv_rd32(dev, 0x402000) & 0x7fffffff;
 990                 if (display)
 991                         NV_INFO(dev, "PGRAPH_TRAP_UNKC04 - Unhandled ustatus 0x%08x\n", ustatus);
 992                 nv_wr32(dev, 0x402000, 0xc0000000);
 993                 /* no status modifiction on purpose */
 994         }
 995
 996         /* TEXTURE: CUDA texturing units */
 997         if (status & 0x040) {
 998                 nv50_pgraph_tp_trap (dev, 6, 0x408900, 0x408600, display,
 999                                 "PGRAPH_TRAP_TEXTURE");
1000                 nv_wr32(dev, 0x400108, 0x040);
1001                 status &= ~0x040;
1002         }
1003
1004         /* MP: CUDA execution engines. */
1005         if (status & 0x080) {
1006                 nv50_pgraph_tp_trap (dev, 7, 0x408314, 0x40831c, display,
1007                                 "PGRAPH_TRAP_MP");
1008                 nv_wr32(dev, 0x400108, 0x080);
1009                 status &= ~0x080;
1010         }
1011
1012         /* TPDMA:  Handles TP-initiated uncached memory accesses:
1013          * l[], g[], stack, 2d surfaces, render targets. */
1014         if (status & 0x100) {
1015                 nv50_pgraph_tp_trap (dev, 8, 0x408e08, 0x408708, display,
1016                                 "PGRAPH_TRAP_TPDMA");
1017                 nv_wr32(dev, 0x400108, 0x100);
1018                 status &= ~0x100;
1019         }
1020
1021         if (status) {
1022                 if (display)
1023                         NV_INFO(dev, "PGRAPH_TRAP - Unknown trap 0x%08x\n",
1024                                 status);
1025                 nv_wr32(dev, 0x400108, status);
1026         }
1027 }
1028
1029 /* There must be a *lot* of these. Will take some time to gather them up. */
1030 static struct nouveau_enum_names nv50_data_error_names[] =
1031 {
1032         { 4,    "INVALID_VALUE" },
1033         { 5,    "INVALID_ENUM" },
1034         { 8,    "INVALID_OBJECT" },
1035         { 0xc,  "INVALID_BITFIELD" },
1036         { 0x28, "MP_NO_REG_SPACE" },
1037         { 0x2b, "MP_BLOCK_SIZE_MISMATCH" },
1038 };
1039
1040 static void
1041 nv50_pgraph_irq_handler(struct drm_device *dev)
1042 {
1043         struct nouveau_pgraph_trap trap;
1044         int unhandled = 0;
1045         uint32_t status;
1046
1047         while ((status = nv_rd32(dev, NV03_PGRAPH_INTR))) {
1048                 /* NOTIFY: You've set a NOTIFY an a command and it's done. */
1049                 if (status & 0x00000001) {
1050                         nouveau_graph_trap_info(dev, &trap);
1051                         if (nouveau_ratelimit())
1052                                 nouveau_graph_dump_trap_info(dev,
1053                                                 "PGRAPH_NOTIFY", &trap);
1054                         status &= ~0x00000001;
1055                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000001);
1056                 }
1057
1058                 /* COMPUTE_QUERY: Purpose and exact cause unknown, happens
1059                  * when you write 0x200 to 0x50c0 method 0x31c. */
1060                 if (status & 0x00000002) {
1061                         nouveau_graph_trap_info(dev, &trap);
1062                         if (nouveau_ratelimit())
1063                                 nouveau_graph_dump_trap_info(dev,
1064                                                 "PGRAPH_COMPUTE_QUERY", &trap);
1065                         status &= ~0x00000002;
1066                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000002);
1067                 }
1068
1069                 /* Unknown, never seen: 0x4 */
1070
1071                 /* ILLEGAL_MTHD: You used a wrong method for this class. */
1072                 if (status & 0x00000010) {
1073                         nouveau_graph_trap_info(dev, &trap);
1074                         if (nouveau_pgraph_intr_swmthd(dev, &trap))
1075                                 unhandled = 1;
1076                         if (unhandled && nouveau_ratelimit())
1077                                 nouveau_graph_dump_trap_info(dev,
1078                                                 "PGRAPH_ILLEGAL_MTHD", &trap);
1079                         status &= ~0x00000010;
1080                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000010);
1081                 }
1082
1083                 /* ILLEGAL_CLASS: You used a wrong class. */
1084                 if (status & 0x00000020) {
1085                         nouveau_graph_trap_info(dev, &trap);
1086                         if (nouveau_ratelimit())
1087                                 nouveau_graph_dump_trap_info(dev,
1088                                                 "PGRAPH_ILLEGAL_CLASS", &trap);
1089                         status &= ~0x00000020;
1090                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000020);
1091                 }
1092
1093                 /* DOUBLE_NOTIFY: You tried to set a NOTIFY on another NOTIFY. */
1094                 if (status & 0x00000040) {
1095                         nouveau_graph_trap_info(dev, &trap);
1096                         if (nouveau_ratelimit())
1097                                 nouveau_graph_dump_trap_info(dev,
1098                                                 "PGRAPH_DOUBLE_NOTIFY", &trap);
1099                         status &= ~0x00000040;
1100                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00000040);
1101                 }
1102
1103                 /* CONTEXT_SWITCH: PGRAPH needs us to load a new context */
1104                 if (status & 0x00001000) {
1105                         nv_wr32(dev, 0x400500, 0x00000000);
1106                         nv_wr32(dev, NV03_PGRAPH_INTR,
1107                                 NV_PGRAPH_INTR_CONTEXT_SWITCH);
1108                         nv_wr32(dev, NV40_PGRAPH_INTR_EN, nv_rd32(dev,
1109                                 NV40_PGRAPH_INTR_EN) &
1110                                 ~NV_PGRAPH_INTR_CONTEXT_SWITCH);
1111                         nv_wr32(dev, 0x400500, 0x00010001);
1112
1113                         nv50_graph_context_switch(dev);
1114
1115                         status &= ~NV_PGRAPH_INTR_CONTEXT_SWITCH;
1116                 }
1117
1118                 /* BUFFER_NOTIFY: Your m2mf transfer finished */
1119                 if (status & 0x00010000) {
1120                         nouveau_graph_trap_info(dev, &trap);
1121                         if (nouveau_ratelimit())
1122                                 nouveau_graph_dump_trap_info(dev,
1123                                                 "PGRAPH_BUFFER_NOTIFY", &trap);
1124                         status &= ~0x00010000;
1125                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00010000);
1126                 }
1127
1128                 /* DATA_ERROR: Invalid value for this method, or invalid
1129                  * state in current PGRAPH context for this operation */
1130                 if (status & 0x00100000) {
1131                         nouveau_graph_trap_info(dev, &trap);
1132                         if (nouveau_ratelimit()) {
1133                                 nouveau_graph_dump_trap_info(dev,
1134                                                 "PGRAPH_DATA_ERROR", &trap);
1135                                 NV_INFO (dev, "PGRAPH_DATA_ERROR - ");
1136                                 nouveau_print_enum_names(nv_rd32(dev, 0x400110),
1137                                                 nv50_data_error_names);
1138                                 printk("\n");
1139                         }
1140                         status &= ~0x00100000;
1141                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00100000);
1142                 }
1143
1144                 /* TRAP: Something bad happened in the middle of command
1145                  * execution.  Has a billion types, subtypes, and even
1146                  * subsubtypes. */
1147                 if (status & 0x00200000) {
1148                         nv50_pgraph_trap_handler(dev);
1149                         status &= ~0x00200000;
1150                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x00200000);
1151                 }
1152
1153                 /* Unknown, never seen: 0x00400000 */
1154
1155                 /* SINGLE_STEP: Happens on every method if you turned on
1156                  * single stepping in 40008c */
1157                 if (status & 0x01000000) {
1158                         nouveau_graph_trap_info(dev, &trap);
1159                         if (nouveau_ratelimit())
1160                                 nouveau_graph_dump_trap_info(dev,
1161                                                 "PGRAPH_SINGLE_STEP", &trap);
1162                         status &= ~0x01000000;
1163                         nv_wr32(dev, NV03_PGRAPH_INTR, 0x01000000);
1164                 }
1165
1166                 /* 0x02000000 happens when you pause a ctxprog...
1167                  * but the only way this can happen that I know is by
1168                  * poking the relevant MMIO register, and we don't
1169                  * do that. */
1170
1171                 if (status) {
1172                         NV_INFO(dev, "Unhandled PGRAPH_INTR - 0x%08x\n",
1173                                 status);
1174                         nv_wr32(dev, NV03_PGRAPH_INTR, status);
1175                 }
1176
1177                 {
1178                         const int isb = (1 << 16) | (1 << 0);
1179
1180                         if ((nv_rd32(dev, 0x400500) & isb) != isb)
1181                                 nv_wr32(dev, 0x400500,
1182                                         nv_rd32(dev, 0x400500) | isb);
1183                 }
1184         }
1185
1186         nv_wr32(dev, NV03_PMC_INTR_0, NV_PMC_INTR_0_PGRAPH_PENDING);
1187         if (nv_rd32(dev, 0x400824) & (1 << 31))
1188                 nv_wr32(dev, 0x400824, nv_rd32(dev, 0x400824) & ~(1 << 31));
1189 }
1190
1191 static void
1192 nouveau_crtc_irq_handler(struct drm_device *dev, int crtc)
1193 {
1194         if (crtc & 1)
1195                 nv_wr32(dev, NV_CRTC0_INTSTAT, NV_CRTC_INTR_VBLANK);
1196
1197         if (crtc & 2)
1198                 nv_wr32(dev, NV_CRTC1_INTSTAT, NV_CRTC_INTR_VBLANK);
1199 }
1200
1201 irqreturn_t
1202 nouveau_irq_handler(DRM_IRQ_ARGS)
1203 {
1204         struct drm_device *dev = (struct drm_device *)arg;
1205         struct drm_nouveau_private *dev_priv = dev->dev_private;
1206         uint32_t status, fbdev_flags = 0;
1207         unsigned long flags;
1208
1209         status = nv_rd32(dev, NV03_PMC_INTR_0);
1210         if (!status)
1211                 return IRQ_NONE;
1212
1213         spin_lock_irqsave(&dev_priv->context_switch_lock, flags);
1214
1215         if (dev_priv->fbdev_info) {
1216                 fbdev_flags = dev_priv->fbdev_info->flags;
1217                 dev_priv->fbdev_info->flags |= FBINFO_HWACCEL_DISABLED;
1218         }
1219
1220         if (status & NV_PMC_INTR_0_PFIFO_PENDING) {
1221                 nouveau_fifo_irq_handler(dev);
1222                 status &= ~NV_PMC_INTR_0_PFIFO_PENDING;
1223         }
1224
1225         if (status & NV_PMC_INTR_0_PGRAPH_PENDING) {
1226                 if (dev_priv->card_type >= NV_50)
1227                         nv50_pgraph_irq_handler(dev);
1228                 else
1229                         nouveau_pgraph_irq_handler(dev);
1230
1231                 status &= ~NV_PMC_INTR_0_PGRAPH_PENDING;
1232         }
1233
1234         if (status & NV_PMC_INTR_0_CRTCn_PENDING) {
1235                 nouveau_crtc_irq_handler(dev, (status>>24)&3);
1236                 status &= ~NV_PMC_INTR_0_CRTCn_PENDING;
1237         }
1238
1239         if (status & (NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1240                       NV_PMC_INTR_0_NV50_I2C_PENDING)) {
1241                 nv50_display_irq_handler(dev);
1242                 status &= ~(NV_PMC_INTR_0_NV50_DISPLAY_PENDING |
1243                             NV_PMC_INTR_0_NV50_I2C_PENDING);
1244         }
1245
1246         if (status)
1247                 NV_ERROR(dev, "Unhandled PMC INTR status bits 0x%08x\n", status);
1248
1249         if (dev_priv->fbdev_info)
1250                 dev_priv->fbdev_info->flags = fbdev_flags;
1251
1252         spin_unlock_irqrestore(&dev_priv->context_switch_lock, flags);
1253
1254         return IRQ_HANDLED;
1255 }