SAFE public projects git trees. - safe/jmp/linux-2.6/blob - drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (IS_IRONLAKE(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_connector *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 747             if (l_entry->encoder &&
 748                 l_entry->encoder->crtc == crtc) {
 749                     struct intel_output *intel_output = to_intel_output(l_entry);
 750                     if (intel_output->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 struct drm_connector *
 758 intel_pipe_get_output (struct drm_crtc *crtc)
 759 {
 760     struct drm_device *dev = crtc->dev;
 761     struct drm_mode_config *mode_config = &dev->mode_config;
 762     struct drm_connector *l_entry, *ret = NULL;
 763
 764     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 765             if (l_entry->encoder &&
 766                 l_entry->encoder->crtc == crtc) {
 767                     ret = l_entry;
 768                     break;
 769             }
 770     }
 771     return ret;
 772 }
 773
 774 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 775 /**
 776  * Returns whether the given set of divisors are valid for a given refclk with
 777  * the given connectors.
 778  */
 779
 780 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 781 {
 782         const intel_limit_t *limit = intel_limit (crtc);
 783         struct drm_device *dev = crtc->dev;
 784
 785         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 786                 INTELPllInvalid ("p1 out of range\n");
 787         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 788                 INTELPllInvalid ("p out of range\n");
 789         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 790                 INTELPllInvalid ("m2 out of range\n");
 791         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 792                 INTELPllInvalid ("m1 out of range\n");
 793         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 794                 INTELPllInvalid ("m1 <= m2\n");
 795         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 796                 INTELPllInvalid ("m out of range\n");
 797         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 798                 INTELPllInvalid ("n out of range\n");
 799         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 800                 INTELPllInvalid ("vco out of range\n");
 801         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 802          * connector, etc., rather than just a single range.
 803          */
 804         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 805                 INTELPllInvalid ("dot out of range\n");
 806
 807         return true;
 808 }
 809
 810 static bool
 811 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 812                     int target, int refclk, intel_clock_t *best_clock)
 813
 814 {
 815         struct drm_device *dev = crtc->dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         intel_clock_t clock;
 818         int err = target;
 819
 820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 821             (I915_READ(LVDS)) != 0) {
 822                 /*
 823                  * For LVDS, if the panel is on, just rely on its current
 824                  * settings for dual-channel.  We haven't figured out how to
 825                  * reliably set up different single/dual channel state, if we
 826                  * even can.
 827                  */
 828                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 829                     LVDS_CLKB_POWER_UP)
 830                         clock.p2 = limit->p2.p2_fast;
 831                 else
 832                         clock.p2 = limit->p2.p2_slow;
 833         } else {
 834                 if (target < limit->p2.dot_limit)
 835                         clock.p2 = limit->p2.p2_slow;
 836                 else
 837                         clock.p2 = limit->p2.p2_fast;
 838         }
 839
 840         memset (best_clock, 0, sizeof (*best_clock));
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         /* m1 is always 0 in Pineview */
 847                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 848                                 break;
 849                         for (clock.n = limit->n.min;
 850                              clock.n <= limit->n.max; clock.n++) {
 851                                 for (clock.p1 = limit->p1.min;
 852                                         clock.p1 <= limit->p1.max; clock.p1++) {
 853                                         int this_err;
 854
 855                                         intel_clock(dev, refclk, &clock);
 856
 857                                         if (!intel_PLL_is_valid(crtc, &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 875                         int target, int refclk, intel_clock_t *best_clock)
 876 {
 877         struct drm_device *dev = crtc->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         intel_clock_t clock;
 880         int max_n;
 881         bool found;
 882         /* approximately equals target * 0.00488 */
 883         int err_most = (target >> 8) + (target >> 10);
 884         found = false;
 885
 886         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 887                 int lvds_reg;
 888
 889                 if (IS_IRONLAKE(dev))
 890                         lvds_reg = PCH_LVDS;
 891                 else
 892                         lvds_reg = LVDS;
 893                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 894                     LVDS_CLKB_POWER_UP)
 895                         clock.p2 = limit->p2.p2_fast;
 896                 else
 897                         clock.p2 = limit->p2.p2_slow;
 898         } else {
 899                 if (target < limit->p2.dot_limit)
 900                         clock.p2 = limit->p2.p2_slow;
 901                 else
 902                         clock.p2 = limit->p2.p2_fast;
 903         }
 904
 905         memset(best_clock, 0, sizeof(*best_clock));
 906         max_n = limit->n.max;
 907         /* based on hardware requriment prefer smaller n to precision */
 908         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 909                 /* based on hardware requirment prefere larger m1,m2 */
 910                 for (clock.m1 = limit->m1.max;
 911                      clock.m1 >= limit->m1.min; clock.m1--) {
 912                         for (clock.m2 = limit->m2.max;
 913                              clock.m2 >= limit->m2.min; clock.m2--) {
 914                                 for (clock.p1 = limit->p1.max;
 915                                      clock.p1 >= limit->p1.min; clock.p1--) {
 916                                         int this_err;
 917
 918                                         intel_clock(dev, refclk, &clock);
 919                                         if (!intel_PLL_is_valid(crtc, &clock))
 920                                                 continue;
 921                                         this_err = abs(clock.dot - target) ;
 922                                         if (this_err < err_most) {
 923                                                 *best_clock = clock;
 924                                                 err_most = this_err;
 925                                                 max_n = clock.n;
 926                                                 found = true;
 927                                         }
 928                                 }
 929                         }
 930                 }
 931         }
 932         return found;
 933 }
 934
 935 static bool
 936 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 937                            int target, int refclk, intel_clock_t *best_clock)
 938 {
 939         struct drm_device *dev = crtc->dev;
 940         intel_clock_t clock;
 941
 942         /* return directly when it is eDP */
 943         if (HAS_eDP)
 944                 return true;
 945
 946         if (target < 200000) {
 947                 clock.n = 1;
 948                 clock.p1 = 2;
 949                 clock.p2 = 10;
 950                 clock.m1 = 12;
 951                 clock.m2 = 9;
 952         } else {
 953                 clock.n = 2;
 954                 clock.p1 = 1;
 955                 clock.p2 = 10;
 956                 clock.m1 = 14;
 957                 clock.m2 = 8;
 958         }
 959         intel_clock(dev, refclk, &clock);
 960         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 961         return true;
 962 }
 963
 964 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 965 static bool
 966 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 967                       int target, int refclk, intel_clock_t *best_clock)
 968 {
 969     intel_clock_t clock;
 970     if (target < 200000) {
 971         clock.p1 = 2;
 972         clock.p2 = 10;
 973         clock.n = 2;
 974         clock.m1 = 23;
 975         clock.m2 = 8;
 976     } else {
 977         clock.p1 = 1;
 978         clock.p2 = 10;
 979         clock.n = 1;
 980         clock.m1 = 14;
 981         clock.m2 = 2;
 982     }
 983     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 984     clock.p = (clock.p1 * clock.p2);
 985     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 986     clock.vco = 0;
 987     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 988     return true;
 989 }
 990
 991 void
 992 intel_wait_for_vblank(struct drm_device *dev)
 993 {
 994         /* Wait for 20ms, i.e. one cycle at 50hz. */
 995         msleep(20);
 996 }
 997
 998 /* Parameters have changed, update FBC info */
 999 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1000 {
1001         struct drm_device *dev = crtc->dev;
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         struct drm_framebuffer *fb = crtc->fb;
1004         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1005         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007         int plane, i;
1008         u32 fbc_ctl, fbc_ctl2;
1009
1010         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1011
1012         if (fb->pitch < dev_priv->cfb_pitch)
1013                 dev_priv->cfb_pitch = fb->pitch;
1014
1015         /* FBC_CTL wants 64B units */
1016         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1017         dev_priv->cfb_fence = obj_priv->fence_reg;
1018         dev_priv->cfb_plane = intel_crtc->plane;
1019         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1020
1021         /* Clear old tags */
1022         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1023                 I915_WRITE(FBC_TAG + (i * 4), 0);
1024
1025         /* Set it up... */
1026         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1027         if (obj_priv->tiling_mode != I915_TILING_NONE)
1028                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1029         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1030         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1031
1032         /* enable it... */
1033         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034         if (IS_I945GM(dev))
1035                 fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
1036         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1037         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1038         if (obj_priv->tiling_mode != I915_TILING_NONE)
1039                 fbc_ctl |= dev_priv->cfb_fence;
1040         I915_WRITE(FBC_CONTROL, fbc_ctl);
1041
1042         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1043                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1044 }
1045
1046 void i8xx_disable_fbc(struct drm_device *dev)
1047 {
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         u32 fbc_ctl;
1050
1051         if (!I915_HAS_FBC(dev))
1052                 return;
1053
1054         /* Disable compression */
1055         fbc_ctl = I915_READ(FBC_CONTROL);
1056         fbc_ctl &= ~FBC_CTL_EN;
1057         I915_WRITE(FBC_CONTROL, fbc_ctl);
1058
1059         /* Wait for compressing bit to clear */
1060         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1061                 ; /* nothing */
1062
1063         intel_wait_for_vblank(dev);
1064
1065         DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1069 {
1070         struct drm_device *dev = crtc->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072
1073         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1074 }
1075
1076 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1077 {
1078         struct drm_device *dev = crtc->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         struct drm_framebuffer *fb = crtc->fb;
1081         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1082         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1084         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1085                      DPFC_CTL_PLANEB);
1086         unsigned long stall_watermark = 200;
1087         u32 dpfc_ctl;
1088
1089         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1090         dev_priv->cfb_fence = obj_priv->fence_reg;
1091         dev_priv->cfb_plane = intel_crtc->plane;
1092
1093         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1094         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1095                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1096                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1097         } else {
1098                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1099         }
1100
1101         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1102         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1103                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1104                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1105         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1106
1107         /* enable it... */
1108         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1109
1110         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1111 }
1112
1113 void g4x_disable_fbc(struct drm_device *dev)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         u32 dpfc_ctl;
1117
1118         /* Disable compression */
1119         dpfc_ctl = I915_READ(DPFC_CONTROL);
1120         dpfc_ctl &= ~DPFC_CTL_EN;
1121         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1122         intel_wait_for_vblank(dev);
1123
1124         DRM_DEBUG_KMS("disabled FBC\n");
1125 }
1126
1127 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1128 {
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1133 }
1134
1135 /**
1136  * intel_update_fbc - enable/disable FBC as needed
1137  * @crtc: CRTC to point the compressor at
1138  * @mode: mode in use
1139  *
1140  * Set up the framebuffer compression hardware at mode set time.  We
1141  * enable it if possible:
1142  *   - plane A only (on pre-965)
1143  *   - no pixel mulitply/line duplication
1144  *   - no alpha buffer discard
1145  *   - no dual wide
1146  *   - framebuffer <= 2048 in width, 1536 in height
1147  *
1148  * We can't assume that any compression will take place (worst case),
1149  * so the compressed buffer has to be the same size as the uncompressed
1150  * one.  It also must reside (along with the line length buffer) in
1151  * stolen memory.
1152  *
1153  * We need to enable/disable FBC on a global basis.
1154  */
1155 static void intel_update_fbc(struct drm_crtc *crtc,
1156                              struct drm_display_mode *mode)
1157 {
1158         struct drm_device *dev = crtc->dev;
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160         struct drm_framebuffer *fb = crtc->fb;
1161         struct intel_framebuffer *intel_fb;
1162         struct drm_i915_gem_object *obj_priv;
1163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1164         int plane = intel_crtc->plane;
1165
1166         if (!i915_powersave)
1167                 return;
1168
1169         if (!dev_priv->display.fbc_enabled ||
1170             !dev_priv->display.enable_fbc ||
1171             !dev_priv->display.disable_fbc)
1172                 return;
1173
1174         if (!crtc->fb)
1175                 return;
1176
1177         intel_fb = to_intel_framebuffer(fb);
1178         obj_priv = intel_fb->obj->driver_private;
1179
1180         /*
1181          * If FBC is already on, we just have to verify that we can
1182          * keep it that way...
1183          * Need to disable if:
1184          *   - changing FBC params (stride, fence, mode)
1185          *   - new fb is too large to fit in compressed buffer
1186          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1187          */
1188         if (intel_fb->obj->size > dev_priv->cfb_size) {
1189                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1190                                 "compression\n");
1191                 goto out_disable;
1192         }
1193         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195                 DRM_DEBUG_KMS("mode incompatible with compression, "
1196                                 "disabling\n");
1197                 goto out_disable;
1198         }
1199         if ((mode->hdisplay > 2048) ||
1200             (mode->vdisplay > 1536)) {
1201                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1202                 goto out_disable;
1203         }
1204         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1205                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1206                 goto out_disable;
1207         }
1208         if (obj_priv->tiling_mode != I915_TILING_X) {
1209                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1210                 goto out_disable;
1211         }
1212
1213         if (dev_priv->display.fbc_enabled(crtc)) {
1214                 /* We can re-enable it in this case, but need to update pitch */
1215                 if (fb->pitch > dev_priv->cfb_pitch)
1216                         dev_priv->display.disable_fbc(dev);
1217                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1218                         dev_priv->display.disable_fbc(dev);
1219                 if (plane != dev_priv->cfb_plane)
1220                         dev_priv->display.disable_fbc(dev);
1221         }
1222
1223         if (!dev_priv->display.fbc_enabled(crtc)) {
1224                 /* Now try to turn it back on if possible */
1225                 dev_priv->display.enable_fbc(crtc, 500);
1226         }
1227
1228         return;
1229
1230 out_disable:
1231         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1232         /* Multiple disables should be harmless */
1233         if (dev_priv->display.fbc_enabled(crtc))
1234                 dev_priv->display.disable_fbc(dev);
1235 }
1236
1237 static int
1238 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1239 {
1240         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241         u32 alignment;
1242         int ret;
1243
1244         switch (obj_priv->tiling_mode) {
1245         case I915_TILING_NONE:
1246                 alignment = 64 * 1024;
1247                 break;
1248         case I915_TILING_X:
1249                 /* pin() will align the object as required by fence */
1250                 alignment = 0;
1251                 break;
1252         case I915_TILING_Y:
1253                 /* FIXME: Is this true? */
1254                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1255                 return -EINVAL;
1256         default:
1257                 BUG();
1258         }
1259
1260         ret = i915_gem_object_pin(obj, alignment);
1261         if (ret != 0)
1262                 return ret;
1263
1264         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1265          * fence, whereas 965+ only requires a fence if using
1266          * framebuffer compression.  For simplicity, we always install
1267          * a fence as the cost is not that onerous.
1268          */
1269         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1270             obj_priv->tiling_mode != I915_TILING_NONE) {
1271                 ret = i915_gem_object_get_fence_reg(obj);
1272                 if (ret != 0) {
1273                         i915_gem_object_unpin(obj);
1274                         return ret;
1275                 }
1276         }
1277
1278         return 0;
1279 }
1280
1281 static int
1282 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1283                     struct drm_framebuffer *old_fb)
1284 {
1285         struct drm_device *dev = crtc->dev;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         struct drm_i915_master_private *master_priv;
1288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1289         struct intel_framebuffer *intel_fb;
1290         struct drm_i915_gem_object *obj_priv;
1291         struct drm_gem_object *obj;
1292         int pipe = intel_crtc->pipe;
1293         int plane = intel_crtc->plane;
1294         unsigned long Start, Offset;
1295         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1296         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1297         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1298         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1299         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1300         u32 dspcntr;
1301         int ret;
1302
1303         /* no fb bound */
1304         if (!crtc->fb) {
1305                 DRM_DEBUG_KMS("No FB bound\n");
1306                 return 0;
1307         }
1308
1309         switch (plane) {
1310         case 0:
1311         case 1:
1312                 break;
1313         default:
1314                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1315                 return -EINVAL;
1316         }
1317
1318         intel_fb = to_intel_framebuffer(crtc->fb);
1319         obj = intel_fb->obj;
1320         obj_priv = obj->driver_private;
1321
1322         mutex_lock(&dev->struct_mutex);
1323         ret = intel_pin_and_fence_fb_obj(dev, obj);
1324         if (ret != 0) {
1325                 mutex_unlock(&dev->struct_mutex);
1326                 return ret;
1327         }
1328
1329         ret = i915_gem_object_set_to_display_plane(obj);
1330         if (ret != 0) {
1331                 i915_gem_object_unpin(obj);
1332                 mutex_unlock(&dev->struct_mutex);
1333                 return ret;
1334         }
1335
1336         dspcntr = I915_READ(dspcntr_reg);
1337         /* Mask out pixel format bits in case we change it */
1338         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1339         switch (crtc->fb->bits_per_pixel) {
1340         case 8:
1341                 dspcntr |= DISPPLANE_8BPP;
1342                 break;
1343         case 16:
1344                 if (crtc->fb->depth == 15)
1345                         dspcntr |= DISPPLANE_15_16BPP;
1346                 else
1347                         dspcntr |= DISPPLANE_16BPP;
1348                 break;
1349         case 24:
1350         case 32:
1351                 if (crtc->fb->depth == 30)
1352                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1353                 else
1354                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1355                 break;
1356         default:
1357                 DRM_ERROR("Unknown color depth\n");
1358                 i915_gem_object_unpin(obj);
1359                 mutex_unlock(&dev->struct_mutex);
1360                 return -EINVAL;
1361         }
1362         if (IS_I965G(dev)) {
1363                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1364                         dspcntr |= DISPPLANE_TILED;
1365                 else
1366                         dspcntr &= ~DISPPLANE_TILED;
1367         }
1368
1369         if (IS_IRONLAKE(dev))
1370                 /* must disable */
1371                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1372
1373         I915_WRITE(dspcntr_reg, dspcntr);
1374
1375         Start = obj_priv->gtt_offset;
1376         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1377
1378         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1379         I915_WRITE(dspstride, crtc->fb->pitch);
1380         if (IS_I965G(dev)) {
1381                 I915_WRITE(dspbase, Offset);
1382                 I915_READ(dspbase);
1383                 I915_WRITE(dspsurf, Start);
1384                 I915_READ(dspsurf);
1385                 I915_WRITE(dsptileoff, (y << 16) | x);
1386         } else {
1387                 I915_WRITE(dspbase, Start + Offset);
1388                 I915_READ(dspbase);
1389         }
1390
1391         if ((IS_I965G(dev) || plane == 0))
1392                 intel_update_fbc(crtc, &crtc->mode);
1393
1394         intel_wait_for_vblank(dev);
1395
1396         if (old_fb) {
1397                 intel_fb = to_intel_framebuffer(old_fb);
1398                 obj_priv = intel_fb->obj->driver_private;
1399                 i915_gem_object_unpin(intel_fb->obj);
1400         }
1401         intel_increase_pllclock(crtc, true);
1402
1403         mutex_unlock(&dev->struct_mutex);
1404
1405         if (!dev->primary->master)
1406                 return 0;
1407
1408         master_priv = dev->primary->master->driver_priv;
1409         if (!master_priv->sarea_priv)
1410                 return 0;
1411
1412         if (pipe) {
1413                 master_priv->sarea_priv->pipeB_x = x;
1414                 master_priv->sarea_priv->pipeB_y = y;
1415         } else {
1416                 master_priv->sarea_priv->pipeA_x = x;
1417                 master_priv->sarea_priv->pipeA_y = y;
1418         }
1419
1420         return 0;
1421 }
1422
1423 /* Disable the VGA plane that we never use */
1424 static void i915_disable_vga (struct drm_device *dev)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         u8 sr1;
1428         u32 vga_reg;
1429
1430         if (IS_IRONLAKE(dev))
1431                 vga_reg = CPU_VGACNTRL;
1432         else
1433                 vga_reg = VGACNTRL;
1434
1435         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1436                 return;
1437
1438         I915_WRITE8(VGA_SR_INDEX, 1);
1439         sr1 = I915_READ8(VGA_SR_DATA);
1440         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1441         udelay(100);
1442
1443         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1444 }
1445
1446 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1447 {
1448         struct drm_device *dev = crtc->dev;
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450         u32 dpa_ctl;
1451
1452         DRM_DEBUG_KMS("\n");
1453         dpa_ctl = I915_READ(DP_A);
1454         dpa_ctl &= ~DP_PLL_ENABLE;
1455         I915_WRITE(DP_A, dpa_ctl);
1456 }
1457
1458 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1459 {
1460         struct drm_device *dev = crtc->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 dpa_ctl;
1463
1464         dpa_ctl = I915_READ(DP_A);
1465         dpa_ctl |= DP_PLL_ENABLE;
1466         I915_WRITE(DP_A, dpa_ctl);
1467         udelay(200);
1468 }
1469
1470
1471 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1472 {
1473         struct drm_device *dev = crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         u32 dpa_ctl;
1476
1477         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1478         dpa_ctl = I915_READ(DP_A);
1479         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1480
1481         if (clock < 200000) {
1482                 u32 temp;
1483                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1484                 /* workaround for 160Mhz:
1485                    1) program 0x4600c bits 15:0 = 0x8124
1486                    2) program 0x46010 bit 0 = 1
1487                    3) program 0x46034 bit 24 = 1
1488                    4) program 0x64000 bit 14 = 1
1489                    */
1490                 temp = I915_READ(0x4600c);
1491                 temp &= 0xffff0000;
1492                 I915_WRITE(0x4600c, temp | 0x8124);
1493
1494                 temp = I915_READ(0x46010);
1495                 I915_WRITE(0x46010, temp | 1);
1496
1497                 temp = I915_READ(0x46034);
1498                 I915_WRITE(0x46034, temp | (1 << 24));
1499         } else {
1500                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1501         }
1502         I915_WRITE(DP_A, dpa_ctl);
1503
1504         udelay(500);
1505 }
1506
1507 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1508 {
1509         struct drm_device *dev = crtc->dev;
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1512         int pipe = intel_crtc->pipe;
1513         int plane = intel_crtc->plane;
1514         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1515         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1516         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1517         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1518         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1519         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1520         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1521         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1522         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1523         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1524         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1525         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1526         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1527         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1528         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1529         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1530         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1531         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1532         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1533         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1534         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1535         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1536         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1537         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1538         u32 temp;
1539         int tries = 5, j, n;
1540         u32 pipe_bpc;
1541
1542         temp = I915_READ(pipeconf_reg);
1543         pipe_bpc = temp & PIPE_BPC_MASK;
1544
1545         /* XXX: When our outputs are all unaware of DPMS modes other than off
1546          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1547          */
1548         switch (mode) {
1549         case DRM_MODE_DPMS_ON:
1550         case DRM_MODE_DPMS_STANDBY:
1551         case DRM_MODE_DPMS_SUSPEND:
1552                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1553
1554                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1555                         temp = I915_READ(PCH_LVDS);
1556                         if ((temp & LVDS_PORT_EN) == 0) {
1557                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1558                                 POSTING_READ(PCH_LVDS);
1559                         }
1560                 }
1561
1562                 if (HAS_eDP) {
1563                         /* enable eDP PLL */
1564                         ironlake_enable_pll_edp(crtc);
1565                 } else {
1566                         /* enable PCH DPLL */
1567                         temp = I915_READ(pch_dpll_reg);
1568                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1569                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1570                                 I915_READ(pch_dpll_reg);
1571                         }
1572
1573                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1574                         temp = I915_READ(fdi_rx_reg);
1575                         /*
1576                          * make the BPC in FDI Rx be consistent with that in
1577                          * pipeconf reg.
1578                          */
1579                         temp &= ~(0x7 << 16);
1580                         temp |= (pipe_bpc << 11);
1581                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1582                                         FDI_SEL_PCDCLK |
1583                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1584                         I915_READ(fdi_rx_reg);
1585                         udelay(200);
1586
1587                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1588                         temp = I915_READ(fdi_tx_reg);
1589                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1590                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1591                                 I915_READ(fdi_tx_reg);
1592                                 udelay(100);
1593                         }
1594                 }
1595
1596                 /* Enable panel fitting for LVDS */
1597                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1598                         temp = I915_READ(pf_ctl_reg);
1599                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1600
1601                         /* currently full aspect */
1602                         I915_WRITE(pf_win_pos, 0);
1603
1604                         I915_WRITE(pf_win_size,
1605                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1606                                    (dev_priv->panel_fixed_mode->vdisplay));
1607                 }
1608
1609                 /* Enable CPU pipe */
1610                 temp = I915_READ(pipeconf_reg);
1611                 if ((temp & PIPEACONF_ENABLE) == 0) {
1612                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1613                         I915_READ(pipeconf_reg);
1614                         udelay(100);
1615                 }
1616
1617                 /* configure and enable CPU plane */
1618                 temp = I915_READ(dspcntr_reg);
1619                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1620                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1621                         /* Flush the plane changes */
1622                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1623                 }
1624
1625                 if (!HAS_eDP) {
1626                         /* enable CPU FDI TX and PCH FDI RX */
1627                         temp = I915_READ(fdi_tx_reg);
1628                         temp |= FDI_TX_ENABLE;
1629                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1630                         temp &= ~FDI_LINK_TRAIN_NONE;
1631                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1632                         I915_WRITE(fdi_tx_reg, temp);
1633                         I915_READ(fdi_tx_reg);
1634
1635                         temp = I915_READ(fdi_rx_reg);
1636                         temp &= ~FDI_LINK_TRAIN_NONE;
1637                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1638                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1639                         I915_READ(fdi_rx_reg);
1640
1641                         udelay(150);
1642
1643                         /* Train FDI. */
1644                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1645                            for train result */
1646                         temp = I915_READ(fdi_rx_imr_reg);
1647                         temp &= ~FDI_RX_SYMBOL_LOCK;
1648                         temp &= ~FDI_RX_BIT_LOCK;
1649                         I915_WRITE(fdi_rx_imr_reg, temp);
1650                         I915_READ(fdi_rx_imr_reg);
1651                         udelay(150);
1652
1653                         temp = I915_READ(fdi_rx_iir_reg);
1654                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1655
1656                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1657                                 for (j = 0; j < tries; j++) {
1658                                         temp = I915_READ(fdi_rx_iir_reg);
1659                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1660                                                                 temp);
1661                                         if (temp & FDI_RX_BIT_LOCK)
1662                                                 break;
1663                                         udelay(200);
1664                                 }
1665                                 if (j != tries)
1666                                         I915_WRITE(fdi_rx_iir_reg,
1667                                                         temp | FDI_RX_BIT_LOCK);
1668                                 else
1669                                         DRM_DEBUG_KMS("train 1 fail\n");
1670                         } else {
1671                                 I915_WRITE(fdi_rx_iir_reg,
1672                                                 temp | FDI_RX_BIT_LOCK);
1673                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1674                         }
1675                         temp = I915_READ(fdi_tx_reg);
1676                         temp &= ~FDI_LINK_TRAIN_NONE;
1677                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1678                         I915_WRITE(fdi_tx_reg, temp);
1679
1680                         temp = I915_READ(fdi_rx_reg);
1681                         temp &= ~FDI_LINK_TRAIN_NONE;
1682                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1683                         I915_WRITE(fdi_rx_reg, temp);
1684
1685                         udelay(150);
1686
1687                         temp = I915_READ(fdi_rx_iir_reg);
1688                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1689
1690                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1691                                 for (j = 0; j < tries; j++) {
1692                                         temp = I915_READ(fdi_rx_iir_reg);
1693                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1694                                                                 temp);
1695                                         if (temp & FDI_RX_SYMBOL_LOCK)
1696                                                 break;
1697                                         udelay(200);
1698                                 }
1699                                 if (j != tries) {
1700                                         I915_WRITE(fdi_rx_iir_reg,
1701                                                         temp | FDI_RX_SYMBOL_LOCK);
1702                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1703                                 } else
1704                                         DRM_DEBUG_KMS("train 2 fail\n");
1705                         } else {
1706                                 I915_WRITE(fdi_rx_iir_reg,
1707                                                 temp | FDI_RX_SYMBOL_LOCK);
1708                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1709                         }
1710                         DRM_DEBUG_KMS("train done\n");
1711
1712                         /* set transcoder timing */
1713                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1714                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1715                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1716
1717                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1718                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1719                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1720
1721                         /* enable PCH transcoder */
1722                         temp = I915_READ(transconf_reg);
1723                         /*
1724                          * make the BPC in transcoder be consistent with
1725                          * that in pipeconf reg.
1726                          */
1727                         temp &= ~PIPE_BPC_MASK;
1728                         temp |= pipe_bpc;
1729                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1730                         I915_READ(transconf_reg);
1731
1732                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1733                                 ;
1734
1735                         /* enable normal */
1736
1737                         temp = I915_READ(fdi_tx_reg);
1738                         temp &= ~FDI_LINK_TRAIN_NONE;
1739                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1740                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1741                         I915_READ(fdi_tx_reg);
1742
1743                         temp = I915_READ(fdi_rx_reg);
1744                         temp &= ~FDI_LINK_TRAIN_NONE;
1745                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1746                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1747                         I915_READ(fdi_rx_reg);
1748
1749                         /* wait one idle pattern time */
1750                         udelay(100);
1751
1752                 }
1753
1754                 intel_crtc_load_lut(crtc);
1755
1756         break;
1757         case DRM_MODE_DPMS_OFF:
1758                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1759
1760                 drm_vblank_off(dev, pipe);
1761                 /* Disable display plane */
1762                 temp = I915_READ(dspcntr_reg);
1763                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1764                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1765                         /* Flush the plane changes */
1766                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1767                         I915_READ(dspbase_reg);
1768                 }
1769
1770                 i915_disable_vga(dev);
1771
1772                 /* disable cpu pipe, disable after all planes disabled */
1773                 temp = I915_READ(pipeconf_reg);
1774                 if ((temp & PIPEACONF_ENABLE) != 0) {
1775                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1776                         I915_READ(pipeconf_reg);
1777                         n = 0;
1778                         /* wait for cpu pipe off, pipe state */
1779                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1780                                 n++;
1781                                 if (n < 60) {
1782                                         udelay(500);
1783                                         continue;
1784                                 } else {
1785                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1786                                                                 pipe);
1787                                         break;
1788                                 }
1789                         }
1790                 } else
1791                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1792
1793                 udelay(100);
1794
1795                 /* Disable PF */
1796                 temp = I915_READ(pf_ctl_reg);
1797                 if ((temp & PF_ENABLE) != 0) {
1798                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1799                         I915_READ(pf_ctl_reg);
1800                 }
1801                 I915_WRITE(pf_win_size, 0);
1802
1803                 /* disable CPU FDI tx and PCH FDI rx */
1804                 temp = I915_READ(fdi_tx_reg);
1805                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1806                 I915_READ(fdi_tx_reg);
1807
1808                 temp = I915_READ(fdi_rx_reg);
1809                 /* BPC in FDI rx is consistent with that in pipeconf */
1810                 temp &= ~(0x07 << 16);
1811                 temp |= (pipe_bpc << 11);
1812                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1813                 I915_READ(fdi_rx_reg);
1814
1815                 udelay(100);
1816
1817                 /* still set train pattern 1 */
1818                 temp = I915_READ(fdi_tx_reg);
1819                 temp &= ~FDI_LINK_TRAIN_NONE;
1820                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1821                 I915_WRITE(fdi_tx_reg, temp);
1822
1823                 temp = I915_READ(fdi_rx_reg);
1824                 temp &= ~FDI_LINK_TRAIN_NONE;
1825                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1826                 I915_WRITE(fdi_rx_reg, temp);
1827
1828                 udelay(100);
1829
1830                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1831                         temp = I915_READ(PCH_LVDS);
1832                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1833                         I915_READ(PCH_LVDS);
1834                         udelay(100);
1835                 }
1836
1837                 /* disable PCH transcoder */
1838                 temp = I915_READ(transconf_reg);
1839                 if ((temp & TRANS_ENABLE) != 0) {
1840                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1841                         I915_READ(transconf_reg);
1842                         n = 0;
1843                         /* wait for PCH transcoder off, transcoder state */
1844                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1845                                 n++;
1846                                 if (n < 60) {
1847                                         udelay(500);
1848                                         continue;
1849                                 } else {
1850                                         DRM_DEBUG_KMS("transcoder %d off "
1851                                                         "delay\n", pipe);
1852                                         break;
1853                                 }
1854                         }
1855                 }
1856                 temp = I915_READ(transconf_reg);
1857                 /* BPC in transcoder is consistent with that in pipeconf */
1858                 temp &= ~PIPE_BPC_MASK;
1859                 temp |= pipe_bpc;
1860                 I915_WRITE(transconf_reg, temp);
1861                 I915_READ(transconf_reg);
1862                 udelay(100);
1863
1864                 /* disable PCH DPLL */
1865                 temp = I915_READ(pch_dpll_reg);
1866                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1867                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1868                         I915_READ(pch_dpll_reg);
1869                 }
1870
1871                 if (HAS_eDP) {
1872                         ironlake_disable_pll_edp(crtc);
1873                 }
1874
1875                 temp = I915_READ(fdi_rx_reg);
1876                 temp &= ~FDI_SEL_PCDCLK;
1877                 I915_WRITE(fdi_rx_reg, temp);
1878                 I915_READ(fdi_rx_reg);
1879
1880                 temp = I915_READ(fdi_rx_reg);
1881                 temp &= ~FDI_RX_PLL_ENABLE;
1882                 I915_WRITE(fdi_rx_reg, temp);
1883                 I915_READ(fdi_rx_reg);
1884
1885                 /* Disable CPU FDI TX PLL */
1886                 temp = I915_READ(fdi_tx_reg);
1887                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1888                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1889                         I915_READ(fdi_tx_reg);
1890                         udelay(100);
1891                 }
1892
1893                 /* Wait for the clocks to turn off. */
1894                 udelay(100);
1895                 break;
1896         }
1897 }
1898
1899 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1900 {
1901         struct intel_overlay *overlay;
1902         int ret;
1903
1904         if (!enable && intel_crtc->overlay) {
1905                 overlay = intel_crtc->overlay;
1906                 mutex_lock(&overlay->dev->struct_mutex);
1907                 for (;;) {
1908                         ret = intel_overlay_switch_off(overlay);
1909                         if (ret == 0)
1910                                 break;
1911
1912                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1913                         if (ret != 0) {
1914                                 /* overlay doesn't react anymore. Usually
1915                                  * results in a black screen and an unkillable
1916                                  * X server. */
1917                                 BUG();
1918                                 overlay->hw_wedged = HW_WEDGED;
1919                                 break;
1920                         }
1921                 }
1922                 mutex_unlock(&overlay->dev->struct_mutex);
1923         }
1924         /* Let userspace switch the overlay on again. In most cases userspace
1925          * has to recompute where to put it anyway. */
1926
1927         return;
1928 }
1929
1930 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1931 {
1932         struct drm_device *dev = crtc->dev;
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1935         int pipe = intel_crtc->pipe;
1936         int plane = intel_crtc->plane;
1937         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1938         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1939         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1940         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1941         u32 temp;
1942
1943         /* XXX: When our outputs are all unaware of DPMS modes other than off
1944          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1945          */
1946         switch (mode) {
1947         case DRM_MODE_DPMS_ON:
1948         case DRM_MODE_DPMS_STANDBY:
1949         case DRM_MODE_DPMS_SUSPEND:
1950                 intel_update_watermarks(dev);
1951
1952                 /* Enable the DPLL */
1953                 temp = I915_READ(dpll_reg);
1954                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1955                         I915_WRITE(dpll_reg, temp);
1956                         I915_READ(dpll_reg);
1957                         /* Wait for the clocks to stabilize. */
1958                         udelay(150);
1959                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1960                         I915_READ(dpll_reg);
1961                         /* Wait for the clocks to stabilize. */
1962                         udelay(150);
1963                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1964                         I915_READ(dpll_reg);
1965                         /* Wait for the clocks to stabilize. */
1966                         udelay(150);
1967                 }
1968
1969                 /* Enable the pipe */
1970                 temp = I915_READ(pipeconf_reg);
1971                 if ((temp & PIPEACONF_ENABLE) == 0)
1972                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1973
1974                 /* Enable the plane */
1975                 temp = I915_READ(dspcntr_reg);
1976                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1977                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1978                         /* Flush the plane changes */
1979                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1980                 }
1981
1982                 intel_crtc_load_lut(crtc);
1983
1984                 if ((IS_I965G(dev) || plane == 0))
1985                         intel_update_fbc(crtc, &crtc->mode);
1986
1987                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1988                 intel_crtc_dpms_overlay(intel_crtc, true);
1989         break;
1990         case DRM_MODE_DPMS_OFF:
1991                 intel_update_watermarks(dev);
1992
1993                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1994                 intel_crtc_dpms_overlay(intel_crtc, false);
1995                 drm_vblank_off(dev, pipe);
1996
1997                 if (dev_priv->cfb_plane == plane &&
1998                     dev_priv->display.disable_fbc)
1999                         dev_priv->display.disable_fbc(dev);
2000
2001                 /* Disable the VGA plane that we never use */
2002                 i915_disable_vga(dev);
2003
2004                 /* Disable display plane */
2005                 temp = I915_READ(dspcntr_reg);
2006                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2007                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2008                         /* Flush the plane changes */
2009                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2010                         I915_READ(dspbase_reg);
2011                 }
2012
2013                 if (!IS_I9XX(dev)) {
2014                         /* Wait for vblank for the disable to take effect */
2015                         intel_wait_for_vblank(dev);
2016                 }
2017
2018                 /* Next, disable display pipes */
2019                 temp = I915_READ(pipeconf_reg);
2020                 if ((temp & PIPEACONF_ENABLE) != 0) {
2021                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2022                         I915_READ(pipeconf_reg);
2023                 }
2024
2025                 /* Wait for vblank for the disable to take effect. */
2026                 intel_wait_for_vblank(dev);
2027
2028                 temp = I915_READ(dpll_reg);
2029                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2030                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2031                         I915_READ(dpll_reg);
2032                 }
2033
2034                 /* Wait for the clocks to turn off. */
2035                 udelay(150);
2036                 break;
2037         }
2038 }
2039
2040 /**
2041  * Sets the power management mode of the pipe and plane.
2042  *
2043  * This code should probably grow support for turning the cursor off and back
2044  * on appropriately at the same time as we're turning the pipe off/on.
2045  */
2046 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2047 {
2048         struct drm_device *dev = crtc->dev;
2049         struct drm_i915_private *dev_priv = dev->dev_private;
2050         struct drm_i915_master_private *master_priv;
2051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2052         int pipe = intel_crtc->pipe;
2053         bool enabled;
2054
2055         dev_priv->display.dpms(crtc, mode);
2056
2057         intel_crtc->dpms_mode = mode;
2058
2059         if (!dev->primary->master)
2060                 return;
2061
2062         master_priv = dev->primary->master->driver_priv;
2063         if (!master_priv->sarea_priv)
2064                 return;
2065
2066         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2067
2068         switch (pipe) {
2069         case 0:
2070                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2071                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2072                 break;
2073         case 1:
2074                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2075                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2076                 break;
2077         default:
2078                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2079                 break;
2080         }
2081 }
2082
2083 static void intel_crtc_prepare (struct drm_crtc *crtc)
2084 {
2085         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2086         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2087 }
2088
2089 static void intel_crtc_commit (struct drm_crtc *crtc)
2090 {
2091         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2092         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2093 }
2094
2095 void intel_encoder_prepare (struct drm_encoder *encoder)
2096 {
2097         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2098         /* lvds has its own version of prepare see intel_lvds_prepare */
2099         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2100 }
2101
2102 void intel_encoder_commit (struct drm_encoder *encoder)
2103 {
2104         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2105         /* lvds has its own version of commit see intel_lvds_commit */
2106         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2107 }
2108
2109 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2110                                   struct drm_display_mode *mode,
2111                                   struct drm_display_mode *adjusted_mode)
2112 {
2113         struct drm_device *dev = crtc->dev;
2114         if (IS_IRONLAKE(dev)) {
2115                 /* FDI link clock is fixed at 2.7G */
2116                 if (mode->clock * 3 > 27000 * 4)
2117                         return MODE_CLOCK_HIGH;
2118         }
2119         return true;
2120 }
2121
2122 static int i945_get_display_clock_speed(struct drm_device *dev)
2123 {
2124         return 400000;
2125 }
2126
2127 static int i915_get_display_clock_speed(struct drm_device *dev)
2128 {
2129         return 333000;
2130 }
2131
2132 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2133 {
2134         return 200000;
2135 }
2136
2137 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2138 {
2139         u16 gcfgc = 0;
2140
2141         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2142
2143         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2144                 return 133000;
2145         else {
2146                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2147                 case GC_DISPLAY_CLOCK_333_MHZ:
2148                         return 333000;
2149                 default:
2150                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2151                         return 190000;
2152                 }
2153         }
2154 }
2155
2156 static int i865_get_display_clock_speed(struct drm_device *dev)
2157 {
2158         return 266000;
2159 }
2160
2161 static int i855_get_display_clock_speed(struct drm_device *dev)
2162 {
2163         u16 hpllcc = 0;
2164         /* Assume that the hardware is in the high speed state.  This
2165          * should be the default.
2166          */
2167         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2168         case GC_CLOCK_133_200:
2169         case GC_CLOCK_100_200:
2170                 return 200000;
2171         case GC_CLOCK_166_250:
2172                 return 250000;
2173         case GC_CLOCK_100_133:
2174                 return 133000;
2175         }
2176
2177         /* Shouldn't happen */
2178         return 0;
2179 }
2180
2181 static int i830_get_display_clock_speed(struct drm_device *dev)
2182 {
2183         return 133000;
2184 }
2185
2186 /**
2187  * Return the pipe currently connected to the panel fitter,
2188  * or -1 if the panel fitter is not present or not in use
2189  */
2190 int intel_panel_fitter_pipe (struct drm_device *dev)
2191 {
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         u32  pfit_control;
2194
2195         /* i830 doesn't have a panel fitter */
2196         if (IS_I830(dev))
2197                 return -1;
2198
2199         pfit_control = I915_READ(PFIT_CONTROL);
2200
2201         /* See if the panel fitter is in use */
2202         if ((pfit_control & PFIT_ENABLE) == 0)
2203                 return -1;
2204
2205         /* 965 can place panel fitter on either pipe */
2206         if (IS_I965G(dev))
2207                 return (pfit_control >> 29) & 0x3;
2208
2209         /* older chips can only use pipe 1 */
2210         return 1;
2211 }
2212
2213 struct fdi_m_n {
2214         u32        tu;
2215         u32        gmch_m;
2216         u32        gmch_n;
2217         u32        link_m;
2218         u32        link_n;
2219 };
2220
2221 static void
2222 fdi_reduce_ratio(u32 *num, u32 *den)
2223 {
2224         while (*num > 0xffffff || *den > 0xffffff) {
2225                 *num >>= 1;
2226                 *den >>= 1;
2227         }
2228 }
2229
2230 #define DATA_N 0x800000
2231 #define LINK_N 0x80000
2232
2233 static void
2234 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2235                      int link_clock, struct fdi_m_n *m_n)
2236 {
2237         u64 temp;
2238
2239         m_n->tu = 64; /* default size */
2240
2241         temp = (u64) DATA_N * pixel_clock;
2242         temp = div_u64(temp, link_clock);
2243         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2244         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2245         m_n->gmch_n = DATA_N;
2246         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2247
2248         temp = (u64) LINK_N * pixel_clock;
2249         m_n->link_m = div_u64(temp, link_clock);
2250         m_n->link_n = LINK_N;
2251         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2252 }
2253
2254
2255 struct intel_watermark_params {
2256         unsigned long fifo_size;
2257         unsigned long max_wm;
2258         unsigned long default_wm;
2259         unsigned long guard_size;
2260         unsigned long cacheline_size;
2261 };
2262
2263 /* Pineview has different values for various configs */
2264 static struct intel_watermark_params pineview_display_wm = {
2265         PINEVIEW_DISPLAY_FIFO,
2266         PINEVIEW_MAX_WM,
2267         PINEVIEW_DFT_WM,
2268         PINEVIEW_GUARD_WM,
2269         PINEVIEW_FIFO_LINE_SIZE
2270 };
2271 static struct intel_watermark_params pineview_display_hplloff_wm = {
2272         PINEVIEW_DISPLAY_FIFO,
2273         PINEVIEW_MAX_WM,
2274         PINEVIEW_DFT_HPLLOFF_WM,
2275         PINEVIEW_GUARD_WM,
2276         PINEVIEW_FIFO_LINE_SIZE
2277 };
2278 static struct intel_watermark_params pineview_cursor_wm = {
2279         PINEVIEW_CURSOR_FIFO,
2280         PINEVIEW_CURSOR_MAX_WM,
2281         PINEVIEW_CURSOR_DFT_WM,
2282         PINEVIEW_CURSOR_GUARD_WM,
2283         PINEVIEW_FIFO_LINE_SIZE,
2284 };
2285 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2286         PINEVIEW_CURSOR_FIFO,
2287         PINEVIEW_CURSOR_MAX_WM,
2288         PINEVIEW_CURSOR_DFT_WM,
2289         PINEVIEW_CURSOR_GUARD_WM,
2290         PINEVIEW_FIFO_LINE_SIZE
2291 };
2292 static struct intel_watermark_params g4x_wm_info = {
2293         G4X_FIFO_SIZE,
2294         G4X_MAX_WM,
2295         G4X_MAX_WM,
2296         2,
2297         G4X_FIFO_LINE_SIZE,
2298 };
2299 static struct intel_watermark_params i945_wm_info = {
2300         I945_FIFO_SIZE,
2301         I915_MAX_WM,
2302         1,
2303         2,
2304         I915_FIFO_LINE_SIZE
2305 };
2306 static struct intel_watermark_params i915_wm_info = {
2307         I915_FIFO_SIZE,
2308         I915_MAX_WM,
2309         1,
2310         2,
2311         I915_FIFO_LINE_SIZE
2312 };
2313 static struct intel_watermark_params i855_wm_info = {
2314         I855GM_FIFO_SIZE,
2315         I915_MAX_WM,
2316         1,
2317         2,
2318         I830_FIFO_LINE_SIZE
2319 };
2320 static struct intel_watermark_params i830_wm_info = {
2321         I830_FIFO_SIZE,
2322         I915_MAX_WM,
2323         1,
2324         2,
2325         I830_FIFO_LINE_SIZE
2326 };
2327
2328 /**
2329  * intel_calculate_wm - calculate watermark level
2330  * @clock_in_khz: pixel clock
2331  * @wm: chip FIFO params
2332  * @pixel_size: display pixel size
2333  * @latency_ns: memory latency for the platform
2334  *
2335  * Calculate the watermark level (the level at which the display plane will
2336  * start fetching from memory again).  Each chip has a different display
2337  * FIFO size and allocation, so the caller needs to figure that out and pass
2338  * in the correct intel_watermark_params structure.
2339  *
2340  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2341  * on the pixel size.  When it reaches the watermark level, it'll start
2342  * fetching FIFO line sized based chunks from memory until the FIFO fills
2343  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2344  * will occur, and a display engine hang could result.
2345  */
2346 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2347                                         struct intel_watermark_params *wm,
2348                                         int pixel_size,
2349                                         unsigned long latency_ns)
2350 {
2351         long entries_required, wm_size;
2352
2353         /*
2354          * Note: we need to make sure we don't overflow for various clock &
2355          * latency values.
2356          * clocks go from a few thousand to several hundred thousand.
2357          * latency is usually a few thousand
2358          */
2359         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2360                 1000;
2361         entries_required /= wm->cacheline_size;
2362
2363         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2364
2365         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2366
2367         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2368
2369         /* Don't promote wm_size to unsigned... */
2370         if (wm_size > (long)wm->max_wm)
2371                 wm_size = wm->max_wm;
2372         if (wm_size <= 0)
2373                 wm_size = wm->default_wm;
2374         return wm_size;
2375 }
2376
2377 struct cxsr_latency {
2378         int is_desktop;
2379         unsigned long fsb_freq;
2380         unsigned long mem_freq;
2381         unsigned long display_sr;
2382         unsigned long display_hpll_disable;
2383         unsigned long cursor_sr;
2384         unsigned long cursor_hpll_disable;
2385 };
2386
2387 static struct cxsr_latency cxsr_latency_table[] = {
2388         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2389         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2390         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2391
2392         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2393         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2394         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2395
2396         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2397         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2398         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2399
2400         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2401         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2402         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2403
2404         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2405         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2406         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2407
2408         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2409         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2410         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2411 };
2412
2413 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2414                                                    int mem)
2415 {
2416         int i;
2417         struct cxsr_latency *latency;
2418
2419         if (fsb == 0 || mem == 0)
2420                 return NULL;
2421
2422         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2423                 latency = &cxsr_latency_table[i];
2424                 if (is_desktop == latency->is_desktop &&
2425                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2426                         return latency;
2427         }
2428
2429         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2430
2431         return NULL;
2432 }
2433
2434 static void pineview_disable_cxsr(struct drm_device *dev)
2435 {
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         u32 reg;
2438
2439         /* deactivate cxsr */
2440         reg = I915_READ(DSPFW3);
2441         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2442         I915_WRITE(DSPFW3, reg);
2443         DRM_INFO("Big FIFO is disabled\n");
2444 }
2445
2446 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2447                                  int pixel_size)
2448 {
2449         struct drm_i915_private *dev_priv = dev->dev_private;
2450         u32 reg;
2451         unsigned long wm;
2452         struct cxsr_latency *latency;
2453
2454         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2455                 dev_priv->mem_freq);
2456         if (!latency) {
2457                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2458                 pineview_disable_cxsr(dev);
2459                 return;
2460         }
2461
2462         /* Display SR */
2463         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2464                                 latency->display_sr);
2465         reg = I915_READ(DSPFW1);
2466         reg &= 0x7fffff;
2467         reg |= wm << 23;
2468         I915_WRITE(DSPFW1, reg);
2469         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2470
2471         /* cursor SR */
2472         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2473                                 latency->cursor_sr);
2474         reg = I915_READ(DSPFW3);
2475         reg &= ~(0x3f << 24);
2476         reg |= (wm & 0x3f) << 24;
2477         I915_WRITE(DSPFW3, reg);
2478
2479         /* Display HPLL off SR */
2480         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2481                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2482         reg = I915_READ(DSPFW3);
2483         reg &= 0xfffffe00;
2484         reg |= wm & 0x1ff;
2485         I915_WRITE(DSPFW3, reg);
2486
2487         /* cursor HPLL off SR */
2488         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2489                                 latency->cursor_hpll_disable);
2490         reg = I915_READ(DSPFW3);
2491         reg &= ~(0x3f << 16);
2492         reg |= (wm & 0x3f) << 16;
2493         I915_WRITE(DSPFW3, reg);
2494         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2495
2496         /* activate cxsr */
2497         reg = I915_READ(DSPFW3);
2498         reg |= PINEVIEW_SELF_REFRESH_EN;
2499         I915_WRITE(DSPFW3, reg);
2500
2501         DRM_INFO("Big FIFO is enabled\n");
2502
2503         return;
2504 }
2505
2506 /*
2507  * Latency for FIFO fetches is dependent on several factors:
2508  *   - memory configuration (speed, channels)
2509  *   - chipset
2510  *   - current MCH state
2511  * It can be fairly high in some situations, so here we assume a fairly
2512  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2513  * set this value too high, the FIFO will fetch frequently to stay full)
2514  * and power consumption (set it too low to save power and we might see
2515  * FIFO underruns and display "flicker").
2516  *
2517  * A value of 5us seems to be a good balance; safe for very low end
2518  * platforms but not overly aggressive on lower latency configs.
2519  */
2520 static const int latency_ns = 5000;
2521
2522 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         uint32_t dsparb = I915_READ(DSPARB);
2526         int size;
2527
2528         if (plane == 0)
2529                 size = dsparb & 0x7f;
2530         else
2531                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2532                         (dsparb & 0x7f);
2533
2534         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2535                         plane ? "B" : "A", size);
2536
2537         return size;
2538 }
2539
2540 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2541 {
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         uint32_t dsparb = I915_READ(DSPARB);
2544         int size;
2545
2546         if (plane == 0)
2547                 size = dsparb & 0x1ff;
2548         else
2549                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2550                         (dsparb & 0x1ff);
2551         size >>= 1; /* Convert to cachelines */
2552
2553         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2554                         plane ? "B" : "A", size);
2555
2556         return size;
2557 }
2558
2559 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2560 {
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         uint32_t dsparb = I915_READ(DSPARB);
2563         int size;
2564
2565         size = dsparb & 0x7f;
2566         size >>= 2; /* Convert to cachelines */
2567
2568         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2569                         plane ? "B" : "A",
2570                   size);
2571
2572         return size;
2573 }
2574
2575 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2576 {
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         uint32_t dsparb = I915_READ(DSPARB);
2579         int size;
2580
2581         size = dsparb & 0x7f;
2582         size >>= 1; /* Convert to cachelines */
2583
2584         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2585                         plane ? "B" : "A", size);
2586
2587         return size;
2588 }
2589
2590 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2591                           int planeb_clock, int sr_hdisplay, int pixel_size)
2592 {
2593         struct drm_i915_private *dev_priv = dev->dev_private;
2594         int total_size, cacheline_size;
2595         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2596         struct intel_watermark_params planea_params, planeb_params;
2597         unsigned long line_time_us;
2598         int sr_clock, sr_entries = 0, entries_required;
2599
2600         /* Create copies of the base settings for each pipe */
2601         planea_params = planeb_params = g4x_wm_info;
2602
2603         /* Grab a couple of global values before we overwrite them */
2604         total_size = planea_params.fifo_size;
2605         cacheline_size = planea_params.cacheline_size;
2606
2607         /*
2608          * Note: we need to make sure we don't overflow for various clock &
2609          * latency values.
2610          * clocks go from a few thousand to several hundred thousand.
2611          * latency is usually a few thousand
2612          */
2613         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2614                 1000;
2615         entries_required /= G4X_FIFO_LINE_SIZE;
2616         planea_wm = entries_required + planea_params.guard_size;
2617
2618         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2619                 1000;
2620         entries_required /= G4X_FIFO_LINE_SIZE;
2621         planeb_wm = entries_required + planeb_params.guard_size;
2622
2623         cursora_wm = cursorb_wm = 16;
2624         cursor_sr = 32;
2625
2626         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2627
2628         /* Calc sr entries for one plane configs */
2629         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2630                 /* self-refresh has much higher latency */
2631                 static const int sr_latency_ns = 12000;
2632
2633                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2634                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2635
2636                 /* Use ns/us then divide to preserve precision */
2637                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2638                               pixel_size * sr_hdisplay) / 1000;
2639                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2640                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2641                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2642         } else {
2643                 /* Turn off self refresh if both pipes are enabled */
2644                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2645                                         & ~FW_BLC_SELF_EN);
2646         }
2647
2648         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2649                   planea_wm, planeb_wm, sr_entries);
2650
2651         planea_wm &= 0x3f;
2652         planeb_wm &= 0x3f;
2653
2654         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2655                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2656                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2657         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2658                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2659         /* HPLL off in SR has some issues on G4x... disable it */
2660         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2661                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2662 }
2663
2664 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2665                            int planeb_clock, int sr_hdisplay, int pixel_size)
2666 {
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         unsigned long line_time_us;
2669         int sr_clock, sr_entries, srwm = 1;
2670
2671         /* Calc sr entries for one plane configs */
2672         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2673                 /* self-refresh has much higher latency */
2674                 static const int sr_latency_ns = 12000;
2675
2676                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2677                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2678
2679                 /* Use ns/us then divide to preserve precision */
2680                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2681                               pixel_size * sr_hdisplay) / 1000;
2682                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2683                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2684                 srwm = I945_FIFO_SIZE - sr_entries;
2685                 if (srwm < 0)
2686                         srwm = 1;
2687                 srwm &= 0x3f;
2688                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2689         } else {
2690                 /* Turn off self refresh if both pipes are enabled */
2691                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2692                                         & ~FW_BLC_SELF_EN);
2693         }
2694
2695         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2696                       srwm);
2697
2698         /* 965 has limitations... */
2699         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2700                    (8 << 0));
2701         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2702 }
2703
2704 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2705                            int planeb_clock, int sr_hdisplay, int pixel_size)
2706 {
2707         struct drm_i915_private *dev_priv = dev->dev_private;
2708         uint32_t fwater_lo;
2709         uint32_t fwater_hi;
2710         int total_size, cacheline_size, cwm, srwm = 1;
2711         int planea_wm, planeb_wm;
2712         struct intel_watermark_params planea_params, planeb_params;
2713         unsigned long line_time_us;
2714         int sr_clock, sr_entries = 0;
2715
2716         /* Create copies of the base settings for each pipe */
2717         if (IS_I965GM(dev) || IS_I945GM(dev))
2718                 planea_params = planeb_params = i945_wm_info;
2719         else if (IS_I9XX(dev))
2720                 planea_params = planeb_params = i915_wm_info;
2721         else
2722                 planea_params = planeb_params = i855_wm_info;
2723
2724         /* Grab a couple of global values before we overwrite them */
2725         total_size = planea_params.fifo_size;
2726         cacheline_size = planea_params.cacheline_size;
2727
2728         /* Update per-plane FIFO sizes */
2729         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2730         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2731
2732         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2733                                        pixel_size, latency_ns);
2734         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2735                                        pixel_size, latency_ns);
2736         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2737
2738         /*
2739          * Overlay gets an aggressive default since video jitter is bad.
2740          */
2741         cwm = 2;
2742
2743         /* Calc sr entries for one plane configs */
2744         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2745             (!planea_clock || !planeb_clock)) {
2746                 /* self-refresh has much higher latency */
2747                 static const int sr_latency_ns = 6000;
2748
2749                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2750                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2751
2752                 /* Use ns/us then divide to preserve precision */
2753                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2754                               pixel_size * sr_hdisplay) / 1000;
2755                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2756                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2757                 srwm = total_size - sr_entries;
2758                 if (srwm < 0)
2759                         srwm = 1;
2760
2761                 if (IS_I945G(dev) || IS_I945GM(dev))
2762                         I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
2763                 else if (IS_I915GM(dev)) {
2764                         /* 915M has a smaller SRWM field */
2765                         I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
2766                         I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
2767                 }
2768         } else {
2769                 /* Turn off self refresh if both pipes are enabled */
2770                 if (IS_I945G(dev) || IS_I945GM(dev)) {
2771                         I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2772                                    & ~FW_BLC_SELF_EN);
2773                 } else if (IS_I915GM(dev)) {
2774                         I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
2775                 }
2776         }
2777
2778         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2779                   planea_wm, planeb_wm, cwm, srwm);
2780
2781         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2782         fwater_hi = (cwm & 0x1f);
2783
2784         /* Set request length to 8 cachelines per fetch */
2785         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2786         fwater_hi = fwater_hi | (1 << 8);
2787
2788         I915_WRITE(FW_BLC, fwater_lo);
2789         I915_WRITE(FW_BLC2, fwater_hi);
2790 }
2791
2792 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2793                            int unused2, int pixel_size)
2794 {
2795         struct drm_i915_private *dev_priv = dev->dev_private;
2796         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2797         int planea_wm;
2798
2799         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2800
2801         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2802                                        pixel_size, latency_ns);
2803         fwater_lo |= (3<<8) | planea_wm;
2804
2805         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2806
2807         I915_WRITE(FW_BLC, fwater_lo);
2808 }
2809
2810 /**
2811  * intel_update_watermarks - update FIFO watermark values based on current modes
2812  *
2813  * Calculate watermark values for the various WM regs based on current mode
2814  * and plane configuration.
2815  *
2816  * There are several cases to deal with here:
2817  *   - normal (i.e. non-self-refresh)
2818  *   - self-refresh (SR) mode
2819  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2820  *   - lines are small relative to FIFO size (buffer can hold more than 2
2821  *     lines), so need to account for TLB latency
2822  *
2823  *   The normal calculation is:
2824  *     watermark = dotclock * bytes per pixel * latency
2825  *   where latency is platform & configuration dependent (we assume pessimal
2826  *   values here).
2827  *
2828  *   The SR calculation is:
2829  *     watermark = (trunc(latency/line time)+1) * surface width *
2830  *       bytes per pixel
2831  *   where
2832  *     line time = htotal / dotclock
2833  *   and latency is assumed to be high, as above.
2834  *
2835  * The final value programmed to the register should always be rounded up,
2836  * and include an extra 2 entries to account for clock crossings.
2837  *
2838  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2839  * to set the non-SR watermarks to 8.
2840   */
2841 static void intel_update_watermarks(struct drm_device *dev)
2842 {
2843         struct drm_i915_private *dev_priv = dev->dev_private;
2844         struct drm_crtc *crtc;
2845         struct intel_crtc *intel_crtc;
2846         int sr_hdisplay = 0;
2847         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2848         int enabled = 0, pixel_size = 0;
2849
2850         if (!dev_priv->display.update_wm)
2851                 return;
2852
2853         /* Get the clock config from both planes */
2854         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2855                 intel_crtc = to_intel_crtc(crtc);
2856                 if (crtc->enabled) {
2857                         enabled++;
2858                         if (intel_crtc->plane == 0) {
2859                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2860                                           intel_crtc->pipe, crtc->mode.clock);
2861                                 planea_clock = crtc->mode.clock;
2862                         } else {
2863                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2864                                           intel_crtc->pipe, crtc->mode.clock);
2865                                 planeb_clock = crtc->mode.clock;
2866                         }
2867                         sr_hdisplay = crtc->mode.hdisplay;
2868                         sr_clock = crtc->mode.clock;
2869                         if (crtc->fb)
2870                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2871                         else
2872                                 pixel_size = 4; /* by default */
2873                 }
2874         }
2875
2876         if (enabled <= 0)
2877                 return;
2878
2879         /* Single plane configs can enable self refresh */
2880         if (enabled == 1 && IS_PINEVIEW(dev))
2881                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2882         else if (IS_PINEVIEW(dev))
2883                 pineview_disable_cxsr(dev);
2884
2885         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2886                                     sr_hdisplay, pixel_size);
2887 }
2888
2889 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2890                                struct drm_display_mode *mode,
2891                                struct drm_display_mode *adjusted_mode,
2892                                int x, int y,
2893                                struct drm_framebuffer *old_fb)
2894 {
2895         struct drm_device *dev = crtc->dev;
2896         struct drm_i915_private *dev_priv = dev->dev_private;
2897         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2898         int pipe = intel_crtc->pipe;
2899         int plane = intel_crtc->plane;
2900         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2901         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2902         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2903         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2904         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2905         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2906         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2907         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2908         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2909         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2910         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2911         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2912         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2913         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2914         int refclk, num_outputs = 0;
2915         intel_clock_t clock, reduced_clock;
2916         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2917         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2918         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2919         bool is_edp = false;
2920         struct drm_mode_config *mode_config = &dev->mode_config;
2921         struct drm_connector *connector;
2922         const intel_limit_t *limit;
2923         int ret;
2924         struct fdi_m_n m_n = {0};
2925         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2926         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2927         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2928         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2929         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2930         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2931         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2932         int lvds_reg = LVDS;
2933         u32 temp;
2934         int sdvo_pixel_multiply;
2935         int target_clock;
2936
2937         drm_vblank_pre_modeset(dev, pipe);
2938
2939         list_for_each_entry(connector, &mode_config->connector_list, head) {
2940                 struct intel_output *intel_output = to_intel_output(connector);
2941
2942                 if (!connector->encoder || connector->encoder->crtc != crtc)
2943                         continue;
2944
2945                 switch (intel_output->type) {
2946                 case INTEL_OUTPUT_LVDS:
2947                         is_lvds = true;
2948                         break;
2949                 case INTEL_OUTPUT_SDVO:
2950                 case INTEL_OUTPUT_HDMI:
2951                         is_sdvo = true;
2952                         if (intel_output->needs_tv_clock)
2953                                 is_tv = true;
2954                         break;
2955                 case INTEL_OUTPUT_DVO:
2956                         is_dvo = true;
2957                         break;
2958                 case INTEL_OUTPUT_TVOUT:
2959                         is_tv = true;
2960                         break;
2961                 case INTEL_OUTPUT_ANALOG:
2962                         is_crt = true;
2963                         break;
2964                 case INTEL_OUTPUT_DISPLAYPORT:
2965                         is_dp = true;
2966                         break;
2967                 case INTEL_OUTPUT_EDP:
2968                         is_edp = true;
2969                         break;
2970                 }
2971
2972                 num_outputs++;
2973         }
2974
2975         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2976                 refclk = dev_priv->lvds_ssc_freq * 1000;
2977                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2978                                         refclk / 1000);
2979         } else if (IS_I9XX(dev)) {
2980                 refclk = 96000;
2981                 if (IS_IRONLAKE(dev))
2982                         refclk = 120000; /* 120Mhz refclk */
2983         } else {
2984                 refclk = 48000;
2985         }
2986
2987
2988         /*
2989          * Returns a set of divisors for the desired target clock with the given
2990          * refclk, or FALSE.  The returned values represent the clock equation:
2991          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2992          */
2993         limit = intel_limit(crtc);
2994         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2995         if (!ok) {
2996                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2997                 drm_vblank_post_modeset(dev, pipe);
2998                 return -EINVAL;
2999         }
3000
3001         if (is_lvds && dev_priv->lvds_downclock_avail) {
3002                 has_reduced_clock = limit->find_pll(limit, crtc,
3003                                                             dev_priv->lvds_downclock,
3004                                                             refclk,
3005                                                             &reduced_clock);
3006                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
3007                         /*
3008                          * If the different P is found, it means that we can't
3009                          * switch the display clock by using the FP0/FP1.
3010                          * In such case we will disable the LVDS downclock
3011                          * feature.
3012                          */
3013                         DRM_DEBUG_KMS("Different P is found for "
3014                                                 "LVDS clock/downclock\n");
3015                         has_reduced_clock = 0;
3016                 }
3017         }
3018         /* SDVO TV has fixed PLL values depend on its clock range,
3019            this mirrors vbios setting. */
3020         if (is_sdvo && is_tv) {
3021                 if (adjusted_mode->clock >= 100000
3022                                 && adjusted_mode->clock < 140500) {
3023                         clock.p1 = 2;
3024                         clock.p2 = 10;
3025                         clock.n = 3;
3026                         clock.m1 = 16;
3027                         clock.m2 = 8;
3028                 } else if (adjusted_mode->clock >= 140500
3029                                 && adjusted_mode->clock <= 200000) {
3030                         clock.p1 = 1;
3031                         clock.p2 = 10;
3032                         clock.n = 6;
3033                         clock.m1 = 12;
3034                         clock.m2 = 8;
3035                 }
3036         }
3037
3038         /* FDI link */
3039         if (IS_IRONLAKE(dev)) {
3040                 int lane, link_bw, bpp;
3041                 /* eDP doesn't require FDI link, so just set DP M/N
3042                    according to current link config */
3043                 if (is_edp) {
3044                         struct drm_connector *edp;
3045                         target_clock = mode->clock;
3046                         edp = intel_pipe_get_output(crtc);
3047                         intel_edp_link_config(to_intel_output(edp),
3048                                         &lane, &link_bw);
3049                 } else {
3050                         /* DP over FDI requires target mode clock
3051                            instead of link clock */
3052                         if (is_dp)
3053                                 target_clock = mode->clock;
3054                         else
3055                                 target_clock = adjusted_mode->clock;
3056                         lane = 4;
3057                         link_bw = 270000;
3058                 }
3059
3060                 /* determine panel color depth */
3061                 temp = I915_READ(pipeconf_reg);
3062                 temp &= ~PIPE_BPC_MASK;
3063                 if (is_lvds) {
3064                         int lvds_reg = I915_READ(PCH_LVDS);
3065                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3066                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3067                                 temp |= PIPE_8BPC;
3068                         else
3069                                 temp |= PIPE_6BPC;
3070                 } else if (is_edp) {
3071                         switch (dev_priv->edp_bpp/3) {
3072                         case 8:
3073                                 temp |= PIPE_8BPC;
3074                                 break;
3075                         case 10:
3076                                 temp |= PIPE_10BPC;
3077                                 break;
3078                         case 6:
3079                                 temp |= PIPE_6BPC;
3080                                 break;
3081                         case 12:
3082                                 temp |= PIPE_12BPC;
3083                                 break;
3084                         }
3085                 } else
3086                         temp |= PIPE_8BPC;
3087                 I915_WRITE(pipeconf_reg, temp);
3088                 I915_READ(pipeconf_reg);
3089
3090                 switch (temp & PIPE_BPC_MASK) {
3091                 case PIPE_8BPC:
3092                         bpp = 24;
3093                         break;
3094                 case PIPE_10BPC:
3095                         bpp = 30;
3096                         break;
3097                 case PIPE_6BPC:
3098                         bpp = 18;
3099                         break;
3100                 case PIPE_12BPC:
3101                         bpp = 36;
3102                         break;
3103                 default:
3104                         DRM_ERROR("unknown pipe bpc value\n");
3105                         bpp = 24;
3106                 }
3107
3108                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3109         }
3110
3111         /* Ironlake: try to setup display ref clock before DPLL
3112          * enabling. This is only under driver's control after
3113          * PCH B stepping, previous chipset stepping should be
3114          * ignoring this setting.
3115          */
3116         if (IS_IRONLAKE(dev)) {
3117                 temp = I915_READ(PCH_DREF_CONTROL);
3118                 /* Always enable nonspread source */
3119                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3120                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3121                 I915_WRITE(PCH_DREF_CONTROL, temp);
3122                 POSTING_READ(PCH_DREF_CONTROL);
3123
3124                 temp &= ~DREF_SSC_SOURCE_MASK;
3125                 temp |= DREF_SSC_SOURCE_ENABLE;
3126                 I915_WRITE(PCH_DREF_CONTROL, temp);
3127                 POSTING_READ(PCH_DREF_CONTROL);
3128
3129                 udelay(200);
3130
3131                 if (is_edp) {
3132                         if (dev_priv->lvds_use_ssc) {
3133                                 temp |= DREF_SSC1_ENABLE;
3134                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3135                                 POSTING_READ(PCH_DREF_CONTROL);
3136
3137                                 udelay(200);
3138
3139                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3140                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3141                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3142                                 POSTING_READ(PCH_DREF_CONTROL);
3143                         } else {
3144                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3145                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3146                                 POSTING_READ(PCH_DREF_CONTROL);
3147                         }
3148                 }
3149         }
3150
3151         if (IS_PINEVIEW(dev)) {
3152                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3153                 if (has_reduced_clock)
3154                         fp2 = (1 << reduced_clock.n) << 16 |
3155                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3156         } else {
3157                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3158                 if (has_reduced_clock)
3159                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3160                                 reduced_clock.m2;
3161         }
3162
3163         if (!IS_IRONLAKE(dev))
3164                 dpll = DPLL_VGA_MODE_DIS;
3165
3166         if (IS_I9XX(dev)) {
3167                 if (is_lvds)
3168                         dpll |= DPLLB_MODE_LVDS;
3169                 else
3170                         dpll |= DPLLB_MODE_DAC_SERIAL;
3171                 if (is_sdvo) {
3172                         dpll |= DPLL_DVO_HIGH_SPEED;
3173                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3174                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3175                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3176                         else if (IS_IRONLAKE(dev))
3177                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3178                 }
3179                 if (is_dp)
3180                         dpll |= DPLL_DVO_HIGH_SPEED;
3181
3182                 /* compute bitmask from p1 value */
3183                 if (IS_PINEVIEW(dev))
3184                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3185                 else {
3186                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3187                         /* also FPA1 */
3188                         if (IS_IRONLAKE(dev))
3189                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3190                         if (IS_G4X(dev) && has_reduced_clock)
3191                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3192                 }
3193                 switch (clock.p2) {
3194                 case 5:
3195                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3196                         break;
3197                 case 7:
3198                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3199                         break;
3200                 case 10:
3201                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3202                         break;
3203                 case 14:
3204                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3205                         break;
3206                 }
3207                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3208                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3209         } else {
3210                 if (is_lvds) {
3211                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3212                 } else {
3213                         if (clock.p1 == 2)
3214                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3215                         else
3216                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3217                         if (clock.p2 == 4)
3218                                 dpll |= PLL_P2_DIVIDE_BY_4;
3219                 }
3220         }
3221
3222         if (is_sdvo && is_tv)
3223                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3224         else if (is_tv)
3225                 /* XXX: just matching BIOS for now */
3226                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3227                 dpll |= 3;
3228         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3229                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3230         else
3231                 dpll |= PLL_REF_INPUT_DREFCLK;
3232
3233         /* setup pipeconf */
3234         pipeconf = I915_READ(pipeconf_reg);
3235
3236         /* Set up the display plane register */
3237         dspcntr = DISPPLANE_GAMMA_ENABLE;
3238
3239         /* Ironlake's plane is forced to pipe, bit 24 is to
3240            enable color space conversion */
3241         if (!IS_IRONLAKE(dev)) {
3242                 if (pipe == 0)
3243                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3244                 else
3245                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3246         }
3247
3248         if (pipe == 0 && !IS_I965G(dev)) {
3249                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3250                  * core speed.
3251                  *
3252                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3253                  * pipe == 0 check?
3254                  */
3255                 if (mode->clock >
3256                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3257                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3258                 else
3259                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3260         }
3261
3262         dspcntr |= DISPLAY_PLANE_ENABLE;
3263         pipeconf |= PIPEACONF_ENABLE;
3264         dpll |= DPLL_VCO_ENABLE;
3265
3266
3267         /* Disable the panel fitter if it was on our pipe */
3268         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3269                 I915_WRITE(PFIT_CONTROL, 0);
3270
3271         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3272         drm_mode_debug_printmodeline(mode);
3273
3274         /* assign to Ironlake registers */
3275         if (IS_IRONLAKE(dev)) {
3276                 fp_reg = pch_fp_reg;
3277                 dpll_reg = pch_dpll_reg;
3278         }
3279
3280         if (is_edp) {
3281                 ironlake_disable_pll_edp(crtc);
3282         } else if ((dpll & DPLL_VCO_ENABLE)) {
3283                 I915_WRITE(fp_reg, fp);
3284                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3285                 I915_READ(dpll_reg);
3286                 udelay(150);
3287         }
3288
3289         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3290          * This is an exception to the general rule that mode_set doesn't turn
3291          * things on.
3292          */
3293         if (is_lvds) {
3294                 u32 lvds;
3295
3296                 if (IS_IRONLAKE(dev))
3297                         lvds_reg = PCH_LVDS;
3298
3299                 lvds = I915_READ(lvds_reg);
3300                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3301                 /* set the corresponsding LVDS_BORDER bit */
3302                 lvds |= dev_priv->lvds_border_bits;
3303                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3304                  * set the DPLLs for dual-channel mode or not.
3305                  */
3306                 if (clock.p2 == 7)
3307                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3308                 else
3309                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3310
3311                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3312                  * appropriately here, but we need to look more thoroughly into how
3313                  * panels behave in the two modes.
3314                  */
3315                 /* set the dithering flag */
3316                 if (IS_I965G(dev)) {
3317                         if (dev_priv->lvds_dither) {
3318                                 if (IS_IRONLAKE(dev))
3319                                         pipeconf |= PIPE_ENABLE_DITHER;
3320                                 else
3321                                         lvds |= LVDS_ENABLE_DITHER;
3322                         } else {
3323                                 if (IS_IRONLAKE(dev))
3324                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3325                                 else
3326                                         lvds &= ~LVDS_ENABLE_DITHER;
3327                         }
3328                 }
3329                 I915_WRITE(lvds_reg, lvds);
3330                 I915_READ(lvds_reg);
3331         }
3332         if (is_dp)
3333                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3334
3335         if (!is_edp) {
3336                 I915_WRITE(fp_reg, fp);
3337                 I915_WRITE(dpll_reg, dpll);
3338                 I915_READ(dpll_reg);
3339                 /* Wait for the clocks to stabilize. */
3340                 udelay(150);
3341
3342                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3343                         if (is_sdvo) {
3344                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3345                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3346                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3347                         } else
3348                                 I915_WRITE(dpll_md_reg, 0);
3349                 } else {
3350                         /* write it again -- the BIOS does, after all */
3351                         I915_WRITE(dpll_reg, dpll);
3352                 }
3353                 I915_READ(dpll_reg);
3354                 /* Wait for the clocks to stabilize. */
3355                 udelay(150);
3356         }
3357
3358         if (is_lvds && has_reduced_clock && i915_powersave) {
3359                 I915_WRITE(fp_reg + 4, fp2);
3360                 intel_crtc->lowfreq_avail = true;
3361                 if (HAS_PIPE_CXSR(dev)) {
3362                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3363                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3364                 }
3365         } else {
3366                 I915_WRITE(fp_reg + 4, fp);
3367                 intel_crtc->lowfreq_avail = false;
3368                 if (HAS_PIPE_CXSR(dev)) {
3369                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3370                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3371                 }
3372         }
3373
3374         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3375                    ((adjusted_mode->crtc_htotal - 1) << 16));
3376         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3377                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3378         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3379                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3380         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3381                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3382         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3383                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3384         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3385                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3386         /* pipesrc and dspsize control the size that is scaled from, which should
3387          * always be the user's requested size.
3388          */
3389         if (!IS_IRONLAKE(dev)) {
3390                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3391                                 (mode->hdisplay - 1));
3392                 I915_WRITE(dsppos_reg, 0);
3393         }
3394         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3395
3396         if (IS_IRONLAKE(dev)) {
3397                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3398                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3399                 I915_WRITE(link_m1_reg, m_n.link_m);
3400                 I915_WRITE(link_n1_reg, m_n.link_n);
3401
3402                 if (is_edp) {
3403                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3404                 } else {
3405                         /* enable FDI RX PLL too */
3406                         temp = I915_READ(fdi_rx_reg);
3407                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3408                         udelay(200);
3409                 }
3410         }
3411
3412         I915_WRITE(pipeconf_reg, pipeconf);
3413         I915_READ(pipeconf_reg);
3414
3415         intel_wait_for_vblank(dev);
3416
3417         if (IS_IRONLAKE(dev)) {
3418                 /* enable address swizzle for tiling buffer */
3419                 temp = I915_READ(DISP_ARB_CTL);
3420                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3421         }
3422
3423         I915_WRITE(dspcntr_reg, dspcntr);
3424
3425         /* Flush the plane changes */
3426         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3427
3428         if ((IS_I965G(dev) || plane == 0))
3429                 intel_update_fbc(crtc, &crtc->mode);
3430
3431         intel_update_watermarks(dev);
3432
3433         drm_vblank_post_modeset(dev, pipe);
3434
3435         return ret;
3436 }
3437
3438 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3439 void intel_crtc_load_lut(struct drm_crtc *crtc)
3440 {
3441         struct drm_device *dev = crtc->dev;
3442         struct drm_i915_private *dev_priv = dev->dev_private;
3443         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3444         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3445         int i;
3446
3447         /* The clocks have to be on to load the palette. */
3448         if (!crtc->enabled)
3449                 return;
3450
3451         /* use legacy palette for Ironlake */
3452         if (IS_IRONLAKE(dev))
3453                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3454                                                    LGC_PALETTE_B;
3455
3456         for (i = 0; i < 256; i++) {
3457                 I915_WRITE(palreg + 4 * i,
3458                            (intel_crtc->lut_r[i] << 16) |
3459                            (intel_crtc->lut_g[i] << 8) |
3460                            intel_crtc->lut_b[i]);
3461         }
3462 }
3463
3464 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3465                                  struct drm_file *file_priv,
3466                                  uint32_t handle,
3467                                  uint32_t width, uint32_t height)
3468 {
3469         struct drm_device *dev = crtc->dev;
3470         struct drm_i915_private *dev_priv = dev->dev_private;
3471         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3472         struct drm_gem_object *bo;
3473         struct drm_i915_gem_object *obj_priv;
3474         int pipe = intel_crtc->pipe;
3475         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3476         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3477         uint32_t temp = I915_READ(control);
3478         size_t addr;
3479         int ret;
3480
3481         DRM_DEBUG_KMS("\n");
3482
3483         /* if we want to turn off the cursor ignore width and height */
3484         if (!handle) {
3485                 DRM_DEBUG_KMS("cursor off\n");
3486                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3487                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3488                         temp |= CURSOR_MODE_DISABLE;
3489                 } else {
3490                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3491                 }
3492                 addr = 0;
3493                 bo = NULL;
3494                 mutex_lock(&dev->struct_mutex);
3495                 goto finish;
3496         }
3497
3498         /* Currently we only support 64x64 cursors */
3499         if (width != 64 || height != 64) {
3500                 DRM_ERROR("we currently only support 64x64 cursors\n");
3501                 return -EINVAL;
3502         }
3503
3504         bo = drm_gem_object_lookup(dev, file_priv, handle);
3505         if (!bo)
3506                 return -ENOENT;
3507
3508         obj_priv = bo->driver_private;
3509
3510         if (bo->size < width * height * 4) {
3511                 DRM_ERROR("buffer is to small\n");
3512                 ret = -ENOMEM;
3513                 goto fail;
3514         }
3515
3516         /* we only need to pin inside GTT if cursor is non-phy */
3517         mutex_lock(&dev->struct_mutex);
3518         if (!dev_priv->info->cursor_needs_physical) {
3519                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3520                 if (ret) {
3521                         DRM_ERROR("failed to pin cursor bo\n");
3522                         goto fail_locked;
3523                 }
3524                 addr = obj_priv->gtt_offset;
3525         } else {
3526                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3527                 if (ret) {
3528                         DRM_ERROR("failed to attach phys object\n");
3529                         goto fail_locked;
3530                 }
3531                 addr = obj_priv->phys_obj->handle->busaddr;
3532         }
3533
3534         if (!IS_I9XX(dev))
3535                 I915_WRITE(CURSIZE, (height << 12) | width);
3536
3537         /* Hooray for CUR*CNTR differences */
3538         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3539                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3540                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3541                 temp |= (pipe << 28); /* Connect to correct pipe */
3542         } else {
3543                 temp &= ~(CURSOR_FORMAT_MASK);
3544                 temp |= CURSOR_ENABLE;
3545                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3546         }
3547
3548  finish:
3549         I915_WRITE(control, temp);
3550         I915_WRITE(base, addr);
3551
3552         if (intel_crtc->cursor_bo) {
3553                 if (dev_priv->info->cursor_needs_physical) {
3554                         if (intel_crtc->cursor_bo != bo)
3555                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3556                 } else
3557                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3558                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3559         }
3560
3561         mutex_unlock(&dev->struct_mutex);
3562
3563         intel_crtc->cursor_addr = addr;
3564         intel_crtc->cursor_bo = bo;
3565
3566         return 0;
3567 fail:
3568         mutex_lock(&dev->struct_mutex);
3569 fail_locked:
3570         drm_gem_object_unreference(bo);
3571         mutex_unlock(&dev->struct_mutex);
3572         return ret;
3573 }
3574
3575 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3576 {
3577         struct drm_device *dev = crtc->dev;
3578         struct drm_i915_private *dev_priv = dev->dev_private;
3579         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3580         struct intel_framebuffer *intel_fb;
3581         int pipe = intel_crtc->pipe;
3582         uint32_t temp = 0;
3583         uint32_t adder;
3584
3585         if (crtc->fb) {
3586                 intel_fb = to_intel_framebuffer(crtc->fb);
3587                 intel_mark_busy(dev, intel_fb->obj);
3588         }
3589
3590         if (x < 0) {
3591                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3592                 x = -x;
3593         }
3594         if (y < 0) {
3595                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3596                 y = -y;
3597         }
3598
3599         temp |= x << CURSOR_X_SHIFT;
3600         temp |= y << CURSOR_Y_SHIFT;
3601
3602         adder = intel_crtc->cursor_addr;
3603         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3604         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3605
3606         return 0;
3607 }
3608
3609 /** Sets the color ramps on behalf of RandR */
3610 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3611                                  u16 blue, int regno)
3612 {
3613         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3614
3615         intel_crtc->lut_r[regno] = red >> 8;
3616         intel_crtc->lut_g[regno] = green >> 8;
3617         intel_crtc->lut_b[regno] = blue >> 8;
3618 }
3619
3620 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3621                              u16 *blue, int regno)
3622 {
3623         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3624
3625         *red = intel_crtc->lut_r[regno] << 8;
3626         *green = intel_crtc->lut_g[regno] << 8;
3627         *blue = intel_crtc->lut_b[regno] << 8;
3628 }
3629
3630 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3631                                  u16 *blue, uint32_t size)
3632 {
3633         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3634         int i;
3635
3636         if (size != 256)
3637                 return;
3638
3639         for (i = 0; i < 256; i++) {
3640                 intel_crtc->lut_r[i] = red[i] >> 8;
3641                 intel_crtc->lut_g[i] = green[i] >> 8;
3642                 intel_crtc->lut_b[i] = blue[i] >> 8;
3643         }
3644
3645         intel_crtc_load_lut(crtc);
3646 }
3647
3648 /**
3649  * Get a pipe with a simple mode set on it for doing load-based monitor
3650  * detection.
3651  *
3652  * It will be up to the load-detect code to adjust the pipe as appropriate for
3653  * its requirements.  The pipe will be connected to no other outputs.
3654  *
3655  * Currently this code will only succeed if there is a pipe with no outputs
3656  * configured for it.  In the future, it could choose to temporarily disable
3657  * some outputs to free up a pipe for its use.
3658  *
3659  * \return crtc, or NULL if no pipes are available.
3660  */
3661
3662 /* VESA 640x480x72Hz mode to set on the pipe */
3663 static struct drm_display_mode load_detect_mode = {
3664         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3665                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3666 };
3667
3668 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3669                                             struct drm_display_mode *mode,
3670                                             int *dpms_mode)
3671 {
3672         struct intel_crtc *intel_crtc;
3673         struct drm_crtc *possible_crtc;
3674         struct drm_crtc *supported_crtc =NULL;
3675         struct drm_encoder *encoder = &intel_output->enc;
3676         struct drm_crtc *crtc = NULL;
3677         struct drm_device *dev = encoder->dev;
3678         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3679         struct drm_crtc_helper_funcs *crtc_funcs;
3680         int i = -1;
3681
3682         /*
3683          * Algorithm gets a little messy:
3684          *   - if the connector already has an assigned crtc, use it (but make
3685          *     sure it's on first)
3686          *   - try to find the first unused crtc that can drive this connector,
3687          *     and use that if we find one
3688          *   - if there are no unused crtcs available, try to use the first
3689          *     one we found that supports the connector
3690          */
3691
3692         /* See if we already have a CRTC for this connector */
3693         if (encoder->crtc) {
3694                 crtc = encoder->crtc;
3695                 /* Make sure the crtc and connector are running */
3696                 intel_crtc = to_intel_crtc(crtc);
3697                 *dpms_mode = intel_crtc->dpms_mode;
3698                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3699                         crtc_funcs = crtc->helper_private;
3700                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3701                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3702                 }
3703                 return crtc;
3704         }
3705
3706         /* Find an unused one (if possible) */
3707         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3708                 i++;
3709                 if (!(encoder->possible_crtcs & (1 << i)))
3710                         continue;
3711                 if (!possible_crtc->enabled) {
3712                         crtc = possible_crtc;
3713                         break;
3714                 }
3715                 if (!supported_crtc)
3716                         supported_crtc = possible_crtc;
3717         }
3718
3719         /*
3720          * If we didn't find an unused CRTC, don't use any.
3721          */
3722         if (!crtc) {
3723                 return NULL;
3724         }
3725
3726         encoder->crtc = crtc;
3727         intel_output->base.encoder = encoder;
3728         intel_output->load_detect_temp = true;
3729
3730         intel_crtc = to_intel_crtc(crtc);
3731         *dpms_mode = intel_crtc->dpms_mode;
3732
3733         if (!crtc->enabled) {
3734                 if (!mode)
3735                         mode = &load_detect_mode;
3736                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3737         } else {
3738                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3739                         crtc_funcs = crtc->helper_private;
3740                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3741                 }
3742
3743                 /* Add this connector to the crtc */
3744                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3745                 encoder_funcs->commit(encoder);
3746         }
3747         /* let the connector get through one full cycle before testing */
3748         intel_wait_for_vblank(dev);
3749
3750         return crtc;
3751 }
3752
3753 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3754 {
3755         struct drm_encoder *encoder = &intel_output->enc;
3756         struct drm_device *dev = encoder->dev;
3757         struct drm_crtc *crtc = encoder->crtc;
3758         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3759         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3760
3761         if (intel_output->load_detect_temp) {
3762                 encoder->crtc = NULL;
3763                 intel_output->base.encoder = NULL;
3764                 intel_output->load_detect_temp = false;
3765                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3766                 drm_helper_disable_unused_functions(dev);
3767         }
3768
3769         /* Switch crtc and output back off if necessary */
3770         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3771                 if (encoder->crtc == crtc)
3772                         encoder_funcs->dpms(encoder, dpms_mode);
3773                 crtc_funcs->dpms(crtc, dpms_mode);
3774         }
3775 }
3776
3777 /* Returns the clock of the currently programmed mode of the given pipe. */
3778 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3779 {
3780         struct drm_i915_private *dev_priv = dev->dev_private;
3781         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3782         int pipe = intel_crtc->pipe;
3783         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3784         u32 fp;
3785         intel_clock_t clock;
3786
3787         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3788                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3789         else
3790                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3791
3792         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3793         if (IS_PINEVIEW(dev)) {
3794                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3795                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3796         } else {
3797                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3798                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3799         }
3800
3801         if (IS_I9XX(dev)) {
3802                 if (IS_PINEVIEW(dev))
3803                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3804                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3805                 else
3806                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3807                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3808
3809                 switch (dpll & DPLL_MODE_MASK) {
3810                 case DPLLB_MODE_DAC_SERIAL:
3811                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3812                                 5 : 10;
3813                         break;
3814                 case DPLLB_MODE_LVDS:
3815                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3816                                 7 : 14;
3817                         break;
3818                 default:
3819                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3820                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3821                         return 0;
3822                 }
3823
3824                 /* XXX: Handle the 100Mhz refclk */
3825                 intel_clock(dev, 96000, &clock);
3826         } else {
3827                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3828
3829                 if (is_lvds) {
3830                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3831                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3832                         clock.p2 = 14;
3833
3834                         if ((dpll & PLL_REF_INPUT_MASK) ==
3835                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3836                                 /* XXX: might not be 66MHz */
3837                                 intel_clock(dev, 66000, &clock);
3838                         } else
3839                                 intel_clock(dev, 48000, &clock);
3840                 } else {
3841                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3842                                 clock.p1 = 2;
3843                         else {
3844                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3845                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3846                         }
3847                         if (dpll & PLL_P2_DIVIDE_BY_4)
3848                                 clock.p2 = 4;
3849                         else
3850                                 clock.p2 = 2;
3851
3852                         intel_clock(dev, 48000, &clock);
3853                 }
3854         }
3855
3856         /* XXX: It would be nice to validate the clocks, but we can't reuse
3857          * i830PllIsValid() because it relies on the xf86_config connector
3858          * configuration being accurate, which it isn't necessarily.
3859          */
3860
3861         return clock.dot;
3862 }
3863
3864 /** Returns the currently programmed mode of the given pipe. */
3865 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3866                                              struct drm_crtc *crtc)
3867 {
3868         struct drm_i915_private *dev_priv = dev->dev_private;
3869         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3870         int pipe = intel_crtc->pipe;
3871         struct drm_display_mode *mode;
3872         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3873         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3874         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3875         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3876
3877         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3878         if (!mode)
3879                 return NULL;
3880
3881         mode->clock = intel_crtc_clock_get(dev, crtc);
3882         mode->hdisplay = (htot & 0xffff) + 1;
3883         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3884         mode->hsync_start = (hsync & 0xffff) + 1;
3885         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3886         mode->vdisplay = (vtot & 0xffff) + 1;
3887         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3888         mode->vsync_start = (vsync & 0xffff) + 1;
3889         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3890
3891         drm_mode_set_name(mode);
3892         drm_mode_set_crtcinfo(mode, 0);
3893
3894         return mode;
3895 }
3896
3897 #define GPU_IDLE_TIMEOUT 500 /* ms */
3898
3899 /* When this timer fires, we've been idle for awhile */
3900 static void intel_gpu_idle_timer(unsigned long arg)
3901 {
3902         struct drm_device *dev = (struct drm_device *)arg;
3903         drm_i915_private_t *dev_priv = dev->dev_private;
3904
3905         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3906
3907         dev_priv->busy = false;
3908
3909         queue_work(dev_priv->wq, &dev_priv->idle_work);
3910 }
3911
3912 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3913
3914 static void intel_crtc_idle_timer(unsigned long arg)
3915 {
3916         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3917         struct drm_crtc *crtc = &intel_crtc->base;
3918         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3919
3920         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3921
3922         intel_crtc->busy = false;
3923
3924         queue_work(dev_priv->wq, &dev_priv->idle_work);
3925 }
3926
3927 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3928 {
3929         struct drm_device *dev = crtc->dev;
3930         drm_i915_private_t *dev_priv = dev->dev_private;
3931         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3932         int pipe = intel_crtc->pipe;
3933         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3934         int dpll = I915_READ(dpll_reg);
3935
3936         if (IS_IRONLAKE(dev))
3937                 return;
3938
3939         if (!dev_priv->lvds_downclock_avail)
3940                 return;
3941
3942         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3943                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3944
3945                 /* Unlock panel regs */
3946                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3947
3948                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3949                 I915_WRITE(dpll_reg, dpll);
3950                 dpll = I915_READ(dpll_reg);
3951                 intel_wait_for_vblank(dev);
3952                 dpll = I915_READ(dpll_reg);
3953                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3954                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3955
3956                 /* ...and lock them again */
3957                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3958         }
3959
3960         /* Schedule downclock */
3961         if (schedule)
3962                 mod_timer(&intel_crtc->idle_timer, jiffies +
3963                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3964 }
3965
3966 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3967 {
3968         struct drm_device *dev = crtc->dev;
3969         drm_i915_private_t *dev_priv = dev->dev_private;
3970         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3971         int pipe = intel_crtc->pipe;
3972         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3973         int dpll = I915_READ(dpll_reg);
3974
3975         if (IS_IRONLAKE(dev))
3976                 return;
3977
3978         if (!dev_priv->lvds_downclock_avail)
3979                 return;
3980
3981         /*
3982          * Since this is called by a timer, we should never get here in
3983          * the manual case.
3984          */
3985         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3986                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3987
3988                 /* Unlock panel regs */
3989                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3990
3991                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3992                 I915_WRITE(dpll_reg, dpll);
3993                 dpll = I915_READ(dpll_reg);
3994                 intel_wait_for_vblank(dev);
3995                 dpll = I915_READ(dpll_reg);
3996                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3997                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3998
3999                 /* ...and lock them again */
4000                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
4001         }
4002
4003 }
4004
4005 /**
4006  * intel_idle_update - adjust clocks for idleness
4007  * @work: work struct
4008  *
4009  * Either the GPU or display (or both) went idle.  Check the busy status
4010  * here and adjust the CRTC and GPU clocks as necessary.
4011  */
4012 static void intel_idle_update(struct work_struct *work)
4013 {
4014         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4015                                                     idle_work);
4016         struct drm_device *dev = dev_priv->dev;
4017         struct drm_crtc *crtc;
4018         struct intel_crtc *intel_crtc;
4019
4020         if (!i915_powersave)
4021                 return;
4022
4023         mutex_lock(&dev->struct_mutex);
4024
4025         if (IS_I945G(dev) || IS_I945GM(dev)) {
4026                 DRM_DEBUG_DRIVER("enable memory self refresh on 945\n");
4027                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
4028         }
4029
4030         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4031                 /* Skip inactive CRTCs */
4032                 if (!crtc->fb)
4033                         continue;
4034
4035                 intel_crtc = to_intel_crtc(crtc);
4036                 if (!intel_crtc->busy)
4037                         intel_decrease_pllclock(crtc);
4038         }
4039
4040         mutex_unlock(&dev->struct_mutex);
4041 }
4042
4043 /**
4044  * intel_mark_busy - mark the GPU and possibly the display busy
4045  * @dev: drm device
4046  * @obj: object we're operating on
4047  *
4048  * Callers can use this function to indicate that the GPU is busy processing
4049  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4050  * buffer), we'll also mark the display as busy, so we know to increase its
4051  * clock frequency.
4052  */
4053 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4054 {
4055         drm_i915_private_t *dev_priv = dev->dev_private;
4056         struct drm_crtc *crtc = NULL;
4057         struct intel_framebuffer *intel_fb;
4058         struct intel_crtc *intel_crtc;
4059
4060         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4061                 return;
4062
4063         if (IS_I945G(dev) || IS_I945GM(dev)) {
4064                 u32 fw_blc_self;
4065
4066                 DRM_DEBUG_DRIVER("disable memory self refresh on 945\n");
4067                 fw_blc_self = I915_READ(FW_BLC_SELF);
4068                 fw_blc_self &= ~FW_BLC_SELF_EN;
4069                 I915_WRITE(FW_BLC_SELF, fw_blc_self | FW_BLC_SELF_EN_MASK);
4070         }
4071
4072         if (!dev_priv->busy)
4073                 dev_priv->busy = true;
4074         else
4075                 mod_timer(&dev_priv->idle_timer, jiffies +
4076                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4077
4078         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4079                 if (!crtc->fb)
4080                         continue;
4081
4082                 intel_crtc = to_intel_crtc(crtc);
4083                 intel_fb = to_intel_framebuffer(crtc->fb);
4084                 if (intel_fb->obj == obj) {
4085                         if (!intel_crtc->busy) {
4086                                 /* Non-busy -> busy, upclock */
4087                                 intel_increase_pllclock(crtc, true);
4088                                 intel_crtc->busy = true;
4089                         } else {
4090                                 /* Busy -> busy, put off timer */
4091                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4092                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4093                         }
4094                 }
4095         }
4096 }
4097
4098 static void intel_crtc_destroy(struct drm_crtc *crtc)
4099 {
4100         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4101
4102         drm_crtc_cleanup(crtc);
4103         kfree(intel_crtc);
4104 }
4105
4106 struct intel_unpin_work {
4107         struct work_struct work;
4108         struct drm_device *dev;
4109         struct drm_gem_object *old_fb_obj;
4110         struct drm_gem_object *pending_flip_obj;
4111         struct drm_pending_vblank_event *event;
4112         int pending;
4113 };
4114
4115 static void intel_unpin_work_fn(struct work_struct *__work)
4116 {
4117         struct intel_unpin_work *work =
4118                 container_of(__work, struct intel_unpin_work, work);
4119
4120         mutex_lock(&work->dev->struct_mutex);
4121         i915_gem_object_unpin(work->old_fb_obj);
4122         drm_gem_object_unreference(work->pending_flip_obj);
4123         drm_gem_object_unreference(work->old_fb_obj);
4124         mutex_unlock(&work->dev->struct_mutex);
4125         kfree(work);
4126 }
4127
4128 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4129 {
4130         drm_i915_private_t *dev_priv = dev->dev_private;
4131         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4132         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4133         struct intel_unpin_work *work;
4134         struct drm_i915_gem_object *obj_priv;
4135         struct drm_pending_vblank_event *e;
4136         struct timeval now;
4137         unsigned long flags;
4138
4139         /* Ignore early vblank irqs */
4140         if (intel_crtc == NULL)
4141                 return;
4142
4143         spin_lock_irqsave(&dev->event_lock, flags);
4144         work = intel_crtc->unpin_work;
4145         if (work == NULL || !work->pending) {
4146                 if (work && !work->pending) {
4147                         obj_priv = work->pending_flip_obj->driver_private;
4148                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4149                                          obj_priv,
4150                                          atomic_read(&obj_priv->pending_flip));
4151                 }
4152                 spin_unlock_irqrestore(&dev->event_lock, flags);
4153                 return;
4154         }
4155
4156         intel_crtc->unpin_work = NULL;
4157         drm_vblank_put(dev, intel_crtc->pipe);
4158
4159         if (work->event) {
4160                 e = work->event;
4161                 do_gettimeofday(&now);
4162                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4163                 e->event.tv_sec = now.tv_sec;
4164                 e->event.tv_usec = now.tv_usec;
4165                 list_add_tail(&e->base.link,
4166                               &e->base.file_priv->event_list);
4167                 wake_up_interruptible(&e->base.file_priv->event_wait);
4168         }
4169
4170         spin_unlock_irqrestore(&dev->event_lock, flags);
4171
4172         obj_priv = work->pending_flip_obj->driver_private;
4173
4174         /* Initial scanout buffer will have a 0 pending flip count */
4175         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4176             atomic_dec_and_test(&obj_priv->pending_flip))
4177                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4178         schedule_work(&work->work);
4179 }
4180
4181 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4182 {
4183         drm_i915_private_t *dev_priv = dev->dev_private;
4184         struct intel_crtc *intel_crtc =
4185                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4186         unsigned long flags;
4187
4188         spin_lock_irqsave(&dev->event_lock, flags);
4189         if (intel_crtc->unpin_work) {
4190                 intel_crtc->unpin_work->pending = 1;
4191         } else {
4192                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4193         }
4194         spin_unlock_irqrestore(&dev->event_lock, flags);
4195 }
4196
4197 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4198                                 struct drm_framebuffer *fb,
4199                                 struct drm_pending_vblank_event *event)
4200 {
4201         struct drm_device *dev = crtc->dev;
4202         struct drm_i915_private *dev_priv = dev->dev_private;
4203         struct intel_framebuffer *intel_fb;
4204         struct drm_i915_gem_object *obj_priv;
4205         struct drm_gem_object *obj;
4206         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4207         struct intel_unpin_work *work;
4208         unsigned long flags;
4209         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4210         int ret, pipesrc;
4211         RING_LOCALS;
4212
4213         work = kzalloc(sizeof *work, GFP_KERNEL);
4214         if (work == NULL)
4215                 return -ENOMEM;
4216
4217         mutex_lock(&dev->struct_mutex);
4218
4219         work->event = event;
4220         work->dev = crtc->dev;
4221         intel_fb = to_intel_framebuffer(crtc->fb);
4222         work->old_fb_obj = intel_fb->obj;
4223         INIT_WORK(&work->work, intel_unpin_work_fn);
4224
4225         /* We borrow the event spin lock for protecting unpin_work */
4226         spin_lock_irqsave(&dev->event_lock, flags);
4227         if (intel_crtc->unpin_work) {
4228                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4229                 spin_unlock_irqrestore(&dev->event_lock, flags);
4230                 kfree(work);
4231                 mutex_unlock(&dev->struct_mutex);
4232                 return -EBUSY;
4233         }
4234         intel_crtc->unpin_work = work;
4235         spin_unlock_irqrestore(&dev->event_lock, flags);
4236
4237         intel_fb = to_intel_framebuffer(fb);
4238         obj = intel_fb->obj;
4239
4240         ret = intel_pin_and_fence_fb_obj(dev, obj);
4241         if (ret != 0) {
4242                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4243                           obj->driver_private);
4244                 kfree(work);
4245                 intel_crtc->unpin_work = NULL;
4246                 mutex_unlock(&dev->struct_mutex);
4247                 return ret;
4248         }
4249
4250         /* Reference the objects for the scheduled work. */
4251         drm_gem_object_reference(work->old_fb_obj);
4252         drm_gem_object_reference(obj);
4253
4254         crtc->fb = fb;
4255         i915_gem_object_flush_write_domain(obj);
4256         drm_vblank_get(dev, intel_crtc->pipe);
4257         obj_priv = obj->driver_private;
4258         atomic_inc(&obj_priv->pending_flip);
4259         work->pending_flip_obj = obj;
4260
4261         BEGIN_LP_RING(4);
4262         OUT_RING(MI_DISPLAY_FLIP |
4263                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4264         OUT_RING(fb->pitch);
4265         if (IS_I965G(dev)) {
4266                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4267                 pipesrc = I915_READ(pipesrc_reg);
4268                 OUT_RING(pipesrc & 0x0fff0fff);
4269         } else {
4270                 OUT_RING(obj_priv->gtt_offset);
4271                 OUT_RING(MI_NOOP);
4272         }
4273         ADVANCE_LP_RING();
4274
4275         mutex_unlock(&dev->struct_mutex);
4276
4277         return 0;
4278 }
4279
4280 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4281         .dpms = intel_crtc_dpms,
4282         .mode_fixup = intel_crtc_mode_fixup,
4283         .mode_set = intel_crtc_mode_set,
4284         .mode_set_base = intel_pipe_set_base,
4285         .prepare = intel_crtc_prepare,
4286         .commit = intel_crtc_commit,
4287         .load_lut = intel_crtc_load_lut,
4288 };
4289
4290 static const struct drm_crtc_funcs intel_crtc_funcs = {
4291         .cursor_set = intel_crtc_cursor_set,
4292         .cursor_move = intel_crtc_cursor_move,
4293         .gamma_set = intel_crtc_gamma_set,
4294         .set_config = drm_crtc_helper_set_config,
4295         .destroy = intel_crtc_destroy,
4296         .page_flip = intel_crtc_page_flip,
4297 };
4298
4299
4300 static void intel_crtc_init(struct drm_device *dev, int pipe)
4301 {
4302         drm_i915_private_t *dev_priv = dev->dev_private;
4303         struct intel_crtc *intel_crtc;
4304         int i;
4305
4306         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4307         if (intel_crtc == NULL)
4308                 return;
4309
4310         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4311
4312         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4313         intel_crtc->pipe = pipe;
4314         intel_crtc->plane = pipe;
4315         for (i = 0; i < 256; i++) {
4316                 intel_crtc->lut_r[i] = i;
4317                 intel_crtc->lut_g[i] = i;
4318                 intel_crtc->lut_b[i] = i;
4319         }
4320
4321         /* Swap pipes & planes for FBC on pre-965 */
4322         intel_crtc->pipe = pipe;
4323         intel_crtc->plane = pipe;
4324         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4325                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4326                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4327         }
4328
4329         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4330                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4331         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4332         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4333
4334         intel_crtc->cursor_addr = 0;
4335         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4336         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4337
4338         intel_crtc->busy = false;
4339
4340         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4341                     (unsigned long)intel_crtc);
4342 }
4343
4344 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4345                                 struct drm_file *file_priv)
4346 {
4347         drm_i915_private_t *dev_priv = dev->dev_private;
4348         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4349         struct drm_mode_object *drmmode_obj;
4350         struct intel_crtc *crtc;
4351
4352         if (!dev_priv) {
4353                 DRM_ERROR("called with no initialization\n");
4354                 return -EINVAL;
4355         }
4356
4357         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4358                         DRM_MODE_OBJECT_CRTC);
4359
4360         if (!drmmode_obj) {
4361                 DRM_ERROR("no such CRTC id\n");
4362                 return -EINVAL;
4363         }
4364
4365         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4366         pipe_from_crtc_id->pipe = crtc->pipe;
4367
4368         return 0;
4369 }
4370
4371 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4372 {
4373         struct drm_crtc *crtc = NULL;
4374
4375         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4376                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4377                 if (intel_crtc->pipe == pipe)
4378                         break;
4379         }
4380         return crtc;
4381 }
4382
4383 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4384 {
4385         int index_mask = 0;
4386         struct drm_connector *connector;
4387         int entry = 0;
4388
4389         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4390                 struct intel_output *intel_output = to_intel_output(connector);
4391                 if (type_mask & intel_output->clone_mask)
4392                         index_mask |= (1 << entry);
4393                 entry++;
4394         }
4395         return index_mask;
4396 }
4397
4398
4399 static void intel_setup_outputs(struct drm_device *dev)
4400 {
4401         struct drm_i915_private *dev_priv = dev->dev_private;
4402         struct drm_connector *connector;
4403
4404         intel_crt_init(dev);
4405
4406         /* Set up integrated LVDS */
4407         if (IS_MOBILE(dev) && !IS_I830(dev))
4408                 intel_lvds_init(dev);
4409
4410         if (IS_IRONLAKE(dev)) {
4411                 int found;
4412
4413                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4414                         intel_dp_init(dev, DP_A);
4415
4416                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4417                         /* check SDVOB */
4418                         /* found = intel_sdvo_init(dev, HDMIB); */
4419                         found = 0;
4420                         if (!found)
4421                                 intel_hdmi_init(dev, HDMIB);
4422                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4423                                 intel_dp_init(dev, PCH_DP_B);
4424                 }
4425
4426                 if (I915_READ(HDMIC) & PORT_DETECTED)
4427                         intel_hdmi_init(dev, HDMIC);
4428
4429                 if (I915_READ(HDMID) & PORT_DETECTED)
4430                         intel_hdmi_init(dev, HDMID);
4431
4432                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4433                         intel_dp_init(dev, PCH_DP_C);
4434
4435                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4436                         intel_dp_init(dev, PCH_DP_D);
4437
4438         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4439                 bool found = false;
4440
4441                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4442                         DRM_DEBUG_KMS("probing SDVOB\n");
4443                         found = intel_sdvo_init(dev, SDVOB);
4444                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4445                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4446                                 intel_hdmi_init(dev, SDVOB);
4447                         }
4448
4449                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4450                                 DRM_DEBUG_KMS("probing DP_B\n");
4451                                 intel_dp_init(dev, DP_B);
4452                         }
4453                 }
4454
4455                 /* Before G4X SDVOC doesn't have its own detect register */
4456
4457                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4458                         DRM_DEBUG_KMS("probing SDVOC\n");
4459                         found = intel_sdvo_init(dev, SDVOC);
4460                 }
4461
4462                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4463
4464                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4465                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4466                                 intel_hdmi_init(dev, SDVOC);
4467                         }
4468                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4469                                 DRM_DEBUG_KMS("probing DP_C\n");
4470                                 intel_dp_init(dev, DP_C);
4471                         }
4472                 }
4473
4474                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4475                     (I915_READ(DP_D) & DP_DETECTED)) {
4476                         DRM_DEBUG_KMS("probing DP_D\n");
4477                         intel_dp_init(dev, DP_D);
4478                 }
4479         } else if (IS_I8XX(dev))
4480                 intel_dvo_init(dev);
4481
4482         if (SUPPORTS_TV(dev))
4483                 intel_tv_init(dev);
4484
4485         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4486                 struct intel_output *intel_output = to_intel_output(connector);
4487                 struct drm_encoder *encoder = &intel_output->enc;
4488
4489                 encoder->possible_crtcs = intel_output->crtc_mask;
4490                 encoder->possible_clones = intel_connector_clones(dev,
4491                                                 intel_output->clone_mask);
4492         }
4493 }
4494
4495 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4496 {
4497         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4498         struct drm_device *dev = fb->dev;
4499
4500         if (fb->fbdev)
4501                 intelfb_remove(dev, fb);
4502
4503         drm_framebuffer_cleanup(fb);
4504         mutex_lock(&dev->struct_mutex);
4505         drm_gem_object_unreference(intel_fb->obj);
4506         mutex_unlock(&dev->struct_mutex);
4507
4508         kfree(intel_fb);
4509 }
4510
4511 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4512                                                 struct drm_file *file_priv,
4513                                                 unsigned int *handle)
4514 {
4515         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4516         struct drm_gem_object *object = intel_fb->obj;
4517
4518         return drm_gem_handle_create(file_priv, object, handle);
4519 }
4520
4521 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4522         .destroy = intel_user_framebuffer_destroy,
4523         .create_handle = intel_user_framebuffer_create_handle,
4524 };
4525
4526 int intel_framebuffer_create(struct drm_device *dev,
4527                              struct drm_mode_fb_cmd *mode_cmd,
4528                              struct drm_framebuffer **fb,
4529                              struct drm_gem_object *obj)
4530 {
4531         struct intel_framebuffer *intel_fb;
4532         int ret;
4533
4534         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4535         if (!intel_fb)
4536                 return -ENOMEM;
4537
4538         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4539         if (ret) {
4540                 DRM_ERROR("framebuffer init failed %d\n", ret);
4541                 return ret;
4542         }
4543
4544         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4545
4546         intel_fb->obj = obj;
4547
4548         *fb = &intel_fb->base;
4549
4550         return 0;
4551 }
4552
4553
4554 static struct drm_framebuffer *
4555 intel_user_framebuffer_create(struct drm_device *dev,
4556                               struct drm_file *filp,
4557                               struct drm_mode_fb_cmd *mode_cmd)
4558 {
4559         struct drm_gem_object *obj;
4560         struct drm_framebuffer *fb;
4561         int ret;
4562
4563         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4564         if (!obj)
4565                 return NULL;
4566
4567         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4568         if (ret) {
4569                 mutex_lock(&dev->struct_mutex);
4570                 drm_gem_object_unreference(obj);
4571                 mutex_unlock(&dev->struct_mutex);
4572                 return NULL;
4573         }
4574
4575         return fb;
4576 }
4577
4578 static const struct drm_mode_config_funcs intel_mode_funcs = {
4579         .fb_create = intel_user_framebuffer_create,
4580         .fb_changed = intelfb_probe,
4581 };
4582
4583 static struct drm_gem_object *
4584 intel_alloc_power_context(struct drm_device *dev)
4585 {
4586         struct drm_gem_object *pwrctx;
4587         int ret;
4588
4589         pwrctx = drm_gem_object_alloc(dev, 4096);
4590         if (!pwrctx) {
4591                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4592                 return NULL;
4593         }
4594
4595         mutex_lock(&dev->struct_mutex);
4596         ret = i915_gem_object_pin(pwrctx, 4096);
4597         if (ret) {
4598                 DRM_ERROR("failed to pin power context: %d\n", ret);
4599                 goto err_unref;
4600         }
4601
4602         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4603         if (ret) {
4604                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4605                 goto err_unpin;
4606         }
4607         mutex_unlock(&dev->struct_mutex);
4608
4609         return pwrctx;
4610
4611 err_unpin:
4612         i915_gem_object_unpin(pwrctx);
4613 err_unref:
4614         drm_gem_object_unreference(pwrctx);
4615         mutex_unlock(&dev->struct_mutex);
4616         return NULL;
4617 }
4618
4619 void ironlake_enable_drps(struct drm_device *dev)
4620 {
4621         struct drm_i915_private *dev_priv = dev->dev_private;
4622         u32 rgvmodectl = I915_READ(MEMMODECTL), rgvswctl;
4623         u8 fmax, fmin, fstart, vstart;
4624         int i = 0;
4625
4626         /* 100ms RC evaluation intervals */
4627         I915_WRITE(RCUPEI, 100000);
4628         I915_WRITE(RCDNEI, 100000);
4629
4630         /* Set max/min thresholds to 90ms and 80ms respectively */
4631         I915_WRITE(RCBMAXAVG, 90000);
4632         I915_WRITE(RCBMINAVG, 80000);
4633
4634         I915_WRITE(MEMIHYST, 1);
4635
4636         /* Set up min, max, and cur for interrupt handling */
4637         fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4638         fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4639         fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4640                 MEMMODE_FSTART_SHIFT;
4641         vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4642                 PXVFREQ_PX_SHIFT;
4643
4644         dev_priv->max_delay = fstart; /* can't go to fmax w/o IPS */
4645         dev_priv->min_delay = fmin;
4646         dev_priv->cur_delay = fstart;
4647
4648         I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4649
4650         /*
4651          * Interrupts will be enabled in ironlake_irq_postinstall
4652          */
4653
4654         I915_WRITE(VIDSTART, vstart);
4655         POSTING_READ(VIDSTART);
4656
4657         rgvmodectl |= MEMMODE_SWMODE_EN;
4658         I915_WRITE(MEMMODECTL, rgvmodectl);
4659
4660         while (I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) {
4661                 if (i++ > 100) {
4662                         DRM_ERROR("stuck trying to change perf mode\n");
4663                         break;
4664                 }
4665                 msleep(1);
4666         }
4667         msleep(1);
4668
4669         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4670                 (fstart << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4671         I915_WRITE(MEMSWCTL, rgvswctl);
4672         POSTING_READ(MEMSWCTL);
4673
4674         rgvswctl |= MEMCTL_CMD_STS;
4675         I915_WRITE(MEMSWCTL, rgvswctl);
4676 }
4677
4678 void ironlake_disable_drps(struct drm_device *dev)
4679 {
4680         struct drm_i915_private *dev_priv = dev->dev_private;
4681         u32 rgvswctl;
4682         u8 fstart;
4683
4684         /* Ack interrupts, disable EFC interrupt */
4685         I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4686         I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4687         I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4688         I915_WRITE(DEIIR, DE_PCU_EVENT);
4689         I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4690
4691         /* Go back to the starting frequency */
4692         fstart = (I915_READ(MEMMODECTL) & MEMMODE_FSTART_MASK) >>
4693                 MEMMODE_FSTART_SHIFT;
4694         rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4695                 (fstart << MEMCTL_FREQ_SHIFT);
4696         I915_WRITE(MEMSWCTL, rgvswctl);
4697         msleep(1);
4698         rgvswctl |= MEMCTL_CMD_STS;
4699         I915_WRITE(MEMSWCTL, rgvswctl);
4700         msleep(1);
4701
4702 }
4703
4704 void intel_init_clock_gating(struct drm_device *dev)
4705 {
4706         struct drm_i915_private *dev_priv = dev->dev_private;
4707
4708         /*
4709          * Disable clock gating reported to work incorrectly according to the
4710          * specs, but enable as much else as we can.
4711          */
4712         if (IS_IRONLAKE(dev)) {
4713                 return;
4714         } else if (IS_G4X(dev)) {
4715                 uint32_t dspclk_gate;
4716                 I915_WRITE(RENCLK_GATE_D1, 0);
4717                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4718                        GS_UNIT_CLOCK_GATE_DISABLE |
4719                        CL_UNIT_CLOCK_GATE_DISABLE);
4720                 I915_WRITE(RAMCLK_GATE_D, 0);
4721                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4722                         OVRUNIT_CLOCK_GATE_DISABLE |
4723                         OVCUNIT_CLOCK_GATE_DISABLE;
4724                 if (IS_GM45(dev))
4725                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4726                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4727         } else if (IS_I965GM(dev)) {
4728                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4729                 I915_WRITE(RENCLK_GATE_D2, 0);
4730                 I915_WRITE(DSPCLK_GATE_D, 0);
4731                 I915_WRITE(RAMCLK_GATE_D, 0);
4732                 I915_WRITE16(DEUC, 0);
4733         } else if (IS_I965G(dev)) {
4734                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4735                        I965_RCC_CLOCK_GATE_DISABLE |
4736                        I965_RCPB_CLOCK_GATE_DISABLE |
4737                        I965_ISC_CLOCK_GATE_DISABLE |
4738                        I965_FBC_CLOCK_GATE_DISABLE);
4739                 I915_WRITE(RENCLK_GATE_D2, 0);
4740         } else if (IS_I9XX(dev)) {
4741                 u32 dstate = I915_READ(D_STATE);
4742
4743                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4744                         DSTATE_DOT_CLOCK_GATING;
4745                 I915_WRITE(D_STATE, dstate);
4746         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4747                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4748         } else if (IS_I830(dev)) {
4749                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4750         }
4751
4752         /*
4753          * GPU can automatically power down the render unit if given a page
4754          * to save state.
4755          */
4756         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4757                 struct drm_i915_gem_object *obj_priv = NULL;
4758
4759                 if (dev_priv->pwrctx) {
4760                         obj_priv = dev_priv->pwrctx->driver_private;
4761                 } else {
4762                         struct drm_gem_object *pwrctx;
4763
4764                         pwrctx = intel_alloc_power_context(dev);
4765                         if (pwrctx) {
4766                                 dev_priv->pwrctx = pwrctx;
4767                                 obj_priv = pwrctx->driver_private;
4768                         }
4769                 }
4770
4771                 if (obj_priv) {
4772                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4773                         I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) &
4774                                    ~RCX_SW_EXIT);
4775                 }
4776         }
4777 }
4778
4779 /* Set up chip specific display functions */
4780 static void intel_init_display(struct drm_device *dev)
4781 {
4782         struct drm_i915_private *dev_priv = dev->dev_private;
4783
4784         /* We always want a DPMS function */
4785         if (IS_IRONLAKE(dev))
4786                 dev_priv->display.dpms = ironlake_crtc_dpms;
4787         else
4788                 dev_priv->display.dpms = i9xx_crtc_dpms;
4789
4790         /* Only mobile has FBC, leave pointers NULL for other chips */
4791         if (IS_MOBILE(dev)) {
4792                 if (IS_GM45(dev)) {
4793                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4794                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4795                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4796                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4797                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4798                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4799                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4800                 }
4801                 /* 855GM needs testing */
4802         }
4803
4804         /* Returns the core display clock speed */
4805         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4806                 dev_priv->display.get_display_clock_speed =
4807                         i945_get_display_clock_speed;
4808         else if (IS_I915G(dev))
4809                 dev_priv->display.get_display_clock_speed =
4810                         i915_get_display_clock_speed;
4811         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4812                 dev_priv->display.get_display_clock_speed =
4813                         i9xx_misc_get_display_clock_speed;
4814         else if (IS_I915GM(dev))
4815                 dev_priv->display.get_display_clock_speed =
4816                         i915gm_get_display_clock_speed;
4817         else if (IS_I865G(dev))
4818                 dev_priv->display.get_display_clock_speed =
4819                         i865_get_display_clock_speed;
4820         else if (IS_I85X(dev))
4821                 dev_priv->display.get_display_clock_speed =
4822                         i855_get_display_clock_speed;
4823         else /* 852, 830 */
4824                 dev_priv->display.get_display_clock_speed =
4825                         i830_get_display_clock_speed;
4826
4827         /* For FIFO watermark updates */
4828         if (IS_IRONLAKE(dev))
4829                 dev_priv->display.update_wm = NULL;
4830         else if (IS_G4X(dev))
4831                 dev_priv->display.update_wm = g4x_update_wm;
4832         else if (IS_I965G(dev))
4833                 dev_priv->display.update_wm = i965_update_wm;
4834         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4835                 dev_priv->display.update_wm = i9xx_update_wm;
4836                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4837         } else {
4838                 if (IS_I85X(dev))
4839                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4840                 else if (IS_845G(dev))
4841                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4842                 else
4843                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4844                 dev_priv->display.update_wm = i830_update_wm;
4845         }
4846 }
4847
4848 void intel_modeset_init(struct drm_device *dev)
4849 {
4850         struct drm_i915_private *dev_priv = dev->dev_private;
4851         int num_pipe;
4852         int i;
4853
4854         drm_mode_config_init(dev);
4855
4856         dev->mode_config.min_width = 0;
4857         dev->mode_config.min_height = 0;
4858
4859         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4860
4861         intel_init_display(dev);
4862
4863         if (IS_I965G(dev)) {
4864                 dev->mode_config.max_width = 8192;
4865                 dev->mode_config.max_height = 8192;
4866         } else if (IS_I9XX(dev)) {
4867                 dev->mode_config.max_width = 4096;
4868                 dev->mode_config.max_height = 4096;
4869         } else {
4870                 dev->mode_config.max_width = 2048;
4871                 dev->mode_config.max_height = 2048;
4872         }
4873
4874         /* set memory base */
4875         if (IS_I9XX(dev))
4876                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4877         else
4878                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4879
4880         if (IS_MOBILE(dev) || IS_I9XX(dev))
4881                 num_pipe = 2;
4882         else
4883                 num_pipe = 1;
4884         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4885                   num_pipe, num_pipe > 1 ? "s" : "");
4886
4887         for (i = 0; i < num_pipe; i++) {
4888                 intel_crtc_init(dev, i);
4889         }
4890
4891         intel_setup_outputs(dev);
4892
4893         intel_init_clock_gating(dev);
4894
4895         if (IS_IRONLAKE_M(dev))
4896                 ironlake_enable_drps(dev);
4897
4898         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4899         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4900                     (unsigned long)dev);
4901
4902         intel_setup_overlay(dev);
4903
4904         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4905                                                         dev_priv->fsb_freq,
4906                                                         dev_priv->mem_freq))
4907                 DRM_INFO("failed to find known CxSR latency "
4908                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4909                          dev_priv->fsb_freq, dev_priv->mem_freq);
4910 }
4911
4912 void intel_modeset_cleanup(struct drm_device *dev)
4913 {
4914         struct drm_i915_private *dev_priv = dev->dev_private;
4915         struct drm_crtc *crtc;
4916         struct intel_crtc *intel_crtc;
4917
4918         mutex_lock(&dev->struct_mutex);
4919
4920         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4921                 /* Skip inactive CRTCs */
4922                 if (!crtc->fb)
4923                         continue;
4924
4925                 intel_crtc = to_intel_crtc(crtc);
4926                 intel_increase_pllclock(crtc, false);
4927                 del_timer_sync(&intel_crtc->idle_timer);
4928         }
4929
4930         del_timer_sync(&dev_priv->idle_timer);
4931
4932         if (dev_priv->display.disable_fbc)
4933                 dev_priv->display.disable_fbc(dev);
4934
4935         if (dev_priv->pwrctx) {
4936                 struct drm_i915_gem_object *obj_priv;
4937
4938                 obj_priv = dev_priv->pwrctx->driver_private;
4939                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4940                 I915_READ(PWRCTXA);
4941                 i915_gem_object_unpin(dev_priv->pwrctx);
4942                 drm_gem_object_unreference(dev_priv->pwrctx);
4943         }
4944
4945         if (IS_IRONLAKE_M(dev))
4946                 ironlake_disable_drps(dev);
4947
4948         mutex_unlock(&dev->struct_mutex);
4949
4950         drm_mode_config_cleanup(dev);
4951 }
4952
4953
4954 /* current intel driver doesn't take advantage of encoders
4955    always give back the encoder for the connector
4956 */
4957 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4958 {
4959         struct intel_output *intel_output = to_intel_output(connector);
4960
4961         return &intel_output->enc;
4962 }
4963
4964 /*
4965  * set vga decode state - true == enable VGA decode
4966  */
4967 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4968 {
4969         struct drm_i915_private *dev_priv = dev->dev_private;
4970         u16 gmch_ctrl;
4971
4972         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4973         if (state)
4974                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4975         else
4976                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4977         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4978         return 0;
4979 }