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   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/module.h>
  28 #include <linux/input.h>
  29 #include <linux/i2c.h>
  30 #include <linux/kernel.h>
  31 #include "drmP.h"
  32 #include "intel_drv.h"
  33 #include "i915_drm.h"
  34 #include "i915_drv.h"
  35 #include "drm_dp_helper.h"
  36
  37 #include "drm_crtc_helper.h"
  38
  39 #define HAS_eDP (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
  40
  41 bool intel_pipe_has_type (struct drm_crtc *crtc, int type);
  42 static void intel_update_watermarks(struct drm_device *dev);
  43 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule);
  44
  45 typedef struct {
  46     /* given values */
  47     int n;
  48     int m1, m2;
  49     int p1, p2;
  50     /* derived values */
  51     int dot;
  52     int vco;
  53     int m;
  54     int p;
  55 } intel_clock_t;
  56
  57 typedef struct {
  58     int min, max;
  59 } intel_range_t;
  60
  61 typedef struct {
  62     int dot_limit;
  63     int p2_slow, p2_fast;
  64 } intel_p2_t;
  65
  66 #define INTEL_P2_NUM                  2
  67 typedef struct intel_limit intel_limit_t;
  68 struct intel_limit {
  69     intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  70     intel_p2_t      p2;
  71     bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  72                       int, int, intel_clock_t *);
  73 };
  74
  75 #define I8XX_DOT_MIN              25000
  76 #define I8XX_DOT_MAX             350000
  77 #define I8XX_VCO_MIN             930000
  78 #define I8XX_VCO_MAX            1400000
  79 #define I8XX_N_MIN                    3
  80 #define I8XX_N_MAX                   16
  81 #define I8XX_M_MIN                   96
  82 #define I8XX_M_MAX                  140
  83 #define I8XX_M1_MIN                  18
  84 #define I8XX_M1_MAX                  26
  85 #define I8XX_M2_MIN                   6
  86 #define I8XX_M2_MAX                  16
  87 #define I8XX_P_MIN                    4
  88 #define I8XX_P_MAX                  128
  89 #define I8XX_P1_MIN                   2
  90 #define I8XX_P1_MAX                  33
  91 #define I8XX_P1_LVDS_MIN              1
  92 #define I8XX_P1_LVDS_MAX              6
  93 #define I8XX_P2_SLOW                  4
  94 #define I8XX_P2_FAST                  2
  95 #define I8XX_P2_LVDS_SLOW             14
  96 #define I8XX_P2_LVDS_FAST             7
  97 #define I8XX_P2_SLOW_LIMIT       165000
  98
  99 #define I9XX_DOT_MIN              20000
 100 #define I9XX_DOT_MAX             400000
 101 #define I9XX_VCO_MIN            1400000
 102 #define I9XX_VCO_MAX            2800000
 103 #define PINEVIEW_VCO_MIN                1700000
 104 #define PINEVIEW_VCO_MAX                3500000
 105 #define I9XX_N_MIN                    1
 106 #define I9XX_N_MAX                    6
 107 /* Pineview's Ncounter is a ring counter */
 108 #define PINEVIEW_N_MIN                3
 109 #define PINEVIEW_N_MAX                6
 110 #define I9XX_M_MIN                   70
 111 #define I9XX_M_MAX                  120
 112 #define PINEVIEW_M_MIN                2
 113 #define PINEVIEW_M_MAX              256
 114 #define I9XX_M1_MIN                  10
 115 #define I9XX_M1_MAX                  22
 116 #define I9XX_M2_MIN                   5
 117 #define I9XX_M2_MAX                   9
 118 /* Pineview M1 is reserved, and must be 0 */
 119 #define PINEVIEW_M1_MIN               0
 120 #define PINEVIEW_M1_MAX               0
 121 #define PINEVIEW_M2_MIN               0
 122 #define PINEVIEW_M2_MAX               254
 123 #define I9XX_P_SDVO_DAC_MIN           5
 124 #define I9XX_P_SDVO_DAC_MAX          80
 125 #define I9XX_P_LVDS_MIN               7
 126 #define I9XX_P_LVDS_MAX              98
 127 #define PINEVIEW_P_LVDS_MIN                   7
 128 #define PINEVIEW_P_LVDS_MAX                  112
 129 #define I9XX_P1_MIN                   1
 130 #define I9XX_P1_MAX                   8
 131 #define I9XX_P2_SDVO_DAC_SLOW                10
 132 #define I9XX_P2_SDVO_DAC_FAST                 5
 133 #define I9XX_P2_SDVO_DAC_SLOW_LIMIT      200000
 134 #define I9XX_P2_LVDS_SLOW                    14
 135 #define I9XX_P2_LVDS_FAST                     7
 136 #define I9XX_P2_LVDS_SLOW_LIMIT          112000
 137
 138 /*The parameter is for SDVO on G4x platform*/
 139 #define G4X_DOT_SDVO_MIN           25000
 140 #define G4X_DOT_SDVO_MAX           270000
 141 #define G4X_VCO_MIN                1750000
 142 #define G4X_VCO_MAX                3500000
 143 #define G4X_N_SDVO_MIN             1
 144 #define G4X_N_SDVO_MAX             4
 145 #define G4X_M_SDVO_MIN             104
 146 #define G4X_M_SDVO_MAX             138
 147 #define G4X_M1_SDVO_MIN            17
 148 #define G4X_M1_SDVO_MAX            23
 149 #define G4X_M2_SDVO_MIN            5
 150 #define G4X_M2_SDVO_MAX            11
 151 #define G4X_P_SDVO_MIN             10
 152 #define G4X_P_SDVO_MAX             30
 153 #define G4X_P1_SDVO_MIN            1
 154 #define G4X_P1_SDVO_MAX            3
 155 #define G4X_P2_SDVO_SLOW           10
 156 #define G4X_P2_SDVO_FAST           10
 157 #define G4X_P2_SDVO_LIMIT          270000
 158
 159 /*The parameter is for HDMI_DAC on G4x platform*/
 160 #define G4X_DOT_HDMI_DAC_MIN           22000
 161 #define G4X_DOT_HDMI_DAC_MAX           400000
 162 #define G4X_N_HDMI_DAC_MIN             1
 163 #define G4X_N_HDMI_DAC_MAX             4
 164 #define G4X_M_HDMI_DAC_MIN             104
 165 #define G4X_M_HDMI_DAC_MAX             138
 166 #define G4X_M1_HDMI_DAC_MIN            16
 167 #define G4X_M1_HDMI_DAC_MAX            23
 168 #define G4X_M2_HDMI_DAC_MIN            5
 169 #define G4X_M2_HDMI_DAC_MAX            11
 170 #define G4X_P_HDMI_DAC_MIN             5
 171 #define G4X_P_HDMI_DAC_MAX             80
 172 #define G4X_P1_HDMI_DAC_MIN            1
 173 #define G4X_P1_HDMI_DAC_MAX            8
 174 #define G4X_P2_HDMI_DAC_SLOW           10
 175 #define G4X_P2_HDMI_DAC_FAST           5
 176 #define G4X_P2_HDMI_DAC_LIMIT          165000
 177
 178 /*The parameter is for SINGLE_CHANNEL_LVDS on G4x platform*/
 179 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MIN           20000
 180 #define G4X_DOT_SINGLE_CHANNEL_LVDS_MAX           115000
 181 #define G4X_N_SINGLE_CHANNEL_LVDS_MIN             1
 182 #define G4X_N_SINGLE_CHANNEL_LVDS_MAX             3
 183 #define G4X_M_SINGLE_CHANNEL_LVDS_MIN             104
 184 #define G4X_M_SINGLE_CHANNEL_LVDS_MAX             138
 185 #define G4X_M1_SINGLE_CHANNEL_LVDS_MIN            17
 186 #define G4X_M1_SINGLE_CHANNEL_LVDS_MAX            23
 187 #define G4X_M2_SINGLE_CHANNEL_LVDS_MIN            5
 188 #define G4X_M2_SINGLE_CHANNEL_LVDS_MAX            11
 189 #define G4X_P_SINGLE_CHANNEL_LVDS_MIN             28
 190 #define G4X_P_SINGLE_CHANNEL_LVDS_MAX             112
 191 #define G4X_P1_SINGLE_CHANNEL_LVDS_MIN            2
 192 #define G4X_P1_SINGLE_CHANNEL_LVDS_MAX            8
 193 #define G4X_P2_SINGLE_CHANNEL_LVDS_SLOW           14
 194 #define G4X_P2_SINGLE_CHANNEL_LVDS_FAST           14
 195 #define G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT          0
 196
 197 /*The parameter is for DUAL_CHANNEL_LVDS on G4x platform*/
 198 #define G4X_DOT_DUAL_CHANNEL_LVDS_MIN           80000
 199 #define G4X_DOT_DUAL_CHANNEL_LVDS_MAX           224000
 200 #define G4X_N_DUAL_CHANNEL_LVDS_MIN             1
 201 #define G4X_N_DUAL_CHANNEL_LVDS_MAX             3
 202 #define G4X_M_DUAL_CHANNEL_LVDS_MIN             104
 203 #define G4X_M_DUAL_CHANNEL_LVDS_MAX             138
 204 #define G4X_M1_DUAL_CHANNEL_LVDS_MIN            17
 205 #define G4X_M1_DUAL_CHANNEL_LVDS_MAX            23
 206 #define G4X_M2_DUAL_CHANNEL_LVDS_MIN            5
 207 #define G4X_M2_DUAL_CHANNEL_LVDS_MAX            11
 208 #define G4X_P_DUAL_CHANNEL_LVDS_MIN             14
 209 #define G4X_P_DUAL_CHANNEL_LVDS_MAX             42
 210 #define G4X_P1_DUAL_CHANNEL_LVDS_MIN            2
 211 #define G4X_P1_DUAL_CHANNEL_LVDS_MAX            6
 212 #define G4X_P2_DUAL_CHANNEL_LVDS_SLOW           7
 213 #define G4X_P2_DUAL_CHANNEL_LVDS_FAST           7
 214 #define G4X_P2_DUAL_CHANNEL_LVDS_LIMIT          0
 215
 216 /*The parameter is for DISPLAY PORT on G4x platform*/
 217 #define G4X_DOT_DISPLAY_PORT_MIN           161670
 218 #define G4X_DOT_DISPLAY_PORT_MAX           227000
 219 #define G4X_N_DISPLAY_PORT_MIN             1
 220 #define G4X_N_DISPLAY_PORT_MAX             2
 221 #define G4X_M_DISPLAY_PORT_MIN             97
 222 #define G4X_M_DISPLAY_PORT_MAX             108
 223 #define G4X_M1_DISPLAY_PORT_MIN            0x10
 224 #define G4X_M1_DISPLAY_PORT_MAX            0x12
 225 #define G4X_M2_DISPLAY_PORT_MIN            0x05
 226 #define G4X_M2_DISPLAY_PORT_MAX            0x06
 227 #define G4X_P_DISPLAY_PORT_MIN             10
 228 #define G4X_P_DISPLAY_PORT_MAX             20
 229 #define G4X_P1_DISPLAY_PORT_MIN            1
 230 #define G4X_P1_DISPLAY_PORT_MAX            2
 231 #define G4X_P2_DISPLAY_PORT_SLOW           10
 232 #define G4X_P2_DISPLAY_PORT_FAST           10
 233 #define G4X_P2_DISPLAY_PORT_LIMIT          0
 234
 235 /* Ironlake */
 236 /* as we calculate clock using (register_value + 2) for
 237    N/M1/M2, so here the range value for them is (actual_value-2).
 238  */
 239 #define IRONLAKE_DOT_MIN         25000
 240 #define IRONLAKE_DOT_MAX         350000
 241 #define IRONLAKE_VCO_MIN         1760000
 242 #define IRONLAKE_VCO_MAX         3510000
 243 #define IRONLAKE_M1_MIN          12
 244 #define IRONLAKE_M1_MAX          22
 245 #define IRONLAKE_M2_MIN          5
 246 #define IRONLAKE_M2_MAX          9
 247 #define IRONLAKE_P2_DOT_LIMIT    225000 /* 225Mhz */
 248
 249 /* We have parameter ranges for different type of outputs. */
 250
 251 /* DAC & HDMI Refclk 120Mhz */
 252 #define IRONLAKE_DAC_N_MIN      1
 253 #define IRONLAKE_DAC_N_MAX      5
 254 #define IRONLAKE_DAC_M_MIN      79
 255 #define IRONLAKE_DAC_M_MAX      127
 256 #define IRONLAKE_DAC_P_MIN      5
 257 #define IRONLAKE_DAC_P_MAX      80
 258 #define IRONLAKE_DAC_P1_MIN     1
 259 #define IRONLAKE_DAC_P1_MAX     8
 260 #define IRONLAKE_DAC_P2_SLOW    10
 261 #define IRONLAKE_DAC_P2_FAST    5
 262
 263 /* LVDS single-channel 120Mhz refclk */
 264 #define IRONLAKE_LVDS_S_N_MIN   1
 265 #define IRONLAKE_LVDS_S_N_MAX   3
 266 #define IRONLAKE_LVDS_S_M_MIN   79
 267 #define IRONLAKE_LVDS_S_M_MAX   118
 268 #define IRONLAKE_LVDS_S_P_MIN   28
 269 #define IRONLAKE_LVDS_S_P_MAX   112
 270 #define IRONLAKE_LVDS_S_P1_MIN  2
 271 #define IRONLAKE_LVDS_S_P1_MAX  8
 272 #define IRONLAKE_LVDS_S_P2_SLOW 14
 273 #define IRONLAKE_LVDS_S_P2_FAST 14
 274
 275 /* LVDS dual-channel 120Mhz refclk */
 276 #define IRONLAKE_LVDS_D_N_MIN   1
 277 #define IRONLAKE_LVDS_D_N_MAX   3
 278 #define IRONLAKE_LVDS_D_M_MIN   79
 279 #define IRONLAKE_LVDS_D_M_MAX   127
 280 #define IRONLAKE_LVDS_D_P_MIN   14
 281 #define IRONLAKE_LVDS_D_P_MAX   56
 282 #define IRONLAKE_LVDS_D_P1_MIN  2
 283 #define IRONLAKE_LVDS_D_P1_MAX  8
 284 #define IRONLAKE_LVDS_D_P2_SLOW 7
 285 #define IRONLAKE_LVDS_D_P2_FAST 7
 286
 287 /* LVDS single-channel 100Mhz refclk */
 288 #define IRONLAKE_LVDS_S_SSC_N_MIN       1
 289 #define IRONLAKE_LVDS_S_SSC_N_MAX       2
 290 #define IRONLAKE_LVDS_S_SSC_M_MIN       79
 291 #define IRONLAKE_LVDS_S_SSC_M_MAX       126
 292 #define IRONLAKE_LVDS_S_SSC_P_MIN       28
 293 #define IRONLAKE_LVDS_S_SSC_P_MAX       112
 294 #define IRONLAKE_LVDS_S_SSC_P1_MIN      2
 295 #define IRONLAKE_LVDS_S_SSC_P1_MAX      8
 296 #define IRONLAKE_LVDS_S_SSC_P2_SLOW     14
 297 #define IRONLAKE_LVDS_S_SSC_P2_FAST     14
 298
 299 /* LVDS dual-channel 100Mhz refclk */
 300 #define IRONLAKE_LVDS_D_SSC_N_MIN       1
 301 #define IRONLAKE_LVDS_D_SSC_N_MAX       3
 302 #define IRONLAKE_LVDS_D_SSC_M_MIN       79
 303 #define IRONLAKE_LVDS_D_SSC_M_MAX       126
 304 #define IRONLAKE_LVDS_D_SSC_P_MIN       14
 305 #define IRONLAKE_LVDS_D_SSC_P_MAX       42
 306 #define IRONLAKE_LVDS_D_SSC_P1_MIN      2
 307 #define IRONLAKE_LVDS_D_SSC_P1_MAX      6
 308 #define IRONLAKE_LVDS_D_SSC_P2_SLOW     7
 309 #define IRONLAKE_LVDS_D_SSC_P2_FAST     7
 310
 311 /* DisplayPort */
 312 #define IRONLAKE_DP_N_MIN               1
 313 #define IRONLAKE_DP_N_MAX               2
 314 #define IRONLAKE_DP_M_MIN               81
 315 #define IRONLAKE_DP_M_MAX               90
 316 #define IRONLAKE_DP_P_MIN               10
 317 #define IRONLAKE_DP_P_MAX               20
 318 #define IRONLAKE_DP_P2_FAST             10
 319 #define IRONLAKE_DP_P2_SLOW             10
 320 #define IRONLAKE_DP_P2_LIMIT            0
 321 #define IRONLAKE_DP_P1_MIN              1
 322 #define IRONLAKE_DP_P1_MAX              2
 323
 324 static bool
 325 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 326                     int target, int refclk, intel_clock_t *best_clock);
 327 static bool
 328 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 329                         int target, int refclk, intel_clock_t *best_clock);
 330
 331 static bool
 332 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 333                       int target, int refclk, intel_clock_t *best_clock);
 334 static bool
 335 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 336                            int target, int refclk, intel_clock_t *best_clock);
 337
 338 static const intel_limit_t intel_limits_i8xx_dvo = {
 339         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 340         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 341         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 342         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 343         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 344         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 345         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 346         .p1  = { .min = I8XX_P1_MIN,            .max = I8XX_P1_MAX },
 347         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 348                  .p2_slow = I8XX_P2_SLOW,       .p2_fast = I8XX_P2_FAST },
 349         .find_pll = intel_find_best_PLL,
 350 };
 351
 352 static const intel_limit_t intel_limits_i8xx_lvds = {
 353         .dot = { .min = I8XX_DOT_MIN,           .max = I8XX_DOT_MAX },
 354         .vco = { .min = I8XX_VCO_MIN,           .max = I8XX_VCO_MAX },
 355         .n   = { .min = I8XX_N_MIN,             .max = I8XX_N_MAX },
 356         .m   = { .min = I8XX_M_MIN,             .max = I8XX_M_MAX },
 357         .m1  = { .min = I8XX_M1_MIN,            .max = I8XX_M1_MAX },
 358         .m2  = { .min = I8XX_M2_MIN,            .max = I8XX_M2_MAX },
 359         .p   = { .min = I8XX_P_MIN,             .max = I8XX_P_MAX },
 360         .p1  = { .min = I8XX_P1_LVDS_MIN,       .max = I8XX_P1_LVDS_MAX },
 361         .p2  = { .dot_limit = I8XX_P2_SLOW_LIMIT,
 362                  .p2_slow = I8XX_P2_LVDS_SLOW,  .p2_fast = I8XX_P2_LVDS_FAST },
 363         .find_pll = intel_find_best_PLL,
 364 };
 365
 366 static const intel_limit_t intel_limits_i9xx_sdvo = {
 367         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 368         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 369         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 370         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 371         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 372         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 373         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 374         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 375         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 376                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 377         .find_pll = intel_find_best_PLL,
 378 };
 379
 380 static const intel_limit_t intel_limits_i9xx_lvds = {
 381         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 382         .vco = { .min = I9XX_VCO_MIN,           .max = I9XX_VCO_MAX },
 383         .n   = { .min = I9XX_N_MIN,             .max = I9XX_N_MAX },
 384         .m   = { .min = I9XX_M_MIN,             .max = I9XX_M_MAX },
 385         .m1  = { .min = I9XX_M1_MIN,            .max = I9XX_M1_MAX },
 386         .m2  = { .min = I9XX_M2_MIN,            .max = I9XX_M2_MAX },
 387         .p   = { .min = I9XX_P_LVDS_MIN,        .max = I9XX_P_LVDS_MAX },
 388         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 389         /* The single-channel range is 25-112Mhz, and dual-channel
 390          * is 80-224Mhz.  Prefer single channel as much as possible.
 391          */
 392         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 393                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_FAST },
 394         .find_pll = intel_find_best_PLL,
 395 };
 396
 397     /* below parameter and function is for G4X Chipset Family*/
 398 static const intel_limit_t intel_limits_g4x_sdvo = {
 399         .dot = { .min = G4X_DOT_SDVO_MIN,       .max = G4X_DOT_SDVO_MAX },
 400         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 401         .n   = { .min = G4X_N_SDVO_MIN,         .max = G4X_N_SDVO_MAX },
 402         .m   = { .min = G4X_M_SDVO_MIN,         .max = G4X_M_SDVO_MAX },
 403         .m1  = { .min = G4X_M1_SDVO_MIN,        .max = G4X_M1_SDVO_MAX },
 404         .m2  = { .min = G4X_M2_SDVO_MIN,        .max = G4X_M2_SDVO_MAX },
 405         .p   = { .min = G4X_P_SDVO_MIN,         .max = G4X_P_SDVO_MAX },
 406         .p1  = { .min = G4X_P1_SDVO_MIN,        .max = G4X_P1_SDVO_MAX},
 407         .p2  = { .dot_limit = G4X_P2_SDVO_LIMIT,
 408                  .p2_slow = G4X_P2_SDVO_SLOW,
 409                  .p2_fast = G4X_P2_SDVO_FAST
 410         },
 411         .find_pll = intel_g4x_find_best_PLL,
 412 };
 413
 414 static const intel_limit_t intel_limits_g4x_hdmi = {
 415         .dot = { .min = G4X_DOT_HDMI_DAC_MIN,   .max = G4X_DOT_HDMI_DAC_MAX },
 416         .vco = { .min = G4X_VCO_MIN,            .max = G4X_VCO_MAX},
 417         .n   = { .min = G4X_N_HDMI_DAC_MIN,     .max = G4X_N_HDMI_DAC_MAX },
 418         .m   = { .min = G4X_M_HDMI_DAC_MIN,     .max = G4X_M_HDMI_DAC_MAX },
 419         .m1  = { .min = G4X_M1_HDMI_DAC_MIN,    .max = G4X_M1_HDMI_DAC_MAX },
 420         .m2  = { .min = G4X_M2_HDMI_DAC_MIN,    .max = G4X_M2_HDMI_DAC_MAX },
 421         .p   = { .min = G4X_P_HDMI_DAC_MIN,     .max = G4X_P_HDMI_DAC_MAX },
 422         .p1  = { .min = G4X_P1_HDMI_DAC_MIN,    .max = G4X_P1_HDMI_DAC_MAX},
 423         .p2  = { .dot_limit = G4X_P2_HDMI_DAC_LIMIT,
 424                  .p2_slow = G4X_P2_HDMI_DAC_SLOW,
 425                  .p2_fast = G4X_P2_HDMI_DAC_FAST
 426         },
 427         .find_pll = intel_g4x_find_best_PLL,
 428 };
 429
 430 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 431         .dot = { .min = G4X_DOT_SINGLE_CHANNEL_LVDS_MIN,
 432                  .max = G4X_DOT_SINGLE_CHANNEL_LVDS_MAX },
 433         .vco = { .min = G4X_VCO_MIN,
 434                  .max = G4X_VCO_MAX },
 435         .n   = { .min = G4X_N_SINGLE_CHANNEL_LVDS_MIN,
 436                  .max = G4X_N_SINGLE_CHANNEL_LVDS_MAX },
 437         .m   = { .min = G4X_M_SINGLE_CHANNEL_LVDS_MIN,
 438                  .max = G4X_M_SINGLE_CHANNEL_LVDS_MAX },
 439         .m1  = { .min = G4X_M1_SINGLE_CHANNEL_LVDS_MIN,
 440                  .max = G4X_M1_SINGLE_CHANNEL_LVDS_MAX },
 441         .m2  = { .min = G4X_M2_SINGLE_CHANNEL_LVDS_MIN,
 442                  .max = G4X_M2_SINGLE_CHANNEL_LVDS_MAX },
 443         .p   = { .min = G4X_P_SINGLE_CHANNEL_LVDS_MIN,
 444                  .max = G4X_P_SINGLE_CHANNEL_LVDS_MAX },
 445         .p1  = { .min = G4X_P1_SINGLE_CHANNEL_LVDS_MIN,
 446                  .max = G4X_P1_SINGLE_CHANNEL_LVDS_MAX },
 447         .p2  = { .dot_limit = G4X_P2_SINGLE_CHANNEL_LVDS_LIMIT,
 448                  .p2_slow = G4X_P2_SINGLE_CHANNEL_LVDS_SLOW,
 449                  .p2_fast = G4X_P2_SINGLE_CHANNEL_LVDS_FAST
 450         },
 451         .find_pll = intel_g4x_find_best_PLL,
 452 };
 453
 454 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 455         .dot = { .min = G4X_DOT_DUAL_CHANNEL_LVDS_MIN,
 456                  .max = G4X_DOT_DUAL_CHANNEL_LVDS_MAX },
 457         .vco = { .min = G4X_VCO_MIN,
 458                  .max = G4X_VCO_MAX },
 459         .n   = { .min = G4X_N_DUAL_CHANNEL_LVDS_MIN,
 460                  .max = G4X_N_DUAL_CHANNEL_LVDS_MAX },
 461         .m   = { .min = G4X_M_DUAL_CHANNEL_LVDS_MIN,
 462                  .max = G4X_M_DUAL_CHANNEL_LVDS_MAX },
 463         .m1  = { .min = G4X_M1_DUAL_CHANNEL_LVDS_MIN,
 464                  .max = G4X_M1_DUAL_CHANNEL_LVDS_MAX },
 465         .m2  = { .min = G4X_M2_DUAL_CHANNEL_LVDS_MIN,
 466                  .max = G4X_M2_DUAL_CHANNEL_LVDS_MAX },
 467         .p   = { .min = G4X_P_DUAL_CHANNEL_LVDS_MIN,
 468                  .max = G4X_P_DUAL_CHANNEL_LVDS_MAX },
 469         .p1  = { .min = G4X_P1_DUAL_CHANNEL_LVDS_MIN,
 470                  .max = G4X_P1_DUAL_CHANNEL_LVDS_MAX },
 471         .p2  = { .dot_limit = G4X_P2_DUAL_CHANNEL_LVDS_LIMIT,
 472                  .p2_slow = G4X_P2_DUAL_CHANNEL_LVDS_SLOW,
 473                  .p2_fast = G4X_P2_DUAL_CHANNEL_LVDS_FAST
 474         },
 475         .find_pll = intel_g4x_find_best_PLL,
 476 };
 477
 478 static const intel_limit_t intel_limits_g4x_display_port = {
 479         .dot = { .min = G4X_DOT_DISPLAY_PORT_MIN,
 480                  .max = G4X_DOT_DISPLAY_PORT_MAX },
 481         .vco = { .min = G4X_VCO_MIN,
 482                  .max = G4X_VCO_MAX},
 483         .n   = { .min = G4X_N_DISPLAY_PORT_MIN,
 484                  .max = G4X_N_DISPLAY_PORT_MAX },
 485         .m   = { .min = G4X_M_DISPLAY_PORT_MIN,
 486                  .max = G4X_M_DISPLAY_PORT_MAX },
 487         .m1  = { .min = G4X_M1_DISPLAY_PORT_MIN,
 488                  .max = G4X_M1_DISPLAY_PORT_MAX },
 489         .m2  = { .min = G4X_M2_DISPLAY_PORT_MIN,
 490                  .max = G4X_M2_DISPLAY_PORT_MAX },
 491         .p   = { .min = G4X_P_DISPLAY_PORT_MIN,
 492                  .max = G4X_P_DISPLAY_PORT_MAX },
 493         .p1  = { .min = G4X_P1_DISPLAY_PORT_MIN,
 494                  .max = G4X_P1_DISPLAY_PORT_MAX},
 495         .p2  = { .dot_limit = G4X_P2_DISPLAY_PORT_LIMIT,
 496                  .p2_slow = G4X_P2_DISPLAY_PORT_SLOW,
 497                  .p2_fast = G4X_P2_DISPLAY_PORT_FAST },
 498         .find_pll = intel_find_pll_g4x_dp,
 499 };
 500
 501 static const intel_limit_t intel_limits_pineview_sdvo = {
 502         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX},
 503         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 504         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 505         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 506         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 507         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 508         .p   = { .min = I9XX_P_SDVO_DAC_MIN,    .max = I9XX_P_SDVO_DAC_MAX },
 509         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 510         .p2  = { .dot_limit = I9XX_P2_SDVO_DAC_SLOW_LIMIT,
 511                  .p2_slow = I9XX_P2_SDVO_DAC_SLOW,      .p2_fast = I9XX_P2_SDVO_DAC_FAST },
 512         .find_pll = intel_find_best_PLL,
 513 };
 514
 515 static const intel_limit_t intel_limits_pineview_lvds = {
 516         .dot = { .min = I9XX_DOT_MIN,           .max = I9XX_DOT_MAX },
 517         .vco = { .min = PINEVIEW_VCO_MIN,               .max = PINEVIEW_VCO_MAX },
 518         .n   = { .min = PINEVIEW_N_MIN,         .max = PINEVIEW_N_MAX },
 519         .m   = { .min = PINEVIEW_M_MIN,         .max = PINEVIEW_M_MAX },
 520         .m1  = { .min = PINEVIEW_M1_MIN,                .max = PINEVIEW_M1_MAX },
 521         .m2  = { .min = PINEVIEW_M2_MIN,                .max = PINEVIEW_M2_MAX },
 522         .p   = { .min = PINEVIEW_P_LVDS_MIN,    .max = PINEVIEW_P_LVDS_MAX },
 523         .p1  = { .min = I9XX_P1_MIN,            .max = I9XX_P1_MAX },
 524         /* Pineview only supports single-channel mode. */
 525         .p2  = { .dot_limit = I9XX_P2_LVDS_SLOW_LIMIT,
 526                  .p2_slow = I9XX_P2_LVDS_SLOW,  .p2_fast = I9XX_P2_LVDS_SLOW },
 527         .find_pll = intel_find_best_PLL,
 528 };
 529
 530 static const intel_limit_t intel_limits_ironlake_dac = {
 531         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 532         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 533         .n   = { .min = IRONLAKE_DAC_N_MIN,        .max = IRONLAKE_DAC_N_MAX },
 534         .m   = { .min = IRONLAKE_DAC_M_MIN,        .max = IRONLAKE_DAC_M_MAX },
 535         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 536         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 537         .p   = { .min = IRONLAKE_DAC_P_MIN,        .max = IRONLAKE_DAC_P_MAX },
 538         .p1  = { .min = IRONLAKE_DAC_P1_MIN,       .max = IRONLAKE_DAC_P1_MAX },
 539         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 540                  .p2_slow = IRONLAKE_DAC_P2_SLOW,
 541                  .p2_fast = IRONLAKE_DAC_P2_FAST },
 542         .find_pll = intel_g4x_find_best_PLL,
 543 };
 544
 545 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 546         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 547         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 548         .n   = { .min = IRONLAKE_LVDS_S_N_MIN,     .max = IRONLAKE_LVDS_S_N_MAX },
 549         .m   = { .min = IRONLAKE_LVDS_S_M_MIN,     .max = IRONLAKE_LVDS_S_M_MAX },
 550         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 551         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 552         .p   = { .min = IRONLAKE_LVDS_S_P_MIN,     .max = IRONLAKE_LVDS_S_P_MAX },
 553         .p1  = { .min = IRONLAKE_LVDS_S_P1_MIN,    .max = IRONLAKE_LVDS_S_P1_MAX },
 554         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 555                  .p2_slow = IRONLAKE_LVDS_S_P2_SLOW,
 556                  .p2_fast = IRONLAKE_LVDS_S_P2_FAST },
 557         .find_pll = intel_g4x_find_best_PLL,
 558 };
 559
 560 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 561         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 562         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 563         .n   = { .min = IRONLAKE_LVDS_D_N_MIN,     .max = IRONLAKE_LVDS_D_N_MAX },
 564         .m   = { .min = IRONLAKE_LVDS_D_M_MIN,     .max = IRONLAKE_LVDS_D_M_MAX },
 565         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 566         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 567         .p   = { .min = IRONLAKE_LVDS_D_P_MIN,     .max = IRONLAKE_LVDS_D_P_MAX },
 568         .p1  = { .min = IRONLAKE_LVDS_D_P1_MIN,    .max = IRONLAKE_LVDS_D_P1_MAX },
 569         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 570                  .p2_slow = IRONLAKE_LVDS_D_P2_SLOW,
 571                  .p2_fast = IRONLAKE_LVDS_D_P2_FAST },
 572         .find_pll = intel_g4x_find_best_PLL,
 573 };
 574
 575 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 576         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 577         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 578         .n   = { .min = IRONLAKE_LVDS_S_SSC_N_MIN, .max = IRONLAKE_LVDS_S_SSC_N_MAX },
 579         .m   = { .min = IRONLAKE_LVDS_S_SSC_M_MIN, .max = IRONLAKE_LVDS_S_SSC_M_MAX },
 580         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 581         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 582         .p   = { .min = IRONLAKE_LVDS_S_SSC_P_MIN, .max = IRONLAKE_LVDS_S_SSC_P_MAX },
 583         .p1  = { .min = IRONLAKE_LVDS_S_SSC_P1_MIN,.max = IRONLAKE_LVDS_S_SSC_P1_MAX },
 584         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 585                  .p2_slow = IRONLAKE_LVDS_S_SSC_P2_SLOW,
 586                  .p2_fast = IRONLAKE_LVDS_S_SSC_P2_FAST },
 587         .find_pll = intel_g4x_find_best_PLL,
 588 };
 589
 590 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 591         .dot = { .min = IRONLAKE_DOT_MIN,          .max = IRONLAKE_DOT_MAX },
 592         .vco = { .min = IRONLAKE_VCO_MIN,          .max = IRONLAKE_VCO_MAX },
 593         .n   = { .min = IRONLAKE_LVDS_D_SSC_N_MIN, .max = IRONLAKE_LVDS_D_SSC_N_MAX },
 594         .m   = { .min = IRONLAKE_LVDS_D_SSC_M_MIN, .max = IRONLAKE_LVDS_D_SSC_M_MAX },
 595         .m1  = { .min = IRONLAKE_M1_MIN,           .max = IRONLAKE_M1_MAX },
 596         .m2  = { .min = IRONLAKE_M2_MIN,           .max = IRONLAKE_M2_MAX },
 597         .p   = { .min = IRONLAKE_LVDS_D_SSC_P_MIN, .max = IRONLAKE_LVDS_D_SSC_P_MAX },
 598         .p1  = { .min = IRONLAKE_LVDS_D_SSC_P1_MIN,.max = IRONLAKE_LVDS_D_SSC_P1_MAX },
 599         .p2  = { .dot_limit = IRONLAKE_P2_DOT_LIMIT,
 600                  .p2_slow = IRONLAKE_LVDS_D_SSC_P2_SLOW,
 601                  .p2_fast = IRONLAKE_LVDS_D_SSC_P2_FAST },
 602         .find_pll = intel_g4x_find_best_PLL,
 603 };
 604
 605 static const intel_limit_t intel_limits_ironlake_display_port = {
 606         .dot = { .min = IRONLAKE_DOT_MIN,
 607                  .max = IRONLAKE_DOT_MAX },
 608         .vco = { .min = IRONLAKE_VCO_MIN,
 609                  .max = IRONLAKE_VCO_MAX},
 610         .n   = { .min = IRONLAKE_DP_N_MIN,
 611                  .max = IRONLAKE_DP_N_MAX },
 612         .m   = { .min = IRONLAKE_DP_M_MIN,
 613                  .max = IRONLAKE_DP_M_MAX },
 614         .m1  = { .min = IRONLAKE_M1_MIN,
 615                  .max = IRONLAKE_M1_MAX },
 616         .m2  = { .min = IRONLAKE_M2_MIN,
 617                  .max = IRONLAKE_M2_MAX },
 618         .p   = { .min = IRONLAKE_DP_P_MIN,
 619                  .max = IRONLAKE_DP_P_MAX },
 620         .p1  = { .min = IRONLAKE_DP_P1_MIN,
 621                  .max = IRONLAKE_DP_P1_MAX},
 622         .p2  = { .dot_limit = IRONLAKE_DP_P2_LIMIT,
 623                  .p2_slow = IRONLAKE_DP_P2_SLOW,
 624                  .p2_fast = IRONLAKE_DP_P2_FAST },
 625         .find_pll = intel_find_pll_ironlake_dp,
 626 };
 627
 628 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc)
 629 {
 630         struct drm_device *dev = crtc->dev;
 631         struct drm_i915_private *dev_priv = dev->dev_private;
 632         const intel_limit_t *limit;
 633         int refclk = 120;
 634
 635         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 636                 if (dev_priv->lvds_use_ssc && dev_priv->lvds_ssc_freq == 100)
 637                         refclk = 100;
 638
 639                 if ((I915_READ(PCH_LVDS) & LVDS_CLKB_POWER_MASK) ==
 640                     LVDS_CLKB_POWER_UP) {
 641                         /* LVDS dual channel */
 642                         if (refclk == 100)
 643                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 644                         else
 645                                 limit = &intel_limits_ironlake_dual_lvds;
 646                 } else {
 647                         if (refclk == 100)
 648                                 limit = &intel_limits_ironlake_single_lvds_100m;
 649                         else
 650                                 limit = &intel_limits_ironlake_single_lvds;
 651                 }
 652         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 653                         HAS_eDP)
 654                 limit = &intel_limits_ironlake_display_port;
 655         else
 656                 limit = &intel_limits_ironlake_dac;
 657
 658         return limit;
 659 }
 660
 661 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 662 {
 663         struct drm_device *dev = crtc->dev;
 664         struct drm_i915_private *dev_priv = dev->dev_private;
 665         const intel_limit_t *limit;
 666
 667         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 668                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 669                     LVDS_CLKB_POWER_UP)
 670                         /* LVDS with dual channel */
 671                         limit = &intel_limits_g4x_dual_channel_lvds;
 672                 else
 673                         /* LVDS with dual channel */
 674                         limit = &intel_limits_g4x_single_channel_lvds;
 675         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 676                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 677                 limit = &intel_limits_g4x_hdmi;
 678         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 679                 limit = &intel_limits_g4x_sdvo;
 680         } else if (intel_pipe_has_type (crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 681                 limit = &intel_limits_g4x_display_port;
 682         } else /* The option is for other outputs */
 683                 limit = &intel_limits_i9xx_sdvo;
 684
 685         return limit;
 686 }
 687
 688 static const intel_limit_t *intel_limit(struct drm_crtc *crtc)
 689 {
 690         struct drm_device *dev = crtc->dev;
 691         const intel_limit_t *limit;
 692
 693         if (IS_IRONLAKE(dev))
 694                 limit = intel_ironlake_limit(crtc);
 695         else if (IS_G4X(dev)) {
 696                 limit = intel_g4x_limit(crtc);
 697         } else if (IS_I9XX(dev) && !IS_PINEVIEW(dev)) {
 698                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 699                         limit = &intel_limits_i9xx_lvds;
 700                 else
 701                         limit = &intel_limits_i9xx_sdvo;
 702         } else if (IS_PINEVIEW(dev)) {
 703                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 704                         limit = &intel_limits_pineview_lvds;
 705                 else
 706                         limit = &intel_limits_pineview_sdvo;
 707         } else {
 708                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 709                         limit = &intel_limits_i8xx_lvds;
 710                 else
 711                         limit = &intel_limits_i8xx_dvo;
 712         }
 713         return limit;
 714 }
 715
 716 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 717 static void pineview_clock(int refclk, intel_clock_t *clock)
 718 {
 719         clock->m = clock->m2 + 2;
 720         clock->p = clock->p1 * clock->p2;
 721         clock->vco = refclk * clock->m / clock->n;
 722         clock->dot = clock->vco / clock->p;
 723 }
 724
 725 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 726 {
 727         if (IS_PINEVIEW(dev)) {
 728                 pineview_clock(refclk, clock);
 729                 return;
 730         }
 731         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 732         clock->p = clock->p1 * clock->p2;
 733         clock->vco = refclk * clock->m / (clock->n + 2);
 734         clock->dot = clock->vco / clock->p;
 735 }
 736
 737 /**
 738  * Returns whether any output on the specified pipe is of the specified type
 739  */
 740 bool intel_pipe_has_type (struct drm_crtc *crtc, int type)
 741 {
 742     struct drm_device *dev = crtc->dev;
 743     struct drm_mode_config *mode_config = &dev->mode_config;
 744     struct drm_connector *l_entry;
 745
 746     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 747             if (l_entry->encoder &&
 748                 l_entry->encoder->crtc == crtc) {
 749                     struct intel_output *intel_output = to_intel_output(l_entry);
 750                     if (intel_output->type == type)
 751                             return true;
 752             }
 753     }
 754     return false;
 755 }
 756
 757 struct drm_connector *
 758 intel_pipe_get_output (struct drm_crtc *crtc)
 759 {
 760     struct drm_device *dev = crtc->dev;
 761     struct drm_mode_config *mode_config = &dev->mode_config;
 762     struct drm_connector *l_entry, *ret = NULL;
 763
 764     list_for_each_entry(l_entry, &mode_config->connector_list, head) {
 765             if (l_entry->encoder &&
 766                 l_entry->encoder->crtc == crtc) {
 767                     ret = l_entry;
 768                     break;
 769             }
 770     }
 771     return ret;
 772 }
 773
 774 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 775 /**
 776  * Returns whether the given set of divisors are valid for a given refclk with
 777  * the given connectors.
 778  */
 779
 780 static bool intel_PLL_is_valid(struct drm_crtc *crtc, intel_clock_t *clock)
 781 {
 782         const intel_limit_t *limit = intel_limit (crtc);
 783         struct drm_device *dev = crtc->dev;
 784
 785         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 786                 INTELPllInvalid ("p1 out of range\n");
 787         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 788                 INTELPllInvalid ("p out of range\n");
 789         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 790                 INTELPllInvalid ("m2 out of range\n");
 791         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 792                 INTELPllInvalid ("m1 out of range\n");
 793         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 794                 INTELPllInvalid ("m1 <= m2\n");
 795         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 796                 INTELPllInvalid ("m out of range\n");
 797         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 798                 INTELPllInvalid ("n out of range\n");
 799         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 800                 INTELPllInvalid ("vco out of range\n");
 801         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 802          * connector, etc., rather than just a single range.
 803          */
 804         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 805                 INTELPllInvalid ("dot out of range\n");
 806
 807         return true;
 808 }
 809
 810 static bool
 811 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 812                     int target, int refclk, intel_clock_t *best_clock)
 813
 814 {
 815         struct drm_device *dev = crtc->dev;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         intel_clock_t clock;
 818         int err = target;
 819
 820         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
 821             (I915_READ(LVDS)) != 0) {
 822                 /*
 823                  * For LVDS, if the panel is on, just rely on its current
 824                  * settings for dual-channel.  We haven't figured out how to
 825                  * reliably set up different single/dual channel state, if we
 826                  * even can.
 827                  */
 828                 if ((I915_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
 829                     LVDS_CLKB_POWER_UP)
 830                         clock.p2 = limit->p2.p2_fast;
 831                 else
 832                         clock.p2 = limit->p2.p2_slow;
 833         } else {
 834                 if (target < limit->p2.dot_limit)
 835                         clock.p2 = limit->p2.p2_slow;
 836                 else
 837                         clock.p2 = limit->p2.p2_fast;
 838         }
 839
 840         memset (best_clock, 0, sizeof (*best_clock));
 841
 842         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 843              clock.m1++) {
 844                 for (clock.m2 = limit->m2.min;
 845                      clock.m2 <= limit->m2.max; clock.m2++) {
 846                         /* m1 is always 0 in Pineview */
 847                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 848                                 break;
 849                         for (clock.n = limit->n.min;
 850                              clock.n <= limit->n.max; clock.n++) {
 851                                 for (clock.p1 = limit->p1.min;
 852                                         clock.p1 <= limit->p1.max; clock.p1++) {
 853                                         int this_err;
 854
 855                                         intel_clock(dev, refclk, &clock);
 856
 857                                         if (!intel_PLL_is_valid(crtc, &clock))
 858                                                 continue;
 859
 860                                         this_err = abs(clock.dot - target);
 861                                         if (this_err < err) {
 862                                                 *best_clock = clock;
 863                                                 err = this_err;
 864                                         }
 865                                 }
 866                         }
 867                 }
 868         }
 869
 870         return (err != target);
 871 }
 872
 873 static bool
 874 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 875                         int target, int refclk, intel_clock_t *best_clock)
 876 {
 877         struct drm_device *dev = crtc->dev;
 878         struct drm_i915_private *dev_priv = dev->dev_private;
 879         intel_clock_t clock;
 880         int max_n;
 881         bool found;
 882         /* approximately equals target * 0.00488 */
 883         int err_most = (target >> 8) + (target >> 10);
 884         found = false;
 885
 886         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 887                 int lvds_reg;
 888
 889                 if (IS_IRONLAKE(dev))
 890                         lvds_reg = PCH_LVDS;
 891                 else
 892                         lvds_reg = LVDS;
 893                 if ((I915_READ(lvds_reg) & LVDS_CLKB_POWER_MASK) ==
 894                     LVDS_CLKB_POWER_UP)
 895                         clock.p2 = limit->p2.p2_fast;
 896                 else
 897                         clock.p2 = limit->p2.p2_slow;
 898         } else {
 899                 if (target < limit->p2.dot_limit)
 900                         clock.p2 = limit->p2.p2_slow;
 901                 else
 902                         clock.p2 = limit->p2.p2_fast;
 903         }
 904
 905         memset(best_clock, 0, sizeof(*best_clock));
 906         max_n = limit->n.max;
 907         /* based on hardware requriment prefer smaller n to precision */
 908         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 909                 /* based on hardware requirment prefere larger m1,m2 */
 910                 for (clock.m1 = limit->m1.max;
 911                      clock.m1 >= limit->m1.min; clock.m1--) {
 912                         for (clock.m2 = limit->m2.max;
 913                              clock.m2 >= limit->m2.min; clock.m2--) {
 914                                 for (clock.p1 = limit->p1.max;
 915                                      clock.p1 >= limit->p1.min; clock.p1--) {
 916                                         int this_err;
 917
 918                                         intel_clock(dev, refclk, &clock);
 919                                         if (!intel_PLL_is_valid(crtc, &clock))
 920                                                 continue;
 921                                         this_err = abs(clock.dot - target) ;
 922                                         if (this_err < err_most) {
 923                                                 *best_clock = clock;
 924                                                 err_most = this_err;
 925                                                 max_n = clock.n;
 926                                                 found = true;
 927                                         }
 928                                 }
 929                         }
 930                 }
 931         }
 932         return found;
 933 }
 934
 935 static bool
 936 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 937                            int target, int refclk, intel_clock_t *best_clock)
 938 {
 939         struct drm_device *dev = crtc->dev;
 940         intel_clock_t clock;
 941
 942         /* return directly when it is eDP */
 943         if (HAS_eDP)
 944                 return true;
 945
 946         if (target < 200000) {
 947                 clock.n = 1;
 948                 clock.p1 = 2;
 949                 clock.p2 = 10;
 950                 clock.m1 = 12;
 951                 clock.m2 = 9;
 952         } else {
 953                 clock.n = 2;
 954                 clock.p1 = 1;
 955                 clock.p2 = 10;
 956                 clock.m1 = 14;
 957                 clock.m2 = 8;
 958         }
 959         intel_clock(dev, refclk, &clock);
 960         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 961         return true;
 962 }
 963
 964 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 965 static bool
 966 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 967                       int target, int refclk, intel_clock_t *best_clock)
 968 {
 969     intel_clock_t clock;
 970     if (target < 200000) {
 971         clock.p1 = 2;
 972         clock.p2 = 10;
 973         clock.n = 2;
 974         clock.m1 = 23;
 975         clock.m2 = 8;
 976     } else {
 977         clock.p1 = 1;
 978         clock.p2 = 10;
 979         clock.n = 1;
 980         clock.m1 = 14;
 981         clock.m2 = 2;
 982     }
 983     clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 984     clock.p = (clock.p1 * clock.p2);
 985     clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 986     clock.vco = 0;
 987     memcpy(best_clock, &clock, sizeof(intel_clock_t));
 988     return true;
 989 }
 990
 991 void
 992 intel_wait_for_vblank(struct drm_device *dev)
 993 {
 994         /* Wait for 20ms, i.e. one cycle at 50hz. */
 995         msleep(20);
 996 }
 997
 998 /* Parameters have changed, update FBC info */
 999 static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1000 {
1001         struct drm_device *dev = crtc->dev;
1002         struct drm_i915_private *dev_priv = dev->dev_private;
1003         struct drm_framebuffer *fb = crtc->fb;
1004         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1005         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1006         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1007         int plane, i;
1008         u32 fbc_ctl, fbc_ctl2;
1009
1010         dev_priv->cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
1011
1012         if (fb->pitch < dev_priv->cfb_pitch)
1013                 dev_priv->cfb_pitch = fb->pitch;
1014
1015         /* FBC_CTL wants 64B units */
1016         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1017         dev_priv->cfb_fence = obj_priv->fence_reg;
1018         dev_priv->cfb_plane = intel_crtc->plane;
1019         plane = dev_priv->cfb_plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
1020
1021         /* Clear old tags */
1022         for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
1023                 I915_WRITE(FBC_TAG + (i * 4), 0);
1024
1025         /* Set it up... */
1026         fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | plane;
1027         if (obj_priv->tiling_mode != I915_TILING_NONE)
1028                 fbc_ctl2 |= FBC_CTL_CPU_FENCE;
1029         I915_WRITE(FBC_CONTROL2, fbc_ctl2);
1030         I915_WRITE(FBC_FENCE_OFF, crtc->y);
1031
1032         /* enable it... */
1033         fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
1034         if (IS_I945GM(dev))
1035                 fbc_ctl |= FBC_C3_IDLE; /* 945 needs special SR handling */
1036         fbc_ctl |= (dev_priv->cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
1037         fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
1038         if (obj_priv->tiling_mode != I915_TILING_NONE)
1039                 fbc_ctl |= dev_priv->cfb_fence;
1040         I915_WRITE(FBC_CONTROL, fbc_ctl);
1041
1042         DRM_DEBUG_KMS("enabled FBC, pitch %ld, yoff %d, plane %d, ",
1043                   dev_priv->cfb_pitch, crtc->y, dev_priv->cfb_plane);
1044 }
1045
1046 void i8xx_disable_fbc(struct drm_device *dev)
1047 {
1048         struct drm_i915_private *dev_priv = dev->dev_private;
1049         u32 fbc_ctl;
1050
1051         if (!I915_HAS_FBC(dev))
1052                 return;
1053
1054         /* Disable compression */
1055         fbc_ctl = I915_READ(FBC_CONTROL);
1056         fbc_ctl &= ~FBC_CTL_EN;
1057         I915_WRITE(FBC_CONTROL, fbc_ctl);
1058
1059         /* Wait for compressing bit to clear */
1060         while (I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING)
1061                 ; /* nothing */
1062
1063         intel_wait_for_vblank(dev);
1064
1065         DRM_DEBUG_KMS("disabled FBC\n");
1066 }
1067
1068 static bool i8xx_fbc_enabled(struct drm_crtc *crtc)
1069 {
1070         struct drm_device *dev = crtc->dev;
1071         struct drm_i915_private *dev_priv = dev->dev_private;
1072
1073         return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
1074 }
1075
1076 static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
1077 {
1078         struct drm_device *dev = crtc->dev;
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         struct drm_framebuffer *fb = crtc->fb;
1081         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
1082         struct drm_i915_gem_object *obj_priv = intel_fb->obj->driver_private;
1083         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1084         int plane = (intel_crtc->plane == 0 ? DPFC_CTL_PLANEA :
1085                      DPFC_CTL_PLANEB);
1086         unsigned long stall_watermark = 200;
1087         u32 dpfc_ctl;
1088
1089         dev_priv->cfb_pitch = (dev_priv->cfb_pitch / 64) - 1;
1090         dev_priv->cfb_fence = obj_priv->fence_reg;
1091         dev_priv->cfb_plane = intel_crtc->plane;
1092
1093         dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
1094         if (obj_priv->tiling_mode != I915_TILING_NONE) {
1095                 dpfc_ctl |= DPFC_CTL_FENCE_EN | dev_priv->cfb_fence;
1096                 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
1097         } else {
1098                 I915_WRITE(DPFC_CHICKEN, ~DPFC_HT_MODIFY);
1099         }
1100
1101         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1102         I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
1103                    (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
1104                    (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
1105         I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
1106
1107         /* enable it... */
1108         I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
1109
1110         DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
1111 }
1112
1113 void g4x_disable_fbc(struct drm_device *dev)
1114 {
1115         struct drm_i915_private *dev_priv = dev->dev_private;
1116         u32 dpfc_ctl;
1117
1118         /* Disable compression */
1119         dpfc_ctl = I915_READ(DPFC_CONTROL);
1120         dpfc_ctl &= ~DPFC_CTL_EN;
1121         I915_WRITE(DPFC_CONTROL, dpfc_ctl);
1122         intel_wait_for_vblank(dev);
1123
1124         DRM_DEBUG_KMS("disabled FBC\n");
1125 }
1126
1127 static bool g4x_fbc_enabled(struct drm_crtc *crtc)
1128 {
1129         struct drm_device *dev = crtc->dev;
1130         struct drm_i915_private *dev_priv = dev->dev_private;
1131
1132         return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
1133 }
1134
1135 /**
1136  * intel_update_fbc - enable/disable FBC as needed
1137  * @crtc: CRTC to point the compressor at
1138  * @mode: mode in use
1139  *
1140  * Set up the framebuffer compression hardware at mode set time.  We
1141  * enable it if possible:
1142  *   - plane A only (on pre-965)
1143  *   - no pixel mulitply/line duplication
1144  *   - no alpha buffer discard
1145  *   - no dual wide
1146  *   - framebuffer <= 2048 in width, 1536 in height
1147  *
1148  * We can't assume that any compression will take place (worst case),
1149  * so the compressed buffer has to be the same size as the uncompressed
1150  * one.  It also must reside (along with the line length buffer) in
1151  * stolen memory.
1152  *
1153  * We need to enable/disable FBC on a global basis.
1154  */
1155 static void intel_update_fbc(struct drm_crtc *crtc,
1156                              struct drm_display_mode *mode)
1157 {
1158         struct drm_device *dev = crtc->dev;
1159         struct drm_i915_private *dev_priv = dev->dev_private;
1160         struct drm_framebuffer *fb = crtc->fb;
1161         struct intel_framebuffer *intel_fb;
1162         struct drm_i915_gem_object *obj_priv;
1163         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1164         int plane = intel_crtc->plane;
1165
1166         if (!i915_powersave)
1167                 return;
1168
1169         if (!dev_priv->display.fbc_enabled ||
1170             !dev_priv->display.enable_fbc ||
1171             !dev_priv->display.disable_fbc)
1172                 return;
1173
1174         if (!crtc->fb)
1175                 return;
1176
1177         intel_fb = to_intel_framebuffer(fb);
1178         obj_priv = intel_fb->obj->driver_private;
1179
1180         /*
1181          * If FBC is already on, we just have to verify that we can
1182          * keep it that way...
1183          * Need to disable if:
1184          *   - changing FBC params (stride, fence, mode)
1185          *   - new fb is too large to fit in compressed buffer
1186          *   - going to an unsupported config (interlace, pixel multiply, etc.)
1187          */
1188         if (intel_fb->obj->size > dev_priv->cfb_size) {
1189                 DRM_DEBUG_KMS("framebuffer too large, disabling "
1190                                 "compression\n");
1191                 goto out_disable;
1192         }
1193         if ((mode->flags & DRM_MODE_FLAG_INTERLACE) ||
1194             (mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
1195                 DRM_DEBUG_KMS("mode incompatible with compression, "
1196                                 "disabling\n");
1197                 goto out_disable;
1198         }
1199         if ((mode->hdisplay > 2048) ||
1200             (mode->vdisplay > 1536)) {
1201                 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
1202                 goto out_disable;
1203         }
1204         if ((IS_I915GM(dev) || IS_I945GM(dev)) && plane != 0) {
1205                 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
1206                 goto out_disable;
1207         }
1208         if (obj_priv->tiling_mode != I915_TILING_X) {
1209                 DRM_DEBUG_KMS("framebuffer not tiled, disabling compression\n");
1210                 goto out_disable;
1211         }
1212
1213         if (dev_priv->display.fbc_enabled(crtc)) {
1214                 /* We can re-enable it in this case, but need to update pitch */
1215                 if (fb->pitch > dev_priv->cfb_pitch)
1216                         dev_priv->display.disable_fbc(dev);
1217                 if (obj_priv->fence_reg != dev_priv->cfb_fence)
1218                         dev_priv->display.disable_fbc(dev);
1219                 if (plane != dev_priv->cfb_plane)
1220                         dev_priv->display.disable_fbc(dev);
1221         }
1222
1223         if (!dev_priv->display.fbc_enabled(crtc)) {
1224                 /* Now try to turn it back on if possible */
1225                 dev_priv->display.enable_fbc(crtc, 500);
1226         }
1227
1228         return;
1229
1230 out_disable:
1231         DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
1232         /* Multiple disables should be harmless */
1233         if (dev_priv->display.fbc_enabled(crtc))
1234                 dev_priv->display.disable_fbc(dev);
1235 }
1236
1237 static int
1238 intel_pin_and_fence_fb_obj(struct drm_device *dev, struct drm_gem_object *obj)
1239 {
1240         struct drm_i915_gem_object *obj_priv = obj->driver_private;
1241         u32 alignment;
1242         int ret;
1243
1244         switch (obj_priv->tiling_mode) {
1245         case I915_TILING_NONE:
1246                 alignment = 64 * 1024;
1247                 break;
1248         case I915_TILING_X:
1249                 /* pin() will align the object as required by fence */
1250                 alignment = 0;
1251                 break;
1252         case I915_TILING_Y:
1253                 /* FIXME: Is this true? */
1254                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1255                 return -EINVAL;
1256         default:
1257                 BUG();
1258         }
1259
1260         ret = i915_gem_object_pin(obj, alignment);
1261         if (ret != 0)
1262                 return ret;
1263
1264         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1265          * fence, whereas 965+ only requires a fence if using
1266          * framebuffer compression.  For simplicity, we always install
1267          * a fence as the cost is not that onerous.
1268          */
1269         if (obj_priv->fence_reg == I915_FENCE_REG_NONE &&
1270             obj_priv->tiling_mode != I915_TILING_NONE) {
1271                 ret = i915_gem_object_get_fence_reg(obj);
1272                 if (ret != 0) {
1273                         i915_gem_object_unpin(obj);
1274                         return ret;
1275                 }
1276         }
1277
1278         return 0;
1279 }
1280
1281 static int
1282 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
1283                     struct drm_framebuffer *old_fb)
1284 {
1285         struct drm_device *dev = crtc->dev;
1286         struct drm_i915_private *dev_priv = dev->dev_private;
1287         struct drm_i915_master_private *master_priv;
1288         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1289         struct intel_framebuffer *intel_fb;
1290         struct drm_i915_gem_object *obj_priv;
1291         struct drm_gem_object *obj;
1292         int pipe = intel_crtc->pipe;
1293         int plane = intel_crtc->plane;
1294         unsigned long Start, Offset;
1295         int dspbase = (plane == 0 ? DSPAADDR : DSPBADDR);
1296         int dspsurf = (plane == 0 ? DSPASURF : DSPBSURF);
1297         int dspstride = (plane == 0) ? DSPASTRIDE : DSPBSTRIDE;
1298         int dsptileoff = (plane == 0 ? DSPATILEOFF : DSPBTILEOFF);
1299         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1300         u32 dspcntr;
1301         int ret;
1302
1303         /* no fb bound */
1304         if (!crtc->fb) {
1305                 DRM_DEBUG_KMS("No FB bound\n");
1306                 return 0;
1307         }
1308
1309         switch (plane) {
1310         case 0:
1311         case 1:
1312                 break;
1313         default:
1314                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1315                 return -EINVAL;
1316         }
1317
1318         intel_fb = to_intel_framebuffer(crtc->fb);
1319         obj = intel_fb->obj;
1320         obj_priv = obj->driver_private;
1321
1322         mutex_lock(&dev->struct_mutex);
1323         ret = intel_pin_and_fence_fb_obj(dev, obj);
1324         if (ret != 0) {
1325                 mutex_unlock(&dev->struct_mutex);
1326                 return ret;
1327         }
1328
1329         ret = i915_gem_object_set_to_display_plane(obj);
1330         if (ret != 0) {
1331                 i915_gem_object_unpin(obj);
1332                 mutex_unlock(&dev->struct_mutex);
1333                 return ret;
1334         }
1335
1336         dspcntr = I915_READ(dspcntr_reg);
1337         /* Mask out pixel format bits in case we change it */
1338         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
1339         switch (crtc->fb->bits_per_pixel) {
1340         case 8:
1341                 dspcntr |= DISPPLANE_8BPP;
1342                 break;
1343         case 16:
1344                 if (crtc->fb->depth == 15)
1345                         dspcntr |= DISPPLANE_15_16BPP;
1346                 else
1347                         dspcntr |= DISPPLANE_16BPP;
1348                 break;
1349         case 24:
1350         case 32:
1351                 if (crtc->fb->depth == 30)
1352                         dspcntr |= DISPPLANE_32BPP_30BIT_NO_ALPHA;
1353                 else
1354                         dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
1355                 break;
1356         default:
1357                 DRM_ERROR("Unknown color depth\n");
1358                 i915_gem_object_unpin(obj);
1359                 mutex_unlock(&dev->struct_mutex);
1360                 return -EINVAL;
1361         }
1362         if (IS_I965G(dev)) {
1363                 if (obj_priv->tiling_mode != I915_TILING_NONE)
1364                         dspcntr |= DISPPLANE_TILED;
1365                 else
1366                         dspcntr &= ~DISPPLANE_TILED;
1367         }
1368
1369         if (IS_IRONLAKE(dev))
1370                 /* must disable */
1371                 dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
1372
1373         I915_WRITE(dspcntr_reg, dspcntr);
1374
1375         Start = obj_priv->gtt_offset;
1376         Offset = y * crtc->fb->pitch + x * (crtc->fb->bits_per_pixel / 8);
1377
1378         DRM_DEBUG_KMS("Writing base %08lX %08lX %d %d\n", Start, Offset, x, y);
1379         I915_WRITE(dspstride, crtc->fb->pitch);
1380         if (IS_I965G(dev)) {
1381                 I915_WRITE(dspbase, Offset);
1382                 I915_READ(dspbase);
1383                 I915_WRITE(dspsurf, Start);
1384                 I915_READ(dspsurf);
1385                 I915_WRITE(dsptileoff, (y << 16) | x);
1386         } else {
1387                 I915_WRITE(dspbase, Start + Offset);
1388                 I915_READ(dspbase);
1389         }
1390
1391         if ((IS_I965G(dev) || plane == 0))
1392                 intel_update_fbc(crtc, &crtc->mode);
1393
1394         intel_wait_for_vblank(dev);
1395
1396         if (old_fb) {
1397                 intel_fb = to_intel_framebuffer(old_fb);
1398                 obj_priv = intel_fb->obj->driver_private;
1399                 i915_gem_object_unpin(intel_fb->obj);
1400         }
1401         intel_increase_pllclock(crtc, true);
1402
1403         mutex_unlock(&dev->struct_mutex);
1404
1405         if (!dev->primary->master)
1406                 return 0;
1407
1408         master_priv = dev->primary->master->driver_priv;
1409         if (!master_priv->sarea_priv)
1410                 return 0;
1411
1412         if (pipe) {
1413                 master_priv->sarea_priv->pipeB_x = x;
1414                 master_priv->sarea_priv->pipeB_y = y;
1415         } else {
1416                 master_priv->sarea_priv->pipeA_x = x;
1417                 master_priv->sarea_priv->pipeA_y = y;
1418         }
1419
1420         return 0;
1421 }
1422
1423 /* Disable the VGA plane that we never use */
1424 static void i915_disable_vga (struct drm_device *dev)
1425 {
1426         struct drm_i915_private *dev_priv = dev->dev_private;
1427         u8 sr1;
1428         u32 vga_reg;
1429
1430         if (IS_IRONLAKE(dev))
1431                 vga_reg = CPU_VGACNTRL;
1432         else
1433                 vga_reg = VGACNTRL;
1434
1435         if (I915_READ(vga_reg) & VGA_DISP_DISABLE)
1436                 return;
1437
1438         I915_WRITE8(VGA_SR_INDEX, 1);
1439         sr1 = I915_READ8(VGA_SR_DATA);
1440         I915_WRITE8(VGA_SR_DATA, sr1 | (1 << 5));
1441         udelay(100);
1442
1443         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
1444 }
1445
1446 static void ironlake_disable_pll_edp (struct drm_crtc *crtc)
1447 {
1448         struct drm_device *dev = crtc->dev;
1449         struct drm_i915_private *dev_priv = dev->dev_private;
1450         u32 dpa_ctl;
1451
1452         DRM_DEBUG_KMS("\n");
1453         dpa_ctl = I915_READ(DP_A);
1454         dpa_ctl &= ~DP_PLL_ENABLE;
1455         I915_WRITE(DP_A, dpa_ctl);
1456 }
1457
1458 static void ironlake_enable_pll_edp (struct drm_crtc *crtc)
1459 {
1460         struct drm_device *dev = crtc->dev;
1461         struct drm_i915_private *dev_priv = dev->dev_private;
1462         u32 dpa_ctl;
1463
1464         dpa_ctl = I915_READ(DP_A);
1465         dpa_ctl |= DP_PLL_ENABLE;
1466         I915_WRITE(DP_A, dpa_ctl);
1467         udelay(200);
1468 }
1469
1470
1471 static void ironlake_set_pll_edp (struct drm_crtc *crtc, int clock)
1472 {
1473         struct drm_device *dev = crtc->dev;
1474         struct drm_i915_private *dev_priv = dev->dev_private;
1475         u32 dpa_ctl;
1476
1477         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
1478         dpa_ctl = I915_READ(DP_A);
1479         dpa_ctl &= ~DP_PLL_FREQ_MASK;
1480
1481         if (clock < 200000) {
1482                 u32 temp;
1483                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
1484                 /* workaround for 160Mhz:
1485                    1) program 0x4600c bits 15:0 = 0x8124
1486                    2) program 0x46010 bit 0 = 1
1487                    3) program 0x46034 bit 24 = 1
1488                    4) program 0x64000 bit 14 = 1
1489                    */
1490                 temp = I915_READ(0x4600c);
1491                 temp &= 0xffff0000;
1492                 I915_WRITE(0x4600c, temp | 0x8124);
1493
1494                 temp = I915_READ(0x46010);
1495                 I915_WRITE(0x46010, temp | 1);
1496
1497                 temp = I915_READ(0x46034);
1498                 I915_WRITE(0x46034, temp | (1 << 24));
1499         } else {
1500                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
1501         }
1502         I915_WRITE(DP_A, dpa_ctl);
1503
1504         udelay(500);
1505 }
1506
1507 static void ironlake_crtc_dpms(struct drm_crtc *crtc, int mode)
1508 {
1509         struct drm_device *dev = crtc->dev;
1510         struct drm_i915_private *dev_priv = dev->dev_private;
1511         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1512         int pipe = intel_crtc->pipe;
1513         int plane = intel_crtc->plane;
1514         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
1515         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1516         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1517         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1518         int fdi_tx_reg = (pipe == 0) ? FDI_TXA_CTL : FDI_TXB_CTL;
1519         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
1520         int fdi_rx_iir_reg = (pipe == 0) ? FDI_RXA_IIR : FDI_RXB_IIR;
1521         int fdi_rx_imr_reg = (pipe == 0) ? FDI_RXA_IMR : FDI_RXB_IMR;
1522         int transconf_reg = (pipe == 0) ? TRANSACONF : TRANSBCONF;
1523         int pf_ctl_reg = (pipe == 0) ? PFA_CTL_1 : PFB_CTL_1;
1524         int pf_win_size = (pipe == 0) ? PFA_WIN_SZ : PFB_WIN_SZ;
1525         int pf_win_pos = (pipe == 0) ? PFA_WIN_POS : PFB_WIN_POS;
1526         int cpu_htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
1527         int cpu_hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
1528         int cpu_hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
1529         int cpu_vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
1530         int cpu_vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
1531         int cpu_vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
1532         int trans_htot_reg = (pipe == 0) ? TRANS_HTOTAL_A : TRANS_HTOTAL_B;
1533         int trans_hblank_reg = (pipe == 0) ? TRANS_HBLANK_A : TRANS_HBLANK_B;
1534         int trans_hsync_reg = (pipe == 0) ? TRANS_HSYNC_A : TRANS_HSYNC_B;
1535         int trans_vtot_reg = (pipe == 0) ? TRANS_VTOTAL_A : TRANS_VTOTAL_B;
1536         int trans_vblank_reg = (pipe == 0) ? TRANS_VBLANK_A : TRANS_VBLANK_B;
1537         int trans_vsync_reg = (pipe == 0) ? TRANS_VSYNC_A : TRANS_VSYNC_B;
1538         u32 temp;
1539         int tries = 5, j, n;
1540         u32 pipe_bpc;
1541
1542         temp = I915_READ(pipeconf_reg);
1543         pipe_bpc = temp & PIPE_BPC_MASK;
1544
1545         /* XXX: When our outputs are all unaware of DPMS modes other than off
1546          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1547          */
1548         switch (mode) {
1549         case DRM_MODE_DPMS_ON:
1550         case DRM_MODE_DPMS_STANDBY:
1551         case DRM_MODE_DPMS_SUSPEND:
1552                 DRM_DEBUG_KMS("crtc %d dpms on\n", pipe);
1553
1554                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1555                         temp = I915_READ(PCH_LVDS);
1556                         if ((temp & LVDS_PORT_EN) == 0) {
1557                                 I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
1558                                 POSTING_READ(PCH_LVDS);
1559                         }
1560                 }
1561
1562                 if (HAS_eDP) {
1563                         /* enable eDP PLL */
1564                         ironlake_enable_pll_edp(crtc);
1565                 } else {
1566                         /* enable PCH DPLL */
1567                         temp = I915_READ(pch_dpll_reg);
1568                         if ((temp & DPLL_VCO_ENABLE) == 0) {
1569                                 I915_WRITE(pch_dpll_reg, temp | DPLL_VCO_ENABLE);
1570                                 I915_READ(pch_dpll_reg);
1571                         }
1572
1573                         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
1574                         temp = I915_READ(fdi_rx_reg);
1575                         /*
1576                          * make the BPC in FDI Rx be consistent with that in
1577                          * pipeconf reg.
1578                          */
1579                         temp &= ~(0x7 << 16);
1580                         temp |= (pipe_bpc << 11);
1581                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE |
1582                                         FDI_SEL_PCDCLK |
1583                                         FDI_DP_PORT_WIDTH_X4); /* default 4 lanes */
1584                         I915_READ(fdi_rx_reg);
1585                         udelay(200);
1586
1587                         /* Enable CPU FDI TX PLL, always on for Ironlake */
1588                         temp = I915_READ(fdi_tx_reg);
1589                         if ((temp & FDI_TX_PLL_ENABLE) == 0) {
1590                                 I915_WRITE(fdi_tx_reg, temp | FDI_TX_PLL_ENABLE);
1591                                 I915_READ(fdi_tx_reg);
1592                                 udelay(100);
1593                         }
1594                 }
1595
1596                 /* Enable panel fitting for LVDS */
1597                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1598                         temp = I915_READ(pf_ctl_reg);
1599                         I915_WRITE(pf_ctl_reg, temp | PF_ENABLE | PF_FILTER_MED_3x3);
1600
1601                         /* currently full aspect */
1602                         I915_WRITE(pf_win_pos, 0);
1603
1604                         I915_WRITE(pf_win_size,
1605                                    (dev_priv->panel_fixed_mode->hdisplay << 16) |
1606                                    (dev_priv->panel_fixed_mode->vdisplay));
1607                 }
1608
1609                 /* Enable CPU pipe */
1610                 temp = I915_READ(pipeconf_reg);
1611                 if ((temp & PIPEACONF_ENABLE) == 0) {
1612                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1613                         I915_READ(pipeconf_reg);
1614                         udelay(100);
1615                 }
1616
1617                 /* configure and enable CPU plane */
1618                 temp = I915_READ(dspcntr_reg);
1619                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1620                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1621                         /* Flush the plane changes */
1622                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1623                 }
1624
1625                 if (!HAS_eDP) {
1626                         /* enable CPU FDI TX and PCH FDI RX */
1627                         temp = I915_READ(fdi_tx_reg);
1628                         temp |= FDI_TX_ENABLE;
1629                         temp |= FDI_DP_PORT_WIDTH_X4; /* default */
1630                         temp &= ~FDI_LINK_TRAIN_NONE;
1631                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1632                         I915_WRITE(fdi_tx_reg, temp);
1633                         I915_READ(fdi_tx_reg);
1634
1635                         temp = I915_READ(fdi_rx_reg);
1636                         temp &= ~FDI_LINK_TRAIN_NONE;
1637                         temp |= FDI_LINK_TRAIN_PATTERN_1;
1638                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_ENABLE);
1639                         I915_READ(fdi_rx_reg);
1640
1641                         udelay(150);
1642
1643                         /* Train FDI. */
1644                         /* umask FDI RX Interrupt symbol_lock and bit_lock bit
1645                            for train result */
1646                         temp = I915_READ(fdi_rx_imr_reg);
1647                         temp &= ~FDI_RX_SYMBOL_LOCK;
1648                         temp &= ~FDI_RX_BIT_LOCK;
1649                         I915_WRITE(fdi_rx_imr_reg, temp);
1650                         I915_READ(fdi_rx_imr_reg);
1651                         udelay(150);
1652
1653                         temp = I915_READ(fdi_rx_iir_reg);
1654                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1655
1656                         if ((temp & FDI_RX_BIT_LOCK) == 0) {
1657                                 for (j = 0; j < tries; j++) {
1658                                         temp = I915_READ(fdi_rx_iir_reg);
1659                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1660                                                                 temp);
1661                                         if (temp & FDI_RX_BIT_LOCK)
1662                                                 break;
1663                                         udelay(200);
1664                                 }
1665                                 if (j != tries)
1666                                         I915_WRITE(fdi_rx_iir_reg,
1667                                                         temp | FDI_RX_BIT_LOCK);
1668                                 else
1669                                         DRM_DEBUG_KMS("train 1 fail\n");
1670                         } else {
1671                                 I915_WRITE(fdi_rx_iir_reg,
1672                                                 temp | FDI_RX_BIT_LOCK);
1673                                 DRM_DEBUG_KMS("train 1 ok 2!\n");
1674                         }
1675                         temp = I915_READ(fdi_tx_reg);
1676                         temp &= ~FDI_LINK_TRAIN_NONE;
1677                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1678                         I915_WRITE(fdi_tx_reg, temp);
1679
1680                         temp = I915_READ(fdi_rx_reg);
1681                         temp &= ~FDI_LINK_TRAIN_NONE;
1682                         temp |= FDI_LINK_TRAIN_PATTERN_2;
1683                         I915_WRITE(fdi_rx_reg, temp);
1684
1685                         udelay(150);
1686
1687                         temp = I915_READ(fdi_rx_iir_reg);
1688                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
1689
1690                         if ((temp & FDI_RX_SYMBOL_LOCK) == 0) {
1691                                 for (j = 0; j < tries; j++) {
1692                                         temp = I915_READ(fdi_rx_iir_reg);
1693                                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n",
1694                                                                 temp);
1695                                         if (temp & FDI_RX_SYMBOL_LOCK)
1696                                                 break;
1697                                         udelay(200);
1698                                 }
1699                                 if (j != tries) {
1700                                         I915_WRITE(fdi_rx_iir_reg,
1701                                                         temp | FDI_RX_SYMBOL_LOCK);
1702                                         DRM_DEBUG_KMS("train 2 ok 1!\n");
1703                                 } else
1704                                         DRM_DEBUG_KMS("train 2 fail\n");
1705                         } else {
1706                                 I915_WRITE(fdi_rx_iir_reg,
1707                                                 temp | FDI_RX_SYMBOL_LOCK);
1708                                 DRM_DEBUG_KMS("train 2 ok 2!\n");
1709                         }
1710                         DRM_DEBUG_KMS("train done\n");
1711
1712                         /* set transcoder timing */
1713                         I915_WRITE(trans_htot_reg, I915_READ(cpu_htot_reg));
1714                         I915_WRITE(trans_hblank_reg, I915_READ(cpu_hblank_reg));
1715                         I915_WRITE(trans_hsync_reg, I915_READ(cpu_hsync_reg));
1716
1717                         I915_WRITE(trans_vtot_reg, I915_READ(cpu_vtot_reg));
1718                         I915_WRITE(trans_vblank_reg, I915_READ(cpu_vblank_reg));
1719                         I915_WRITE(trans_vsync_reg, I915_READ(cpu_vsync_reg));
1720
1721                         /* enable PCH transcoder */
1722                         temp = I915_READ(transconf_reg);
1723                         /*
1724                          * make the BPC in transcoder be consistent with
1725                          * that in pipeconf reg.
1726                          */
1727                         temp &= ~PIPE_BPC_MASK;
1728                         temp |= pipe_bpc;
1729                         I915_WRITE(transconf_reg, temp | TRANS_ENABLE);
1730                         I915_READ(transconf_reg);
1731
1732                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) == 0)
1733                                 ;
1734
1735                         /* enable normal */
1736
1737                         temp = I915_READ(fdi_tx_reg);
1738                         temp &= ~FDI_LINK_TRAIN_NONE;
1739                         I915_WRITE(fdi_tx_reg, temp | FDI_LINK_TRAIN_NONE |
1740                                         FDI_TX_ENHANCE_FRAME_ENABLE);
1741                         I915_READ(fdi_tx_reg);
1742
1743                         temp = I915_READ(fdi_rx_reg);
1744                         temp &= ~FDI_LINK_TRAIN_NONE;
1745                         I915_WRITE(fdi_rx_reg, temp | FDI_LINK_TRAIN_NONE |
1746                                         FDI_RX_ENHANCE_FRAME_ENABLE);
1747                         I915_READ(fdi_rx_reg);
1748
1749                         /* wait one idle pattern time */
1750                         udelay(100);
1751
1752                 }
1753
1754                 intel_crtc_load_lut(crtc);
1755
1756         break;
1757         case DRM_MODE_DPMS_OFF:
1758                 DRM_DEBUG_KMS("crtc %d dpms off\n", pipe);
1759
1760                 drm_vblank_off(dev, pipe);
1761                 /* Disable display plane */
1762                 temp = I915_READ(dspcntr_reg);
1763                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
1764                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
1765                         /* Flush the plane changes */
1766                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1767                         I915_READ(dspbase_reg);
1768                 }
1769
1770                 i915_disable_vga(dev);
1771
1772                 /* disable cpu pipe, disable after all planes disabled */
1773                 temp = I915_READ(pipeconf_reg);
1774                 if ((temp & PIPEACONF_ENABLE) != 0) {
1775                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
1776                         I915_READ(pipeconf_reg);
1777                         n = 0;
1778                         /* wait for cpu pipe off, pipe state */
1779                         while ((I915_READ(pipeconf_reg) & I965_PIPECONF_ACTIVE) != 0) {
1780                                 n++;
1781                                 if (n < 60) {
1782                                         udelay(500);
1783                                         continue;
1784                                 } else {
1785                                         DRM_DEBUG_KMS("pipe %d off delay\n",
1786                                                                 pipe);
1787                                         break;
1788                                 }
1789                         }
1790                 } else
1791                         DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
1792
1793                 udelay(100);
1794
1795                 /* Disable PF */
1796                 temp = I915_READ(pf_ctl_reg);
1797                 if ((temp & PF_ENABLE) != 0) {
1798                         I915_WRITE(pf_ctl_reg, temp & ~PF_ENABLE);
1799                         I915_READ(pf_ctl_reg);
1800                 }
1801                 I915_WRITE(pf_win_size, 0);
1802
1803                 /* disable CPU FDI tx and PCH FDI rx */
1804                 temp = I915_READ(fdi_tx_reg);
1805                 I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_ENABLE);
1806                 I915_READ(fdi_tx_reg);
1807
1808                 temp = I915_READ(fdi_rx_reg);
1809                 /* BPC in FDI rx is consistent with that in pipeconf */
1810                 temp &= ~(0x07 << 16);
1811                 temp |= (pipe_bpc << 11);
1812                 I915_WRITE(fdi_rx_reg, temp & ~FDI_RX_ENABLE);
1813                 I915_READ(fdi_rx_reg);
1814
1815                 udelay(100);
1816
1817                 /* still set train pattern 1 */
1818                 temp = I915_READ(fdi_tx_reg);
1819                 temp &= ~FDI_LINK_TRAIN_NONE;
1820                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1821                 I915_WRITE(fdi_tx_reg, temp);
1822
1823                 temp = I915_READ(fdi_rx_reg);
1824                 temp &= ~FDI_LINK_TRAIN_NONE;
1825                 temp |= FDI_LINK_TRAIN_PATTERN_1;
1826                 I915_WRITE(fdi_rx_reg, temp);
1827
1828                 udelay(100);
1829
1830                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
1831                         temp = I915_READ(PCH_LVDS);
1832                         I915_WRITE(PCH_LVDS, temp & ~LVDS_PORT_EN);
1833                         I915_READ(PCH_LVDS);
1834                         udelay(100);
1835                 }
1836
1837                 /* disable PCH transcoder */
1838                 temp = I915_READ(transconf_reg);
1839                 if ((temp & TRANS_ENABLE) != 0) {
1840                         I915_WRITE(transconf_reg, temp & ~TRANS_ENABLE);
1841                         I915_READ(transconf_reg);
1842                         n = 0;
1843                         /* wait for PCH transcoder off, transcoder state */
1844                         while ((I915_READ(transconf_reg) & TRANS_STATE_ENABLE) != 0) {
1845                                 n++;
1846                                 if (n < 60) {
1847                                         udelay(500);
1848                                         continue;
1849                                 } else {
1850                                         DRM_DEBUG_KMS("transcoder %d off "
1851                                                         "delay\n", pipe);
1852                                         break;
1853                                 }
1854                         }
1855                 }
1856                 temp = I915_READ(transconf_reg);
1857                 /* BPC in transcoder is consistent with that in pipeconf */
1858                 temp &= ~PIPE_BPC_MASK;
1859                 temp |= pipe_bpc;
1860                 I915_WRITE(transconf_reg, temp);
1861                 I915_READ(transconf_reg);
1862                 udelay(100);
1863
1864                 /* disable PCH DPLL */
1865                 temp = I915_READ(pch_dpll_reg);
1866                 if ((temp & DPLL_VCO_ENABLE) != 0) {
1867                         I915_WRITE(pch_dpll_reg, temp & ~DPLL_VCO_ENABLE);
1868                         I915_READ(pch_dpll_reg);
1869                 }
1870
1871                 if (HAS_eDP) {
1872                         ironlake_disable_pll_edp(crtc);
1873                 }
1874
1875                 temp = I915_READ(fdi_rx_reg);
1876                 temp &= ~FDI_SEL_PCDCLK;
1877                 I915_WRITE(fdi_rx_reg, temp);
1878                 I915_READ(fdi_rx_reg);
1879
1880                 temp = I915_READ(fdi_rx_reg);
1881                 temp &= ~FDI_RX_PLL_ENABLE;
1882                 I915_WRITE(fdi_rx_reg, temp);
1883                 I915_READ(fdi_rx_reg);
1884
1885                 /* Disable CPU FDI TX PLL */
1886                 temp = I915_READ(fdi_tx_reg);
1887                 if ((temp & FDI_TX_PLL_ENABLE) != 0) {
1888                         I915_WRITE(fdi_tx_reg, temp & ~FDI_TX_PLL_ENABLE);
1889                         I915_READ(fdi_tx_reg);
1890                         udelay(100);
1891                 }
1892
1893                 /* Wait for the clocks to turn off. */
1894                 udelay(100);
1895                 break;
1896         }
1897 }
1898
1899 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
1900 {
1901         struct intel_overlay *overlay;
1902         int ret;
1903
1904         if (!enable && intel_crtc->overlay) {
1905                 overlay = intel_crtc->overlay;
1906                 mutex_lock(&overlay->dev->struct_mutex);
1907                 for (;;) {
1908                         ret = intel_overlay_switch_off(overlay);
1909                         if (ret == 0)
1910                                 break;
1911
1912                         ret = intel_overlay_recover_from_interrupt(overlay, 0);
1913                         if (ret != 0) {
1914                                 /* overlay doesn't react anymore. Usually
1915                                  * results in a black screen and an unkillable
1916                                  * X server. */
1917                                 BUG();
1918                                 overlay->hw_wedged = HW_WEDGED;
1919                                 break;
1920                         }
1921                 }
1922                 mutex_unlock(&overlay->dev->struct_mutex);
1923         }
1924         /* Let userspace switch the overlay on again. In most cases userspace
1925          * has to recompute where to put it anyway. */
1926
1927         return;
1928 }
1929
1930 static void i9xx_crtc_dpms(struct drm_crtc *crtc, int mode)
1931 {
1932         struct drm_device *dev = crtc->dev;
1933         struct drm_i915_private *dev_priv = dev->dev_private;
1934         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1935         int pipe = intel_crtc->pipe;
1936         int plane = intel_crtc->plane;
1937         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
1938         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
1939         int dspbase_reg = (plane == 0) ? DSPAADDR : DSPBADDR;
1940         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
1941         u32 temp;
1942
1943         /* XXX: When our outputs are all unaware of DPMS modes other than off
1944          * and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
1945          */
1946         switch (mode) {
1947         case DRM_MODE_DPMS_ON:
1948         case DRM_MODE_DPMS_STANDBY:
1949         case DRM_MODE_DPMS_SUSPEND:
1950                 intel_update_watermarks(dev);
1951
1952                 /* Enable the DPLL */
1953                 temp = I915_READ(dpll_reg);
1954                 if ((temp & DPLL_VCO_ENABLE) == 0) {
1955                         I915_WRITE(dpll_reg, temp);
1956                         I915_READ(dpll_reg);
1957                         /* Wait for the clocks to stabilize. */
1958                         udelay(150);
1959                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1960                         I915_READ(dpll_reg);
1961                         /* Wait for the clocks to stabilize. */
1962                         udelay(150);
1963                         I915_WRITE(dpll_reg, temp | DPLL_VCO_ENABLE);
1964                         I915_READ(dpll_reg);
1965                         /* Wait for the clocks to stabilize. */
1966                         udelay(150);
1967                 }
1968
1969                 /* Enable the pipe */
1970                 temp = I915_READ(pipeconf_reg);
1971                 if ((temp & PIPEACONF_ENABLE) == 0)
1972                         I915_WRITE(pipeconf_reg, temp | PIPEACONF_ENABLE);
1973
1974                 /* Enable the plane */
1975                 temp = I915_READ(dspcntr_reg);
1976                 if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
1977                         I915_WRITE(dspcntr_reg, temp | DISPLAY_PLANE_ENABLE);
1978                         /* Flush the plane changes */
1979                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
1980                 }
1981
1982                 intel_crtc_load_lut(crtc);
1983
1984                 if ((IS_I965G(dev) || plane == 0))
1985                         intel_update_fbc(crtc, &crtc->mode);
1986
1987                 /* Give the overlay scaler a chance to enable if it's on this pipe */
1988                 intel_crtc_dpms_overlay(intel_crtc, true);
1989         break;
1990         case DRM_MODE_DPMS_OFF:
1991                 intel_update_watermarks(dev);
1992
1993                 /* Give the overlay scaler a chance to disable if it's on this pipe */
1994                 intel_crtc_dpms_overlay(intel_crtc, false);
1995                 drm_vblank_off(dev, pipe);
1996
1997                 if (dev_priv->cfb_plane == plane &&
1998                     dev_priv->display.disable_fbc)
1999                         dev_priv->display.disable_fbc(dev);
2000
2001                 /* Disable the VGA plane that we never use */
2002                 i915_disable_vga(dev);
2003
2004                 /* Disable display plane */
2005                 temp = I915_READ(dspcntr_reg);
2006                 if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
2007                         I915_WRITE(dspcntr_reg, temp & ~DISPLAY_PLANE_ENABLE);
2008                         /* Flush the plane changes */
2009                         I915_WRITE(dspbase_reg, I915_READ(dspbase_reg));
2010                         I915_READ(dspbase_reg);
2011                 }
2012
2013                 if (!IS_I9XX(dev)) {
2014                         /* Wait for vblank for the disable to take effect */
2015                         intel_wait_for_vblank(dev);
2016                 }
2017
2018                 /* Next, disable display pipes */
2019                 temp = I915_READ(pipeconf_reg);
2020                 if ((temp & PIPEACONF_ENABLE) != 0) {
2021                         I915_WRITE(pipeconf_reg, temp & ~PIPEACONF_ENABLE);
2022                         I915_READ(pipeconf_reg);
2023                 }
2024
2025                 /* Wait for vblank for the disable to take effect. */
2026                 intel_wait_for_vblank(dev);
2027
2028                 temp = I915_READ(dpll_reg);
2029                 if ((temp & DPLL_VCO_ENABLE) != 0) {
2030                         I915_WRITE(dpll_reg, temp & ~DPLL_VCO_ENABLE);
2031                         I915_READ(dpll_reg);
2032                 }
2033
2034                 /* Wait for the clocks to turn off. */
2035                 udelay(150);
2036                 break;
2037         }
2038 }
2039
2040 /**
2041  * Sets the power management mode of the pipe and plane.
2042  *
2043  * This code should probably grow support for turning the cursor off and back
2044  * on appropriately at the same time as we're turning the pipe off/on.
2045  */
2046 static void intel_crtc_dpms(struct drm_crtc *crtc, int mode)
2047 {
2048         struct drm_device *dev = crtc->dev;
2049         struct drm_i915_private *dev_priv = dev->dev_private;
2050         struct drm_i915_master_private *master_priv;
2051         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2052         int pipe = intel_crtc->pipe;
2053         bool enabled;
2054
2055         dev_priv->display.dpms(crtc, mode);
2056
2057         intel_crtc->dpms_mode = mode;
2058
2059         if (!dev->primary->master)
2060                 return;
2061
2062         master_priv = dev->primary->master->driver_priv;
2063         if (!master_priv->sarea_priv)
2064                 return;
2065
2066         enabled = crtc->enabled && mode != DRM_MODE_DPMS_OFF;
2067
2068         switch (pipe) {
2069         case 0:
2070                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
2071                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
2072                 break;
2073         case 1:
2074                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
2075                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
2076                 break;
2077         default:
2078                 DRM_ERROR("Can't update pipe %d in SAREA\n", pipe);
2079                 break;
2080         }
2081 }
2082
2083 static void intel_crtc_prepare (struct drm_crtc *crtc)
2084 {
2085         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2086         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
2087 }
2088
2089 static void intel_crtc_commit (struct drm_crtc *crtc)
2090 {
2091         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
2092         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
2093 }
2094
2095 void intel_encoder_prepare (struct drm_encoder *encoder)
2096 {
2097         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2098         /* lvds has its own version of prepare see intel_lvds_prepare */
2099         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
2100 }
2101
2102 void intel_encoder_commit (struct drm_encoder *encoder)
2103 {
2104         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
2105         /* lvds has its own version of commit see intel_lvds_commit */
2106         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
2107 }
2108
2109 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
2110                                   struct drm_display_mode *mode,
2111                                   struct drm_display_mode *adjusted_mode)
2112 {
2113         struct drm_device *dev = crtc->dev;
2114         if (IS_IRONLAKE(dev)) {
2115                 /* FDI link clock is fixed at 2.7G */
2116                 if (mode->clock * 3 > 27000 * 4)
2117                         return MODE_CLOCK_HIGH;
2118         }
2119         return true;
2120 }
2121
2122 static int i945_get_display_clock_speed(struct drm_device *dev)
2123 {
2124         return 400000;
2125 }
2126
2127 static int i915_get_display_clock_speed(struct drm_device *dev)
2128 {
2129         return 333000;
2130 }
2131
2132 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
2133 {
2134         return 200000;
2135 }
2136
2137 static int i915gm_get_display_clock_speed(struct drm_device *dev)
2138 {
2139         u16 gcfgc = 0;
2140
2141         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
2142
2143         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
2144                 return 133000;
2145         else {
2146                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
2147                 case GC_DISPLAY_CLOCK_333_MHZ:
2148                         return 333000;
2149                 default:
2150                 case GC_DISPLAY_CLOCK_190_200_MHZ:
2151                         return 190000;
2152                 }
2153         }
2154 }
2155
2156 static int i865_get_display_clock_speed(struct drm_device *dev)
2157 {
2158         return 266000;
2159 }
2160
2161 static int i855_get_display_clock_speed(struct drm_device *dev)
2162 {
2163         u16 hpllcc = 0;
2164         /* Assume that the hardware is in the high speed state.  This
2165          * should be the default.
2166          */
2167         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
2168         case GC_CLOCK_133_200:
2169         case GC_CLOCK_100_200:
2170                 return 200000;
2171         case GC_CLOCK_166_250:
2172                 return 250000;
2173         case GC_CLOCK_100_133:
2174                 return 133000;
2175         }
2176
2177         /* Shouldn't happen */
2178         return 0;
2179 }
2180
2181 static int i830_get_display_clock_speed(struct drm_device *dev)
2182 {
2183         return 133000;
2184 }
2185
2186 /**
2187  * Return the pipe currently connected to the panel fitter,
2188  * or -1 if the panel fitter is not present or not in use
2189  */
2190 int intel_panel_fitter_pipe (struct drm_device *dev)
2191 {
2192         struct drm_i915_private *dev_priv = dev->dev_private;
2193         u32  pfit_control;
2194
2195         /* i830 doesn't have a panel fitter */
2196         if (IS_I830(dev))
2197                 return -1;
2198
2199         pfit_control = I915_READ(PFIT_CONTROL);
2200
2201         /* See if the panel fitter is in use */
2202         if ((pfit_control & PFIT_ENABLE) == 0)
2203                 return -1;
2204
2205         /* 965 can place panel fitter on either pipe */
2206         if (IS_I965G(dev))
2207                 return (pfit_control >> 29) & 0x3;
2208
2209         /* older chips can only use pipe 1 */
2210         return 1;
2211 }
2212
2213 struct fdi_m_n {
2214         u32        tu;
2215         u32        gmch_m;
2216         u32        gmch_n;
2217         u32        link_m;
2218         u32        link_n;
2219 };
2220
2221 static void
2222 fdi_reduce_ratio(u32 *num, u32 *den)
2223 {
2224         while (*num > 0xffffff || *den > 0xffffff) {
2225                 *num >>= 1;
2226                 *den >>= 1;
2227         }
2228 }
2229
2230 #define DATA_N 0x800000
2231 #define LINK_N 0x80000
2232
2233 static void
2234 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
2235                      int link_clock, struct fdi_m_n *m_n)
2236 {
2237         u64 temp;
2238
2239         m_n->tu = 64; /* default size */
2240
2241         temp = (u64) DATA_N * pixel_clock;
2242         temp = div_u64(temp, link_clock);
2243         m_n->gmch_m = div_u64(temp * bits_per_pixel, nlanes);
2244         m_n->gmch_m >>= 3; /* convert to bytes_per_pixel */
2245         m_n->gmch_n = DATA_N;
2246         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
2247
2248         temp = (u64) LINK_N * pixel_clock;
2249         m_n->link_m = div_u64(temp, link_clock);
2250         m_n->link_n = LINK_N;
2251         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
2252 }
2253
2254
2255 struct intel_watermark_params {
2256         unsigned long fifo_size;
2257         unsigned long max_wm;
2258         unsigned long default_wm;
2259         unsigned long guard_size;
2260         unsigned long cacheline_size;
2261 };
2262
2263 /* Pineview has different values for various configs */
2264 static struct intel_watermark_params pineview_display_wm = {
2265         PINEVIEW_DISPLAY_FIFO,
2266         PINEVIEW_MAX_WM,
2267         PINEVIEW_DFT_WM,
2268         PINEVIEW_GUARD_WM,
2269         PINEVIEW_FIFO_LINE_SIZE
2270 };
2271 static struct intel_watermark_params pineview_display_hplloff_wm = {
2272         PINEVIEW_DISPLAY_FIFO,
2273         PINEVIEW_MAX_WM,
2274         PINEVIEW_DFT_HPLLOFF_WM,
2275         PINEVIEW_GUARD_WM,
2276         PINEVIEW_FIFO_LINE_SIZE
2277 };
2278 static struct intel_watermark_params pineview_cursor_wm = {
2279         PINEVIEW_CURSOR_FIFO,
2280         PINEVIEW_CURSOR_MAX_WM,
2281         PINEVIEW_CURSOR_DFT_WM,
2282         PINEVIEW_CURSOR_GUARD_WM,
2283         PINEVIEW_FIFO_LINE_SIZE,
2284 };
2285 static struct intel_watermark_params pineview_cursor_hplloff_wm = {
2286         PINEVIEW_CURSOR_FIFO,
2287         PINEVIEW_CURSOR_MAX_WM,
2288         PINEVIEW_CURSOR_DFT_WM,
2289         PINEVIEW_CURSOR_GUARD_WM,
2290         PINEVIEW_FIFO_LINE_SIZE
2291 };
2292 static struct intel_watermark_params g4x_wm_info = {
2293         G4X_FIFO_SIZE,
2294         G4X_MAX_WM,
2295         G4X_MAX_WM,
2296         2,
2297         G4X_FIFO_LINE_SIZE,
2298 };
2299 static struct intel_watermark_params i945_wm_info = {
2300         I945_FIFO_SIZE,
2301         I915_MAX_WM,
2302         1,
2303         2,
2304         I915_FIFO_LINE_SIZE
2305 };
2306 static struct intel_watermark_params i915_wm_info = {
2307         I915_FIFO_SIZE,
2308         I915_MAX_WM,
2309         1,
2310         2,
2311         I915_FIFO_LINE_SIZE
2312 };
2313 static struct intel_watermark_params i855_wm_info = {
2314         I855GM_FIFO_SIZE,
2315         I915_MAX_WM,
2316         1,
2317         2,
2318         I830_FIFO_LINE_SIZE
2319 };
2320 static struct intel_watermark_params i830_wm_info = {
2321         I830_FIFO_SIZE,
2322         I915_MAX_WM,
2323         1,
2324         2,
2325         I830_FIFO_LINE_SIZE
2326 };
2327
2328 /**
2329  * intel_calculate_wm - calculate watermark level
2330  * @clock_in_khz: pixel clock
2331  * @wm: chip FIFO params
2332  * @pixel_size: display pixel size
2333  * @latency_ns: memory latency for the platform
2334  *
2335  * Calculate the watermark level (the level at which the display plane will
2336  * start fetching from memory again).  Each chip has a different display
2337  * FIFO size and allocation, so the caller needs to figure that out and pass
2338  * in the correct intel_watermark_params structure.
2339  *
2340  * As the pixel clock runs, the FIFO will be drained at a rate that depends
2341  * on the pixel size.  When it reaches the watermark level, it'll start
2342  * fetching FIFO line sized based chunks from memory until the FIFO fills
2343  * past the watermark point.  If the FIFO drains completely, a FIFO underrun
2344  * will occur, and a display engine hang could result.
2345  */
2346 static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
2347                                         struct intel_watermark_params *wm,
2348                                         int pixel_size,
2349                                         unsigned long latency_ns)
2350 {
2351         long entries_required, wm_size;
2352
2353         /*
2354          * Note: we need to make sure we don't overflow for various clock &
2355          * latency values.
2356          * clocks go from a few thousand to several hundred thousand.
2357          * latency is usually a few thousand
2358          */
2359         entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
2360                 1000;
2361         entries_required /= wm->cacheline_size;
2362
2363         DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries_required);
2364
2365         wm_size = wm->fifo_size - (entries_required + wm->guard_size);
2366
2367         DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size);
2368
2369         /* Don't promote wm_size to unsigned... */
2370         if (wm_size > (long)wm->max_wm)
2371                 wm_size = wm->max_wm;
2372         if (wm_size <= 0)
2373                 wm_size = wm->default_wm;
2374         return wm_size;
2375 }
2376
2377 struct cxsr_latency {
2378         int is_desktop;
2379         unsigned long fsb_freq;
2380         unsigned long mem_freq;
2381         unsigned long display_sr;
2382         unsigned long display_hpll_disable;
2383         unsigned long cursor_sr;
2384         unsigned long cursor_hpll_disable;
2385 };
2386
2387 static struct cxsr_latency cxsr_latency_table[] = {
2388         {1, 800, 400, 3382, 33382, 3983, 33983},    /* DDR2-400 SC */
2389         {1, 800, 667, 3354, 33354, 3807, 33807},    /* DDR2-667 SC */
2390         {1, 800, 800, 3347, 33347, 3763, 33763},    /* DDR2-800 SC */
2391
2392         {1, 667, 400, 3400, 33400, 4021, 34021},    /* DDR2-400 SC */
2393         {1, 667, 667, 3372, 33372, 3845, 33845},    /* DDR2-667 SC */
2394         {1, 667, 800, 3386, 33386, 3822, 33822},    /* DDR2-800 SC */
2395
2396         {1, 400, 400, 3472, 33472, 4173, 34173},    /* DDR2-400 SC */
2397         {1, 400, 667, 3443, 33443, 3996, 33996},    /* DDR2-667 SC */
2398         {1, 400, 800, 3430, 33430, 3946, 33946},    /* DDR2-800 SC */
2399
2400         {0, 800, 400, 3438, 33438, 4065, 34065},    /* DDR2-400 SC */
2401         {0, 800, 667, 3410, 33410, 3889, 33889},    /* DDR2-667 SC */
2402         {0, 800, 800, 3403, 33403, 3845, 33845},    /* DDR2-800 SC */
2403
2404         {0, 667, 400, 3456, 33456, 4103, 34106},    /* DDR2-400 SC */
2405         {0, 667, 667, 3428, 33428, 3927, 33927},    /* DDR2-667 SC */
2406         {0, 667, 800, 3443, 33443, 3905, 33905},    /* DDR2-800 SC */
2407
2408         {0, 400, 400, 3528, 33528, 4255, 34255},    /* DDR2-400 SC */
2409         {0, 400, 667, 3500, 33500, 4079, 34079},    /* DDR2-667 SC */
2410         {0, 400, 800, 3487, 33487, 4029, 34029},    /* DDR2-800 SC */
2411 };
2412
2413 static struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, int fsb,
2414                                                    int mem)
2415 {
2416         int i;
2417         struct cxsr_latency *latency;
2418
2419         if (fsb == 0 || mem == 0)
2420                 return NULL;
2421
2422         for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
2423                 latency = &cxsr_latency_table[i];
2424                 if (is_desktop == latency->is_desktop &&
2425                     fsb == latency->fsb_freq && mem == latency->mem_freq)
2426                         return latency;
2427         }
2428
2429         DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2430
2431         return NULL;
2432 }
2433
2434 static void pineview_disable_cxsr(struct drm_device *dev)
2435 {
2436         struct drm_i915_private *dev_priv = dev->dev_private;
2437         u32 reg;
2438
2439         /* deactivate cxsr */
2440         reg = I915_READ(DSPFW3);
2441         reg &= ~(PINEVIEW_SELF_REFRESH_EN);
2442         I915_WRITE(DSPFW3, reg);
2443         DRM_INFO("Big FIFO is disabled\n");
2444 }
2445
2446 static void pineview_enable_cxsr(struct drm_device *dev, unsigned long clock,
2447                                  int pixel_size)
2448 {
2449         struct drm_i915_private *dev_priv = dev->dev_private;
2450         u32 reg;
2451         unsigned long wm;
2452         struct cxsr_latency *latency;
2453
2454         latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->fsb_freq,
2455                 dev_priv->mem_freq);
2456         if (!latency) {
2457                 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
2458                 pineview_disable_cxsr(dev);
2459                 return;
2460         }
2461
2462         /* Display SR */
2463         wm = intel_calculate_wm(clock, &pineview_display_wm, pixel_size,
2464                                 latency->display_sr);
2465         reg = I915_READ(DSPFW1);
2466         reg &= 0x7fffff;
2467         reg |= wm << 23;
2468         I915_WRITE(DSPFW1, reg);
2469         DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
2470
2471         /* cursor SR */
2472         wm = intel_calculate_wm(clock, &pineview_cursor_wm, pixel_size,
2473                                 latency->cursor_sr);
2474         reg = I915_READ(DSPFW3);
2475         reg &= ~(0x3f << 24);
2476         reg |= (wm & 0x3f) << 24;
2477         I915_WRITE(DSPFW3, reg);
2478
2479         /* Display HPLL off SR */
2480         wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
2481                 latency->display_hpll_disable, I915_FIFO_LINE_SIZE);
2482         reg = I915_READ(DSPFW3);
2483         reg &= 0xfffffe00;
2484         reg |= wm & 0x1ff;
2485         I915_WRITE(DSPFW3, reg);
2486
2487         /* cursor HPLL off SR */
2488         wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, pixel_size,
2489                                 latency->cursor_hpll_disable);
2490         reg = I915_READ(DSPFW3);
2491         reg &= ~(0x3f << 16);
2492         reg |= (wm & 0x3f) << 16;
2493         I915_WRITE(DSPFW3, reg);
2494         DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
2495
2496         /* activate cxsr */
2497         reg = I915_READ(DSPFW3);
2498         reg |= PINEVIEW_SELF_REFRESH_EN;
2499         I915_WRITE(DSPFW3, reg);
2500
2501         DRM_INFO("Big FIFO is enabled\n");
2502
2503         return;
2504 }
2505
2506 /*
2507  * Latency for FIFO fetches is dependent on several factors:
2508  *   - memory configuration (speed, channels)
2509  *   - chipset
2510  *   - current MCH state
2511  * It can be fairly high in some situations, so here we assume a fairly
2512  * pessimal value.  It's a tradeoff between extra memory fetches (if we
2513  * set this value too high, the FIFO will fetch frequently to stay full)
2514  * and power consumption (set it too low to save power and we might see
2515  * FIFO underruns and display "flicker").
2516  *
2517  * A value of 5us seems to be a good balance; safe for very low end
2518  * platforms but not overly aggressive on lower latency configs.
2519  */
2520 static const int latency_ns = 5000;
2521
2522 static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
2523 {
2524         struct drm_i915_private *dev_priv = dev->dev_private;
2525         uint32_t dsparb = I915_READ(DSPARB);
2526         int size;
2527
2528         if (plane == 0)
2529                 size = dsparb & 0x7f;
2530         else
2531                 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) -
2532                         (dsparb & 0x7f);
2533
2534         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2535                         plane ? "B" : "A", size);
2536
2537         return size;
2538 }
2539
2540 static int i85x_get_fifo_size(struct drm_device *dev, int plane)
2541 {
2542         struct drm_i915_private *dev_priv = dev->dev_private;
2543         uint32_t dsparb = I915_READ(DSPARB);
2544         int size;
2545
2546         if (plane == 0)
2547                 size = dsparb & 0x1ff;
2548         else
2549                 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) -
2550                         (dsparb & 0x1ff);
2551         size >>= 1; /* Convert to cachelines */
2552
2553         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2554                         plane ? "B" : "A", size);
2555
2556         return size;
2557 }
2558
2559 static int i845_get_fifo_size(struct drm_device *dev, int plane)
2560 {
2561         struct drm_i915_private *dev_priv = dev->dev_private;
2562         uint32_t dsparb = I915_READ(DSPARB);
2563         int size;
2564
2565         size = dsparb & 0x7f;
2566         size >>= 2; /* Convert to cachelines */
2567
2568         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2569                         plane ? "B" : "A",
2570                   size);
2571
2572         return size;
2573 }
2574
2575 static int i830_get_fifo_size(struct drm_device *dev, int plane)
2576 {
2577         struct drm_i915_private *dev_priv = dev->dev_private;
2578         uint32_t dsparb = I915_READ(DSPARB);
2579         int size;
2580
2581         size = dsparb & 0x7f;
2582         size >>= 1; /* Convert to cachelines */
2583
2584         DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
2585                         plane ? "B" : "A", size);
2586
2587         return size;
2588 }
2589
2590 static void g4x_update_wm(struct drm_device *dev,  int planea_clock,
2591                           int planeb_clock, int sr_hdisplay, int pixel_size)
2592 {
2593         struct drm_i915_private *dev_priv = dev->dev_private;
2594         int total_size, cacheline_size;
2595         int planea_wm, planeb_wm, cursora_wm, cursorb_wm, cursor_sr;
2596         struct intel_watermark_params planea_params, planeb_params;
2597         unsigned long line_time_us;
2598         int sr_clock, sr_entries = 0, entries_required;
2599
2600         /* Create copies of the base settings for each pipe */
2601         planea_params = planeb_params = g4x_wm_info;
2602
2603         /* Grab a couple of global values before we overwrite them */
2604         total_size = planea_params.fifo_size;
2605         cacheline_size = planea_params.cacheline_size;
2606
2607         /*
2608          * Note: we need to make sure we don't overflow for various clock &
2609          * latency values.
2610          * clocks go from a few thousand to several hundred thousand.
2611          * latency is usually a few thousand
2612          */
2613         entries_required = ((planea_clock / 1000) * pixel_size * latency_ns) /
2614                 1000;
2615         entries_required /= G4X_FIFO_LINE_SIZE;
2616         planea_wm = entries_required + planea_params.guard_size;
2617
2618         entries_required = ((planeb_clock / 1000) * pixel_size * latency_ns) /
2619                 1000;
2620         entries_required /= G4X_FIFO_LINE_SIZE;
2621         planeb_wm = entries_required + planeb_params.guard_size;
2622
2623         cursora_wm = cursorb_wm = 16;
2624         cursor_sr = 32;
2625
2626         DRM_DEBUG("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2627
2628         /* Calc sr entries for one plane configs */
2629         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2630                 /* self-refresh has much higher latency */
2631                 static const int sr_latency_ns = 12000;
2632
2633                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2634                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2635
2636                 /* Use ns/us then divide to preserve precision */
2637                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2638                               pixel_size * sr_hdisplay) / 1000;
2639                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2640                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2641                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2642         } else {
2643                 /* Turn off self refresh if both pipes are enabled */
2644                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2645                                         & ~FW_BLC_SELF_EN);
2646         }
2647
2648         DRM_DEBUG("Setting FIFO watermarks - A: %d, B: %d, SR %d\n",
2649                   planea_wm, planeb_wm, sr_entries);
2650
2651         planea_wm &= 0x3f;
2652         planeb_wm &= 0x3f;
2653
2654         I915_WRITE(DSPFW1, (sr_entries << DSPFW_SR_SHIFT) |
2655                    (cursorb_wm << DSPFW_CURSORB_SHIFT) |
2656                    (planeb_wm << DSPFW_PLANEB_SHIFT) | planea_wm);
2657         I915_WRITE(DSPFW2, (I915_READ(DSPFW2) & DSPFW_CURSORA_MASK) |
2658                    (cursora_wm << DSPFW_CURSORA_SHIFT));
2659         /* HPLL off in SR has some issues on G4x... disable it */
2660         I915_WRITE(DSPFW3, (I915_READ(DSPFW3) & ~DSPFW_HPLL_SR_EN) |
2661                    (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
2662 }
2663
2664 static void i965_update_wm(struct drm_device *dev, int planea_clock,
2665                            int planeb_clock, int sr_hdisplay, int pixel_size)
2666 {
2667         struct drm_i915_private *dev_priv = dev->dev_private;
2668         unsigned long line_time_us;
2669         int sr_clock, sr_entries, srwm = 1;
2670
2671         /* Calc sr entries for one plane configs */
2672         if (sr_hdisplay && (!planea_clock || !planeb_clock)) {
2673                 /* self-refresh has much higher latency */
2674                 static const int sr_latency_ns = 12000;
2675
2676                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2677                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2678
2679                 /* Use ns/us then divide to preserve precision */
2680                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2681                               pixel_size * sr_hdisplay) / 1000;
2682                 sr_entries = roundup(sr_entries / I915_FIFO_LINE_SIZE, 1);
2683                 DRM_DEBUG("self-refresh entries: %d\n", sr_entries);
2684                 srwm = I945_FIFO_SIZE - sr_entries;
2685                 if (srwm < 0)
2686                         srwm = 1;
2687                 srwm &= 0x3f;
2688                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
2689         } else {
2690                 /* Turn off self refresh if both pipes are enabled */
2691                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2692                                         & ~FW_BLC_SELF_EN);
2693         }
2694
2695         DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
2696                       srwm);
2697
2698         /* 965 has limitations... */
2699         I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | (8 << 16) | (8 << 8) |
2700                    (8 << 0));
2701         I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
2702 }
2703
2704 static void i9xx_update_wm(struct drm_device *dev, int planea_clock,
2705                            int planeb_clock, int sr_hdisplay, int pixel_size)
2706 {
2707         struct drm_i915_private *dev_priv = dev->dev_private;
2708         uint32_t fwater_lo;
2709         uint32_t fwater_hi;
2710         int total_size, cacheline_size, cwm, srwm = 1;
2711         int planea_wm, planeb_wm;
2712         struct intel_watermark_params planea_params, planeb_params;
2713         unsigned long line_time_us;
2714         int sr_clock, sr_entries = 0;
2715
2716         /* Create copies of the base settings for each pipe */
2717         if (IS_I965GM(dev) || IS_I945GM(dev))
2718                 planea_params = planeb_params = i945_wm_info;
2719         else if (IS_I9XX(dev))
2720                 planea_params = planeb_params = i915_wm_info;
2721         else
2722                 planea_params = planeb_params = i855_wm_info;
2723
2724         /* Grab a couple of global values before we overwrite them */
2725         total_size = planea_params.fifo_size;
2726         cacheline_size = planea_params.cacheline_size;
2727
2728         /* Update per-plane FIFO sizes */
2729         planea_params.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2730         planeb_params.fifo_size = dev_priv->display.get_fifo_size(dev, 1);
2731
2732         planea_wm = intel_calculate_wm(planea_clock, &planea_params,
2733                                        pixel_size, latency_ns);
2734         planeb_wm = intel_calculate_wm(planeb_clock, &planeb_params,
2735                                        pixel_size, latency_ns);
2736         DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
2737
2738         /*
2739          * Overlay gets an aggressive default since video jitter is bad.
2740          */
2741         cwm = 2;
2742
2743         /* Calc sr entries for one plane configs */
2744         if (HAS_FW_BLC(dev) && sr_hdisplay &&
2745             (!planea_clock || !planeb_clock)) {
2746                 /* self-refresh has much higher latency */
2747                 static const int sr_latency_ns = 6000;
2748
2749                 sr_clock = planea_clock ? planea_clock : planeb_clock;
2750                 line_time_us = ((sr_hdisplay * 1000) / sr_clock);
2751
2752                 /* Use ns/us then divide to preserve precision */
2753                 sr_entries = (((sr_latency_ns / line_time_us) + 1) *
2754                               pixel_size * sr_hdisplay) / 1000;
2755                 sr_entries = roundup(sr_entries / cacheline_size, 1);
2756                 DRM_DEBUG_KMS("self-refresh entries: %d\n", sr_entries);
2757                 srwm = total_size - sr_entries;
2758                 if (srwm < 0)
2759                         srwm = 1;
2760                 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN | (srwm & 0x3f));
2761         } else {
2762                 /* Turn off self refresh if both pipes are enabled */
2763                 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
2764                                         & ~FW_BLC_SELF_EN);
2765         }
2766
2767         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
2768                   planea_wm, planeb_wm, cwm, srwm);
2769
2770         fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
2771         fwater_hi = (cwm & 0x1f);
2772
2773         /* Set request length to 8 cachelines per fetch */
2774         fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
2775         fwater_hi = fwater_hi | (1 << 8);
2776
2777         I915_WRITE(FW_BLC, fwater_lo);
2778         I915_WRITE(FW_BLC2, fwater_hi);
2779 }
2780
2781 static void i830_update_wm(struct drm_device *dev, int planea_clock, int unused,
2782                            int unused2, int pixel_size)
2783 {
2784         struct drm_i915_private *dev_priv = dev->dev_private;
2785         uint32_t fwater_lo = I915_READ(FW_BLC) & ~0xfff;
2786         int planea_wm;
2787
2788         i830_wm_info.fifo_size = dev_priv->display.get_fifo_size(dev, 0);
2789
2790         planea_wm = intel_calculate_wm(planea_clock, &i830_wm_info,
2791                                        pixel_size, latency_ns);
2792         fwater_lo |= (3<<8) | planea_wm;
2793
2794         DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
2795
2796         I915_WRITE(FW_BLC, fwater_lo);
2797 }
2798
2799 /**
2800  * intel_update_watermarks - update FIFO watermark values based on current modes
2801  *
2802  * Calculate watermark values for the various WM regs based on current mode
2803  * and plane configuration.
2804  *
2805  * There are several cases to deal with here:
2806  *   - normal (i.e. non-self-refresh)
2807  *   - self-refresh (SR) mode
2808  *   - lines are large relative to FIFO size (buffer can hold up to 2)
2809  *   - lines are small relative to FIFO size (buffer can hold more than 2
2810  *     lines), so need to account for TLB latency
2811  *
2812  *   The normal calculation is:
2813  *     watermark = dotclock * bytes per pixel * latency
2814  *   where latency is platform & configuration dependent (we assume pessimal
2815  *   values here).
2816  *
2817  *   The SR calculation is:
2818  *     watermark = (trunc(latency/line time)+1) * surface width *
2819  *       bytes per pixel
2820  *   where
2821  *     line time = htotal / dotclock
2822  *   and latency is assumed to be high, as above.
2823  *
2824  * The final value programmed to the register should always be rounded up,
2825  * and include an extra 2 entries to account for clock crossings.
2826  *
2827  * We don't use the sprite, so we can ignore that.  And on Crestline we have
2828  * to set the non-SR watermarks to 8.
2829   */
2830 static void intel_update_watermarks(struct drm_device *dev)
2831 {
2832         struct drm_i915_private *dev_priv = dev->dev_private;
2833         struct drm_crtc *crtc;
2834         struct intel_crtc *intel_crtc;
2835         int sr_hdisplay = 0;
2836         unsigned long planea_clock = 0, planeb_clock = 0, sr_clock = 0;
2837         int enabled = 0, pixel_size = 0;
2838
2839         if (!dev_priv->display.update_wm)
2840                 return;
2841
2842         /* Get the clock config from both planes */
2843         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2844                 intel_crtc = to_intel_crtc(crtc);
2845                 if (crtc->enabled) {
2846                         enabled++;
2847                         if (intel_crtc->plane == 0) {
2848                                 DRM_DEBUG_KMS("plane A (pipe %d) clock: %d\n",
2849                                           intel_crtc->pipe, crtc->mode.clock);
2850                                 planea_clock = crtc->mode.clock;
2851                         } else {
2852                                 DRM_DEBUG_KMS("plane B (pipe %d) clock: %d\n",
2853                                           intel_crtc->pipe, crtc->mode.clock);
2854                                 planeb_clock = crtc->mode.clock;
2855                         }
2856                         sr_hdisplay = crtc->mode.hdisplay;
2857                         sr_clock = crtc->mode.clock;
2858                         if (crtc->fb)
2859                                 pixel_size = crtc->fb->bits_per_pixel / 8;
2860                         else
2861                                 pixel_size = 4; /* by default */
2862                 }
2863         }
2864
2865         if (enabled <= 0)
2866                 return;
2867
2868         /* Single plane configs can enable self refresh */
2869         if (enabled == 1 && IS_PINEVIEW(dev))
2870                 pineview_enable_cxsr(dev, sr_clock, pixel_size);
2871         else if (IS_PINEVIEW(dev))
2872                 pineview_disable_cxsr(dev);
2873
2874         dev_priv->display.update_wm(dev, planea_clock, planeb_clock,
2875                                     sr_hdisplay, pixel_size);
2876 }
2877
2878 static int intel_crtc_mode_set(struct drm_crtc *crtc,
2879                                struct drm_display_mode *mode,
2880                                struct drm_display_mode *adjusted_mode,
2881                                int x, int y,
2882                                struct drm_framebuffer *old_fb)
2883 {
2884         struct drm_device *dev = crtc->dev;
2885         struct drm_i915_private *dev_priv = dev->dev_private;
2886         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2887         int pipe = intel_crtc->pipe;
2888         int plane = intel_crtc->plane;
2889         int fp_reg = (pipe == 0) ? FPA0 : FPB0;
2890         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
2891         int dpll_md_reg = (intel_crtc->pipe == 0) ? DPLL_A_MD : DPLL_B_MD;
2892         int dspcntr_reg = (plane == 0) ? DSPACNTR : DSPBCNTR;
2893         int pipeconf_reg = (pipe == 0) ? PIPEACONF : PIPEBCONF;
2894         int htot_reg = (pipe == 0) ? HTOTAL_A : HTOTAL_B;
2895         int hblank_reg = (pipe == 0) ? HBLANK_A : HBLANK_B;
2896         int hsync_reg = (pipe == 0) ? HSYNC_A : HSYNC_B;
2897         int vtot_reg = (pipe == 0) ? VTOTAL_A : VTOTAL_B;
2898         int vblank_reg = (pipe == 0) ? VBLANK_A : VBLANK_B;
2899         int vsync_reg = (pipe == 0) ? VSYNC_A : VSYNC_B;
2900         int dspsize_reg = (plane == 0) ? DSPASIZE : DSPBSIZE;
2901         int dsppos_reg = (plane == 0) ? DSPAPOS : DSPBPOS;
2902         int pipesrc_reg = (pipe == 0) ? PIPEASRC : PIPEBSRC;
2903         int refclk, num_outputs = 0;
2904         intel_clock_t clock, reduced_clock;
2905         u32 dpll = 0, fp = 0, fp2 = 0, dspcntr, pipeconf;
2906         bool ok, has_reduced_clock = false, is_sdvo = false, is_dvo = false;
2907         bool is_crt = false, is_lvds = false, is_tv = false, is_dp = false;
2908         bool is_edp = false;
2909         struct drm_mode_config *mode_config = &dev->mode_config;
2910         struct drm_connector *connector;
2911         const intel_limit_t *limit;
2912         int ret;
2913         struct fdi_m_n m_n = {0};
2914         int data_m1_reg = (pipe == 0) ? PIPEA_DATA_M1 : PIPEB_DATA_M1;
2915         int data_n1_reg = (pipe == 0) ? PIPEA_DATA_N1 : PIPEB_DATA_N1;
2916         int link_m1_reg = (pipe == 0) ? PIPEA_LINK_M1 : PIPEB_LINK_M1;
2917         int link_n1_reg = (pipe == 0) ? PIPEA_LINK_N1 : PIPEB_LINK_N1;
2918         int pch_fp_reg = (pipe == 0) ? PCH_FPA0 : PCH_FPB0;
2919         int pch_dpll_reg = (pipe == 0) ? PCH_DPLL_A : PCH_DPLL_B;
2920         int fdi_rx_reg = (pipe == 0) ? FDI_RXA_CTL : FDI_RXB_CTL;
2921         int lvds_reg = LVDS;
2922         u32 temp;
2923         int sdvo_pixel_multiply;
2924         int target_clock;
2925
2926         drm_vblank_pre_modeset(dev, pipe);
2927
2928         list_for_each_entry(connector, &mode_config->connector_list, head) {
2929                 struct intel_output *intel_output = to_intel_output(connector);
2930
2931                 if (!connector->encoder || connector->encoder->crtc != crtc)
2932                         continue;
2933
2934                 switch (intel_output->type) {
2935                 case INTEL_OUTPUT_LVDS:
2936                         is_lvds = true;
2937                         break;
2938                 case INTEL_OUTPUT_SDVO:
2939                 case INTEL_OUTPUT_HDMI:
2940                         is_sdvo = true;
2941                         if (intel_output->needs_tv_clock)
2942                                 is_tv = true;
2943                         break;
2944                 case INTEL_OUTPUT_DVO:
2945                         is_dvo = true;
2946                         break;
2947                 case INTEL_OUTPUT_TVOUT:
2948                         is_tv = true;
2949                         break;
2950                 case INTEL_OUTPUT_ANALOG:
2951                         is_crt = true;
2952                         break;
2953                 case INTEL_OUTPUT_DISPLAYPORT:
2954                         is_dp = true;
2955                         break;
2956                 case INTEL_OUTPUT_EDP:
2957                         is_edp = true;
2958                         break;
2959                 }
2960
2961                 num_outputs++;
2962         }
2963
2964         if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2) {
2965                 refclk = dev_priv->lvds_ssc_freq * 1000;
2966                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
2967                                         refclk / 1000);
2968         } else if (IS_I9XX(dev)) {
2969                 refclk = 96000;
2970                 if (IS_IRONLAKE(dev))
2971                         refclk = 120000; /* 120Mhz refclk */
2972         } else {
2973                 refclk = 48000;
2974         }
2975
2976
2977         /*
2978          * Returns a set of divisors for the desired target clock with the given
2979          * refclk, or FALSE.  The returned values represent the clock equation:
2980          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
2981          */
2982         limit = intel_limit(crtc);
2983         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, &clock);
2984         if (!ok) {
2985                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
2986                 drm_vblank_post_modeset(dev, pipe);
2987                 return -EINVAL;
2988         }
2989
2990         if (is_lvds && dev_priv->lvds_downclock_avail) {
2991                 has_reduced_clock = limit->find_pll(limit, crtc,
2992                                                             dev_priv->lvds_downclock,
2993                                                             refclk,
2994                                                             &reduced_clock);
2995                 if (has_reduced_clock && (clock.p != reduced_clock.p)) {
2996                         /*
2997                          * If the different P is found, it means that we can't
2998                          * switch the display clock by using the FP0/FP1.
2999                          * In such case we will disable the LVDS downclock
3000                          * feature.
3001                          */
3002                         DRM_DEBUG_KMS("Different P is found for "
3003                                                 "LVDS clock/downclock\n");
3004                         has_reduced_clock = 0;
3005                 }
3006         }
3007         /* SDVO TV has fixed PLL values depend on its clock range,
3008            this mirrors vbios setting. */
3009         if (is_sdvo && is_tv) {
3010                 if (adjusted_mode->clock >= 100000
3011                                 && adjusted_mode->clock < 140500) {
3012                         clock.p1 = 2;
3013                         clock.p2 = 10;
3014                         clock.n = 3;
3015                         clock.m1 = 16;
3016                         clock.m2 = 8;
3017                 } else if (adjusted_mode->clock >= 140500
3018                                 && adjusted_mode->clock <= 200000) {
3019                         clock.p1 = 1;
3020                         clock.p2 = 10;
3021                         clock.n = 6;
3022                         clock.m1 = 12;
3023                         clock.m2 = 8;
3024                 }
3025         }
3026
3027         /* FDI link */
3028         if (IS_IRONLAKE(dev)) {
3029                 int lane, link_bw, bpp;
3030                 /* eDP doesn't require FDI link, so just set DP M/N
3031                    according to current link config */
3032                 if (is_edp) {
3033                         struct drm_connector *edp;
3034                         target_clock = mode->clock;
3035                         edp = intel_pipe_get_output(crtc);
3036                         intel_edp_link_config(to_intel_output(edp),
3037                                         &lane, &link_bw);
3038                 } else {
3039                         /* DP over FDI requires target mode clock
3040                            instead of link clock */
3041                         if (is_dp)
3042                                 target_clock = mode->clock;
3043                         else
3044                                 target_clock = adjusted_mode->clock;
3045                         lane = 4;
3046                         link_bw = 270000;
3047                 }
3048
3049                 /* determine panel color depth */
3050                 temp = I915_READ(pipeconf_reg);
3051                 temp &= ~PIPE_BPC_MASK;
3052                 if (is_lvds) {
3053                         int lvds_reg = I915_READ(PCH_LVDS);
3054                         /* the BPC will be 6 if it is 18-bit LVDS panel */
3055                         if ((lvds_reg & LVDS_A3_POWER_MASK) == LVDS_A3_POWER_UP)
3056                                 temp |= PIPE_8BPC;
3057                         else
3058                                 temp |= PIPE_6BPC;
3059                 } else if (is_edp) {
3060                         switch (dev_priv->edp_bpp/3) {
3061                         case 8:
3062                                 temp |= PIPE_8BPC;
3063                                 break;
3064                         case 10:
3065                                 temp |= PIPE_10BPC;
3066                                 break;
3067                         case 6:
3068                                 temp |= PIPE_6BPC;
3069                                 break;
3070                         case 12:
3071                                 temp |= PIPE_12BPC;
3072                                 break;
3073                         }
3074                 } else
3075                         temp |= PIPE_8BPC;
3076                 I915_WRITE(pipeconf_reg, temp);
3077                 I915_READ(pipeconf_reg);
3078
3079                 switch (temp & PIPE_BPC_MASK) {
3080                 case PIPE_8BPC:
3081                         bpp = 24;
3082                         break;
3083                 case PIPE_10BPC:
3084                         bpp = 30;
3085                         break;
3086                 case PIPE_6BPC:
3087                         bpp = 18;
3088                         break;
3089                 case PIPE_12BPC:
3090                         bpp = 36;
3091                         break;
3092                 default:
3093                         DRM_ERROR("unknown pipe bpc value\n");
3094                         bpp = 24;
3095                 }
3096
3097                 ironlake_compute_m_n(bpp, lane, target_clock, link_bw, &m_n);
3098         }
3099
3100         /* Ironlake: try to setup display ref clock before DPLL
3101          * enabling. This is only under driver's control after
3102          * PCH B stepping, previous chipset stepping should be
3103          * ignoring this setting.
3104          */
3105         if (IS_IRONLAKE(dev)) {
3106                 temp = I915_READ(PCH_DREF_CONTROL);
3107                 /* Always enable nonspread source */
3108                 temp &= ~DREF_NONSPREAD_SOURCE_MASK;
3109                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
3110                 I915_WRITE(PCH_DREF_CONTROL, temp);
3111                 POSTING_READ(PCH_DREF_CONTROL);
3112
3113                 temp &= ~DREF_SSC_SOURCE_MASK;
3114                 temp |= DREF_SSC_SOURCE_ENABLE;
3115                 I915_WRITE(PCH_DREF_CONTROL, temp);
3116                 POSTING_READ(PCH_DREF_CONTROL);
3117
3118                 udelay(200);
3119
3120                 if (is_edp) {
3121                         if (dev_priv->lvds_use_ssc) {
3122                                 temp |= DREF_SSC1_ENABLE;
3123                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3124                                 POSTING_READ(PCH_DREF_CONTROL);
3125
3126                                 udelay(200);
3127
3128                                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
3129                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
3130                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3131                                 POSTING_READ(PCH_DREF_CONTROL);
3132                         } else {
3133                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
3134                                 I915_WRITE(PCH_DREF_CONTROL, temp);
3135                                 POSTING_READ(PCH_DREF_CONTROL);
3136                         }
3137                 }
3138         }
3139
3140         if (IS_PINEVIEW(dev)) {
3141                 fp = (1 << clock.n) << 16 | clock.m1 << 8 | clock.m2;
3142                 if (has_reduced_clock)
3143                         fp2 = (1 << reduced_clock.n) << 16 |
3144                                 reduced_clock.m1 << 8 | reduced_clock.m2;
3145         } else {
3146                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
3147                 if (has_reduced_clock)
3148                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
3149                                 reduced_clock.m2;
3150         }
3151
3152         if (!IS_IRONLAKE(dev))
3153                 dpll = DPLL_VGA_MODE_DIS;
3154
3155         if (IS_I9XX(dev)) {
3156                 if (is_lvds)
3157                         dpll |= DPLLB_MODE_LVDS;
3158                 else
3159                         dpll |= DPLLB_MODE_DAC_SERIAL;
3160                 if (is_sdvo) {
3161                         dpll |= DPLL_DVO_HIGH_SPEED;
3162                         sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3163                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
3164                                 dpll |= (sdvo_pixel_multiply - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
3165                         else if (IS_IRONLAKE(dev))
3166                                 dpll |= (sdvo_pixel_multiply - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
3167                 }
3168                 if (is_dp)
3169                         dpll |= DPLL_DVO_HIGH_SPEED;
3170
3171                 /* compute bitmask from p1 value */
3172                 if (IS_PINEVIEW(dev))
3173                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
3174                 else {
3175                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3176                         /* also FPA1 */
3177                         if (IS_IRONLAKE(dev))
3178                                 dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3179                         if (IS_G4X(dev) && has_reduced_clock)
3180                                 dpll |= (1 << (reduced_clock.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
3181                 }
3182                 switch (clock.p2) {
3183                 case 5:
3184                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
3185                         break;
3186                 case 7:
3187                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
3188                         break;
3189                 case 10:
3190                         dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
3191                         break;
3192                 case 14:
3193                         dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
3194                         break;
3195                 }
3196                 if (IS_I965G(dev) && !IS_IRONLAKE(dev))
3197                         dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
3198         } else {
3199                 if (is_lvds) {
3200                         dpll |= (1 << (clock.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3201                 } else {
3202                         if (clock.p1 == 2)
3203                                 dpll |= PLL_P1_DIVIDE_BY_TWO;
3204                         else
3205                                 dpll |= (clock.p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
3206                         if (clock.p2 == 4)
3207                                 dpll |= PLL_P2_DIVIDE_BY_4;
3208                 }
3209         }
3210
3211         if (is_sdvo && is_tv)
3212                 dpll |= PLL_REF_INPUT_TVCLKINBC;
3213         else if (is_tv)
3214                 /* XXX: just matching BIOS for now */
3215                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
3216                 dpll |= 3;
3217         else if (is_lvds && dev_priv->lvds_use_ssc && num_outputs < 2)
3218                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
3219         else
3220                 dpll |= PLL_REF_INPUT_DREFCLK;
3221
3222         /* setup pipeconf */
3223         pipeconf = I915_READ(pipeconf_reg);
3224
3225         /* Set up the display plane register */
3226         dspcntr = DISPPLANE_GAMMA_ENABLE;
3227
3228         /* Ironlake's plane is forced to pipe, bit 24 is to
3229            enable color space conversion */
3230         if (!IS_IRONLAKE(dev)) {
3231                 if (pipe == 0)
3232                         dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
3233                 else
3234                         dspcntr |= DISPPLANE_SEL_PIPE_B;
3235         }
3236
3237         if (pipe == 0 && !IS_I965G(dev)) {
3238                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
3239                  * core speed.
3240                  *
3241                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
3242                  * pipe == 0 check?
3243                  */
3244                 if (mode->clock >
3245                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
3246                         pipeconf |= PIPEACONF_DOUBLE_WIDE;
3247                 else
3248                         pipeconf &= ~PIPEACONF_DOUBLE_WIDE;
3249         }
3250
3251         dspcntr |= DISPLAY_PLANE_ENABLE;
3252         pipeconf |= PIPEACONF_ENABLE;
3253         dpll |= DPLL_VCO_ENABLE;
3254
3255
3256         /* Disable the panel fitter if it was on our pipe */
3257         if (!IS_IRONLAKE(dev) && intel_panel_fitter_pipe(dev) == pipe)
3258                 I915_WRITE(PFIT_CONTROL, 0);
3259
3260         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
3261         drm_mode_debug_printmodeline(mode);
3262
3263         /* assign to Ironlake registers */
3264         if (IS_IRONLAKE(dev)) {
3265                 fp_reg = pch_fp_reg;
3266                 dpll_reg = pch_dpll_reg;
3267         }
3268
3269         if (is_edp) {
3270                 ironlake_disable_pll_edp(crtc);
3271         } else if ((dpll & DPLL_VCO_ENABLE)) {
3272                 I915_WRITE(fp_reg, fp);
3273                 I915_WRITE(dpll_reg, dpll & ~DPLL_VCO_ENABLE);
3274                 I915_READ(dpll_reg);
3275                 udelay(150);
3276         }
3277
3278         /* The LVDS pin pair needs to be on before the DPLLs are enabled.
3279          * This is an exception to the general rule that mode_set doesn't turn
3280          * things on.
3281          */
3282         if (is_lvds) {
3283                 u32 lvds;
3284
3285                 if (IS_IRONLAKE(dev))
3286                         lvds_reg = PCH_LVDS;
3287
3288                 lvds = I915_READ(lvds_reg);
3289                 lvds |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP | LVDS_PIPEB_SELECT;
3290                 /* set the corresponsding LVDS_BORDER bit */
3291                 lvds |= dev_priv->lvds_border_bits;
3292                 /* Set the B0-B3 data pairs corresponding to whether we're going to
3293                  * set the DPLLs for dual-channel mode or not.
3294                  */
3295                 if (clock.p2 == 7)
3296                         lvds |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
3297                 else
3298                         lvds &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
3299
3300                 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
3301                  * appropriately here, but we need to look more thoroughly into how
3302                  * panels behave in the two modes.
3303                  */
3304                 /* set the dithering flag */
3305                 if (IS_I965G(dev)) {
3306                         if (dev_priv->lvds_dither) {
3307                                 if (IS_IRONLAKE(dev))
3308                                         pipeconf |= PIPE_ENABLE_DITHER;
3309                                 else
3310                                         lvds |= LVDS_ENABLE_DITHER;
3311                         } else {
3312                                 if (IS_IRONLAKE(dev))
3313                                         pipeconf &= ~PIPE_ENABLE_DITHER;
3314                                 else
3315                                         lvds &= ~LVDS_ENABLE_DITHER;
3316                         }
3317                 }
3318                 I915_WRITE(lvds_reg, lvds);
3319                 I915_READ(lvds_reg);
3320         }
3321         if (is_dp)
3322                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
3323
3324         if (!is_edp) {
3325                 I915_WRITE(fp_reg, fp);
3326                 I915_WRITE(dpll_reg, dpll);
3327                 I915_READ(dpll_reg);
3328                 /* Wait for the clocks to stabilize. */
3329                 udelay(150);
3330
3331                 if (IS_I965G(dev) && !IS_IRONLAKE(dev)) {
3332                         if (is_sdvo) {
3333                                 sdvo_pixel_multiply = adjusted_mode->clock / mode->clock;
3334                                 I915_WRITE(dpll_md_reg, (0 << DPLL_MD_UDI_DIVIDER_SHIFT) |
3335                                         ((sdvo_pixel_multiply - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT));
3336                         } else
3337                                 I915_WRITE(dpll_md_reg, 0);
3338                 } else {
3339                         /* write it again -- the BIOS does, after all */
3340                         I915_WRITE(dpll_reg, dpll);
3341                 }
3342                 I915_READ(dpll_reg);
3343                 /* Wait for the clocks to stabilize. */
3344                 udelay(150);
3345         }
3346
3347         if (is_lvds && has_reduced_clock && i915_powersave) {
3348                 I915_WRITE(fp_reg + 4, fp2);
3349                 intel_crtc->lowfreq_avail = true;
3350                 if (HAS_PIPE_CXSR(dev)) {
3351                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
3352                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
3353                 }
3354         } else {
3355                 I915_WRITE(fp_reg + 4, fp);
3356                 intel_crtc->lowfreq_avail = false;
3357                 if (HAS_PIPE_CXSR(dev)) {
3358                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
3359                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
3360                 }
3361         }
3362
3363         I915_WRITE(htot_reg, (adjusted_mode->crtc_hdisplay - 1) |
3364                    ((adjusted_mode->crtc_htotal - 1) << 16));
3365         I915_WRITE(hblank_reg, (adjusted_mode->crtc_hblank_start - 1) |
3366                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
3367         I915_WRITE(hsync_reg, (adjusted_mode->crtc_hsync_start - 1) |
3368                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
3369         I915_WRITE(vtot_reg, (adjusted_mode->crtc_vdisplay - 1) |
3370                    ((adjusted_mode->crtc_vtotal - 1) << 16));
3371         I915_WRITE(vblank_reg, (adjusted_mode->crtc_vblank_start - 1) |
3372                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
3373         I915_WRITE(vsync_reg, (adjusted_mode->crtc_vsync_start - 1) |
3374                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
3375         /* pipesrc and dspsize control the size that is scaled from, which should
3376          * always be the user's requested size.
3377          */
3378         if (!IS_IRONLAKE(dev)) {
3379                 I915_WRITE(dspsize_reg, ((mode->vdisplay - 1) << 16) |
3380                                 (mode->hdisplay - 1));
3381                 I915_WRITE(dsppos_reg, 0);
3382         }
3383         I915_WRITE(pipesrc_reg, ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
3384
3385         if (IS_IRONLAKE(dev)) {
3386                 I915_WRITE(data_m1_reg, TU_SIZE(m_n.tu) | m_n.gmch_m);
3387                 I915_WRITE(data_n1_reg, TU_SIZE(m_n.tu) | m_n.gmch_n);
3388                 I915_WRITE(link_m1_reg, m_n.link_m);
3389                 I915_WRITE(link_n1_reg, m_n.link_n);
3390
3391                 if (is_edp) {
3392                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
3393                 } else {
3394                         /* enable FDI RX PLL too */
3395                         temp = I915_READ(fdi_rx_reg);
3396                         I915_WRITE(fdi_rx_reg, temp | FDI_RX_PLL_ENABLE);
3397                         udelay(200);
3398                 }
3399         }
3400
3401         I915_WRITE(pipeconf_reg, pipeconf);
3402         I915_READ(pipeconf_reg);
3403
3404         intel_wait_for_vblank(dev);
3405
3406         if (IS_IRONLAKE(dev)) {
3407                 /* enable address swizzle for tiling buffer */
3408                 temp = I915_READ(DISP_ARB_CTL);
3409                 I915_WRITE(DISP_ARB_CTL, temp | DISP_TILE_SURFACE_SWIZZLING);
3410         }
3411
3412         I915_WRITE(dspcntr_reg, dspcntr);
3413
3414         /* Flush the plane changes */
3415         ret = intel_pipe_set_base(crtc, x, y, old_fb);
3416
3417         if ((IS_I965G(dev) || plane == 0))
3418                 intel_update_fbc(crtc, &crtc->mode);
3419
3420         intel_update_watermarks(dev);
3421
3422         drm_vblank_post_modeset(dev, pipe);
3423
3424         return ret;
3425 }
3426
3427 /** Loads the palette/gamma unit for the CRTC with the prepared values */
3428 void intel_crtc_load_lut(struct drm_crtc *crtc)
3429 {
3430         struct drm_device *dev = crtc->dev;
3431         struct drm_i915_private *dev_priv = dev->dev_private;
3432         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3433         int palreg = (intel_crtc->pipe == 0) ? PALETTE_A : PALETTE_B;
3434         int i;
3435
3436         /* The clocks have to be on to load the palette. */
3437         if (!crtc->enabled)
3438                 return;
3439
3440         /* use legacy palette for Ironlake */
3441         if (IS_IRONLAKE(dev))
3442                 palreg = (intel_crtc->pipe == 0) ? LGC_PALETTE_A :
3443                                                    LGC_PALETTE_B;
3444
3445         for (i = 0; i < 256; i++) {
3446                 I915_WRITE(palreg + 4 * i,
3447                            (intel_crtc->lut_r[i] << 16) |
3448                            (intel_crtc->lut_g[i] << 8) |
3449                            intel_crtc->lut_b[i]);
3450         }
3451 }
3452
3453 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
3454                                  struct drm_file *file_priv,
3455                                  uint32_t handle,
3456                                  uint32_t width, uint32_t height)
3457 {
3458         struct drm_device *dev = crtc->dev;
3459         struct drm_i915_private *dev_priv = dev->dev_private;
3460         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3461         struct drm_gem_object *bo;
3462         struct drm_i915_gem_object *obj_priv;
3463         int pipe = intel_crtc->pipe;
3464         uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
3465         uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
3466         uint32_t temp = I915_READ(control);
3467         size_t addr;
3468         int ret;
3469
3470         DRM_DEBUG_KMS("\n");
3471
3472         /* if we want to turn off the cursor ignore width and height */
3473         if (!handle) {
3474                 DRM_DEBUG_KMS("cursor off\n");
3475                 if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3476                         temp &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
3477                         temp |= CURSOR_MODE_DISABLE;
3478                 } else {
3479                         temp &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
3480                 }
3481                 addr = 0;
3482                 bo = NULL;
3483                 mutex_lock(&dev->struct_mutex);
3484                 goto finish;
3485         }
3486
3487         /* Currently we only support 64x64 cursors */
3488         if (width != 64 || height != 64) {
3489                 DRM_ERROR("we currently only support 64x64 cursors\n");
3490                 return -EINVAL;
3491         }
3492
3493         bo = drm_gem_object_lookup(dev, file_priv, handle);
3494         if (!bo)
3495                 return -ENOENT;
3496
3497         obj_priv = bo->driver_private;
3498
3499         if (bo->size < width * height * 4) {
3500                 DRM_ERROR("buffer is to small\n");
3501                 ret = -ENOMEM;
3502                 goto fail;
3503         }
3504
3505         /* we only need to pin inside GTT if cursor is non-phy */
3506         mutex_lock(&dev->struct_mutex);
3507         if (!dev_priv->info->cursor_needs_physical) {
3508                 ret = i915_gem_object_pin(bo, PAGE_SIZE);
3509                 if (ret) {
3510                         DRM_ERROR("failed to pin cursor bo\n");
3511                         goto fail_locked;
3512                 }
3513                 addr = obj_priv->gtt_offset;
3514         } else {
3515                 ret = i915_gem_attach_phys_object(dev, bo, (pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1);
3516                 if (ret) {
3517                         DRM_ERROR("failed to attach phys object\n");
3518                         goto fail_locked;
3519                 }
3520                 addr = obj_priv->phys_obj->handle->busaddr;
3521         }
3522
3523         if (!IS_I9XX(dev))
3524                 I915_WRITE(CURSIZE, (height << 12) | width);
3525
3526         /* Hooray for CUR*CNTR differences */
3527         if (IS_MOBILE(dev) || IS_I9XX(dev)) {
3528                 temp &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
3529                 temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
3530                 temp |= (pipe << 28); /* Connect to correct pipe */
3531         } else {
3532                 temp &= ~(CURSOR_FORMAT_MASK);
3533                 temp |= CURSOR_ENABLE;
3534                 temp |= CURSOR_FORMAT_ARGB | CURSOR_GAMMA_ENABLE;
3535         }
3536
3537  finish:
3538         I915_WRITE(control, temp);
3539         I915_WRITE(base, addr);
3540
3541         if (intel_crtc->cursor_bo) {
3542                 if (dev_priv->info->cursor_needs_physical) {
3543                         if (intel_crtc->cursor_bo != bo)
3544                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
3545                 } else
3546                         i915_gem_object_unpin(intel_crtc->cursor_bo);
3547                 drm_gem_object_unreference(intel_crtc->cursor_bo);
3548         }
3549
3550         mutex_unlock(&dev->struct_mutex);
3551
3552         intel_crtc->cursor_addr = addr;
3553         intel_crtc->cursor_bo = bo;
3554
3555         return 0;
3556 fail_locked:
3557         mutex_unlock(&dev->struct_mutex);
3558 fail:
3559         drm_gem_object_unreference_unlocked(bo);
3560         return ret;
3561 }
3562
3563 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
3564 {
3565         struct drm_device *dev = crtc->dev;
3566         struct drm_i915_private *dev_priv = dev->dev_private;
3567         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3568         struct intel_framebuffer *intel_fb;
3569         int pipe = intel_crtc->pipe;
3570         uint32_t temp = 0;
3571         uint32_t adder;
3572
3573         if (crtc->fb) {
3574                 intel_fb = to_intel_framebuffer(crtc->fb);
3575                 intel_mark_busy(dev, intel_fb->obj);
3576         }
3577
3578         if (x < 0) {
3579                 temp |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
3580                 x = -x;
3581         }
3582         if (y < 0) {
3583                 temp |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
3584                 y = -y;
3585         }
3586
3587         temp |= x << CURSOR_X_SHIFT;
3588         temp |= y << CURSOR_Y_SHIFT;
3589
3590         adder = intel_crtc->cursor_addr;
3591         I915_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
3592         I915_WRITE((pipe == 0) ? CURABASE : CURBBASE, adder);
3593
3594         return 0;
3595 }
3596
3597 /** Sets the color ramps on behalf of RandR */
3598 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
3599                                  u16 blue, int regno)
3600 {
3601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602
3603         intel_crtc->lut_r[regno] = red >> 8;
3604         intel_crtc->lut_g[regno] = green >> 8;
3605         intel_crtc->lut_b[regno] = blue >> 8;
3606 }
3607
3608 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
3609                              u16 *blue, int regno)
3610 {
3611         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3612
3613         *red = intel_crtc->lut_r[regno] << 8;
3614         *green = intel_crtc->lut_g[regno] << 8;
3615         *blue = intel_crtc->lut_b[regno] << 8;
3616 }
3617
3618 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
3619                                  u16 *blue, uint32_t size)
3620 {
3621         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3622         int i;
3623
3624         if (size != 256)
3625                 return;
3626
3627         for (i = 0; i < 256; i++) {
3628                 intel_crtc->lut_r[i] = red[i] >> 8;
3629                 intel_crtc->lut_g[i] = green[i] >> 8;
3630                 intel_crtc->lut_b[i] = blue[i] >> 8;
3631         }
3632
3633         intel_crtc_load_lut(crtc);
3634 }
3635
3636 /**
3637  * Get a pipe with a simple mode set on it for doing load-based monitor
3638  * detection.
3639  *
3640  * It will be up to the load-detect code to adjust the pipe as appropriate for
3641  * its requirements.  The pipe will be connected to no other outputs.
3642  *
3643  * Currently this code will only succeed if there is a pipe with no outputs
3644  * configured for it.  In the future, it could choose to temporarily disable
3645  * some outputs to free up a pipe for its use.
3646  *
3647  * \return crtc, or NULL if no pipes are available.
3648  */
3649
3650 /* VESA 640x480x72Hz mode to set on the pipe */
3651 static struct drm_display_mode load_detect_mode = {
3652         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
3653                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
3654 };
3655
3656 struct drm_crtc *intel_get_load_detect_pipe(struct intel_output *intel_output,
3657                                             struct drm_display_mode *mode,
3658                                             int *dpms_mode)
3659 {
3660         struct intel_crtc *intel_crtc;
3661         struct drm_crtc *possible_crtc;
3662         struct drm_crtc *supported_crtc =NULL;
3663         struct drm_encoder *encoder = &intel_output->enc;
3664         struct drm_crtc *crtc = NULL;
3665         struct drm_device *dev = encoder->dev;
3666         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3667         struct drm_crtc_helper_funcs *crtc_funcs;
3668         int i = -1;
3669
3670         /*
3671          * Algorithm gets a little messy:
3672          *   - if the connector already has an assigned crtc, use it (but make
3673          *     sure it's on first)
3674          *   - try to find the first unused crtc that can drive this connector,
3675          *     and use that if we find one
3676          *   - if there are no unused crtcs available, try to use the first
3677          *     one we found that supports the connector
3678          */
3679
3680         /* See if we already have a CRTC for this connector */
3681         if (encoder->crtc) {
3682                 crtc = encoder->crtc;
3683                 /* Make sure the crtc and connector are running */
3684                 intel_crtc = to_intel_crtc(crtc);
3685                 *dpms_mode = intel_crtc->dpms_mode;
3686                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3687                         crtc_funcs = crtc->helper_private;
3688                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3689                         encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
3690                 }
3691                 return crtc;
3692         }
3693
3694         /* Find an unused one (if possible) */
3695         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
3696                 i++;
3697                 if (!(encoder->possible_crtcs & (1 << i)))
3698                         continue;
3699                 if (!possible_crtc->enabled) {
3700                         crtc = possible_crtc;
3701                         break;
3702                 }
3703                 if (!supported_crtc)
3704                         supported_crtc = possible_crtc;
3705         }
3706
3707         /*
3708          * If we didn't find an unused CRTC, don't use any.
3709          */
3710         if (!crtc) {
3711                 return NULL;
3712         }
3713
3714         encoder->crtc = crtc;
3715         intel_output->base.encoder = encoder;
3716         intel_output->load_detect_temp = true;
3717
3718         intel_crtc = to_intel_crtc(crtc);
3719         *dpms_mode = intel_crtc->dpms_mode;
3720
3721         if (!crtc->enabled) {
3722                 if (!mode)
3723                         mode = &load_detect_mode;
3724                 drm_crtc_helper_set_mode(crtc, mode, 0, 0, crtc->fb);
3725         } else {
3726                 if (intel_crtc->dpms_mode != DRM_MODE_DPMS_ON) {
3727                         crtc_funcs = crtc->helper_private;
3728                         crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
3729                 }
3730
3731                 /* Add this connector to the crtc */
3732                 encoder_funcs->mode_set(encoder, &crtc->mode, &crtc->mode);
3733                 encoder_funcs->commit(encoder);
3734         }
3735         /* let the connector get through one full cycle before testing */
3736         intel_wait_for_vblank(dev);
3737
3738         return crtc;
3739 }
3740
3741 void intel_release_load_detect_pipe(struct intel_output *intel_output, int dpms_mode)
3742 {
3743         struct drm_encoder *encoder = &intel_output->enc;
3744         struct drm_device *dev = encoder->dev;
3745         struct drm_crtc *crtc = encoder->crtc;
3746         struct drm_encoder_helper_funcs *encoder_funcs = encoder->helper_private;
3747         struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
3748
3749         if (intel_output->load_detect_temp) {
3750                 encoder->crtc = NULL;
3751                 intel_output->base.encoder = NULL;
3752                 intel_output->load_detect_temp = false;
3753                 crtc->enabled = drm_helper_crtc_in_use(crtc);
3754                 drm_helper_disable_unused_functions(dev);
3755         }
3756
3757         /* Switch crtc and output back off if necessary */
3758         if (crtc->enabled && dpms_mode != DRM_MODE_DPMS_ON) {
3759                 if (encoder->crtc == crtc)
3760                         encoder_funcs->dpms(encoder, dpms_mode);
3761                 crtc_funcs->dpms(crtc, dpms_mode);
3762         }
3763 }
3764
3765 /* Returns the clock of the currently programmed mode of the given pipe. */
3766 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
3767 {
3768         struct drm_i915_private *dev_priv = dev->dev_private;
3769         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3770         int pipe = intel_crtc->pipe;
3771         u32 dpll = I915_READ((pipe == 0) ? DPLL_A : DPLL_B);
3772         u32 fp;
3773         intel_clock_t clock;
3774
3775         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
3776                 fp = I915_READ((pipe == 0) ? FPA0 : FPB0);
3777         else
3778                 fp = I915_READ((pipe == 0) ? FPA1 : FPB1);
3779
3780         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
3781         if (IS_PINEVIEW(dev)) {
3782                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
3783                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
3784         } else {
3785                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
3786                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
3787         }
3788
3789         if (IS_I9XX(dev)) {
3790                 if (IS_PINEVIEW(dev))
3791                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
3792                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
3793                 else
3794                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
3795                                DPLL_FPA01_P1_POST_DIV_SHIFT);
3796
3797                 switch (dpll & DPLL_MODE_MASK) {
3798                 case DPLLB_MODE_DAC_SERIAL:
3799                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
3800                                 5 : 10;
3801                         break;
3802                 case DPLLB_MODE_LVDS:
3803                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
3804                                 7 : 14;
3805                         break;
3806                 default:
3807                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
3808                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
3809                         return 0;
3810                 }
3811
3812                 /* XXX: Handle the 100Mhz refclk */
3813                 intel_clock(dev, 96000, &clock);
3814         } else {
3815                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
3816
3817                 if (is_lvds) {
3818                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
3819                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
3820                         clock.p2 = 14;
3821
3822                         if ((dpll & PLL_REF_INPUT_MASK) ==
3823                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
3824                                 /* XXX: might not be 66MHz */
3825                                 intel_clock(dev, 66000, &clock);
3826                         } else
3827                                 intel_clock(dev, 48000, &clock);
3828                 } else {
3829                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
3830                                 clock.p1 = 2;
3831                         else {
3832                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
3833                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
3834                         }
3835                         if (dpll & PLL_P2_DIVIDE_BY_4)
3836                                 clock.p2 = 4;
3837                         else
3838                                 clock.p2 = 2;
3839
3840                         intel_clock(dev, 48000, &clock);
3841                 }
3842         }
3843
3844         /* XXX: It would be nice to validate the clocks, but we can't reuse
3845          * i830PllIsValid() because it relies on the xf86_config connector
3846          * configuration being accurate, which it isn't necessarily.
3847          */
3848
3849         return clock.dot;
3850 }
3851
3852 /** Returns the currently programmed mode of the given pipe. */
3853 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
3854                                              struct drm_crtc *crtc)
3855 {
3856         struct drm_i915_private *dev_priv = dev->dev_private;
3857         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3858         int pipe = intel_crtc->pipe;
3859         struct drm_display_mode *mode;
3860         int htot = I915_READ((pipe == 0) ? HTOTAL_A : HTOTAL_B);
3861         int hsync = I915_READ((pipe == 0) ? HSYNC_A : HSYNC_B);
3862         int vtot = I915_READ((pipe == 0) ? VTOTAL_A : VTOTAL_B);
3863         int vsync = I915_READ((pipe == 0) ? VSYNC_A : VSYNC_B);
3864
3865         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
3866         if (!mode)
3867                 return NULL;
3868
3869         mode->clock = intel_crtc_clock_get(dev, crtc);
3870         mode->hdisplay = (htot & 0xffff) + 1;
3871         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
3872         mode->hsync_start = (hsync & 0xffff) + 1;
3873         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
3874         mode->vdisplay = (vtot & 0xffff) + 1;
3875         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
3876         mode->vsync_start = (vsync & 0xffff) + 1;
3877         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
3878
3879         drm_mode_set_name(mode);
3880         drm_mode_set_crtcinfo(mode, 0);
3881
3882         return mode;
3883 }
3884
3885 #define GPU_IDLE_TIMEOUT 500 /* ms */
3886
3887 /* When this timer fires, we've been idle for awhile */
3888 static void intel_gpu_idle_timer(unsigned long arg)
3889 {
3890         struct drm_device *dev = (struct drm_device *)arg;
3891         drm_i915_private_t *dev_priv = dev->dev_private;
3892
3893         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3894
3895         dev_priv->busy = false;
3896
3897         queue_work(dev_priv->wq, &dev_priv->idle_work);
3898 }
3899
3900 #define CRTC_IDLE_TIMEOUT 1000 /* ms */
3901
3902 static void intel_crtc_idle_timer(unsigned long arg)
3903 {
3904         struct intel_crtc *intel_crtc = (struct intel_crtc *)arg;
3905         struct drm_crtc *crtc = &intel_crtc->base;
3906         drm_i915_private_t *dev_priv = crtc->dev->dev_private;
3907
3908         DRM_DEBUG_DRIVER("idle timer fired, downclocking\n");
3909
3910         intel_crtc->busy = false;
3911
3912         queue_work(dev_priv->wq, &dev_priv->idle_work);
3913 }
3914
3915 static void intel_increase_pllclock(struct drm_crtc *crtc, bool schedule)
3916 {
3917         struct drm_device *dev = crtc->dev;
3918         drm_i915_private_t *dev_priv = dev->dev_private;
3919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920         int pipe = intel_crtc->pipe;
3921         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3922         int dpll = I915_READ(dpll_reg);
3923
3924         if (IS_IRONLAKE(dev))
3925                 return;
3926
3927         if (!dev_priv->lvds_downclock_avail)
3928                 return;
3929
3930         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
3931                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
3932
3933                 /* Unlock panel regs */
3934                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3935
3936                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
3937                 I915_WRITE(dpll_reg, dpll);
3938                 dpll = I915_READ(dpll_reg);
3939                 intel_wait_for_vblank(dev);
3940                 dpll = I915_READ(dpll_reg);
3941                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
3942                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
3943
3944                 /* ...and lock them again */
3945                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3946         }
3947
3948         /* Schedule downclock */
3949         if (schedule)
3950                 mod_timer(&intel_crtc->idle_timer, jiffies +
3951                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
3952 }
3953
3954 static void intel_decrease_pllclock(struct drm_crtc *crtc)
3955 {
3956         struct drm_device *dev = crtc->dev;
3957         drm_i915_private_t *dev_priv = dev->dev_private;
3958         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3959         int pipe = intel_crtc->pipe;
3960         int dpll_reg = (pipe == 0) ? DPLL_A : DPLL_B;
3961         int dpll = I915_READ(dpll_reg);
3962
3963         if (IS_IRONLAKE(dev))
3964                 return;
3965
3966         if (!dev_priv->lvds_downclock_avail)
3967                 return;
3968
3969         /*
3970          * Since this is called by a timer, we should never get here in
3971          * the manual case.
3972          */
3973         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
3974                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
3975
3976                 /* Unlock panel regs */
3977                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) | (0xabcd << 16));
3978
3979                 dpll |= DISPLAY_RATE_SELECT_FPA1;
3980                 I915_WRITE(dpll_reg, dpll);
3981                 dpll = I915_READ(dpll_reg);
3982                 intel_wait_for_vblank(dev);
3983                 dpll = I915_READ(dpll_reg);
3984                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
3985                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
3986
3987                 /* ...and lock them again */
3988                 I915_WRITE(PP_CONTROL, I915_READ(PP_CONTROL) & 0x3);
3989         }
3990
3991 }
3992
3993 /**
3994  * intel_idle_update - adjust clocks for idleness
3995  * @work: work struct
3996  *
3997  * Either the GPU or display (or both) went idle.  Check the busy status
3998  * here and adjust the CRTC and GPU clocks as necessary.
3999  */
4000 static void intel_idle_update(struct work_struct *work)
4001 {
4002         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
4003                                                     idle_work);
4004         struct drm_device *dev = dev_priv->dev;
4005         struct drm_crtc *crtc;
4006         struct intel_crtc *intel_crtc;
4007
4008         if (!i915_powersave)
4009                 return;
4010
4011         mutex_lock(&dev->struct_mutex);
4012
4013         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4014                 /* Skip inactive CRTCs */
4015                 if (!crtc->fb)
4016                         continue;
4017
4018                 intel_crtc = to_intel_crtc(crtc);
4019                 if (!intel_crtc->busy)
4020                         intel_decrease_pllclock(crtc);
4021         }
4022
4023         mutex_unlock(&dev->struct_mutex);
4024 }
4025
4026 /**
4027  * intel_mark_busy - mark the GPU and possibly the display busy
4028  * @dev: drm device
4029  * @obj: object we're operating on
4030  *
4031  * Callers can use this function to indicate that the GPU is busy processing
4032  * commands.  If @obj matches one of the CRTC objects (i.e. it's a scanout
4033  * buffer), we'll also mark the display as busy, so we know to increase its
4034  * clock frequency.
4035  */
4036 void intel_mark_busy(struct drm_device *dev, struct drm_gem_object *obj)
4037 {
4038         drm_i915_private_t *dev_priv = dev->dev_private;
4039         struct drm_crtc *crtc = NULL;
4040         struct intel_framebuffer *intel_fb;
4041         struct intel_crtc *intel_crtc;
4042
4043         if (!drm_core_check_feature(dev, DRIVER_MODESET))
4044                 return;
4045
4046         if (!dev_priv->busy)
4047                 dev_priv->busy = true;
4048         else
4049                 mod_timer(&dev_priv->idle_timer, jiffies +
4050                           msecs_to_jiffies(GPU_IDLE_TIMEOUT));
4051
4052         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4053                 if (!crtc->fb)
4054                         continue;
4055
4056                 intel_crtc = to_intel_crtc(crtc);
4057                 intel_fb = to_intel_framebuffer(crtc->fb);
4058                 if (intel_fb->obj == obj) {
4059                         if (!intel_crtc->busy) {
4060                                 /* Non-busy -> busy, upclock */
4061                                 intel_increase_pllclock(crtc, true);
4062                                 intel_crtc->busy = true;
4063                         } else {
4064                                 /* Busy -> busy, put off timer */
4065                                 mod_timer(&intel_crtc->idle_timer, jiffies +
4066                                           msecs_to_jiffies(CRTC_IDLE_TIMEOUT));
4067                         }
4068                 }
4069         }
4070 }
4071
4072 static void intel_crtc_destroy(struct drm_crtc *crtc)
4073 {
4074         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4075
4076         drm_crtc_cleanup(crtc);
4077         kfree(intel_crtc);
4078 }
4079
4080 struct intel_unpin_work {
4081         struct work_struct work;
4082         struct drm_device *dev;
4083         struct drm_gem_object *old_fb_obj;
4084         struct drm_gem_object *pending_flip_obj;
4085         struct drm_pending_vblank_event *event;
4086         int pending;
4087 };
4088
4089 static void intel_unpin_work_fn(struct work_struct *__work)
4090 {
4091         struct intel_unpin_work *work =
4092                 container_of(__work, struct intel_unpin_work, work);
4093
4094         mutex_lock(&work->dev->struct_mutex);
4095         i915_gem_object_unpin(work->old_fb_obj);
4096         drm_gem_object_unreference(work->pending_flip_obj);
4097         drm_gem_object_unreference(work->old_fb_obj);
4098         mutex_unlock(&work->dev->struct_mutex);
4099         kfree(work);
4100 }
4101
4102 void intel_finish_page_flip(struct drm_device *dev, int pipe)
4103 {
4104         drm_i915_private_t *dev_priv = dev->dev_private;
4105         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
4106         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4107         struct intel_unpin_work *work;
4108         struct drm_i915_gem_object *obj_priv;
4109         struct drm_pending_vblank_event *e;
4110         struct timeval now;
4111         unsigned long flags;
4112
4113         /* Ignore early vblank irqs */
4114         if (intel_crtc == NULL)
4115                 return;
4116
4117         spin_lock_irqsave(&dev->event_lock, flags);
4118         work = intel_crtc->unpin_work;
4119         if (work == NULL || !work->pending) {
4120                 if (work && !work->pending) {
4121                         obj_priv = work->pending_flip_obj->driver_private;
4122                         DRM_DEBUG_DRIVER("flip finish: %p (%d) not pending?\n",
4123                                          obj_priv,
4124                                          atomic_read(&obj_priv->pending_flip));
4125                 }
4126                 spin_unlock_irqrestore(&dev->event_lock, flags);
4127                 return;
4128         }
4129
4130         intel_crtc->unpin_work = NULL;
4131         drm_vblank_put(dev, intel_crtc->pipe);
4132
4133         if (work->event) {
4134                 e = work->event;
4135                 do_gettimeofday(&now);
4136                 e->event.sequence = drm_vblank_count(dev, intel_crtc->pipe);
4137                 e->event.tv_sec = now.tv_sec;
4138                 e->event.tv_usec = now.tv_usec;
4139                 list_add_tail(&e->base.link,
4140                               &e->base.file_priv->event_list);
4141                 wake_up_interruptible(&e->base.file_priv->event_wait);
4142         }
4143
4144         spin_unlock_irqrestore(&dev->event_lock, flags);
4145
4146         obj_priv = work->pending_flip_obj->driver_private;
4147
4148         /* Initial scanout buffer will have a 0 pending flip count */
4149         if ((atomic_read(&obj_priv->pending_flip) == 0) ||
4150             atomic_dec_and_test(&obj_priv->pending_flip))
4151                 DRM_WAKEUP(&dev_priv->pending_flip_queue);
4152         schedule_work(&work->work);
4153 }
4154
4155 void intel_prepare_page_flip(struct drm_device *dev, int plane)
4156 {
4157         drm_i915_private_t *dev_priv = dev->dev_private;
4158         struct intel_crtc *intel_crtc =
4159                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
4160         unsigned long flags;
4161
4162         spin_lock_irqsave(&dev->event_lock, flags);
4163         if (intel_crtc->unpin_work) {
4164                 intel_crtc->unpin_work->pending = 1;
4165         } else {
4166                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
4167         }
4168         spin_unlock_irqrestore(&dev->event_lock, flags);
4169 }
4170
4171 static int intel_crtc_page_flip(struct drm_crtc *crtc,
4172                                 struct drm_framebuffer *fb,
4173                                 struct drm_pending_vblank_event *event)
4174 {
4175         struct drm_device *dev = crtc->dev;
4176         struct drm_i915_private *dev_priv = dev->dev_private;
4177         struct intel_framebuffer *intel_fb;
4178         struct drm_i915_gem_object *obj_priv;
4179         struct drm_gem_object *obj;
4180         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4181         struct intel_unpin_work *work;
4182         unsigned long flags;
4183         int pipesrc_reg = (intel_crtc->pipe == 0) ? PIPEASRC : PIPEBSRC;
4184         int ret, pipesrc;
4185         RING_LOCALS;
4186
4187         work = kzalloc(sizeof *work, GFP_KERNEL);
4188         if (work == NULL)
4189                 return -ENOMEM;
4190
4191         mutex_lock(&dev->struct_mutex);
4192
4193         work->event = event;
4194         work->dev = crtc->dev;
4195         intel_fb = to_intel_framebuffer(crtc->fb);
4196         work->old_fb_obj = intel_fb->obj;
4197         INIT_WORK(&work->work, intel_unpin_work_fn);
4198
4199         /* We borrow the event spin lock for protecting unpin_work */
4200         spin_lock_irqsave(&dev->event_lock, flags);
4201         if (intel_crtc->unpin_work) {
4202                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
4203                 spin_unlock_irqrestore(&dev->event_lock, flags);
4204                 kfree(work);
4205                 mutex_unlock(&dev->struct_mutex);
4206                 return -EBUSY;
4207         }
4208         intel_crtc->unpin_work = work;
4209         spin_unlock_irqrestore(&dev->event_lock, flags);
4210
4211         intel_fb = to_intel_framebuffer(fb);
4212         obj = intel_fb->obj;
4213
4214         ret = intel_pin_and_fence_fb_obj(dev, obj);
4215         if (ret != 0) {
4216                 DRM_DEBUG_DRIVER("flip queue: %p pin & fence failed\n",
4217                           obj->driver_private);
4218                 kfree(work);
4219                 intel_crtc->unpin_work = NULL;
4220                 mutex_unlock(&dev->struct_mutex);
4221                 return ret;
4222         }
4223
4224         /* Reference the objects for the scheduled work. */
4225         drm_gem_object_reference(work->old_fb_obj);
4226         drm_gem_object_reference(obj);
4227
4228         crtc->fb = fb;
4229         i915_gem_object_flush_write_domain(obj);
4230         drm_vblank_get(dev, intel_crtc->pipe);
4231         obj_priv = obj->driver_private;
4232         atomic_inc(&obj_priv->pending_flip);
4233         work->pending_flip_obj = obj;
4234
4235         BEGIN_LP_RING(4);
4236         OUT_RING(MI_DISPLAY_FLIP |
4237                  MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
4238         OUT_RING(fb->pitch);
4239         if (IS_I965G(dev)) {
4240                 OUT_RING(obj_priv->gtt_offset | obj_priv->tiling_mode);
4241                 pipesrc = I915_READ(pipesrc_reg);
4242                 OUT_RING(pipesrc & 0x0fff0fff);
4243         } else {
4244                 OUT_RING(obj_priv->gtt_offset);
4245                 OUT_RING(MI_NOOP);
4246         }
4247         ADVANCE_LP_RING();
4248
4249         mutex_unlock(&dev->struct_mutex);
4250
4251         return 0;
4252 }
4253
4254 static const struct drm_crtc_helper_funcs intel_helper_funcs = {
4255         .dpms = intel_crtc_dpms,
4256         .mode_fixup = intel_crtc_mode_fixup,
4257         .mode_set = intel_crtc_mode_set,
4258         .mode_set_base = intel_pipe_set_base,
4259         .prepare = intel_crtc_prepare,
4260         .commit = intel_crtc_commit,
4261         .load_lut = intel_crtc_load_lut,
4262 };
4263
4264 static const struct drm_crtc_funcs intel_crtc_funcs = {
4265         .cursor_set = intel_crtc_cursor_set,
4266         .cursor_move = intel_crtc_cursor_move,
4267         .gamma_set = intel_crtc_gamma_set,
4268         .set_config = drm_crtc_helper_set_config,
4269         .destroy = intel_crtc_destroy,
4270         .page_flip = intel_crtc_page_flip,
4271 };
4272
4273
4274 static void intel_crtc_init(struct drm_device *dev, int pipe)
4275 {
4276         drm_i915_private_t *dev_priv = dev->dev_private;
4277         struct intel_crtc *intel_crtc;
4278         int i;
4279
4280         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
4281         if (intel_crtc == NULL)
4282                 return;
4283
4284         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
4285
4286         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
4287         intel_crtc->pipe = pipe;
4288         intel_crtc->plane = pipe;
4289         for (i = 0; i < 256; i++) {
4290                 intel_crtc->lut_r[i] = i;
4291                 intel_crtc->lut_g[i] = i;
4292                 intel_crtc->lut_b[i] = i;
4293         }
4294
4295         /* Swap pipes & planes for FBC on pre-965 */
4296         intel_crtc->pipe = pipe;
4297         intel_crtc->plane = pipe;
4298         if (IS_MOBILE(dev) && (IS_I9XX(dev) && !IS_I965G(dev))) {
4299                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
4300                 intel_crtc->plane = ((pipe == 0) ? 1 : 0);
4301         }
4302
4303         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
4304                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
4305         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
4306         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
4307
4308         intel_crtc->cursor_addr = 0;
4309         intel_crtc->dpms_mode = DRM_MODE_DPMS_OFF;
4310         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
4311
4312         intel_crtc->busy = false;
4313
4314         setup_timer(&intel_crtc->idle_timer, intel_crtc_idle_timer,
4315                     (unsigned long)intel_crtc);
4316 }
4317
4318 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
4319                                 struct drm_file *file_priv)
4320 {
4321         drm_i915_private_t *dev_priv = dev->dev_private;
4322         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
4323         struct drm_mode_object *drmmode_obj;
4324         struct intel_crtc *crtc;
4325
4326         if (!dev_priv) {
4327                 DRM_ERROR("called with no initialization\n");
4328                 return -EINVAL;
4329         }
4330
4331         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
4332                         DRM_MODE_OBJECT_CRTC);
4333
4334         if (!drmmode_obj) {
4335                 DRM_ERROR("no such CRTC id\n");
4336                 return -EINVAL;
4337         }
4338
4339         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
4340         pipe_from_crtc_id->pipe = crtc->pipe;
4341
4342         return 0;
4343 }
4344
4345 struct drm_crtc *intel_get_crtc_from_pipe(struct drm_device *dev, int pipe)
4346 {
4347         struct drm_crtc *crtc = NULL;
4348
4349         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4350                 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4351                 if (intel_crtc->pipe == pipe)
4352                         break;
4353         }
4354         return crtc;
4355 }
4356
4357 static int intel_connector_clones(struct drm_device *dev, int type_mask)
4358 {
4359         int index_mask = 0;
4360         struct drm_connector *connector;
4361         int entry = 0;
4362
4363         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4364                 struct intel_output *intel_output = to_intel_output(connector);
4365                 if (type_mask & intel_output->clone_mask)
4366                         index_mask |= (1 << entry);
4367                 entry++;
4368         }
4369         return index_mask;
4370 }
4371
4372
4373 static void intel_setup_outputs(struct drm_device *dev)
4374 {
4375         struct drm_i915_private *dev_priv = dev->dev_private;
4376         struct drm_connector *connector;
4377
4378         intel_crt_init(dev);
4379
4380         /* Set up integrated LVDS */
4381         if (IS_MOBILE(dev) && !IS_I830(dev))
4382                 intel_lvds_init(dev);
4383
4384         if (IS_IRONLAKE(dev)) {
4385                 int found;
4386
4387                 if (IS_MOBILE(dev) && (I915_READ(DP_A) & DP_DETECTED))
4388                         intel_dp_init(dev, DP_A);
4389
4390                 if (I915_READ(HDMIB) & PORT_DETECTED) {
4391                         /* check SDVOB */
4392                         /* found = intel_sdvo_init(dev, HDMIB); */
4393                         found = 0;
4394                         if (!found)
4395                                 intel_hdmi_init(dev, HDMIB);
4396                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
4397                                 intel_dp_init(dev, PCH_DP_B);
4398                 }
4399
4400                 if (I915_READ(HDMIC) & PORT_DETECTED)
4401                         intel_hdmi_init(dev, HDMIC);
4402
4403                 if (I915_READ(HDMID) & PORT_DETECTED)
4404                         intel_hdmi_init(dev, HDMID);
4405
4406                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
4407                         intel_dp_init(dev, PCH_DP_C);
4408
4409                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
4410                         intel_dp_init(dev, PCH_DP_D);
4411
4412         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
4413                 bool found = false;
4414
4415                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4416                         DRM_DEBUG_KMS("probing SDVOB\n");
4417                         found = intel_sdvo_init(dev, SDVOB);
4418                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
4419                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
4420                                 intel_hdmi_init(dev, SDVOB);
4421                         }
4422
4423                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
4424                                 DRM_DEBUG_KMS("probing DP_B\n");
4425                                 intel_dp_init(dev, DP_B);
4426                         }
4427                 }
4428
4429                 /* Before G4X SDVOC doesn't have its own detect register */
4430
4431                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
4432                         DRM_DEBUG_KMS("probing SDVOC\n");
4433                         found = intel_sdvo_init(dev, SDVOC);
4434                 }
4435
4436                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
4437
4438                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
4439                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
4440                                 intel_hdmi_init(dev, SDVOC);
4441                         }
4442                         if (SUPPORTS_INTEGRATED_DP(dev)) {
4443                                 DRM_DEBUG_KMS("probing DP_C\n");
4444                                 intel_dp_init(dev, DP_C);
4445                         }
4446                 }
4447
4448                 if (SUPPORTS_INTEGRATED_DP(dev) &&
4449                     (I915_READ(DP_D) & DP_DETECTED)) {
4450                         DRM_DEBUG_KMS("probing DP_D\n");
4451                         intel_dp_init(dev, DP_D);
4452                 }
4453         } else if (IS_I8XX(dev))
4454                 intel_dvo_init(dev);
4455
4456         if (SUPPORTS_TV(dev))
4457                 intel_tv_init(dev);
4458
4459         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
4460                 struct intel_output *intel_output = to_intel_output(connector);
4461                 struct drm_encoder *encoder = &intel_output->enc;
4462
4463                 encoder->possible_crtcs = intel_output->crtc_mask;
4464                 encoder->possible_clones = intel_connector_clones(dev,
4465                                                 intel_output->clone_mask);
4466         }
4467 }
4468
4469 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
4470 {
4471         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4472         struct drm_device *dev = fb->dev;
4473
4474         if (fb->fbdev)
4475                 intelfb_remove(dev, fb);
4476
4477         drm_framebuffer_cleanup(fb);
4478         drm_gem_object_unreference_unlocked(intel_fb->obj);
4479
4480         kfree(intel_fb);
4481 }
4482
4483 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
4484                                                 struct drm_file *file_priv,
4485                                                 unsigned int *handle)
4486 {
4487         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
4488         struct drm_gem_object *object = intel_fb->obj;
4489
4490         return drm_gem_handle_create(file_priv, object, handle);
4491 }
4492
4493 static const struct drm_framebuffer_funcs intel_fb_funcs = {
4494         .destroy = intel_user_framebuffer_destroy,
4495         .create_handle = intel_user_framebuffer_create_handle,
4496 };
4497
4498 int intel_framebuffer_create(struct drm_device *dev,
4499                              struct drm_mode_fb_cmd *mode_cmd,
4500                              struct drm_framebuffer **fb,
4501                              struct drm_gem_object *obj)
4502 {
4503         struct intel_framebuffer *intel_fb;
4504         int ret;
4505
4506         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
4507         if (!intel_fb)
4508                 return -ENOMEM;
4509
4510         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
4511         if (ret) {
4512                 DRM_ERROR("framebuffer init failed %d\n", ret);
4513                 return ret;
4514         }
4515
4516         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
4517
4518         intel_fb->obj = obj;
4519
4520         *fb = &intel_fb->base;
4521
4522         return 0;
4523 }
4524
4525
4526 static struct drm_framebuffer *
4527 intel_user_framebuffer_create(struct drm_device *dev,
4528                               struct drm_file *filp,
4529                               struct drm_mode_fb_cmd *mode_cmd)
4530 {
4531         struct drm_gem_object *obj;
4532         struct drm_framebuffer *fb;
4533         int ret;
4534
4535         obj = drm_gem_object_lookup(dev, filp, mode_cmd->handle);
4536         if (!obj)
4537                 return NULL;
4538
4539         ret = intel_framebuffer_create(dev, mode_cmd, &fb, obj);
4540         if (ret) {
4541                 drm_gem_object_unreference_unlocked(obj);
4542                 return NULL;
4543         }
4544
4545         return fb;
4546 }
4547
4548 static const struct drm_mode_config_funcs intel_mode_funcs = {
4549         .fb_create = intel_user_framebuffer_create,
4550         .fb_changed = intelfb_probe,
4551 };
4552
4553 static struct drm_gem_object *
4554 intel_alloc_power_context(struct drm_device *dev)
4555 {
4556         struct drm_gem_object *pwrctx;
4557         int ret;
4558
4559         pwrctx = drm_gem_object_alloc(dev, 4096);
4560         if (!pwrctx) {
4561                 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
4562                 return NULL;
4563         }
4564
4565         mutex_lock(&dev->struct_mutex);
4566         ret = i915_gem_object_pin(pwrctx, 4096);
4567         if (ret) {
4568                 DRM_ERROR("failed to pin power context: %d\n", ret);
4569                 goto err_unref;
4570         }
4571
4572         ret = i915_gem_object_set_to_gtt_domain(pwrctx, 1);
4573         if (ret) {
4574                 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
4575                 goto err_unpin;
4576         }
4577         mutex_unlock(&dev->struct_mutex);
4578
4579         return pwrctx;
4580
4581 err_unpin:
4582         i915_gem_object_unpin(pwrctx);
4583 err_unref:
4584         drm_gem_object_unreference(pwrctx);
4585         mutex_unlock(&dev->struct_mutex);
4586         return NULL;
4587 }
4588
4589 void intel_init_clock_gating(struct drm_device *dev)
4590 {
4591         struct drm_i915_private *dev_priv = dev->dev_private;
4592
4593         /*
4594          * Disable clock gating reported to work incorrectly according to the
4595          * specs, but enable as much else as we can.
4596          */
4597         if (IS_IRONLAKE(dev)) {
4598                 return;
4599         } else if (IS_G4X(dev)) {
4600                 uint32_t dspclk_gate;
4601                 I915_WRITE(RENCLK_GATE_D1, 0);
4602                 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4603                        GS_UNIT_CLOCK_GATE_DISABLE |
4604                        CL_UNIT_CLOCK_GATE_DISABLE);
4605                 I915_WRITE(RAMCLK_GATE_D, 0);
4606                 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4607                         OVRUNIT_CLOCK_GATE_DISABLE |
4608                         OVCUNIT_CLOCK_GATE_DISABLE;
4609                 if (IS_GM45(dev))
4610                         dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4611                 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4612         } else if (IS_I965GM(dev)) {
4613                 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4614                 I915_WRITE(RENCLK_GATE_D2, 0);
4615                 I915_WRITE(DSPCLK_GATE_D, 0);
4616                 I915_WRITE(RAMCLK_GATE_D, 0);
4617                 I915_WRITE16(DEUC, 0);
4618         } else if (IS_I965G(dev)) {
4619                 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4620                        I965_RCC_CLOCK_GATE_DISABLE |
4621                        I965_RCPB_CLOCK_GATE_DISABLE |
4622                        I965_ISC_CLOCK_GATE_DISABLE |
4623                        I965_FBC_CLOCK_GATE_DISABLE);
4624                 I915_WRITE(RENCLK_GATE_D2, 0);
4625         } else if (IS_I9XX(dev)) {
4626                 u32 dstate = I915_READ(D_STATE);
4627
4628                 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4629                         DSTATE_DOT_CLOCK_GATING;
4630                 I915_WRITE(D_STATE, dstate);
4631         } else if (IS_I85X(dev) || IS_I865G(dev)) {
4632                 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4633         } else if (IS_I830(dev)) {
4634                 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4635         }
4636
4637         /*
4638          * GPU can automatically power down the render unit if given a page
4639          * to save state.
4640          */
4641         if (I915_HAS_RC6(dev) && drm_core_check_feature(dev, DRIVER_MODESET)) {
4642                 struct drm_i915_gem_object *obj_priv = NULL;
4643
4644                 if (dev_priv->pwrctx) {
4645                         obj_priv = dev_priv->pwrctx->driver_private;
4646                 } else {
4647                         struct drm_gem_object *pwrctx;
4648
4649                         pwrctx = intel_alloc_power_context(dev);
4650                         if (pwrctx) {
4651                                 dev_priv->pwrctx = pwrctx;
4652                                 obj_priv = pwrctx->driver_private;
4653                         }
4654                 }
4655
4656                 if (obj_priv) {
4657                         I915_WRITE(PWRCTXA, obj_priv->gtt_offset | PWRCTX_EN);
4658                         I915_WRITE(MCHBAR_RENDER_STANDBY,
4659                                    I915_READ(MCHBAR_RENDER_STANDBY) & ~RCX_SW_EXIT);
4660                 }
4661         }
4662 }
4663
4664 /* Set up chip specific display functions */
4665 static void intel_init_display(struct drm_device *dev)
4666 {
4667         struct drm_i915_private *dev_priv = dev->dev_private;
4668
4669         /* We always want a DPMS function */
4670         if (IS_IRONLAKE(dev))
4671                 dev_priv->display.dpms = ironlake_crtc_dpms;
4672         else
4673                 dev_priv->display.dpms = i9xx_crtc_dpms;
4674
4675         /* Only mobile has FBC, leave pointers NULL for other chips */
4676         if (IS_MOBILE(dev)) {
4677                 if (IS_GM45(dev)) {
4678                         dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4679                         dev_priv->display.enable_fbc = g4x_enable_fbc;
4680                         dev_priv->display.disable_fbc = g4x_disable_fbc;
4681                 } else if (IS_I965GM(dev) || IS_I945GM(dev) || IS_I915GM(dev)) {
4682                         dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4683                         dev_priv->display.enable_fbc = i8xx_enable_fbc;
4684                         dev_priv->display.disable_fbc = i8xx_disable_fbc;
4685                 }
4686                 /* 855GM needs testing */
4687         }
4688
4689         /* Returns the core display clock speed */
4690         if (IS_I945G(dev) || (IS_G33(dev) && ! IS_PINEVIEW_M(dev)))
4691                 dev_priv->display.get_display_clock_speed =
4692                         i945_get_display_clock_speed;
4693         else if (IS_I915G(dev))
4694                 dev_priv->display.get_display_clock_speed =
4695                         i915_get_display_clock_speed;
4696         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
4697                 dev_priv->display.get_display_clock_speed =
4698                         i9xx_misc_get_display_clock_speed;
4699         else if (IS_I915GM(dev))
4700                 dev_priv->display.get_display_clock_speed =
4701                         i915gm_get_display_clock_speed;
4702         else if (IS_I865G(dev))
4703                 dev_priv->display.get_display_clock_speed =
4704                         i865_get_display_clock_speed;
4705         else if (IS_I85X(dev))
4706                 dev_priv->display.get_display_clock_speed =
4707                         i855_get_display_clock_speed;
4708         else /* 852, 830 */
4709                 dev_priv->display.get_display_clock_speed =
4710                         i830_get_display_clock_speed;
4711
4712         /* For FIFO watermark updates */
4713         if (IS_IRONLAKE(dev))
4714                 dev_priv->display.update_wm = NULL;
4715         else if (IS_G4X(dev))
4716                 dev_priv->display.update_wm = g4x_update_wm;
4717         else if (IS_I965G(dev))
4718                 dev_priv->display.update_wm = i965_update_wm;
4719         else if (IS_I9XX(dev) || IS_MOBILE(dev)) {
4720                 dev_priv->display.update_wm = i9xx_update_wm;
4721                 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4722         } else {
4723                 if (IS_I85X(dev))
4724                         dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4725                 else if (IS_845G(dev))
4726                         dev_priv->display.get_fifo_size = i845_get_fifo_size;
4727                 else
4728                         dev_priv->display.get_fifo_size = i830_get_fifo_size;
4729                 dev_priv->display.update_wm = i830_update_wm;
4730         }
4731 }
4732
4733 void intel_modeset_init(struct drm_device *dev)
4734 {
4735         struct drm_i915_private *dev_priv = dev->dev_private;
4736         int num_pipe;
4737         int i;
4738
4739         drm_mode_config_init(dev);
4740
4741         dev->mode_config.min_width = 0;
4742         dev->mode_config.min_height = 0;
4743
4744         dev->mode_config.funcs = (void *)&intel_mode_funcs;
4745
4746         intel_init_display(dev);
4747
4748         if (IS_I965G(dev)) {
4749                 dev->mode_config.max_width = 8192;
4750                 dev->mode_config.max_height = 8192;
4751         } else if (IS_I9XX(dev)) {
4752                 dev->mode_config.max_width = 4096;
4753                 dev->mode_config.max_height = 4096;
4754         } else {
4755                 dev->mode_config.max_width = 2048;
4756                 dev->mode_config.max_height = 2048;
4757         }
4758
4759         /* set memory base */
4760         if (IS_I9XX(dev))
4761                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 2);
4762         else
4763                 dev->mode_config.fb_base = pci_resource_start(dev->pdev, 0);
4764
4765         if (IS_MOBILE(dev) || IS_I9XX(dev))
4766                 num_pipe = 2;
4767         else
4768                 num_pipe = 1;
4769         DRM_DEBUG_KMS("%d display pipe%s available.\n",
4770                   num_pipe, num_pipe > 1 ? "s" : "");
4771
4772         if (IS_I85X(dev))
4773                 pci_read_config_word(dev->pdev, HPLLCC, &dev_priv->orig_clock);
4774         else if (IS_I9XX(dev) || IS_G4X(dev))
4775                 pci_read_config_word(dev->pdev, GCFGC, &dev_priv->orig_clock);
4776
4777         for (i = 0; i < num_pipe; i++) {
4778                 intel_crtc_init(dev, i);
4779         }
4780
4781         intel_setup_outputs(dev);
4782
4783         intel_init_clock_gating(dev);
4784
4785         INIT_WORK(&dev_priv->idle_work, intel_idle_update);
4786         setup_timer(&dev_priv->idle_timer, intel_gpu_idle_timer,
4787                     (unsigned long)dev);
4788
4789         intel_setup_overlay(dev);
4790
4791         if (IS_PINEVIEW(dev) && !intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4792                                                         dev_priv->fsb_freq,
4793                                                         dev_priv->mem_freq))
4794                 DRM_INFO("failed to find known CxSR latency "
4795                          "(found fsb freq %d, mem freq %d), disabling CxSR\n",
4796                          dev_priv->fsb_freq, dev_priv->mem_freq);
4797 }
4798
4799 void intel_modeset_cleanup(struct drm_device *dev)
4800 {
4801         struct drm_i915_private *dev_priv = dev->dev_private;
4802         struct drm_crtc *crtc;
4803         struct intel_crtc *intel_crtc;
4804
4805         mutex_lock(&dev->struct_mutex);
4806
4807         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4808                 /* Skip inactive CRTCs */
4809                 if (!crtc->fb)
4810                         continue;
4811
4812                 intel_crtc = to_intel_crtc(crtc);
4813                 intel_increase_pllclock(crtc, false);
4814                 del_timer_sync(&intel_crtc->idle_timer);
4815         }
4816
4817         del_timer_sync(&dev_priv->idle_timer);
4818
4819         if (dev_priv->display.disable_fbc)
4820                 dev_priv->display.disable_fbc(dev);
4821
4822         if (dev_priv->pwrctx) {
4823                 struct drm_i915_gem_object *obj_priv;
4824
4825                 obj_priv = dev_priv->pwrctx->driver_private;
4826                 I915_WRITE(PWRCTXA, obj_priv->gtt_offset &~ PWRCTX_EN);
4827                 I915_READ(PWRCTXA);
4828                 i915_gem_object_unpin(dev_priv->pwrctx);
4829                 drm_gem_object_unreference(dev_priv->pwrctx);
4830         }
4831
4832         mutex_unlock(&dev->struct_mutex);
4833
4834         drm_mode_config_cleanup(dev);
4835 }
4836
4837
4838 /* current intel driver doesn't take advantage of encoders
4839    always give back the encoder for the connector
4840 */
4841 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
4842 {
4843         struct intel_output *intel_output = to_intel_output(connector);
4844
4845         return &intel_output->enc;
4846 }
4847
4848 /*
4849  * set vga decode state - true == enable VGA decode
4850  */
4851 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
4852 {
4853         struct drm_i915_private *dev_priv = dev->dev_private;
4854         u16 gmch_ctrl;
4855
4856         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
4857         if (state)
4858                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
4859         else
4860                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
4861         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
4862         return 0;
4863 }